Merge tag 'mvebu-fixes-4.7-1' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for 4.7 (part 1)

Various I/O memory fix for Cortex A9 based SoCs

* tag 'mvebu-fixes-4.7-1' of git://git.infradead.org/linux-mvebu:
  ARM: dts: armada-38x: fix MBUS_ID for crypto SRAM on Armada 385 Linksys
  ARM: mvebu: map PCI I/O regions strongly ordered
  ARM: mvebu: fix HW I/O coherency related deadlocks

Signed-off-by: Olof Johansson <olof@lixom.net>

2 files changed, 11 insertions, 16 deletions

diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index 8450944b28e6..22f7a13e20b4 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -58,8 +58,8 @@
         soc {
                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
-                          MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
-                          MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
+                          MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+                          MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
 
                 internal-regs {
 
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 7e989d61159c..e80f0dde2189 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -162,22 +162,16 @@ exit:
 }
 
 /*
- * This ioremap hook is used on Armada 375/38x to ensure that PCIe
- * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
- * is needed as a workaround for a deadlock issue between the PCIe
- * interface and the cache controller.
+ * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
+ * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
+ * needed for the HW I/O coherency mechanism to work properly without
+ * deadlock.
  */
 static void __iomem *
-armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
-                              unsigned int mtype, void *caller)
+armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
+                         unsigned int mtype, void *caller)
 {
-        struct resource pcie_mem;
-
-        mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
-
-        if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
-                mtype = MT_UNCACHED;
-
+        mtype = MT_UNCACHED;
         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 }
 
@@ -186,7 +180,8 @@ static void __init armada_375_380_coherency_init(struct device_node *np)
         struct device_node *cache_dn;
 
         coherency_cpu_base = of_iomap(np, 0);
-        arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
+        arch_ioremap_caller = armada_wa_ioremap_caller;
+        pci_ioremap_set_mem_type(MT_UNCACHED);
 
         /*
          * We should switch the PL310 to I/O coherency mode only if