diff options
| author | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2015-01-29 09:55:08 -0500 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-01-30 11:31:30 -0500 |
| commit | ed6739efc95e8c049f67000586f6317f3914a696 (patch) | |
| tree | 31ce2863fd7d7d94edd2dbe9d56bbb3ae60bb9c7 | |
| parent | 078595043b490a5cf0c272fe90151be9a5d48973 (diff) | |
drm/i915: Split shared dpll setup out of __intel_set_mode()
This simplifies __intel_set_mode() a little.
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 50 |
1 files changed, 33 insertions, 17 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 423ef959264d..3d220a67f865 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
| @@ -11021,6 +11021,36 @@ out: | |||
| 11021 | return pipe_config; | 11021 | return pipe_config; |
| 11022 | } | 11022 | } |
| 11023 | 11023 | ||
| 11024 | static int __intel_set_mode_setup_plls(struct drm_device *dev, | ||
| 11025 | unsigned modeset_pipes, | ||
| 11026 | unsigned disable_pipes) | ||
| 11027 | { | ||
| 11028 | struct drm_i915_private *dev_priv = to_i915(dev); | ||
| 11029 | unsigned clear_pipes = modeset_pipes | disable_pipes; | ||
| 11030 | struct intel_crtc *intel_crtc; | ||
| 11031 | int ret = 0; | ||
| 11032 | |||
| 11033 | if (!dev_priv->display.crtc_compute_clock) | ||
| 11034 | return 0; | ||
| 11035 | |||
| 11036 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | ||
| 11037 | if (ret) | ||
| 11038 | goto done; | ||
| 11039 | |||
| 11040 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | ||
| 11041 | struct intel_crtc_state *state = intel_crtc->new_config; | ||
| 11042 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | ||
| 11043 | state); | ||
| 11044 | if (ret) { | ||
| 11045 | intel_shared_dpll_abort_config(dev_priv); | ||
| 11046 | goto done; | ||
| 11047 | } | ||
| 11048 | } | ||
| 11049 | |||
| 11050 | done: | ||
| 11051 | return ret; | ||
| 11052 | } | ||
| 11053 | |||
| 11024 | static int __intel_set_mode(struct drm_crtc *crtc, | 11054 | static int __intel_set_mode(struct drm_crtc *crtc, |
| 11025 | struct drm_display_mode *mode, | 11055 | struct drm_display_mode *mode, |
| 11026 | int x, int y, struct drm_framebuffer *fb, | 11056 | int x, int y, struct drm_framebuffer *fb, |
| @@ -11058,23 +11088,9 @@ static int __intel_set_mode(struct drm_crtc *crtc, | |||
| 11058 | prepare_pipes &= ~disable_pipes; | 11088 | prepare_pipes &= ~disable_pipes; |
| 11059 | } | 11089 | } |
| 11060 | 11090 | ||
| 11061 | if (dev_priv->display.crtc_compute_clock) { | 11091 | ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes); |
| 11062 | unsigned clear_pipes = modeset_pipes | disable_pipes; | 11092 | if (ret) |
| 11063 | 11093 | goto done; | |
| 11064 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | ||
| 11065 | if (ret) | ||
| 11066 | goto done; | ||
| 11067 | |||
| 11068 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | ||
| 11069 | struct intel_crtc_state *state = intel_crtc->new_config; | ||
| 11070 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | ||
| 11071 | state); | ||
| 11072 | if (ret) { | ||
| 11073 | intel_shared_dpll_abort_config(dev_priv); | ||
| 11074 | goto done; | ||
| 11075 | } | ||
| 11076 | } | ||
| 11077 | } | ||
| 11078 | 11094 | ||
| 11079 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) | 11095 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
| 11080 | intel_crtc_disable(&intel_crtc->base); | 11096 | intel_crtc_disable(&intel_crtc->base); |
