diff options
author | Nils Wallménius <nils.wallmenius@gmail.com> | 2016-03-19 11:12:17 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-02 13:08:57 -0400 |
commit | eca2240fb044e30276ecbb43eab47a46f96c05c4 (patch) | |
tree | cc6de080eaa6464818d732ea4be6bdc2274f77bf | |
parent | 379548f509b5d4bdfcf252dd33093a45c01ce0d8 (diff) |
drm/amdgpu: mark amdgpu_allowed_register_entry tables as 'const'
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vi.c | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index bddc9ba11495..009598bc4df8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c | |||
@@ -962,7 +962,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, | |||
962 | return true; | 962 | return true; |
963 | } | 963 | } |
964 | 964 | ||
965 | static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { | 965 | static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { |
966 | {mmGRBM_STATUS, false}, | 966 | {mmGRBM_STATUS, false}, |
967 | {mmGB_ADDR_CONFIG, false}, | 967 | {mmGB_ADDR_CONFIG, false}, |
968 | {mmMC_ARB_RAMCFG, false}, | 968 | {mmMC_ARB_RAMCFG, false}, |
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 1c120efa292c..a14555673c40 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c | |||
@@ -414,11 +414,11 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, | |||
414 | return true; | 414 | return true; |
415 | } | 415 | } |
416 | 416 | ||
417 | static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { | 417 | static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = { |
418 | {mmGB_MACROTILE_MODE7, true}, | 418 | {mmGB_MACROTILE_MODE7, true}, |
419 | }; | 419 | }; |
420 | 420 | ||
421 | static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { | 421 | static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { |
422 | {mmGB_TILE_MODE7, true}, | 422 | {mmGB_TILE_MODE7, true}, |
423 | {mmGB_TILE_MODE12, true}, | 423 | {mmGB_TILE_MODE12, true}, |
424 | {mmGB_TILE_MODE17, true}, | 424 | {mmGB_TILE_MODE17, true}, |
@@ -426,7 +426,7 @@ static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = { | |||
426 | {mmGB_MACROTILE_MODE7, true}, | 426 | {mmGB_MACROTILE_MODE7, true}, |
427 | }; | 427 | }; |
428 | 428 | ||
429 | static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { | 429 | static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = { |
430 | {mmGRBM_STATUS, false}, | 430 | {mmGRBM_STATUS, false}, |
431 | {mmGRBM_STATUS2, false}, | 431 | {mmGRBM_STATUS2, false}, |
432 | {mmGRBM_STATUS_SE0, false}, | 432 | {mmGRBM_STATUS_SE0, false}, |
@@ -525,8 +525,8 @@ static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num, | |||
525 | static int vi_read_register(struct amdgpu_device *adev, u32 se_num, | 525 | static int vi_read_register(struct amdgpu_device *adev, u32 se_num, |
526 | u32 sh_num, u32 reg_offset, u32 *value) | 526 | u32 sh_num, u32 reg_offset, u32 *value) |
527 | { | 527 | { |
528 | struct amdgpu_allowed_register_entry *asic_register_table = NULL; | 528 | const struct amdgpu_allowed_register_entry *asic_register_table = NULL; |
529 | struct amdgpu_allowed_register_entry *asic_register_entry; | 529 | const struct amdgpu_allowed_register_entry *asic_register_entry; |
530 | uint32_t size, i; | 530 | uint32_t size, i; |
531 | 531 | ||
532 | *value = 0; | 532 | *value = 0; |