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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2016-02-11 07:18:20 -0500
committerMark Brown <broonie@kernel.org>2016-02-19 11:20:18 -0500
commitec9e0ec84476954f971feb5e0422b48cb25dde58 (patch)
tree2a93884ccf1599b52cf2c7d939ab22762dc68ce6
parent71aaa600787faffd72a9b674c9e5c9ded7cd9a82 (diff)
ASoC: qcom: add generic bit masks for RDMA and WRDMA
This patch adds generic masks for accessing bits in rdma/wrdma registers. Doing this would simplify the driver and adding capture support would be much simpler. Also there is no point in having same bit masks for bits in both rdma and wrdma registers. This patch also deletes the RDMA specific bit masks and makes the code use the generic bit masks. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/qcom/lpass-lpaif-reg.h83
-rw-r--r--sound/soc/qcom/lpass-platform.c54
2 files changed, 79 insertions, 58 deletions
diff --git a/sound/soc/qcom/lpass-lpaif-reg.h b/sound/soc/qcom/lpass-lpaif-reg.h
index 760d21905f90..2240bc68e6ec 100644
--- a/sound/soc/qcom/lpass-lpaif-reg.h
+++ b/sound/soc/qcom/lpass-lpaif-reg.h
@@ -112,39 +112,6 @@
112#define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan)) 112#define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
113#define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan)) 113#define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
114 114
115#define LPAIF_RDMACTL_BURSTEN_MASK 0x800
116#define LPAIF_RDMACTL_BURSTEN_SHIFT 11
117#define LPAIF_RDMACTL_BURSTEN_SINGLE (0 << LPAIF_RDMACTL_BURSTEN_SHIFT)
118#define LPAIF_RDMACTL_BURSTEN_INCR4 (1 << LPAIF_RDMACTL_BURSTEN_SHIFT)
119
120#define LPAIF_RDMACTL_WPSCNT_MASK 0x700
121#define LPAIF_RDMACTL_WPSCNT_SHIFT 8
122#define LPAIF_RDMACTL_WPSCNT_ONE (0 << LPAIF_RDMACTL_WPSCNT_SHIFT)
123#define LPAIF_RDMACTL_WPSCNT_TWO (1 << LPAIF_RDMACTL_WPSCNT_SHIFT)
124#define LPAIF_RDMACTL_WPSCNT_THREE (2 << LPAIF_RDMACTL_WPSCNT_SHIFT)
125#define LPAIF_RDMACTL_WPSCNT_FOUR (3 << LPAIF_RDMACTL_WPSCNT_SHIFT)
126#define LPAIF_RDMACTL_WPSCNT_SIX (5 << LPAIF_RDMACTL_WPSCNT_SHIFT)
127#define LPAIF_RDMACTL_WPSCNT_EIGHT (7 << LPAIF_RDMACTL_WPSCNT_SHIFT)
128
129#define LPAIF_RDMACTL_AUDINTF_MASK 0x0F0
130#define LPAIF_RDMACTL_AUDINTF_SHIFT 4
131
132#define LPAIF_RDMACTL_FIFOWM_MASK 0x00E
133#define LPAIF_RDMACTL_FIFOWM_SHIFT 1
134#define LPAIF_RDMACTL_FIFOWM_1 (0 << LPAIF_RDMACTL_FIFOWM_SHIFT)
135#define LPAIF_RDMACTL_FIFOWM_2 (1 << LPAIF_RDMACTL_FIFOWM_SHIFT)
136#define LPAIF_RDMACTL_FIFOWM_3 (2 << LPAIF_RDMACTL_FIFOWM_SHIFT)
137#define LPAIF_RDMACTL_FIFOWM_4 (3 << LPAIF_RDMACTL_FIFOWM_SHIFT)
138#define LPAIF_RDMACTL_FIFOWM_5 (4 << LPAIF_RDMACTL_FIFOWM_SHIFT)
139#define LPAIF_RDMACTL_FIFOWM_6 (5 << LPAIF_RDMACTL_FIFOWM_SHIFT)
140#define LPAIF_RDMACTL_FIFOWM_7 (6 << LPAIF_RDMACTL_FIFOWM_SHIFT)
141#define LPAIF_RDMACTL_FIFOWM_8 (7 << LPAIF_RDMACTL_FIFOWM_SHIFT)
142
143#define LPAIF_RDMACTL_ENABLE_MASK 0x1
144#define LPAIF_RDMACTL_ENABLE_SHIFT 0
145#define LPAIF_RDMACTL_ENABLE_OFF (0 << LPAIF_RDMACTL_ENABLE_SHIFT)
146#define LPAIF_RDMACTL_ENABLE_ON (1 << LPAIF_RDMACTL_ENABLE_SHIFT)
147
148#define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \ 115#define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
149 (v->wrdma_reg_base + (addr) + \ 116 (v->wrdma_reg_base + (addr) + \
150 v->wrdma_reg_stride * (chan - v->wrdma_channel_start)) 117 v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
@@ -156,4 +123,54 @@
156#define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan)) 123#define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
157#define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan)) 124#define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
158 125
126#define __LPAIF_DMA_REG(v, chan, dir, reg) \
127 (dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
128 LPAIF_RDMA##reg##_REG(v, chan) : \
129 LPAIF_WRDMA##reg##_REG(v, chan)
130
131#define LPAIF_DMACTL_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CTL)
132#define LPAIF_DMABASE_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BASE)
133#define LPAIF_DMABUFF_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, BUFF)
134#define LPAIF_DMACURR_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, CURR)
135#define LPAIF_DMAPER_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PER)
136#define LPAIF_DMAPERCNT_REG(v, chan, dir) __LPAIF_DMA_REG(v, chan, dir, PERCNT)
137
138#define LPAIF_DMACTL_BURSTEN_MASK 0x800
139#define LPAIF_DMACTL_BURSTEN_SHIFT 11
140#define LPAIF_DMACTL_BURSTEN_SINGLE (0 << LPAIF_DMACTL_BURSTEN_SHIFT)
141#define LPAIF_DMACTL_BURSTEN_INCR4 (1 << LPAIF_DMACTL_BURSTEN_SHIFT)
142
143#define LPAIF_DMACTL_WPSCNT_MASK 0x700
144#define LPAIF_DMACTL_WPSCNT_SHIFT 8
145#define LPAIF_DMACTL_WPSCNT_ONE (0 << LPAIF_DMACTL_WPSCNT_SHIFT)
146#define LPAIF_DMACTL_WPSCNT_TWO (1 << LPAIF_DMACTL_WPSCNT_SHIFT)
147#define LPAIF_DMACTL_WPSCNT_THREE (2 << LPAIF_DMACTL_WPSCNT_SHIFT)
148#define LPAIF_DMACTL_WPSCNT_FOUR (3 << LPAIF_DMACTL_WPSCNT_SHIFT)
149#define LPAIF_DMACTL_WPSCNT_SIX (5 << LPAIF_DMACTL_WPSCNT_SHIFT)
150#define LPAIF_DMACTL_WPSCNT_EIGHT (7 << LPAIF_DMACTL_WPSCNT_SHIFT)
151
152#define LPAIF_DMACTL_AUDINTF_MASK 0x0F0
153#define LPAIF_DMACTL_AUDINTF_SHIFT 4
154#define LPAIF_DMACTL_AUDINTF(id) (id << LPAIF_DMACTL_AUDINTF_SHIFT)
155
156#define LPAIF_DMACTL_FIFOWM_MASK 0x00E
157#define LPAIF_DMACTL_FIFOWM_SHIFT 1
158#define LPAIF_DMACTL_FIFOWM_1 (0 << LPAIF_DMACTL_FIFOWM_SHIFT)
159#define LPAIF_DMACTL_FIFOWM_2 (1 << LPAIF_DMACTL_FIFOWM_SHIFT)
160#define LPAIF_DMACTL_FIFOWM_3 (2 << LPAIF_DMACTL_FIFOWM_SHIFT)
161#define LPAIF_DMACTL_FIFOWM_4 (3 << LPAIF_DMACTL_FIFOWM_SHIFT)
162#define LPAIF_DMACTL_FIFOWM_5 (4 << LPAIF_DMACTL_FIFOWM_SHIFT)
163#define LPAIF_DMACTL_FIFOWM_6 (5 << LPAIF_DMACTL_FIFOWM_SHIFT)
164#define LPAIF_DMACTL_FIFOWM_7 (6 << LPAIF_DMACTL_FIFOWM_SHIFT)
165#define LPAIF_DMACTL_FIFOWM_8 (7 << LPAIF_DMACTL_FIFOWM_SHIFT)
166
167#define LPAIF_DMACTL_ENABLE_MASK 0x1
168#define LPAIF_DMACTL_ENABLE_SHIFT 0
169#define LPAIF_DMACTL_ENABLE_OFF (0 << LPAIF_DMACTL_ENABLE_SHIFT)
170#define LPAIF_DMACTL_ENABLE_ON (1 << LPAIF_DMACTL_ENABLE_SHIFT)
171
172#define LPAIF_DMACTL_DYNCLK_MASK BIT(12)
173#define LPAIF_DMACTL_DYNCLK_SHIFT 12
174#define LPAIF_DMACTL_DYNCLK_OFF (0 << LPAIF_DMACTL_DYNCLK_SHIFT)
175#define LPAIF_DMACTL_DYNCLK_ON (1 << LPAIF_DMACTL_DYNCLK_SHIFT)
159#endif /* __LPASS_LPAIF_REG_H__ */ 176#endif /* __LPASS_LPAIF_REG_H__ */
diff --git a/sound/soc/qcom/lpass-platform.c b/sound/soc/qcom/lpass-platform.c
index 69c5ad8e2bd7..348e50bc8891 100644
--- a/sound/soc/qcom/lpass-platform.c
+++ b/sound/soc/qcom/lpass-platform.c
@@ -90,6 +90,7 @@ static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
90 snd_pcm_format_t format = params_format(params); 90 snd_pcm_format_t format = params_format(params);
91 unsigned int channels = params_channels(params); 91 unsigned int channels = params_channels(params);
92 unsigned int regval; 92 unsigned int regval;
93 int dir = substream->stream;
93 int bitwidth; 94 int bitwidth;
94 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start; 95 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start;
95 96
@@ -100,25 +101,25 @@ static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
100 return bitwidth; 101 return bitwidth;
101 } 102 }
102 103
103 regval = LPAIF_RDMACTL_BURSTEN_INCR4 | 104 regval = LPAIF_DMACTL_BURSTEN_INCR4 |
104 LPAIF_RDMACTL_AUDINTF(dma_port) | 105 LPAIF_DMACTL_AUDINTF(dma_port) |
105 LPAIF_RDMACTL_FIFOWM_8; 106 LPAIF_DMACTL_FIFOWM_8;
106 107
107 switch (bitwidth) { 108 switch (bitwidth) {
108 case 16: 109 case 16:
109 switch (channels) { 110 switch (channels) {
110 case 1: 111 case 1:
111 case 2: 112 case 2:
112 regval |= LPAIF_RDMACTL_WPSCNT_ONE; 113 regval |= LPAIF_DMACTL_WPSCNT_ONE;
113 break; 114 break;
114 case 4: 115 case 4:
115 regval |= LPAIF_RDMACTL_WPSCNT_TWO; 116 regval |= LPAIF_DMACTL_WPSCNT_TWO;
116 break; 117 break;
117 case 6: 118 case 6:
118 regval |= LPAIF_RDMACTL_WPSCNT_THREE; 119 regval |= LPAIF_DMACTL_WPSCNT_THREE;
119 break; 120 break;
120 case 8: 121 case 8:
121 regval |= LPAIF_RDMACTL_WPSCNT_FOUR; 122 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
122 break; 123 break;
123 default: 124 default:
124 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", 125 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
@@ -130,19 +131,19 @@ static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
130 case 32: 131 case 32:
131 switch (channels) { 132 switch (channels) {
132 case 1: 133 case 1:
133 regval |= LPAIF_RDMACTL_WPSCNT_ONE; 134 regval |= LPAIF_DMACTL_WPSCNT_ONE;
134 break; 135 break;
135 case 2: 136 case 2:
136 regval |= LPAIF_RDMACTL_WPSCNT_TWO; 137 regval |= LPAIF_DMACTL_WPSCNT_TWO;
137 break; 138 break;
138 case 4: 139 case 4:
139 regval |= LPAIF_RDMACTL_WPSCNT_FOUR; 140 regval |= LPAIF_DMACTL_WPSCNT_FOUR;
140 break; 141 break;
141 case 6: 142 case 6:
142 regval |= LPAIF_RDMACTL_WPSCNT_SIX; 143 regval |= LPAIF_DMACTL_WPSCNT_SIX;
143 break; 144 break;
144 case 8: 145 case 8:
145 regval |= LPAIF_RDMACTL_WPSCNT_EIGHT; 146 regval |= LPAIF_DMACTL_WPSCNT_EIGHT;
146 break; 147 break;
147 default: 148 default:
148 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", 149 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
@@ -157,7 +158,7 @@ static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
157 } 158 }
158 159
159 ret = regmap_write(drvdata->lpaif_map, 160 ret = regmap_write(drvdata->lpaif_map,
160 LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch), regval); 161 LPAIF_DMACTL_REG(v, pcm_data->rdma_ch, dir), regval);
161 if (ret) { 162 if (ret) {
162 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 163 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
163 __func__, ret); 164 __func__, ret);
@@ -194,6 +195,7 @@ static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
194 snd_soc_platform_get_drvdata(soc_runtime->platform); 195 snd_soc_platform_get_drvdata(soc_runtime->platform);
195 struct lpass_variant *v = drvdata->variant; 196 struct lpass_variant *v = drvdata->variant;
196 int ret, ch = pcm_data->rdma_ch; 197 int ret, ch = pcm_data->rdma_ch;
198 int dir = substream->stream;
197 199
198 ret = regmap_write(drvdata->lpaif_map, 200 ret = regmap_write(drvdata->lpaif_map,
199 LPAIF_RDMABASE_REG(v, ch), 201 LPAIF_RDMABASE_REG(v, ch),
@@ -205,7 +207,7 @@ static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
205 } 207 }
206 208
207 ret = regmap_write(drvdata->lpaif_map, 209 ret = regmap_write(drvdata->lpaif_map,
208 LPAIF_RDMABUFF_REG(v, ch), 210 LPAIF_DMABUFF_REG(v, ch, dir),
209 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1); 211 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
210 if (ret) { 212 if (ret) {
211 dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n", 213 dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
@@ -214,7 +216,7 @@ static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
214 } 216 }
215 217
216 ret = regmap_write(drvdata->lpaif_map, 218 ret = regmap_write(drvdata->lpaif_map,
217 LPAIF_RDMAPER_REG(v, ch), 219 LPAIF_DMAPER_REG(v, ch, dir),
218 (snd_pcm_lib_period_bytes(substream) >> 2) - 1); 220 (snd_pcm_lib_period_bytes(substream) >> 2) - 1);
219 if (ret) { 221 if (ret) {
220 dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n", 222 dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
@@ -223,8 +225,8 @@ static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
223 } 225 }
224 226
225 ret = regmap_update_bits(drvdata->lpaif_map, 227 ret = regmap_update_bits(drvdata->lpaif_map,
226 LPAIF_RDMACTL_REG(v, ch), 228 LPAIF_DMACTL_REG(v, ch, dir),
227 LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_ON); 229 LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON);
228 if (ret) { 230 if (ret) {
229 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 231 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
230 __func__, ret); 232 __func__, ret);
@@ -243,6 +245,7 @@ static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
243 snd_soc_platform_get_drvdata(soc_runtime->platform); 245 snd_soc_platform_get_drvdata(soc_runtime->platform);
244 struct lpass_variant *v = drvdata->variant; 246 struct lpass_variant *v = drvdata->variant;
245 int ret, ch = pcm_data->rdma_ch; 247 int ret, ch = pcm_data->rdma_ch;
248 int dir = substream->stream;
246 249
247 switch (cmd) { 250 switch (cmd) {
248 case SNDRV_PCM_TRIGGER_START: 251 case SNDRV_PCM_TRIGGER_START:
@@ -269,9 +272,9 @@ static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
269 } 272 }
270 273
271 ret = regmap_update_bits(drvdata->lpaif_map, 274 ret = regmap_update_bits(drvdata->lpaif_map,
272 LPAIF_RDMACTL_REG(v, ch), 275 LPAIF_DMACTL_REG(v, ch, dir),
273 LPAIF_RDMACTL_ENABLE_MASK, 276 LPAIF_DMACTL_ENABLE_MASK,
274 LPAIF_RDMACTL_ENABLE_ON); 277 LPAIF_DMACTL_ENABLE_ON);
275 if (ret) { 278 if (ret) {
276 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 279 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
277 __func__, ret); 280 __func__, ret);
@@ -282,9 +285,9 @@ static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
282 case SNDRV_PCM_TRIGGER_SUSPEND: 285 case SNDRV_PCM_TRIGGER_SUSPEND:
283 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 286 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
284 ret = regmap_update_bits(drvdata->lpaif_map, 287 ret = regmap_update_bits(drvdata->lpaif_map,
285 LPAIF_RDMACTL_REG(v, ch), 288 LPAIF_DMACTL_REG(v, ch, dir),
286 LPAIF_RDMACTL_ENABLE_MASK, 289 LPAIF_DMACTL_ENABLE_MASK,
287 LPAIF_RDMACTL_ENABLE_OFF); 290 LPAIF_DMACTL_ENABLE_OFF);
288 if (ret) { 291 if (ret) {
289 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 292 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
290 __func__, ret); 293 __func__, ret);
@@ -315,9 +318,10 @@ static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
315 struct lpass_variant *v = drvdata->variant; 318 struct lpass_variant *v = drvdata->variant;
316 unsigned int base_addr, curr_addr; 319 unsigned int base_addr, curr_addr;
317 int ret, ch = pcm_data->rdma_ch; 320 int ret, ch = pcm_data->rdma_ch;
321 int dir = substream->stream;
318 322
319 ret = regmap_read(drvdata->lpaif_map, 323 ret = regmap_read(drvdata->lpaif_map,
320 LPAIF_RDMABASE_REG(v, ch), &base_addr); 324 LPAIF_DMABASE_REG(v, ch, dir), &base_addr);
321 if (ret) { 325 if (ret) {
322 dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n", 326 dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
323 __func__, ret); 327 __func__, ret);
@@ -325,7 +329,7 @@ static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
325 } 329 }
326 330
327 ret = regmap_read(drvdata->lpaif_map, 331 ret = regmap_read(drvdata->lpaif_map,
328 LPAIF_RDMACURR_REG(v, ch), &curr_addr); 332 LPAIF_DMACURR_REG(v, ch, dir), &curr_addr);
329 if (ret) { 333 if (ret) {
330 dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n", 334 dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
331 __func__, ret); 335 __func__, ret);