aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorludovic.desroches@atmel.com <ludovic.desroches@atmel.com>2015-11-23 10:27:30 -0500
committerUlf Hansson <ulf.hansson@linaro.org>2015-12-22 05:32:10 -0500
commitec8fc9cfa060fa41b84fdcf931b90ab2841a64bd (patch)
treeebc29ea2bb80a72fded9bd1d1189b420376d5482
parentfb0229dfec3df9247190f001f1b51d767f2ee035 (diff)
mmc: atmel-mci: move atmel-mci-regs.h content in atmel-mci.c
atmel-mci-regs.h is only included in atmel-mci.c so move its content in the driver and do some cleanup in these definitions to remove checkpatch errors. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat
-rw-r--r--drivers/mmc/host/atmel-mci-regs.h171
-rw-r--r--drivers/mmc/host/atmel-mci.c150
2 files changed, 149 insertions, 172 deletions
diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
deleted file mode 100644
index 0aa44e679df4..000000000000
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
13 * Registers and bitfields marked with [2] are only available in MCI2
14 */
15
16#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
17#define __DRIVERS_MMC_ATMEL_MCI_H__
18
19/* MCI Register Definitions */
20#define ATMCI_CR 0x0000 /* Control */
21# define ATMCI_CR_MCIEN ( 1 << 0) /* MCI Enable */
22# define ATMCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */
23# define ATMCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */
24# define ATMCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */
25# define ATMCI_CR_SWRST ( 1 << 7) /* Software Reset */
26#define ATMCI_MR 0x0004 /* Mode */
27# define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
28# define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
29# define ATMCI_MR_RDPROOF ( 1 << 11) /* Read Proof */
30# define ATMCI_MR_WRPROOF ( 1 << 12) /* Write Proof */
31# define ATMCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */
32# define ATMCI_MR_PDCPADV ( 1 << 14) /* Padding Value */
33# define ATMCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */
34# define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
35#define ATMCI_DTOR 0x0008 /* Data Timeout */
36# define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
37# define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
38#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
39# define ATMCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */
40# define ATMCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */
41# define ATMCI_SDCSEL_MASK ( 3 << 0)
42# define ATMCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */
43# define ATMCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */
44# define ATMCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */
45# define ATMCI_SDCBUS_MASK ( 3 << 6)
46#define ATMCI_ARGR 0x0010 /* Command Argument */
47#define ATMCI_CMDR 0x0014 /* Command */
48# define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
49# define ATMCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */
50# define ATMCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */
51# define ATMCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */
52# define ATMCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */
53# define ATMCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */
54# define ATMCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */
55# define ATMCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */
56# define ATMCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */
57# define ATMCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */
58# define ATMCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */
59# define ATMCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */
60# define ATMCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */
61# define ATMCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */
62# define ATMCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */
63# define ATMCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */
64# define ATMCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */
65# define ATMCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */
66# define ATMCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */
67# define ATMCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */
68# define ATMCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */
69# define ATMCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */
70#define ATMCI_BLKR 0x0018 /* Block */
71# define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
72# define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
73#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
74# define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
75# define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
76#define ATMCI_RSPR 0x0020 /* Response 0 */
77#define ATMCI_RSPR1 0x0024 /* Response 1 */
78#define ATMCI_RSPR2 0x0028 /* Response 2 */
79#define ATMCI_RSPR3 0x002c /* Response 3 */
80#define ATMCI_RDR 0x0030 /* Receive Data */
81#define ATMCI_TDR 0x0034 /* Transmit Data */
82#define ATMCI_SR 0x0040 /* Status */
83#define ATMCI_IER 0x0044 /* Interrupt Enable */
84#define ATMCI_IDR 0x0048 /* Interrupt Disable */
85#define ATMCI_IMR 0x004c /* Interrupt Mask */
86# define ATMCI_CMDRDY ( 1 << 0) /* Command Ready */
87# define ATMCI_RXRDY ( 1 << 1) /* Receiver Ready */
88# define ATMCI_TXRDY ( 1 << 2) /* Transmitter Ready */
89# define ATMCI_BLKE ( 1 << 3) /* Data Block Ended */
90# define ATMCI_DTIP ( 1 << 4) /* Data Transfer In Progress */
91# define ATMCI_NOTBUSY ( 1 << 5) /* Data Not Busy */
92# define ATMCI_ENDRX ( 1 << 6) /* End of RX Buffer */
93# define ATMCI_ENDTX ( 1 << 7) /* End of TX Buffer */
94# define ATMCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */
95# define ATMCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */
96# define ATMCI_SDIOWAIT ( 1 << 12) /* SDIO Read Wait Operation Status */
97# define ATMCI_CSRCV ( 1 << 13) /* CE-ATA Completion Signal Received */
98# define ATMCI_RXBUFF ( 1 << 14) /* RX Buffer Full */
99# define ATMCI_TXBUFE ( 1 << 15) /* TX Buffer Empty */
100# define ATMCI_RINDE ( 1 << 16) /* Response Index Error */
101# define ATMCI_RDIRE ( 1 << 17) /* Response Direction Error */
102# define ATMCI_RCRCE ( 1 << 18) /* Response CRC Error */
103# define ATMCI_RENDE ( 1 << 19) /* Response End Bit Error */
104# define ATMCI_RTOE ( 1 << 20) /* Response Time-Out Error */
105# define ATMCI_DCRCE ( 1 << 21) /* Data CRC Error */
106# define ATMCI_DTOE ( 1 << 22) /* Data Time-Out Error */
107# define ATMCI_CSTOE ( 1 << 23) /* Completion Signal Time-out Error */
108# define ATMCI_BLKOVRE ( 1 << 24) /* DMA Block Overrun Error */
109# define ATMCI_DMADONE ( 1 << 25) /* DMA Transfer Done */
110# define ATMCI_FIFOEMPTY ( 1 << 26) /* FIFO Empty Flag */
111# define ATMCI_XFRDONE ( 1 << 27) /* Transfer Done Flag */
112# define ATMCI_ACKRCV ( 1 << 28) /* Boot Operation Acknowledge Received */
113# define ATMCI_ACKRCVE ( 1 << 29) /* Boot Operation Acknowledge Error */
114# define ATMCI_OVRE ( 1 << 30) /* RX Overrun Error */
115# define ATMCI_UNRE ( 1 << 31) /* TX Underrun Error */
116#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
117# define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
118# define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
119# define ATMCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */
120#define ATMCI_CFG 0x0054 /* Configuration[2] */
121# define ATMCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */
122# define ATMCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */
123# define ATMCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */
124# define ATMCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */
125#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
126# define ATMCI_WP_EN ( 1 << 0) /* WP Enable */
127# define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
128#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
129# define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
130# define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
131#define ATMCI_VERSION 0x00FC /* Version */
132#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
133
134/* This is not including the FIFO Aperture on MCI2 */
135#define ATMCI_REGS_SIZE 0x100
136
137/* Register access macros */
138#ifdef CONFIG_AVR32
139#define atmci_readl(port, reg) \
140 __raw_readl((port)->regs + reg)
141#define atmci_writel(port, reg, value) \
142 __raw_writel((value), (port)->regs + reg)
143#else
144#define atmci_readl(port, reg) \
145 readl_relaxed((port)->regs + reg)
146#define atmci_writel(port, reg, value) \
147 writel_relaxed((value), (port)->regs + reg)
148#endif
149
150/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
151#ifdef CONFIG_AVR32
152# define ATMCI_PDC_CONNECTED 0
153#else
154# define ATMCI_PDC_CONNECTED 1
155#endif
156
157/*
158 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
159 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
160 *
161 * This can be done by finding most significant bit set.
162 */
163static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
164{
165 if (maxburst > 1)
166 return fls(maxburst) - 2;
167 else
168 return 0;
169}
170
171#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index bf62e429f7fc..9f3bb611000f 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -44,7 +44,155 @@
44#include <asm/io.h> 44#include <asm/io.h>
45#include <asm/unaligned.h> 45#include <asm/unaligned.h>
46 46
47#include "atmel-mci-regs.h" 47/*
48 * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
49 * Registers and bitfields marked with [2] are only available in MCI2
50 */
51
52/* MCI Register Definitions */
53#define ATMCI_CR 0x0000 /* Control */
54#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
55#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
56#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
57#define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
58#define ATMCI_CR_SWRST BIT(7) /* Software Reset */
59#define ATMCI_MR 0x0004 /* Mode */
60#define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
61#define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
62#define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
63#define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
64#define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
65#define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
66#define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
67#define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
68#define ATMCI_DTOR 0x0008 /* Data Timeout */
69#define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
70#define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
71#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
72#define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
73#define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
74#define ATMCI_SDCSEL_MASK (3 << 0)
75#define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
76#define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
77#define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
78#define ATMCI_SDCBUS_MASK (3 << 6)
79#define ATMCI_ARGR 0x0010 /* Command Argument */
80#define ATMCI_CMDR 0x0014 /* Command */
81#define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
82#define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
83#define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
84#define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
85#define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
86#define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
87#define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
88#define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
89#define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
90#define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
91#define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
92#define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
93#define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
94#define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
95#define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
96#define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
97#define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
98#define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
99#define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
100#define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
101#define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
102#define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
103#define ATMCI_BLKR 0x0018 /* Block */
104#define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
105#define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
106#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
107#define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
108#define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
109#define ATMCI_RSPR 0x0020 /* Response 0 */
110#define ATMCI_RSPR1 0x0024 /* Response 1 */
111#define ATMCI_RSPR2 0x0028 /* Response 2 */
112#define ATMCI_RSPR3 0x002c /* Response 3 */
113#define ATMCI_RDR 0x0030 /* Receive Data */
114#define ATMCI_TDR 0x0034 /* Transmit Data */
115#define ATMCI_SR 0x0040 /* Status */
116#define ATMCI_IER 0x0044 /* Interrupt Enable */
117#define ATMCI_IDR 0x0048 /* Interrupt Disable */
118#define ATMCI_IMR 0x004c /* Interrupt Mask */
119#define ATMCI_CMDRDY BIT(0) /* Command Ready */
120#define ATMCI_RXRDY BIT(1) /* Receiver Ready */
121#define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
122#define ATMCI_BLKE BIT(3) /* Data Block Ended */
123#define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
124#define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
125#define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
126#define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
127#define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
128#define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
129#define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
130#define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
131#define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
132#define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
133#define ATMCI_RINDE BIT(16) /* Response Index Error */
134#define ATMCI_RDIRE BIT(17) /* Response Direction Error */
135#define ATMCI_RCRCE BIT(18) /* Response CRC Error */
136#define ATMCI_RENDE BIT(19) /* Response End Bit Error */
137#define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
138#define ATMCI_DCRCE BIT(21) /* Data CRC Error */
139#define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
140#define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
141#define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
142#define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
143#define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
144#define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
145#define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
146#define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
147#define ATMCI_OVRE BIT(30) /* RX Overrun Error */
148#define ATMCI_UNRE BIT(31) /* TX Underrun Error */
149#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
150#define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
151#define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
152#define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
153#define ATMCI_CFG 0x0054 /* Configuration[2] */
154#define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
155#define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
156#define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
157#define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
158#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
159#define ATMCI_WP_EN BIT(0) /* WP Enable */
160#define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
161#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
162#define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
163#define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
164#define ATMCI_VERSION 0x00FC /* Version */
165#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
166
167/* This is not including the FIFO Aperture on MCI2 */
168#define ATMCI_REGS_SIZE 0x100
169
170/* Register access macros */
171#define atmci_readl(port, reg) \
172 __raw_readl((port)->regs + reg)
173#define atmci_writel(port, reg, value) \
174 __raw_writel((value), (port)->regs + reg)
175
176/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
177#ifdef CONFIG_AVR32
178# define ATMCI_PDC_CONNECTED 0
179#else
180# define ATMCI_PDC_CONNECTED 1
181#endif
182
183/*
184 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
185 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
186 *
187 * This can be done by finding most significant bit set.
188 */
189static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
190{
191 if (maxburst > 1)
192 return fls(maxburst) - 2;
193 else
194 return 0;
195}
48 196
49#define AUTOSUSPEND_DELAY 50 197#define AUTOSUSPEND_DELAY 50
50 198
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 09:31:17 -0500