diff options
author | Steve Capper <steve.capper@arm.com> | 2018-01-24 03:27:08 -0500 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-01-26 13:23:17 -0500 |
commit | ec89ab50a03a33a4a648869e868b1964354fb2d1 (patch) | |
tree | fca3a39f0042db178584d91eef67f046abe3c2ab | |
parent | 0ba2e29c7fc1d58a90fab614d41bf487e28e3840 (diff) |
arm64: Fix TTBR + PAN + 52-bit PA logic in cpu_do_switch_mm
In cpu_do_switch_mm(.) with ARM64_SW_TTBR0_PAN=y we apply phys_to_ttbr
to a value that already has an ASID inserted into the upper bits. For
52-bit PA configurations this then can give us TTBR0_EL1 registers that
cause translation table walks to attempt to access non-zero PA[51:48]
spuriously. Ultimately leading to a Synchronous External Abort on level
1 translation.
This patch re-arranges the logic in cpu_do_switch_mm(.) such that
phys_to_ttbr is called before the ASID is inserted into the TTBR0 value.
Fixes: 6b88a32c7af6 ("arm64: kpti: Fix the interaction between ASID switching and software PAN")
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-rw-r--r-- | arch/arm64/mm/proc.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index c6a12073ef46..9f177aac6390 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S | |||
@@ -153,14 +153,14 @@ ENDPROC(cpu_do_resume) | |||
153 | ENTRY(cpu_do_switch_mm) | 153 | ENTRY(cpu_do_switch_mm) |
154 | mrs x2, ttbr1_el1 | 154 | mrs x2, ttbr1_el1 |
155 | mmid x1, x1 // get mm->context.id | 155 | mmid x1, x1 // get mm->context.id |
156 | phys_to_ttbr x0, x3 | ||
156 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN | 157 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
157 | bfi x0, x1, #48, #16 // set the ASID field in TTBR0 | 158 | bfi x3, x1, #48, #16 // set the ASID field in TTBR0 |
158 | #endif | 159 | #endif |
159 | bfi x2, x1, #48, #16 // set the ASID | 160 | bfi x2, x1, #48, #16 // set the ASID |
160 | msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) | 161 | msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set) |
161 | isb | 162 | isb |
162 | phys_to_ttbr x0, x2 | 163 | msr ttbr0_el1, x3 // now update TTBR0 |
163 | msr ttbr0_el1, x2 // now update TTBR0 | ||
164 | isb | 164 | isb |
165 | b post_ttbr_update_workaround // Back to C code... | 165 | b post_ttbr_update_workaround // Back to C code... |
166 | ENDPROC(cpu_do_switch_mm) | 166 | ENDPROC(cpu_do_switch_mm) |