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authorIcenowy Zheng <icenowy@aosc.xyz>2017-04-04 05:51:00 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-04-04 11:45:09 -0400
commitec4279053a6434f685246e022be95d2a62f8c608 (patch)
treeaed18d491293c3717a1f04e211e13acc4b1e10ff
parent791a9e001d3ba3b552888b0bf3c592a50b71f57e (diff)
arm64: allwinner: a64: add R_PIO pinctrl node
Allwinner A64 have a dedicated pin controller to manage the PL pin bank. As the driver and the required clock support are added, add the device node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1d4e5bcced0c..6bc606b4d74d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -409,5 +409,17 @@
409 #clock-cells = <1>; 409 #clock-cells = <1>;
410 #reset-cells = <1>; 410 #reset-cells = <1>;
411 }; 411 };
412
413 r_pio: pinctrl@01f02c00 {
414 compatible = "allwinner,sun50i-a64-r-pinctrl";
415 reg = <0x01f02c00 0x400>;
416 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
418 clock-names = "apb", "hosc", "losc";
419 gpio-controller;
420 #gpio-cells = <3>;
421 interrupt-controller;
422 #interrupt-cells = <3>;
423 };
412 }; 424 };
413}; 425};