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authorWill Deacon <will.deacon@arm.com>2019-04-30 11:58:56 -0400
committerWill Deacon <will.deacon@arm.com>2019-05-01 09:48:06 -0400
commiteb337cdfcd5dd3b10522c2f34140a73a4c285c30 (patch)
tree6d180cde9a9dfc0e388063bca1b9da78dc7b6c7b
parent61ae1321f06c4489c724c803e9b8363dea576da3 (diff)
arm64: ssbs: Don't treat CPUs with SSBS as unaffected by SSB
SSBS provides a relatively cheap mitigation for SSB, but it is still a mitigation and its presence does not indicate that the CPU is unaffected by the vulnerability. Tweak the mitigation logic so that we report the correct string in sysfs. Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--arch/arm64/kernel/cpu_errata.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 4bb0f7cad418..44ef98be001e 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -386,15 +386,17 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
386 386
387 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 387 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
388 388
389 /* delay setting __ssb_safe until we get a firmware response */
390 if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list))
391 this_cpu_safe = true;
392
389 if (this_cpu_has_cap(ARM64_SSBS)) { 393 if (this_cpu_has_cap(ARM64_SSBS)) {
394 if (!this_cpu_safe)
395 __ssb_safe = false;
390 required = false; 396 required = false;
391 goto out_printmsg; 397 goto out_printmsg;
392 } 398 }
393 399
394 /* delay setting __ssb_safe until we get a firmware response */
395 if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list))
396 this_cpu_safe = true;
397
398 if (psci_ops.smccc_version == SMCCC_VERSION_1_0) { 400 if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
399 ssbd_state = ARM64_SSBD_UNKNOWN; 401 ssbd_state = ARM64_SSBD_UNKNOWN;
400 if (!this_cpu_safe) 402 if (!this_cpu_safe)