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authorEmil Medve <Emilian.Medve@freescale.com>2014-11-06 10:48:11 -0500
committerScott Wood <scottwood@freescale.com>2014-11-07 19:10:49 -0500
commiteaffcb0f1bebbcfd38ecc9bdca105f7123115ab1 (patch)
tree8e22a3d46426eb5b601e74a72bc16f0c55691bc0
parent94701fcb2f085cef29b29051f21de7fc3718217a (diff)
powerpc/dts: Factorize the clock control node
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1 Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/b4860emu.dts4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-post.dtsi28
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi28
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi48
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi48
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi48
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi48
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi48
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi78
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi61
-rw-r--r--arch/powerpc/boot/dts/fsl/t1040si-post.dtsi30
-rw-r--r--arch/powerpc/boot/dts/fsl/t2081si-post.dtsi29
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi29
-rw-r--r--arch/powerpc/boot/dts/t4240emu.dts4
14 files changed, 163 insertions, 368 deletions
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
index 85646b4f96e1..2aa5cd318ce8 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -193,9 +193,9 @@
193 fsl,liodn-bits = <12>; 193 fsl,liodn-bits = <12>;
194 }; 194 };
195 195
196 clockgen: global-utilities@e1000 { 196/include/ "fsl/qoriq-clockgen2.dtsi"
197 global-utilities@e1000 {
197 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0"; 198 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
198 reg = <0xe1000 0x1000>;
199 }; 199 };
200 200
201/include/ "fsl/qoriq-dma-0.dtsi" 201/include/ "fsl/qoriq-dma-0.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index d67894459ac8..86161ae6c966 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -80,33 +80,9 @@
80 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0"; 80 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
81 }; 81 };
82 82
83 clockgen: global-utilities@e1000 { 83/include/ "qoriq-clockgen2.dtsi"
84 global-utilities@e1000 {
84 compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0"; 85 compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
85 ranges = <0x0 0xe1000 0x1000>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88
89 sysclk: sysclk {
90 #clock-cells = <0>;
91 compatible = "fsl,qoriq-sysclk-2.0";
92 clock-output-names = "sysclk";
93 };
94
95 pll0: pll0@800 {
96 #clock-cells = <1>;
97 reg = <0x800 0x4>;
98 compatible = "fsl,qoriq-core-pll-2.0";
99 clocks = <&sysclk>;
100 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
101 };
102
103 pll1: pll1@820 {
104 #clock-cells = <1>;
105 reg = <0x820 0x4>;
106 compatible = "fsl,qoriq-core-pll-2.0";
107 clocks = <&sysclk>;
108 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
109 };
110 86
111 mux0: mux0@0 { 87 mux0: mux0@0 {
112 #clock-cells = <0>; 88 #clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 582381dba1d7..65100b9636b7 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -124,33 +124,9 @@
124 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0"; 124 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
125 }; 125 };
126 126
127 clockgen: global-utilities@e1000 { 127/include/ "qoriq-clockgen2.dtsi"
128 global-utilities@e1000 {
128 compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0"; 129 compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
129 ranges = <0x0 0xe1000 0x1000>;
130 #address-cells = <1>;
131 #size-cells = <1>;
132
133 sysclk: sysclk {
134 #clock-cells = <0>;
135 compatible = "fsl,qoriq-sysclk-2.0";
136 clock-output-names = "sysclk";
137 };
138
139 pll0: pll0@800 {
140 #clock-cells = <1>;
141 reg = <0x800 0x4>;
142 compatible = "fsl,qoriq-core-pll-2.0";
143 clocks = <&sysclk>;
144 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
145 };
146
147 pll1: pll1@820 {
148 #clock-cells = <1>;
149 reg = <0x820 0x4>;
150 compatible = "fsl,qoriq-core-pll-2.0";
151 clocks = <&sysclk>;
152 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
153 };
154 130
155 mux0: mux0@0 { 131 mux0: mux0@0 {
156 #clock-cells = <0>; 132 #clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 69ce1026c948..efd74db4f9b0 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -305,53 +305,9 @@
305 #sleep-cells = <2>; 305 #sleep-cells = <2>;
306 }; 306 };
307 307
308 clockgen: global-utilities@e1000 { 308/include/ "qoriq-clockgen1.dtsi"
309 global-utilities@e1000 {
309 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; 310 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
310 ranges = <0x0 0xe1000 0x1000>;
311 reg = <0xe1000 0x1000>;
312 clock-frequency = <0>;
313 #address-cells = <1>;
314 #size-cells = <1>;
315
316 sysclk: sysclk {
317 #clock-cells = <0>;
318 compatible = "fsl,qoriq-sysclk-1.0";
319 clock-output-names = "sysclk";
320 };
321
322 pll0: pll0@800 {
323 #clock-cells = <1>;
324 reg = <0x800 0x4>;
325 compatible = "fsl,qoriq-core-pll-1.0";
326 clocks = <&sysclk>;
327 clock-output-names = "pll0", "pll0-div2";
328 };
329
330 pll1: pll1@820 {
331 #clock-cells = <1>;
332 reg = <0x820 0x4>;
333 compatible = "fsl,qoriq-core-pll-1.0";
334 clocks = <&sysclk>;
335 clock-output-names = "pll1", "pll1-div2";
336 };
337
338 mux0: mux0@0 {
339 #clock-cells = <0>;
340 reg = <0x0 0x4>;
341 compatible = "fsl,qoriq-core-mux-1.0";
342 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
343 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clock-output-names = "cmux0";
345 };
346
347 mux1: mux1@20 {
348 #clock-cells = <0>;
349 reg = <0x20 0x4>;
350 compatible = "fsl,qoriq-core-mux-1.0";
351 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
352 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
353 clock-output-names = "cmux1";
354 };
355 311
356 mux2: mux2@40 { 312 mux2: mux2@40 {
357 #clock-cells = <0>; 313 #clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index cd63cb1b1042..d7425ef1ae41 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -332,53 +332,9 @@
332 #sleep-cells = <2>; 332 #sleep-cells = <2>;
333 }; 333 };
334 334
335 clockgen: global-utilities@e1000 { 335/include/ "qoriq-clockgen1.dtsi"
336 global-utilities@e1000 {
336 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; 337 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
337 ranges = <0x0 0xe1000 0x1000>;
338 reg = <0xe1000 0x1000>;
339 clock-frequency = <0>;
340 #address-cells = <1>;
341 #size-cells = <1>;
342
343 sysclk: sysclk {
344 #clock-cells = <0>;
345 compatible = "fsl,qoriq-sysclk-1.0";
346 clock-output-names = "sysclk";
347 };
348
349 pll0: pll0@800 {
350 #clock-cells = <1>;
351 reg = <0x800 0x4>;
352 compatible = "fsl,qoriq-core-pll-1.0";
353 clocks = <&sysclk>;
354 clock-output-names = "pll0", "pll0-div2";
355 };
356
357 pll1: pll1@820 {
358 #clock-cells = <1>;
359 reg = <0x820 0x4>;
360 compatible = "fsl,qoriq-core-pll-1.0";
361 clocks = <&sysclk>;
362 clock-output-names = "pll1", "pll1-div2";
363 };
364
365 mux0: mux0@0 {
366 #clock-cells = <0>;
367 reg = <0x0 0x4>;
368 compatible = "fsl,qoriq-core-mux-1.0";
369 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
370 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
371 clock-output-names = "cmux0";
372 };
373
374 mux1: mux1@20 {
375 #clock-cells = <0>;
376 reg = <0x20 0x4>;
377 compatible = "fsl,qoriq-core-mux-1.0";
378 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
379 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
380 clock-output-names = "cmux1";
381 };
382 338
383 mux2: mux2@40 { 339 mux2: mux2@40 {
384 #clock-cells = <0>; 340 #clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 12947ccddf25..7005a4a4cef0 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -352,35 +352,9 @@
352 #sleep-cells = <2>; 352 #sleep-cells = <2>;
353 }; 353 };
354 354
355 clockgen: global-utilities@e1000 { 355/include/ "qoriq-clockgen1.dtsi"
356 global-utilities@e1000 {
356 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; 357 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
357 ranges = <0x0 0xe1000 0x1000>;
358 reg = <0xe1000 0x1000>;
359 clock-frequency = <0>;
360 #address-cells = <1>;
361 #size-cells = <1>;
362
363 sysclk: sysclk {
364 #clock-cells = <0>;
365 compatible = "fsl,qoriq-sysclk-1.0";
366 clock-output-names = "sysclk";
367 };
368
369 pll0: pll0@800 {
370 #clock-cells = <1>;
371 reg = <0x800 0x4>;
372 compatible = "fsl,qoriq-core-pll-1.0";
373 clocks = <&sysclk>;
374 clock-output-names = "pll0", "pll0-div2";
375 };
376
377 pll1: pll1@820 {
378 #clock-cells = <1>;
379 reg = <0x820 0x4>;
380 compatible = "fsl,qoriq-core-pll-1.0";
381 clocks = <&sysclk>;
382 clock-output-names = "pll1", "pll1-div2";
383 };
384 358
385 pll2: pll2@840 { 359 pll2: pll2@840 {
386 #clock-cells = <1>; 360 #clock-cells = <1>;
@@ -398,24 +372,6 @@
398 clock-output-names = "pll3", "pll3-div2"; 372 clock-output-names = "pll3", "pll3-div2";
399 }; 373 };
400 374
401 mux0: mux0@0 {
402 #clock-cells = <0>;
403 reg = <0x0 0x4>;
404 compatible = "fsl,qoriq-core-mux-1.0";
405 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
406 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
407 clock-output-names = "cmux0";
408 };
409
410 mux1: mux1@20 {
411 #clock-cells = <0>;
412 reg = <0x20 0x4>;
413 compatible = "fsl,qoriq-core-mux-1.0";
414 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
415 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
416 clock-output-names = "cmux1";
417 };
418
419 mux2: mux2@40 { 375 mux2: mux2@40 {
420 #clock-cells = <0>; 376 #clock-cells = <0>;
421 reg = <0x40 0x4>; 377 reg = <0x40 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 4c4a2b0436b2..55834211bd28 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -337,53 +337,9 @@
337 #sleep-cells = <2>; 337 #sleep-cells = <2>;
338 }; 338 };
339 339
340 clockgen: global-utilities@e1000 { 340/include/ "qoriq-clockgen1.dtsi"
341 global-utilities@e1000 {
341 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 342 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
342 ranges = <0x0 0xe1000 0x1000>;
343 reg = <0xe1000 0x1000>;
344 clock-frequency = <0>;
345 #address-cells = <1>;
346 #size-cells = <1>;
347
348 sysclk: sysclk {
349 #clock-cells = <0>;
350 compatible = "fsl,qoriq-sysclk-1.0";
351 clock-output-names = "sysclk";
352 };
353
354 pll0: pll0@800 {
355 #clock-cells = <1>;
356 reg = <0x800 0x4>;
357 compatible = "fsl,qoriq-core-pll-1.0";
358 clocks = <&sysclk>;
359 clock-output-names = "pll0", "pll0-div2";
360 };
361
362 pll1: pll1@820 {
363 #clock-cells = <1>;
364 reg = <0x820 0x4>;
365 compatible = "fsl,qoriq-core-pll-1.0";
366 clocks = <&sysclk>;
367 clock-output-names = "pll1", "pll1-div2";
368 };
369
370 mux0: mux0@0 {
371 #clock-cells = <0>;
372 reg = <0x0 0x4>;
373 compatible = "fsl,qoriq-core-mux-1.0";
374 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
375 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
376 clock-output-names = "cmux0";
377 };
378
379 mux1: mux1@20 {
380 #clock-cells = <0>;
381 reg = <0x20 0x4>;
382 compatible = "fsl,qoriq-core-mux-1.0";
383 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
384 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
385 clock-output-names = "cmux1";
386 };
387 }; 343 };
388 344
389 rcpm: global-utilities@e2000 { 345 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 67296fdd9698..6e4cd6ce363c 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -297,53 +297,9 @@
297 #sleep-cells = <2>; 297 #sleep-cells = <2>;
298 }; 298 };
299 299
300 clockgen: global-utilities@e1000 { 300/include/ "qoriq-clockgen1.dtsi"
301 global-utilities@e1000 {
301 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; 302 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
302 ranges = <0x0 0xe1000 0x1000>;
303 reg = <0xe1000 0x1000>;
304 clock-frequency = <0>;
305 #address-cells = <1>;
306 #size-cells = <1>;
307
308 sysclk: sysclk {
309 #clock-cells = <0>;
310 compatible = "fsl,qoriq-sysclk-1.0";
311 clock-output-names = "sysclk";
312 };
313
314 pll0: pll0@800 {
315 #clock-cells = <1>;
316 reg = <0x800 0x4>;
317 compatible = "fsl,qoriq-core-pll-1.0";
318 clocks = <&sysclk>;
319 clock-output-names = "pll0", "pll0-div2";
320 };
321
322 pll1: pll1@820 {
323 #clock-cells = <1>;
324 reg = <0x820 0x4>;
325 compatible = "fsl,qoriq-core-pll-1.0";
326 clocks = <&sysclk>;
327 clock-output-names = "pll1", "pll1-div2";
328 };
329
330 mux0: mux0@0 {
331 #clock-cells = <0>;
332 reg = <0x0 0x4>;
333 compatible = "fsl,qoriq-core-mux-1.0";
334 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
335 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clock-output-names = "cmux0";
337 };
338
339 mux1: mux1@20 {
340 #clock-cells = <0>;
341 reg = <0x20 0x4>;
342 compatible = "fsl,qoriq-core-mux-1.0";
343 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
344 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
345 clock-output-names = "cmux1";
346 };
347 303
348 mux2: mux2@40 { 304 mux2: mux2@40 {
349 #clock-cells = <0>; 305 #clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
new file mode 100644
index 000000000000..48710482806e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
@@ -0,0 +1,78 @@
1/*
2 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35global-utilities@e1000 {
36 compatible = "fsl,qoriq-clockgen-1.0";
37 ranges = <0x0 0xe1000 0x1000>;
38 reg = <0xe1000 0x1000>;
39 clock-frequency = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42
43 sysclk: sysclk {
44 #clock-cells = <0>;
45 compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
46 clock-output-names = "sysclk";
47 };
48 pll0: pll0@800 {
49 #clock-cells = <1>;
50 reg = <0x800 0x4>;
51 compatible = "fsl,qoriq-core-pll-1.0";
52 clocks = <&sysclk>;
53 clock-output-names = "pll0", "pll0-div2";
54 };
55 pll1: pll1@820 {
56 #clock-cells = <1>;
57 reg = <0x820 0x4>;
58 compatible = "fsl,qoriq-core-pll-1.0";
59 clocks = <&sysclk>;
60 clock-output-names = "pll1", "pll1-div2";
61 };
62 mux0: mux0@0 {
63 #clock-cells = <0>;
64 reg = <0x0 0x4>;
65 compatible = "fsl,qoriq-core-mux-1.0";
66 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
67 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
68 clock-output-names = "cmux0";
69 };
70 mux1: mux1@20 {
71 #clock-cells = <0>;
72 reg = <0x20 0x4>;
73 compatible = "fsl,qoriq-core-mux-1.0";
74 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
75 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
76 clock-output-names = "cmux1";
77 };
78};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
new file mode 100644
index 000000000000..5d18d2a6cf52
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
@@ -0,0 +1,61 @@
1/*
2 * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35global-utilities@e1000 {
36 compatible = "fsl,qoriq-clockgen-2.0";
37 ranges = <0x0 0xe1000 0x1000>;
38 reg = <0xe1000 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41
42 sysclk: sysclk {
43 #clock-cells = <0>;
44 compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
45 clock-output-names = "sysclk";
46 };
47 pll0: pll0@800 {
48 #clock-cells = <1>;
49 reg = <0x800 0x4>;
50 compatible = "fsl,qoriq-core-pll-2.0";
51 clocks = <&sysclk>;
52 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
53 };
54 pll1: pll1@820 {
55 #clock-cells = <1>;
56 reg = <0x820 0x4>;
57 compatible = "fsl,qoriq-core-pll-2.0";
58 clocks = <&sysclk>;
59 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
60 };
61};
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 12e597eea3c8..15ae462e758f 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -281,35 +281,9 @@
281 fsl,liodn-bits = <12>; 281 fsl,liodn-bits = <12>;
282 }; 282 };
283 283
284 clockgen: global-utilities@e1000 { 284/include/ "qoriq-clockgen2.dtsi"
285 global-utilities@e1000 {
285 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; 286 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
286 ranges = <0x0 0xe1000 0x1000>;
287 reg = <0xe1000 0x1000>;
288 #address-cells = <1>;
289 #size-cells = <1>;
290
291 sysclk: sysclk {
292 #clock-cells = <0>;
293 compatible = "fsl,qoriq-sysclk-2.0";
294 clock-output-names = "sysclk", "fixed-clock";
295 };
296
297
298 pll0: pll0@800 {
299 #clock-cells = <1>;
300 reg = <0x800 4>;
301 compatible = "fsl,qoriq-core-pll-2.0";
302 clocks = <&sysclk>;
303 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
304 };
305
306 pll1: pll1@820 {
307 #clock-cells = <1>;
308 reg = <0x820 4>;
309 compatible = "fsl,qoriq-core-pll-2.0";
310 clocks = <&sysclk>;
311 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
312 };
313 287
314 mux0: mux0@0 { 288 mux0: mux0@0 {
315 #clock-cells = <0>; 289 #clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index aecee9690a88..1ce91e3485a9 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -305,34 +305,9 @@
305 fsl,liodn-bits = <12>; 305 fsl,liodn-bits = <12>;
306 }; 306 };
307 307
308 clockgen: global-utilities@e1000 { 308/include/ "qoriq-clockgen2.dtsi"
309 global-utilities@e1000 {
309 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0"; 310 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
310 ranges = <0x0 0xe1000 0x1000>;
311 reg = <0xe1000 0x1000>;
312 #address-cells = <1>;
313 #size-cells = <1>;
314
315 sysclk: sysclk {
316 #clock-cells = <0>;
317 compatible = "fsl,qoriq-sysclk-2.0";
318 clock-output-names = "sysclk", "fixed-clock";
319 };
320
321 pll0: pll0@800 {
322 #clock-cells = <1>;
323 reg = <0x800 4>;
324 compatible = "fsl,qoriq-core-pll-2.0";
325 clocks = <&sysclk>;
326 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
327 };
328
329 pll1: pll1@820 {
330 #clock-cells = <1>;
331 reg = <0x820 4>;
332 compatible = "fsl,qoriq-core-pll-2.0";
333 clocks = <&sysclk>;
334 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
335 };
336 311
337 mux0: mux0@0 { 312 mux0: mux0@0 {
338 #clock-cells = <0>; 313 #clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 7e2fc7cdce48..0e96fcabe812 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -368,34 +368,9 @@
368 fsl,liodn-bits = <12>; 368 fsl,liodn-bits = <12>;
369 }; 369 };
370 370
371 clockgen: global-utilities@e1000 { 371/include/ "qoriq-clockgen2.dtsi"
372 global-utilities@e1000 {
372 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; 373 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
373 ranges = <0x0 0xe1000 0x1000>;
374 reg = <0xe1000 0x1000>;
375 #address-cells = <1>;
376 #size-cells = <1>;
377
378 sysclk: sysclk {
379 #clock-cells = <0>;
380 compatible = "fsl,qoriq-sysclk-2.0";
381 clock-output-names = "sysclk";
382 };
383
384 pll0: pll0@800 {
385 #clock-cells = <1>;
386 reg = <0x800 0x4>;
387 compatible = "fsl,qoriq-core-pll-2.0";
388 clocks = <&sysclk>;
389 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
390 };
391
392 pll1: pll1@820 {
393 #clock-cells = <1>;
394 reg = <0x820 0x4>;
395 compatible = "fsl,qoriq-core-pll-2.0";
396 clocks = <&sysclk>;
397 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
398 };
399 374
400 pll2: pll2@840 { 375 pll2: pll2@840 {
401 #clock-cells = <1>; 376 #clock-cells = <1>;
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
index bc12127a03fb..decaf357db9c 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -250,9 +250,9 @@
250 fsl,liodn-bits = <12>; 250 fsl,liodn-bits = <12>;
251 }; 251 };
252 252
253 clockgen: global-utilities@e1000 { 253/include/ "fsl/qoriq-clockgen2.dtsi"
254 global-utilities@e1000 {
254 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; 255 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
255 reg = <0xe1000 0x1000>;
256 }; 256 };
257 257
258/include/ "fsl/qoriq-dma-0.dtsi" 258/include/ "fsl/qoriq-dma-0.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-16 04:34:22 -0400