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authorMichael Turquette <mturquette@baylibre.com>2015-12-22 13:12:42 -0500
committerMichael Turquette <mturquette@baylibre.com>2015-12-22 14:57:33 -0500
commiteaaa6fb53f2652760c1c512534fe3e71672a7d78 (patch)
tree7d132f3caec6b261f1d86df212962eaabcf59874
parentd90e149666258bc84e14c1c31c2064a345220cd7 (diff)
parentdfff24bde7fb8d57482e907d5dfb0be3a9e28119 (diff)
Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Rockchip clock changes for 4.5 containing - a new pll-type used on rk3036 and other Cortex-A7 socs - new clock-trees for rk3036 and rk3228 - switch rk3288 plls to slow mode on reboot - a bunch of new clock ids - some more critical clocks - wrong register offsets for the rk3368 cpuclks - allowing more than 2 parents for the cpuclk
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt56
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt58
-rw-r--r--drivers/clk/rockchip/Makefile2
-rw-r--r--drivers/clk/rockchip/clk-cpu.c4
-rw-r--r--drivers/clk/rockchip/clk-pll.c258
-rw-r--r--drivers/clk/rockchip/clk-rk3036.c478
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c2
-rw-r--r--drivers/clk/rockchip/clk-rk3228.c678
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c42
-rw-r--r--drivers/clk/rockchip/clk-rk3368.c13
-rw-r--r--drivers/clk/rockchip/clk.c7
-rw-r--r--drivers/clk/rockchip/clk.h43
-rw-r--r--include/dt-bindings/clock/rk3036-cru.h193
-rw-r--r--include/dt-bindings/clock/rk3228-cru.h220
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h4
15 files changed, 2025 insertions, 33 deletions
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
new file mode 100644
index 000000000000..ace05992a262
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
@@ -0,0 +1,56 @@
1* Rockchip RK3036 Clock and Reset Unit
2
3The RK3036 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: should be "rockchip,rk3036-cru"
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18 If missing pll rates are not changeable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "ext_gmac" - external GMAC clock - optional
34
35Example: Clock controller node:
36
37 cru: cru@20000000 {
38 compatible = "rockchip,rk3036-cru";
39 reg = <0x20000000 0x1000>;
40 rockchip,grf = <&grf>;
41
42 #clock-cells = <1>;
43 #reset-cells = <1>;
44 };
45
46Example: UART controller node that consumes the clock generated by the clock
47 controller:
48
49 uart0: serial@20060000 {
50 compatible = "snps,dw-apb-uart";
51 reg = <0x20060000 0x100>;
52 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
53 reg-shift = <2>;
54 reg-io-width = <4>;
55 clocks = <&cru SCLK_UART0>;
56 };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
new file mode 100644
index 000000000000..f323048127eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt
@@ -0,0 +1,58 @@
1* Rockchip RK3228 Clock and Reset Unit
2
3The RK3228 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: should be "rockchip,rk3228-cru"
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18 If missing pll rates are not changeable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "ext_gmac" - external GMAC clock - optional
34 - "ext_hsadc" - external HSADC clock - optional
35 - "phy_50m_out" - output clock of the pll in the mac phy
36
37Example: Clock controller node:
38
39 cru: cru@20000000 {
40 compatible = "rockchip,rk3228-cru";
41 reg = <0x20000000 0x1000>;
42 rockchip,grf = <&grf>;
43
44 #clock-cells = <1>;
45 #reset-cells = <1>;
46 };
47
48Example: UART controller node that consumes the clock generated by the clock
49 controller:
50
51 uart0: serial@10110000 {
52 compatible = "snps,dw-apb-uart";
53 reg = <0x10110000 0x100>;
54 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
55 reg-shift = <2>;
56 reg-io-width = <4>;
57 clocks = <&cru SCLK_UART0>;
58 };
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index b27edd6c8183..80b9a379beb4 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -10,6 +10,8 @@ obj-y += clk-inverter.o
10obj-y += clk-mmc-phase.o 10obj-y += clk-mmc-phase.o
11obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 11obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
12 12
13obj-y += clk-rk3036.o
13obj-y += clk-rk3188.o 14obj-y += clk-rk3188.o
15obj-y += clk-rk3228.o
14obj-y += clk-rk3288.o 16obj-y += clk-rk3288.o
15obj-y += clk-rk3368.o 17obj-y += clk-rk3368.o
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 330870a6d8bf..d07374f48caf 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -242,8 +242,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
242 struct clk *clk, *cclk; 242 struct clk *clk, *cclk;
243 int ret; 243 int ret;
244 244
245 if (num_parents != 2) { 245 if (num_parents < 2) {
246 pr_err("%s: needs two parent clocks\n", __func__); 246 pr_err("%s: needs at least two parent clocks\n", __func__);
247 return ERR_PTR(-EINVAL); 247 return ERR_PTR(-EINVAL);
248 } 248 }
249 249
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 4881eb8a1576..b7e66c9dd9f2 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -2,6 +2,9 @@
2 * Copyright (c) 2014 MundoReader S.L. 2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de> 3 * Author: Heiko Stuebner <heiko@sntech.de>
4 * 4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
5 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
@@ -19,6 +22,7 @@
19#include <linux/delay.h> 22#include <linux/delay.h>
20#include <linux/clk-provider.h> 23#include <linux/clk-provider.h>
21#include <linux/regmap.h> 24#include <linux/regmap.h>
25#include <linux/clk.h>
22#include "clk.h" 26#include "clk.h"
23 27
24#define PLL_MODE_MASK 0x3 28#define PLL_MODE_MASK 0x3
@@ -108,6 +112,252 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
108} 112}
109 113
110/** 114/**
115 * PLL used in RK3036
116 */
117
118#define RK3036_PLLCON(i) (i * 0x4)
119#define RK3036_PLLCON0_FBDIV_MASK 0xfff
120#define RK3036_PLLCON0_FBDIV_SHIFT 0
121#define RK3036_PLLCON0_POSTDIV1_MASK 0x7
122#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
123#define RK3036_PLLCON1_REFDIV_MASK 0x3f
124#define RK3036_PLLCON1_REFDIV_SHIFT 0
125#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
126#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
127#define RK3036_PLLCON1_DSMPD_MASK 0x1
128#define RK3036_PLLCON1_DSMPD_SHIFT 12
129#define RK3036_PLLCON2_FRAC_MASK 0xffffff
130#define RK3036_PLLCON2_FRAC_SHIFT 0
131
132#define RK3036_PLLCON1_PWRDOWN (1 << 13)
133
134static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
135 struct rockchip_pll_rate_table *rate)
136{
137 u32 pllcon;
138
139 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0));
140 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT)
141 & RK3036_PLLCON0_FBDIV_MASK);
142 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT)
143 & RK3036_PLLCON0_POSTDIV1_MASK);
144
145 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1));
146 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT)
147 & RK3036_PLLCON1_REFDIV_MASK);
148 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT)
149 & RK3036_PLLCON1_POSTDIV2_MASK);
150 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT)
151 & RK3036_PLLCON1_DSMPD_MASK);
152
153 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
154 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT)
155 & RK3036_PLLCON2_FRAC_MASK);
156}
157
158static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
159 unsigned long prate)
160{
161 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
162 struct rockchip_pll_rate_table cur;
163 u64 rate64 = prate;
164
165 rockchip_rk3036_pll_get_params(pll, &cur);
166
167 rate64 *= cur.fbdiv;
168 do_div(rate64, cur.refdiv);
169
170 if (cur.dsmpd == 0) {
171 /* fractional mode */
172 u64 frac_rate64 = prate * cur.frac;
173
174 do_div(frac_rate64, cur.refdiv);
175 rate64 += frac_rate64 >> 24;
176 }
177
178 do_div(rate64, cur.postdiv1);
179 do_div(rate64, cur.postdiv2);
180
181 return (unsigned long)rate64;
182}
183
184static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
185 const struct rockchip_pll_rate_table *rate)
186{
187 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
188 struct clk_mux *pll_mux = &pll->pll_mux;
189 struct rockchip_pll_rate_table cur;
190 u32 pllcon;
191 int rate_change_remuxed = 0;
192 int cur_parent;
193 int ret;
194
195 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
196 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv,
197 rate->postdiv2, rate->dsmpd, rate->frac);
198
199 rockchip_rk3036_pll_get_params(pll, &cur);
200 cur.rate = 0;
201
202 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
203 if (cur_parent == PLL_MODE_NORM) {
204 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
205 rate_change_remuxed = 1;
206 }
207
208 /* update pll values */
209 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
210 RK3036_PLLCON0_FBDIV_SHIFT) |
211 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK,
212 RK3036_PLLCON0_POSTDIV1_SHIFT),
213 pll->reg_base + RK3036_PLLCON(0));
214
215 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK,
216 RK3036_PLLCON1_REFDIV_SHIFT) |
217 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK,
218 RK3036_PLLCON1_POSTDIV2_SHIFT) |
219 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK,
220 RK3036_PLLCON1_DSMPD_SHIFT),
221 pll->reg_base + RK3036_PLLCON(1));
222
223 /* GPLL CON2 is not HIWORD_MASK */
224 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2));
225 pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT);
226 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
227 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
228
229 /* wait for the pll to lock */
230 ret = rockchip_pll_wait_lock(pll);
231 if (ret) {
232 pr_warn("%s: pll update unsucessful, trying to restore old params\n",
233 __func__);
234 rockchip_rk3036_pll_set_params(pll, &cur);
235 }
236
237 if (rate_change_remuxed)
238 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
239
240 return ret;
241}
242
243static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate,
244 unsigned long prate)
245{
246 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
247 const struct rockchip_pll_rate_table *rate;
248 unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate);
249 struct regmap *grf = rockchip_clk_get_grf();
250
251 if (IS_ERR(grf)) {
252 pr_debug("%s: grf regmap not available, aborting rate change\n",
253 __func__);
254 return PTR_ERR(grf);
255 }
256
257 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
258 __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
259
260 /* Get required rate settings from table */
261 rate = rockchip_get_pll_settings(pll, drate);
262 if (!rate) {
263 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
264 drate, __clk_get_name(hw->clk));
265 return -EINVAL;
266 }
267
268 return rockchip_rk3036_pll_set_params(pll, rate);
269}
270
271static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
272{
273 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
274
275 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
276 pll->reg_base + RK3036_PLLCON(1));
277
278 return 0;
279}
280
281static void rockchip_rk3036_pll_disable(struct clk_hw *hw)
282{
283 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
284
285 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
286 RK3036_PLLCON1_PWRDOWN, 0),
287 pll->reg_base + RK3036_PLLCON(1));
288}
289
290static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw)
291{
292 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
293 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1));
294
295 return !(pllcon & RK3036_PLLCON1_PWRDOWN);
296}
297
298static void rockchip_rk3036_pll_init(struct clk_hw *hw)
299{
300 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
301 const struct rockchip_pll_rate_table *rate;
302 struct rockchip_pll_rate_table cur;
303 unsigned long drate;
304
305 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
306 return;
307
308 drate = clk_hw_get_rate(hw);
309 rate = rockchip_get_pll_settings(pll, drate);
310
311 /* when no rate setting for the current rate, rely on clk_set_rate */
312 if (!rate)
313 return;
314
315 rockchip_rk3036_pll_get_params(pll, &cur);
316
317 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk),
318 drate);
319 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
320 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2,
321 cur.dsmpd, cur.frac);
322 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n",
323 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2,
324 rate->dsmpd, rate->frac);
325
326 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
327 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
328 rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
329 struct clk *parent = clk_get_parent(hw->clk);
330
331 if (!parent) {
332 pr_warn("%s: parent of %s not available\n",
333 __func__, __clk_get_name(hw->clk));
334 return;
335 }
336
337 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
338 __func__, __clk_get_name(hw->clk));
339 rockchip_rk3036_pll_set_params(pll, rate);
340 }
341}
342
343static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = {
344 .recalc_rate = rockchip_rk3036_pll_recalc_rate,
345 .enable = rockchip_rk3036_pll_enable,
346 .disable = rockchip_rk3036_pll_disable,
347 .is_enabled = rockchip_rk3036_pll_is_enabled,
348};
349
350static const struct clk_ops rockchip_rk3036_pll_clk_ops = {
351 .recalc_rate = rockchip_rk3036_pll_recalc_rate,
352 .round_rate = rockchip_pll_round_rate,
353 .set_rate = rockchip_rk3036_pll_set_rate,
354 .enable = rockchip_rk3036_pll_enable,
355 .disable = rockchip_rk3036_pll_disable,
356 .is_enabled = rockchip_rk3036_pll_is_enabled,
357 .init = rockchip_rk3036_pll_init,
358};
359
360/**
111 * PLL used in RK3066, RK3188 and RK3288 361 * PLL used in RK3066, RK3188 and RK3288
112 */ 362 */
113 363
@@ -376,7 +626,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
376 pll_mux->lock = lock; 626 pll_mux->lock = lock;
377 pll_mux->hw.init = &init; 627 pll_mux->hw.init = &init;
378 628
379 if (pll_type == pll_rk3066) 629 if (pll_type == pll_rk3036 || pll_type == pll_rk3066)
380 pll_mux->flags |= CLK_MUX_HIWORD_MASK; 630 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
381 631
382 /* the actual muxing is xin24m, pll-output, xin32k */ 632 /* the actual muxing is xin24m, pll-output, xin32k */
@@ -421,6 +671,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
421 } 671 }
422 672
423 switch (pll_type) { 673 switch (pll_type) {
674 case pll_rk3036:
675 if (!pll->rate_table)
676 init.ops = &rockchip_rk3036_pll_clk_norate_ops;
677 else
678 init.ops = &rockchip_rk3036_pll_clk_ops;
679 break;
424 case pll_rk3066: 680 case pll_rk3066:
425 if (!pll->rate_table) 681 if (!pll->rate_table)
426 init.ops = &rockchip_rk3066_pll_clk_norate_ops; 682 init.ops = &rockchip_rk3066_pll_clk_norate_ops;
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
new file mode 100644
index 000000000000..7333b05342ff
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -0,0 +1,478 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/syscore_ops.h>
23#include <dt-bindings/clock/rk3036-cru.h>
24#include "clk.h"
25
26#define RK3036_GRF_SOC_STATUS0 0x14c
27
28enum rk3036_plls {
29 apll, dpll, gpll,
30};
31
32static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
55 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
67 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
68 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
69 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
70 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
71 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
72 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
73 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
74 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
75 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
76 { /* sentinel */ },
77};
78
79#define RK3036_DIV_CPU_MASK 0x1f
80#define RK3036_DIV_CPU_SHIFT 8
81
82#define RK3036_DIV_PERI_MASK 0xf
83#define RK3036_DIV_PERI_SHIFT 0
84#define RK3036_DIV_ACLK_MASK 0x7
85#define RK3036_DIV_ACLK_SHIFT 4
86#define RK3036_DIV_HCLK_MASK 0x3
87#define RK3036_DIV_HCLK_SHIFT 8
88#define RK3036_DIV_PCLK_MASK 0x7
89#define RK3036_DIV_PCLK_SHIFT 12
90
91#define RK3036_CLKSEL1(_core_periph_div) \
92 { \
93 .reg = RK2928_CLKSEL_CON(1), \
94 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
95 RK3036_DIV_PERI_SHIFT) \
96 }
97
98#define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \
99 { \
100 .prate = _prate, \
101 .divs = { \
102 RK3036_CLKSEL1(_core_periph_div), \
103 }, \
104 }
105
106static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
107 RK3036_CPUCLK_RATE(816000000, 4),
108 RK3036_CPUCLK_RATE(600000000, 4),
109 RK3036_CPUCLK_RATE(312000000, 4),
110};
111
112static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
113 .core_reg = RK2928_CLKSEL_CON(0),
114 .div_core_shift = 0,
115 .div_core_mask = 0x1f,
116 .mux_core_shift = 7,
117};
118
119PNAME(mux_pll_p) = { "xin24m", "xin24m" };
120
121PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
122PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
123PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
124PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
125PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
126
127PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" };
128
129PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
130PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
131PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
132PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
133PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
134PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
135PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
136PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
137PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" };
138
139static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = {
140 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
141 RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates),
142 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
143 RK2928_MODE_CON, 4, 4, 0, NULL),
144 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
145 RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates),
146};
147
148#define MFLAGS CLK_MUX_HIWORD_MASK
149#define DFLAGS CLK_DIVIDER_HIWORD_MASK
150#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
151
152static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
153 /*
154 * Clock-Architecture Diagram 1
155 */
156
157 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
158 RK2928_CLKGATE_CON(0), 6, GFLAGS),
159
160 /*
161 * Clock-Architecture Diagram 2
162 */
163
164 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
165 RK2928_CLKGATE_CON(0), 2, GFLAGS),
166 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
167 RK2928_CLKGATE_CON(0), 8, GFLAGS),
168 COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
169 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
170
171 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
172 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
173 RK2928_CLKGATE_CON(0), 7, GFLAGS),
174 COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED,
175 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
176 RK2928_CLKGATE_CON(0), 7, GFLAGS),
177
178 GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
179 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
180 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
181 RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
182 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
183 RK2928_CLKGATE_CON(0), 3, GFLAGS),
184 COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
185 RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
186 RK2928_CLKGATE_CON(0), 5, GFLAGS),
187 COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
188 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
189 RK2928_CLKGATE_CON(0), 4, GFLAGS),
190
191 COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
192 RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
193 RK2928_CLKGATE_CON(2), 0, GFLAGS),
194
195 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
196 RK2928_CLKGATE_CON(2), 1, GFLAGS),
197 DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
198 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
199 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
200 RK2928_CLKGATE_CON(2), 3, GFLAGS),
201 DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
202 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
203 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
204 RK2928_CLKGATE_CON(2), 2, GFLAGS),
205
206 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
207 RK2928_CLKSEL_CON(2), 4, 1, DFLAGS,
208 RK2928_CLKGATE_CON(1), 0, GFLAGS),
209 COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED,
210 RK2928_CLKSEL_CON(2), 5, 1, DFLAGS,
211 RK2928_CLKGATE_CON(1), 1, GFLAGS),
212 COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED,
213 RK2928_CLKSEL_CON(2), 6, 1, DFLAGS,
214 RK2928_CLKGATE_CON(2), 4, GFLAGS),
215 COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED,
216 RK2928_CLKSEL_CON(2), 7, 1, DFLAGS,
217 RK2928_CLKGATE_CON(2), 5, GFLAGS),
218
219 MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
220 RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
221 COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
222 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
223 RK2928_CLKGATE_CON(1), 8, GFLAGS),
224 COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
225 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
226 RK2928_CLKGATE_CON(1), 8, GFLAGS),
227 COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
228 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
229 RK2928_CLKGATE_CON(1), 8, GFLAGS),
230 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
231 RK2928_CLKSEL_CON(17), 0,
232 RK2928_CLKGATE_CON(1), 9, GFLAGS),
233 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
234 RK2928_CLKSEL_CON(18), 0,
235 RK2928_CLKGATE_CON(1), 11, GFLAGS),
236 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
237 RK2928_CLKSEL_CON(19), 0,
238 RK2928_CLKGATE_CON(1), 13, GFLAGS),
239 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
240 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
241 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
242 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
243 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
244 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
245
246 COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
247 RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
248 RK2928_CLKGATE_CON(3), 11, GFLAGS),
249
250 COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0,
251 RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
252 RK2928_CLKGATE_CON(10), 6, GFLAGS),
253
254 COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
255 RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
256 RK2928_CLKGATE_CON(1), 4, GFLAGS),
257 COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
258 RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
259 RK2928_CLKGATE_CON(0), 11, GFLAGS),
260 COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
261 RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
262 RK2928_CLKGATE_CON(3), 2, GFLAGS),
263
264 COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0,
265 RK2928_CLKSEL_CON(12), 8, 2, DFLAGS,
266 RK2928_CLKGATE_CON(2), 11, GFLAGS),
267 DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0,
268 RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
269
270 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
271 RK2928_CLKSEL_CON(12), 10, 2, DFLAGS,
272 RK2928_CLKGATE_CON(2), 13, GFLAGS),
273 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
274 RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
275
276 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
277 RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS,
278 RK2928_CLKGATE_CON(2), 14, GFLAGS),
279
280 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3036_SDMMC_CON0, 1),
281 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0),
282
283 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3036_SDIO_CON0, 1),
284 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3036_SDIO_CON1, 0),
285
286 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1),
287 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0),
288
289 COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
290 RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
291 RK2928_CLKGATE_CON(0), 9, GFLAGS),
292 COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
293 RK2928_CLKSEL_CON(7), 0,
294 RK2928_CLKGATE_CON(0), 10, GFLAGS),
295 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
296 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
297 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
298 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
299 RK2928_CLKGATE_CON(0), 13, GFLAGS),
300 GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
301 RK2928_CLKGATE_CON(0), 14, GFLAGS),
302
303 COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
304 RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
305 RK2928_CLKGATE_CON(2), 10, GFLAGS),
306 COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
307 RK2928_CLKSEL_CON(9), 0,
308 RK2928_CLKGATE_CON(2), 12, GFLAGS),
309 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
310 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
311
312 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
313 RK2928_CLKGATE_CON(1), 5, GFLAGS),
314
315 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
316 RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
317 RK2928_CLKGATE_CON(3), 13, GFLAGS),
318
319 COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
320 RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
321 RK2928_CLKGATE_CON(2), 9, GFLAGS),
322
323 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
324 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
325 RK2928_CLKGATE_CON(10), 4, GFLAGS),
326
327 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
328 RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
329 RK2928_CLKGATE_CON(10), 5, GFLAGS),
330
331 COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
332 RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
333 MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
334 RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
335
336 COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
337 RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
338 RK2928_CLKGATE_CON(2), 6, GFLAGS),
339
340 MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
341 RK2928_CLKSEL_CON(31), 0, 1, MFLAGS),
342
343 /*
344 * Clock-Architecture Diagram 3
345 */
346
347 /* aclk_cpu gates */
348 GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS),
349 GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS),
350
351 /* hclk_cpu gates */
352 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS),
353
354 /* pclk_cpu gates */
355 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
356 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
357 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
358 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
359
360 /* aclk_vio gates */
361 GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS),
362 GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
363
364 GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
365 GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
366
367 /* hclk_video gates */
368 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),
369
370 /* xin24m gates */
371 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS),
372 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS),
373
374 /* aclk_peri gates */
375 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS),
376 GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS),
377 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
378 GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS),
379
380 /* hclk_peri gates */
381 GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
382 GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS),
383 GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS),
384 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
385 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
386 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
387 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
388 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
389 GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS),
390 GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
391 GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS),
392 GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS),
393
394 /* pclk_peri gates */
395 GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),
396 GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),
397 GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
398 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
399 GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
400 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
401 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
402 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
403 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
404 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
405 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
406 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
407 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
408 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
409 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
410};
411
412static const char *const rk3036_critical_clocks[] __initconst = {
413 "aclk_cpu",
414 "aclk_peri",
415 "hclk_peri",
416 "pclk_peri",
417};
418
419static void __init rk3036_clk_init(struct device_node *np)
420{
421 void __iomem *reg_base;
422 struct clk *clk;
423
424 reg_base = of_iomap(np, 0);
425 if (!reg_base) {
426 pr_err("%s: could not map cru region\n", __func__);
427 return;
428 }
429
430 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
431
432 /* xin12m is created by an cru-internal divider */
433 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
434 if (IS_ERR(clk))
435 pr_warn("%s: could not register clock xin12m: %ld\n",
436 __func__, PTR_ERR(clk));
437
438 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
439 if (IS_ERR(clk))
440 pr_warn("%s: could not register clock usb480m: %ld\n",
441 __func__, PTR_ERR(clk));
442
443 clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2);
444 if (IS_ERR(clk))
445 pr_warn("%s: could not register clock ddrphy: %ld\n",
446 __func__, PTR_ERR(clk));
447
448 clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
449 "aclk_vcodec", 0, 1, 4);
450 if (IS_ERR(clk))
451 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
452 __func__, PTR_ERR(clk));
453
454 clk = clk_register_fixed_factor(NULL, "sclk_macref_out",
455 "hclk_peri_src", 0, 1, 2);
456 if (IS_ERR(clk))
457 pr_warn("%s: could not register clock sclk_macref_out: %ld\n",
458 __func__, PTR_ERR(clk));
459
460 rockchip_clk_register_plls(rk3036_pll_clks,
461 ARRAY_SIZE(rk3036_pll_clks),
462 RK3036_GRF_SOC_STATUS0);
463 rockchip_clk_register_branches(rk3036_clk_branches,
464 ARRAY_SIZE(rk3036_clk_branches));
465 rockchip_clk_protect_critical(rk3036_critical_clocks,
466 ARRAY_SIZE(rk3036_critical_clocks));
467
468 rockchip_clk_register_armclk(ARMCLK, "armclk",
469 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
470 &rk3036_cpuclk_data, rk3036_cpuclk_rates,
471 ARRAY_SIZE(rk3036_cpuclk_rates));
472
473 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
474 ROCKCHIP_SOFTRST_HIWORD_MASK);
475
476 rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
477}
478CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index abb47608713b..c2c35d4cdda8 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -750,7 +750,7 @@ static void __init rk3188_common_clk_init(struct device_node *np)
750 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), 750 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
751 ROCKCHIP_SOFTRST_HIWORD_MASK); 751 ROCKCHIP_SOFTRST_HIWORD_MASK);
752 752
753 rockchip_register_restart_notifier(RK2928_GLB_SRST_FST); 753 rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
754} 754}
755 755
756static void __init rk3066a_clk_init(struct device_node *np) 756static void __init rk3066a_clk_init(struct device_node *np)
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
new file mode 100644
index 000000000000..981a50205339
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -0,0 +1,678 @@
1/*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 * Jeffy Chen <jeffy.chen@rock-chips.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/syscore_ops.h>
21#include <dt-bindings/clock/rk3228-cru.h>
22#include "clk.h"
23
24#define RK3228_GRF_SOC_STATUS0 0x480
25
26enum rk3228_plls {
27 apll, dpll, cpll, gpll,
28};
29
30static struct rockchip_pll_rate_table rk3228_pll_rates[] = {
31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
53 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
54 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
55 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
67 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
68 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
69 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
70 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
71 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
72 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
73 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
74 { /* sentinel */ },
75};
76
77#define RK3228_DIV_CPU_MASK 0x1f
78#define RK3228_DIV_CPU_SHIFT 8
79
80#define RK3228_DIV_PERI_MASK 0xf
81#define RK3228_DIV_PERI_SHIFT 0
82#define RK3228_DIV_ACLK_MASK 0x7
83#define RK3228_DIV_ACLK_SHIFT 4
84#define RK3228_DIV_HCLK_MASK 0x3
85#define RK3228_DIV_HCLK_SHIFT 8
86#define RK3228_DIV_PCLK_MASK 0x7
87#define RK3228_DIV_PCLK_SHIFT 12
88
89#define RK3228_CLKSEL1(_core_peri_div) \
90 { \
91 .reg = RK2928_CLKSEL_CON(1), \
92 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
93 RK3228_DIV_PERI_SHIFT) \
94 }
95
96#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \
97 { \
98 .prate = _prate, \
99 .divs = { \
100 RK3228_CLKSEL1(_core_peri_div), \
101 }, \
102 }
103
104static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
105 RK3228_CPUCLK_RATE(816000000, 4),
106 RK3228_CPUCLK_RATE(600000000, 4),
107 RK3228_CPUCLK_RATE(312000000, 4),
108};
109
110static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
111 .core_reg = RK2928_CLKSEL_CON(0),
112 .div_core_shift = 0,
113 .div_core_mask = 0x1f,
114 .mux_core_shift = 6,
115};
116
117PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
118
119PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
120PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
121PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
122PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
123PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
124PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
125
126PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
127PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
128PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
129PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
130PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
131PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
132PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
133
134PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
135
136PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
137PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
138
139PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
140PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" };
141PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" };
142PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
143PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" };
144
145PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" };
146
147PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
148PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
149PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
150
151PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" };
152PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" };
153PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
154
155static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
156 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
157 RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates),
158 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
159 RK2928_MODE_CON, 4, 6, 0, NULL),
160 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
161 RK2928_MODE_CON, 8, 8, 0, NULL),
162 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
163 RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
164};
165
166#define MFLAGS CLK_MUX_HIWORD_MASK
167#define DFLAGS CLK_DIVIDER_HIWORD_MASK
168#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
169
170static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
171 /*
172 * Clock-Architecture Diagram 1
173 */
174
175 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
176 RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
177
178 /* PD_DDR */
179 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
180 RK2928_CLKGATE_CON(0), 2, GFLAGS),
181 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
182 RK2928_CLKGATE_CON(0), 2, GFLAGS),
183 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
184 RK2928_CLKGATE_CON(0), 2, GFLAGS),
185 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
186 RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
187 RK2928_CLKGATE_CON(7), 1, GFLAGS),
188 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
189 RK2928_CLKGATE_CON(8), 5, GFLAGS),
190 GATE(0, "ddrphy", "ddrphy_pre", CLK_IGNORE_UNUSED,
191 RK2928_CLKGATE_CON(7), 0, GFLAGS),
192
193 /* PD_CORE */
194 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
195 RK2928_CLKGATE_CON(0), 6, GFLAGS),
196 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
197 RK2928_CLKGATE_CON(0), 6, GFLAGS),
198 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
199 RK2928_CLKGATE_CON(0), 6, GFLAGS),
200 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
201 RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
202 RK2928_CLKGATE_CON(4), 1, GFLAGS),
203 COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED,
204 RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
205 RK2928_CLKGATE_CON(4), 0, GFLAGS),
206
207 /* PD_MISC */
208 MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
209 RK2928_MISC_CON, 13, 1, MFLAGS),
210 MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
211 RK2928_MISC_CON, 14, 1, MFLAGS),
212 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
213 RK2928_MISC_CON, 15, 1, MFLAGS),
214
215 /* PD_BUS */
216 GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
217 RK2928_CLKGATE_CON(0), 1, GFLAGS),
218 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
219 RK2928_CLKGATE_CON(0), 1, GFLAGS),
220 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
221 RK2928_CLKGATE_CON(0), 1, GFLAGS),
222 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
223 RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
224 GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
225 RK2928_CLKGATE_CON(6), 0, GFLAGS),
226 COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
227 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
228 RK2928_CLKGATE_CON(6), 1, GFLAGS),
229 COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
230 RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
231 RK2928_CLKGATE_CON(6), 2, GFLAGS),
232 GATE(0, "pclk_cpu", "pclk_bus_src", 0,
233 RK2928_CLKGATE_CON(6), 3, GFLAGS),
234 GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
235 RK2928_CLKGATE_CON(6), 4, GFLAGS),
236 GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
237 RK2928_CLKGATE_CON(6), 13, GFLAGS),
238
239 /* PD_VIDEO */
240 COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
241 RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
242 RK2928_CLKGATE_CON(3), 11, GFLAGS),
243 GATE(0, "hclk_vpu_src", "aclk_vpu_pre", 0,
244 RK2928_CLKGATE_CON(4), 4, GFLAGS),
245
246 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
247 RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
248 RK2928_CLKGATE_CON(3), 2, GFLAGS),
249 GATE(0, "hclk_rkvdec_src", "aclk_rkvdec_pre", 0,
250 RK2928_CLKGATE_CON(4), 5, GFLAGS),
251
252 COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
253 RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
254 RK2928_CLKGATE_CON(3), 3, GFLAGS),
255
256 COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
257 RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
258 RK2928_CLKGATE_CON(3), 4, GFLAGS),
259
260 /* PD_VIO */
261 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
262 RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
263 RK2928_CLKGATE_CON(3), 0, GFLAGS),
264 DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0,
265 RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
266
267 COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
268 RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
269 RK2928_CLKGATE_CON(1), 4, GFLAGS),
270
271 MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
272 RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
273 COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0,
274 RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
275 RK2928_CLKGATE_CON(1), 2, GFLAGS),
276 COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0,
277 RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
278 RK2928_CLKGATE_CON(3), 6, GFLAGS),
279
280 COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
281 RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
282 RK2928_CLKGATE_CON(1), 1, GFLAGS),
283
284 COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0,
285 RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
286 RK2928_CLKGATE_CON(3), 5, GFLAGS),
287
288 GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
289 RK2928_CLKGATE_CON(3), 7, GFLAGS),
290
291 COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
292 RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
293 RK2928_CLKGATE_CON(3), 8, GFLAGS),
294
295 /* PD_PERI */
296 GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
297 RK2928_CLKGATE_CON(2), 0, GFLAGS),
298 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
299 RK2928_CLKGATE_CON(2), 0, GFLAGS),
300 GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
301 RK2928_CLKGATE_CON(2), 0, GFLAGS),
302 COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
303 RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
304 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
305 RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
306 RK2928_CLKGATE_CON(5), 2, GFLAGS),
307 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
308 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
309 RK2928_CLKGATE_CON(5), 1, GFLAGS),
310 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
311 RK2928_CLKGATE_CON(5), 0, GFLAGS),
312
313 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
314 RK2928_CLKGATE_CON(6), 5, GFLAGS),
315 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
316 RK2928_CLKGATE_CON(6), 6, GFLAGS),
317 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
318 RK2928_CLKGATE_CON(6), 7, GFLAGS),
319 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
320 RK2928_CLKGATE_CON(6), 8, GFLAGS),
321 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
322 RK2928_CLKGATE_CON(6), 9, GFLAGS),
323 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
324 RK2928_CLKGATE_CON(6), 10, GFLAGS),
325
326 COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0,
327 RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
328 RK2928_CLKGATE_CON(2), 7, GFLAGS),
329
330 COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0,
331 RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
332 RK2928_CLKGATE_CON(2), 6, GFLAGS),
333
334 GATE(0, "sclk_hsadc", "ext_hsadc", 0,
335 RK3288_CLKGATE_CON(10), 12, GFLAGS),
336
337 COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
338 RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
339 RK2928_CLKGATE_CON(2), 15, GFLAGS),
340
341 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
342 RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS,
343 RK2928_CLKGATE_CON(2), 11, GFLAGS),
344
345 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
346 RK2928_CLKSEL_CON(11), 10, 2, MFLAGS,
347 RK2928_CLKGATE_CON(2), 13, GFLAGS),
348 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
349 RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
350
351 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
352 RK2928_CLKSEL_CON(11), 12, 2, MFLAGS,
353 RK2928_CLKGATE_CON(2), 14, GFLAGS),
354 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
355 RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
356
357 /*
358 * Clock-Architecture Diagram 2
359 */
360
361 GATE(0, "gpll_vop", "gpll", 0,
362 RK2928_CLKGATE_CON(3), 1, GFLAGS),
363 GATE(0, "cpll_vop", "cpll", 0,
364 RK2928_CLKGATE_CON(3), 1, GFLAGS),
365 MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
366 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
367 DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0,
368 RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
369 DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
370 RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
371 MUX(0, "dclk_vop", mux_dclk_vop_p, 0,
372 RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
373
374 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
375 RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
376 RK2928_CLKGATE_CON(0), 3, GFLAGS),
377 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
378 RK3288_CLKSEL_CON(8), 0,
379 RK3288_CLKGATE_CON(0), 4, GFLAGS),
380 COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
381 RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
382 RK2928_CLKGATE_CON(0), 5, GFLAGS),
383
384 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
385 RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
386 RK2928_CLKGATE_CON(0), 10, GFLAGS),
387 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
388 RK3288_CLKSEL_CON(7), 0,
389 RK3288_CLKGATE_CON(0), 11, GFLAGS),
390 MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
391 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
392 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
393 RK2928_CLKGATE_CON(0), 14, GFLAGS),
394 COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
395 RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
396 RK2928_CLKGATE_CON(0), 13, GFLAGS),
397
398 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
399 RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
400 RK2928_CLKGATE_CON(0), 7, GFLAGS),
401 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
402 RK3288_CLKSEL_CON(30), 0,
403 RK3288_CLKGATE_CON(0), 8, GFLAGS),
404 COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
405 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS,
406 RK2928_CLKGATE_CON(0), 9, GFLAGS),
407
408 COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
409 RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
410 RK2928_CLKGATE_CON(2), 10, GFLAGS),
411 COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
412 RK3288_CLKSEL_CON(20), 0,
413 RK3288_CLKGATE_CON(2), 12, GFLAGS),
414 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
415 RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
416
417 GATE(0, "jtag", "ext_jtag", 0,
418 RK2928_CLKGATE_CON(1), 3, GFLAGS),
419
420 GATE(0, "sclk_otgphy0", "xin24m", 0,
421 RK2928_CLKGATE_CON(1), 5, GFLAGS),
422 GATE(0, "sclk_otgphy1", "xin24m", 0,
423 RK2928_CLKGATE_CON(1), 6, GFLAGS),
424
425 COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
426 RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,
427 RK2928_CLKGATE_CON(2), 8, GFLAGS),
428
429 GATE(0, "cpll_gpu", "cpll", 0,
430 RK2928_CLKGATE_CON(3), 13, GFLAGS),
431 GATE(0, "gpll_gpu", "gpll", 0,
432 RK2928_CLKGATE_CON(3), 13, GFLAGS),
433 GATE(0, "hdmiphy_gpu", "hdmiphy", 0,
434 RK2928_CLKGATE_CON(3), 13, GFLAGS),
435 GATE(0, "usb480m_gpu", "usb480m", 0,
436 RK2928_CLKGATE_CON(3), 13, GFLAGS),
437 COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0,
438 RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS),
439
440 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
441 RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
442 RK2928_CLKGATE_CON(2), 9, GFLAGS),
443
444 /* PD_UART */
445 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
446 RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
447 RK2928_CLKGATE_CON(1), 8, GFLAGS),
448 COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0,
449 RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
450 RK2928_CLKGATE_CON(1), 10, GFLAGS),
451 COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
452 0, RK2928_CLKSEL_CON(15), 12, 2,
453 MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
454 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
455 RK2928_CLKSEL_CON(17), 0,
456 RK2928_CLKGATE_CON(1), 9, GFLAGS),
457 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
458 RK2928_CLKSEL_CON(18), 0,
459 RK2928_CLKGATE_CON(1), 11, GFLAGS),
460 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
461 RK2928_CLKSEL_CON(19), 0,
462 RK2928_CLKGATE_CON(1), 13, GFLAGS),
463 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
464 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
465 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
466 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
467 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
468 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
469
470 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
471 RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
472 RK2928_CLKGATE_CON(1), 0, GFLAGS),
473
474 COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
475 RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
476 RK2928_CLKGATE_CON(1), 7, GFLAGS),
477 MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0,
478 RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
479 MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
480 RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
481 GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0,
482 RK2928_CLKGATE_CON(5), 4, GFLAGS),
483 GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0,
484 RK2928_CLKGATE_CON(5), 3, GFLAGS),
485 GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0,
486 RK2928_CLKGATE_CON(5), 5, GFLAGS),
487 GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0,
488 RK2928_CLKGATE_CON(5), 6, GFLAGS),
489 COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0,
490 RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
491 RK2928_CLKGATE_CON(5), 7, GFLAGS),
492 COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
493 RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
494 RK2928_CLKGATE_CON(2), 2, GFLAGS),
495
496 /*
497 * Clock-Architecture Diagram 3
498 */
499
500 /* PD_VOP */
501 GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
502 GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
503 GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
504 GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
505
506 GATE(0, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
507 GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
508
509 GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
510 GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
511
512 GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
513 GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
514 GATE(0, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
515 GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
516 GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
517 GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
518 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
519 GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
520 GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
521 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
522 GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
523
524 /* PD_PERI */
525 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
526 GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
527
528 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
529 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
530 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
531 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
532 GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
533 GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
534 GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
535 GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
536 GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
537 GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
538 GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
539 GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
540 GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
541
542 GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
543 GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
544
545 /* PD_GPU */
546 GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
547 GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
548
549 /* PD_BUS */
550 GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
551 GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
552 GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
553 GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
554
555 GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
556 GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
557 GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
558 GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
559 GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
560 GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
561 GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
562 GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
563
564 GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
565 GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
566 GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
567
568 GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
569 GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
570 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
571 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
572 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
573 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
574 GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
575 GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
576 GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
577 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
578 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
579 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
580 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS),
581 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS),
582 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),
583 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),
584 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),
585 GATE(0, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),
586 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),
587 GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
588 GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
589 GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
590
591 GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
592 GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
593 GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
594 GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
595 GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
596
597 GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
598 GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
599 GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
600 GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
601 GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
602 GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
603 GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
604 GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
605
606 /* PD_MMC */
607 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
608 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
609
610 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
611 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
612
613 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
614 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
615};
616
617static const char *const rk3228_critical_clocks[] __initconst = {
618 "aclk_cpu",
619 "aclk_peri",
620 "hclk_peri",
621 "pclk_peri",
622};
623
624static void __init rk3228_clk_init(struct device_node *np)
625{
626 void __iomem *reg_base;
627 struct clk *clk;
628
629 reg_base = of_iomap(np, 0);
630 if (!reg_base) {
631 pr_err("%s: could not map cru region\n", __func__);
632 return;
633 }
634
635 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
636
637 /* xin12m is created by an cru-internal divider */
638 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
639 if (IS_ERR(clk))
640 pr_warn("%s: could not register clock xin12m: %ld\n",
641 __func__, PTR_ERR(clk));
642
643 clk = clk_register_fixed_factor(NULL, "ddrphy_pre", "ddrphy4x", 0, 1, 4);
644 if (IS_ERR(clk))
645 pr_warn("%s: could not register clock ddrphy_pre: %ld\n",
646 __func__, PTR_ERR(clk));
647
648 clk = clk_register_fixed_factor(NULL, "hclk_vpu_pre",
649 "hclk_vpu_src", 0, 1, 4);
650 if (IS_ERR(clk))
651 pr_warn("%s: could not register clock hclk_vpu_pre: %ld\n",
652 __func__, PTR_ERR(clk));
653
654 clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",
655 "hclk_rkvdec_src", 0, 1, 4);
656 if (IS_ERR(clk))
657 pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",
658 __func__, PTR_ERR(clk));
659
660 rockchip_clk_register_plls(rk3228_pll_clks,
661 ARRAY_SIZE(rk3228_pll_clks),
662 RK3228_GRF_SOC_STATUS0);
663 rockchip_clk_register_branches(rk3228_clk_branches,
664 ARRAY_SIZE(rk3228_clk_branches));
665 rockchip_clk_protect_critical(rk3228_critical_clocks,
666 ARRAY_SIZE(rk3228_critical_clocks));
667
668 rockchip_clk_register_armclk(ARMCLK, "armclk",
669 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
670 &rk3228_cpuclk_data, rk3228_cpuclk_rates,
671 ARRAY_SIZE(rk3228_cpuclk_rates));
672
673 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
674 ROCKCHIP_SOFTRST_HIWORD_MASK);
675
676 rockchip_register_restart_notifier(RK3228_GLB_SRST_FST, NULL);
677}
678CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 9040878e3e2b..11b40fbc4a53 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -295,7 +295,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
295 RK3288_CLKGATE_CON(0), 4, GFLAGS), 295 RK3288_CLKGATE_CON(0), 4, GFLAGS),
296 GATE(0, "c2c_host", "aclk_cpu_src", 0, 296 GATE(0, "c2c_host", "aclk_cpu_src", 0,
297 RK3288_CLKGATE_CON(13), 8, GFLAGS), 297 RK3288_CLKGATE_CON(13), 8, GFLAGS),
298 COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0, 298 COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
299 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS, 299 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
300 RK3288_CLKGATE_CON(5), 4, GFLAGS), 300 RK3288_CLKGATE_CON(5), 4, GFLAGS),
301 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED, 301 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
@@ -644,10 +644,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
644 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS), 644 GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
645 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS), 645 GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
646 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS), 646 GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
647 GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS), 647 GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
648 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), 648 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
649 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), 649 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
650 GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), 650 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
651 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), 651 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
652 652
653 /* ddrctrl [DDR Controller PHY clock] gates */ 653 /* ddrctrl [DDR Controller PHY clock] gates */
@@ -709,7 +709,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
709 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS), 709 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
710 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS), 710 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
711 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS), 711 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
712 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS), 712 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
713 713
714 /* sclk_gpu gates */ 714 /* sclk_gpu gates */
715 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS), 715 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
@@ -783,10 +783,10 @@ static const char *const rk3288_critical_clocks[] __initconst = {
783 "pclk_pd_pmu", 783 "pclk_pd_pmu",
784}; 784};
785 785
786#ifdef CONFIG_PM_SLEEP
787static void __iomem *rk3288_cru_base; 786static void __iomem *rk3288_cru_base;
788 787
789/* Some CRU registers will be reset in maskrom when the system 788/*
789 * Some CRU registers will be reset in maskrom when the system
790 * wakes up from fastboot. 790 * wakes up from fastboot.
791 * So save them before suspend, restore them after resume. 791 * So save them before suspend, restore them after resume.
792 */ 792 */
@@ -840,33 +840,27 @@ static void rk3288_clk_resume(void)
840 } 840 }
841} 841}
842 842
843static void rk3288_clk_shutdown(void)
844{
845 writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
846}
847
843static struct syscore_ops rk3288_clk_syscore_ops = { 848static struct syscore_ops rk3288_clk_syscore_ops = {
844 .suspend = rk3288_clk_suspend, 849 .suspend = rk3288_clk_suspend,
845 .resume = rk3288_clk_resume, 850 .resume = rk3288_clk_resume,
846}; 851};
847 852
848static void rk3288_clk_sleep_init(void __iomem *reg_base)
849{
850 rk3288_cru_base = reg_base;
851 register_syscore_ops(&rk3288_clk_syscore_ops);
852}
853
854#else /* CONFIG_PM_SLEEP */
855static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
856#endif
857
858static void __init rk3288_clk_init(struct device_node *np) 853static void __init rk3288_clk_init(struct device_node *np)
859{ 854{
860 void __iomem *reg_base;
861 struct clk *clk; 855 struct clk *clk;
862 856
863 reg_base = of_iomap(np, 0); 857 rk3288_cru_base = of_iomap(np, 0);
864 if (!reg_base) { 858 if (!rk3288_cru_base) {
865 pr_err("%s: could not map cru region\n", __func__); 859 pr_err("%s: could not map cru region\n", __func__);
866 return; 860 return;
867 } 861 }
868 862
869 rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 863 rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
870 864
871 /* xin12m is created by an cru-internal divider */ 865 /* xin12m is created by an cru-internal divider */
872 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); 866 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
@@ -907,10 +901,12 @@ static void __init rk3288_clk_init(struct device_node *np)
907 &rk3288_cpuclk_data, rk3288_cpuclk_rates, 901 &rk3288_cpuclk_data, rk3288_cpuclk_rates,
908 ARRAY_SIZE(rk3288_cpuclk_rates)); 902 ARRAY_SIZE(rk3288_cpuclk_rates));
909 903
910 rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0), 904 rockchip_register_softrst(np, 12,
905 rk3288_cru_base + RK3288_SOFTRST_CON(0),
911 ROCKCHIP_SOFTRST_HIWORD_MASK); 906 ROCKCHIP_SOFTRST_HIWORD_MASK);
912 907
913 rockchip_register_restart_notifier(RK3288_GLB_SRST_FST); 908 rockchip_register_restart_notifier(RK3288_GLB_SRST_FST,
914 rk3288_clk_sleep_init(reg_base); 909 rk3288_clk_shutdown);
910 register_syscore_ops(&rk3288_clk_syscore_ops);
915} 911}
916CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init); 912CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 7e6b783e6eee..be0ede522269 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -184,13 +184,13 @@ static const struct rockchip_cpuclk_reg_data rk3368_cpuclkl_data = {
184 184
185#define RK3368_CLKSEL0(_offs, _aclkm) \ 185#define RK3368_CLKSEL0(_offs, _aclkm) \
186 { \ 186 { \
187 .reg = RK3288_CLKSEL_CON(0 + _offs), \ 187 .reg = RK3368_CLKSEL_CON(0 + _offs), \
188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \ 188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
189 RK3368_DIV_ACLKM_SHIFT), \ 189 RK3368_DIV_ACLKM_SHIFT), \
190 } 190 }
191#define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \ 191#define RK3368_CLKSEL1(_offs, _atclk, _pdbg) \
192 { \ 192 { \
193 .reg = RK3288_CLKSEL_CON(1 + _offs), \ 193 .reg = RK3368_CLKSEL_CON(1 + _offs), \
194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \ 194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
195 RK3368_DIV_ATCLK_SHIFT) | \ 195 RK3368_DIV_ATCLK_SHIFT) | \
196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \ 196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
@@ -819,6 +819,13 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
819}; 819};
820 820
821static const char *const rk3368_critical_clocks[] __initconst = { 821static const char *const rk3368_critical_clocks[] __initconst = {
822 "aclk_bus",
823 "aclk_peri",
824 /*
825 * pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
826 * but needs to stay enabled there (including its parents) at all times.
827 */
828 "pclk_pwm1",
822 "pclk_pd_pmu", 829 "pclk_pd_pmu",
823}; 830};
824 831
@@ -882,6 +889,6 @@ static void __init rk3368_clk_init(struct device_node *np)
882 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0), 889 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
883 ROCKCHIP_SOFTRST_HIWORD_MASK); 890 ROCKCHIP_SOFTRST_HIWORD_MASK);
884 891
885 rockchip_register_restart_notifier(RK3368_GLB_SRST_FST); 892 rockchip_register_restart_notifier(RK3368_GLB_SRST_FST, NULL);
886} 893}
887CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init); 894CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index be6c7fd8315d..443d6f07acad 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -341,9 +341,13 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
341} 341}
342 342
343static unsigned int reg_restart; 343static unsigned int reg_restart;
344static void (*cb_restart)(void);
344static int rockchip_restart_notify(struct notifier_block *this, 345static int rockchip_restart_notify(struct notifier_block *this,
345 unsigned long mode, void *cmd) 346 unsigned long mode, void *cmd)
346{ 347{
348 if (cb_restart)
349 cb_restart();
350
347 writel(0xfdb9, reg_base + reg_restart); 351 writel(0xfdb9, reg_base + reg_restart);
348 return NOTIFY_DONE; 352 return NOTIFY_DONE;
349} 353}
@@ -353,11 +357,12 @@ static struct notifier_block rockchip_restart_handler = {
353 .priority = 128, 357 .priority = 128,
354}; 358};
355 359
356void __init rockchip_register_restart_notifier(unsigned int reg) 360void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
357{ 361{
358 int ret; 362 int ret;
359 363
360 reg_restart = reg; 364 reg_restart = reg;
365 cb_restart = cb;
361 ret = register_restart_handler(&rockchip_restart_handler); 366 ret = register_restart_handler(&rockchip_restart_handler);
362 if (ret) 367 if (ret)
363 pr_err("%s: cannot register restart handler, %d\n", 368 pr_err("%s: cannot register restart handler, %d\n",
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index dc8ecb2673b7..809ef81cf63b 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -2,6 +2,9 @@
2 * Copyright (c) 2014 MundoReader S.L. 2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de> 3 * Author: Heiko Stuebner <heiko@sntech.de>
4 * 4 *
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
7 *
5 * based on 8 * based on
6 * 9 *
7 * samsung/clk.h 10 * samsung/clk.h
@@ -30,7 +33,7 @@ struct clk;
30#define HIWORD_UPDATE(val, mask, shift) \ 33#define HIWORD_UPDATE(val, mask, shift) \
31 ((val) << (shift) | (mask) << ((shift) + 16)) 34 ((val) << (shift) | (mask) << ((shift) + 16))
32 35
33/* register positions shared by RK2928, RK3066 and RK3188 */ 36/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
34#define RK2928_PLL_CON(x) ((x) * 0x4) 37#define RK2928_PLL_CON(x) ((x) * 0x4)
35#define RK2928_MODE_CON 0x40 38#define RK2928_MODE_CON 0x40
36#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) 39#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
@@ -40,6 +43,22 @@ struct clk;
40#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110) 43#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
41#define RK2928_MISC_CON 0x134 44#define RK2928_MISC_CON 0x134
42 45
46#define RK3036_SDMMC_CON0 0x144
47#define RK3036_SDMMC_CON1 0x148
48#define RK3036_SDIO_CON0 0x14c
49#define RK3036_SDIO_CON1 0x150
50#define RK3036_EMMC_CON0 0x154
51#define RK3036_EMMC_CON1 0x158
52
53#define RK3228_GLB_SRST_FST 0x1f0
54#define RK3228_GLB_SRST_SND 0x1f4
55#define RK3228_SDMMC_CON0 0x1c0
56#define RK3228_SDMMC_CON1 0x1c4
57#define RK3228_SDIO_CON0 0x1c8
58#define RK3228_SDIO_CON1 0x1cc
59#define RK3228_EMMC_CON0 0x1d8
60#define RK3228_EMMC_CON1 0x1dc
61
43#define RK3288_PLL_CON(x) RK2928_PLL_CON(x) 62#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
44#define RK3288_MODE_CON 0x50 63#define RK3288_MODE_CON 0x50
45#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 64#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
@@ -74,9 +93,22 @@ struct clk;
74#define RK3368_EMMC_CON1 0x41c 93#define RK3368_EMMC_CON1 0x41c
75 94
76enum rockchip_pll_type { 95enum rockchip_pll_type {
96 pll_rk3036,
77 pll_rk3066, 97 pll_rk3066,
78}; 98};
79 99
100#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
101 _postdiv2, _dsmpd, _frac) \
102{ \
103 .rate = _rate##U, \
104 .fbdiv = _fbdiv, \
105 .postdiv1 = _postdiv1, \
106 .refdiv = _refdiv, \
107 .postdiv2 = _postdiv2, \
108 .dsmpd = _dsmpd, \
109 .frac = _frac, \
110}
111
80#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ 112#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
81{ \ 113{ \
82 .rate = _rate##U, \ 114 .rate = _rate##U, \
@@ -101,6 +133,13 @@ struct rockchip_pll_rate_table {
101 unsigned int nf; 133 unsigned int nf;
102 unsigned int no; 134 unsigned int no;
103 unsigned int nb; 135 unsigned int nb;
136 /* for RK3036 */
137 unsigned int fbdiv;
138 unsigned int postdiv1;
139 unsigned int refdiv;
140 unsigned int postdiv2;
141 unsigned int dsmpd;
142 unsigned int frac;
104}; 143};
105 144
106/** 145/**
@@ -464,7 +503,7 @@ void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
464 const struct rockchip_cpuclk_rate_table *rates, 503 const struct rockchip_cpuclk_rate_table *rates,
465 int nrates); 504 int nrates);
466void rockchip_clk_protect_critical(const char *const clocks[], int nclocks); 505void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
467void rockchip_register_restart_notifier(unsigned int reg); 506void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
468 507
469#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0) 508#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
470 509
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 000000000000..ebc7a7b43f52
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,193 @@
1/*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
18
19/* core clocks */
20#define PLL_APLL 1
21#define PLL_DPLL 2
22#define PLL_GPLL 3
23#define ARMCLK 4
24
25/* sclk gates (special clocks) */
26#define SCLK_GPU 64
27#define SCLK_SPI 65
28#define SCLK_SDMMC 68
29#define SCLK_SDIO 69
30#define SCLK_EMMC 71
31#define SCLK_NANDC 76
32#define SCLK_UART0 77
33#define SCLK_UART1 78
34#define SCLK_UART2 79
35#define SCLK_I2S 82
36#define SCLK_SPDIF 83
37#define SCLK_TIMER0 85
38#define SCLK_TIMER1 86
39#define SCLK_TIMER2 87
40#define SCLK_TIMER3 88
41#define SCLK_OTGPHY0 93
42#define SCLK_LCDC 100
43#define SCLK_HDMI 109
44#define SCLK_HEVC 111
45#define SCLK_I2S_OUT 113
46#define SCLK_SDMMC_DRV 114
47#define SCLK_SDIO_DRV 115
48#define SCLK_EMMC_DRV 117
49#define SCLK_SDMMC_SAMPLE 118
50#define SCLK_SDIO_SAMPLE 119
51#define SCLK_EMMC_SAMPLE 121
52#define SCLK_PVTM_CORE 123
53#define SCLK_PVTM_GPU 124
54#define SCLK_PVTM_VIDEO 125
55#define SCLK_MAC 151
56#define SCLK_MACREF 152
57#define SCLK_SFC 160
58
59/* aclk gates */
60#define ACLK_DMAC2 194
61#define ACLK_LCDC 197
62#define ACLK_VIO 203
63#define ACLK_VCODEC 208
64#define ACLK_CPU 209
65#define ACLK_PERI 210
66
67/* pclk gates */
68#define PCLK_GPIO0 320
69#define PCLK_GPIO1 321
70#define PCLK_GPIO2 322
71#define PCLK_GRF 329
72#define PCLK_I2C0 332
73#define PCLK_I2C1 333
74#define PCLK_I2C2 334
75#define PCLK_SPI 338
76#define PCLK_UART0 341
77#define PCLK_UART1 342
78#define PCLK_UART2 343
79#define PCLK_PWM 350
80#define PCLK_TIMER 353
81#define PCLK_HDMI 360
82#define PCLK_CPU 362
83#define PCLK_PERI 363
84#define PCLK_DDRUPCTL 364
85#define PCLK_WDT 368
86#define PCLK_ACODEC 369
87
88/* hclk gates */
89#define HCLK_OTG0 449
90#define HCLK_OTG1 450
91#define HCLK_NANDC 453
92#define HCLK_SDMMC 456
93#define HCLK_SDIO 457
94#define HCLK_EMMC 459
95#define HCLK_I2S 462
96#define HCLK_LCDC 465
97#define HCLK_ROM 467
98#define HCLK_VIO_BUS 472
99#define HCLK_VCODEC 476
100#define HCLK_CPU 477
101#define HCLK_PERI 478
102
103#define CLK_NR_CLKS (HCLK_PERI + 1)
104
105/* soft-reset indices */
106#define SRST_CORE0 0
107#define SRST_CORE1 1
108#define SRST_CORE0_DBG 4
109#define SRST_CORE1_DBG 5
110#define SRST_CORE0_POR 8
111#define SRST_CORE1_POR 9
112#define SRST_L2C 12
113#define SRST_TOPDBG 13
114#define SRST_STRC_SYS_A 14
115#define SRST_PD_CORE_NIU 15
116
117#define SRST_TIMER2 16
118#define SRST_CPUSYS_H 17
119#define SRST_AHB2APB_H 19
120#define SRST_TIMER3 20
121#define SRST_INTMEM 21
122#define SRST_ROM 22
123#define SRST_PERI_NIU 23
124#define SRST_I2S 24
125#define SRST_DDR_PLL 25
126#define SRST_GPU_DLL 26
127#define SRST_TIMER0 27
128#define SRST_TIMER1 28
129#define SRST_CORE_DLL 29
130#define SRST_EFUSE_P 30
131#define SRST_ACODEC_P 31
132
133#define SRST_GPIO0 32
134#define SRST_GPIO1 33
135#define SRST_GPIO2 34
136#define SRST_UART0 39
137#define SRST_UART1 40
138#define SRST_UART2 41
139#define SRST_I2C0 43
140#define SRST_I2C1 44
141#define SRST_I2C2 45
142#define SRST_SFC 47
143
144#define SRST_PWM0 48
145#define SRST_DAP 51
146#define SRST_DAP_SYS 52
147#define SRST_GRF 55
148#define SRST_PERIPHSYS_A 57
149#define SRST_PERIPHSYS_H 58
150#define SRST_PERIPHSYS_P 59
151#define SRST_CPU_PERI 61
152#define SRST_EMEM_PERI 62
153#define SRST_USB_PERI 63
154
155#define SRST_DMA2 64
156#define SRST_MAC 66
157#define SRST_NANDC 68
158#define SRST_USBOTG0 69
159#define SRST_OTGC0 71
160#define SRST_USBOTG1 72
161#define SRST_OTGC1 74
162#define SRST_DDRMSCH 79
163
164#define SRST_MMC0 81
165#define SRST_SDIO 82
166#define SRST_EMMC 83
167#define SRST_SPI0 84
168#define SRST_WDT 86
169#define SRST_DDRPHY 88
170#define SRST_DDRPHY_P 89
171#define SRST_DDRCTRL 90
172#define SRST_DDRCTRL_P 91
173
174#define SRST_HDMI_P 96
175#define SRST_VIO_BUS_H 99
176#define SRST_UTMI0 103
177#define SRST_UTMI1 104
178#define SRST_USBPOR 105
179
180#define SRST_VCODEC_A 112
181#define SRST_VCODEC_H 113
182#define SRST_VIO1_A 114
183#define SRST_HEVC 115
184#define SRST_VCODEC_NIU_A 116
185#define SRST_LCDC1_A 117
186#define SRST_LCDC1_H 118
187#define SRST_LCDC1_D 119
188#define SRST_GPU 120
189#define SRST_GPU_NIU_A 122
190
191#define SRST_DBG_P 131
192
193#endif
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
new file mode 100644
index 000000000000..a78dd891e24a
--- /dev/null
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -0,0 +1,220 @@
1/*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
18
19/* core clocks */
20#define PLL_APLL 1
21#define PLL_DPLL 2
22#define PLL_CPLL 3
23#define PLL_GPLL 4
24#define ARMCLK 5
25
26/* sclk gates (special clocks) */
27#define SCLK_SPI0 65
28#define SCLK_NANDC 67
29#define SCLK_SDMMC 68
30#define SCLK_SDIO 69
31#define SCLK_EMMC 71
32#define SCLK_UART0 77
33#define SCLK_UART1 78
34#define SCLK_UART2 79
35#define SCLK_I2S0 80
36#define SCLK_I2S1 81
37#define SCLK_I2S2 82
38#define SCLK_SPDIF 83
39#define SCLK_TIMER0 85
40#define SCLK_TIMER1 86
41#define SCLK_TIMER2 87
42#define SCLK_TIMER3 88
43#define SCLK_TIMER4 89
44#define SCLK_TIMER5 90
45#define SCLK_I2S_OUT 113
46#define SCLK_SDMMC_DRV 114
47#define SCLK_SDIO_DRV 115
48#define SCLK_EMMC_DRV 117
49#define SCLK_SDMMC_SAMPLE 118
50#define SCLK_SDIO_SAMPLE 119
51#define SCLK_EMMC_SAMPLE 121
52
53/* aclk gates */
54#define ACLK_DMAC 194
55#define ACLK_PERI 210
56
57/* pclk gates */
58#define PCLK_GPIO0 320
59#define PCLK_GPIO1 321
60#define PCLK_GPIO2 322
61#define PCLK_GPIO3 323
62#define PCLK_GRF 329
63#define PCLK_I2C0 332
64#define PCLK_I2C1 333
65#define PCLK_I2C2 334
66#define PCLK_I2C3 335
67#define PCLK_SPI0 338
68#define PCLK_UART0 341
69#define PCLK_UART1 342
70#define PCLK_UART2 343
71#define PCLK_PWM 350
72#define PCLK_TIMER 353
73#define PCLK_PERI 363
74
75/* hclk gates */
76#define HCLK_NANDC 453
77#define HCLK_SDMMC 456
78#define HCLK_SDIO 457
79#define HCLK_EMMC 459
80#define HCLK_PERI 478
81
82#define CLK_NR_CLKS (HCLK_PERI + 1)
83
84/* soft-reset indices */
85#define SRST_CORE0_PO 0
86#define SRST_CORE1_PO 1
87#define SRST_CORE2_PO 2
88#define SRST_CORE3_PO 3
89#define SRST_CORE0 4
90#define SRST_CORE1 5
91#define SRST_CORE2 6
92#define SRST_CORE3 7
93#define SRST_CORE0_DBG 8
94#define SRST_CORE1_DBG 9
95#define SRST_CORE2_DBG 10
96#define SRST_CORE3_DBG 11
97#define SRST_TOPDBG 12
98#define SRST_ACLK_CORE 13
99#define SRST_NOC 14
100#define SRST_L2C 15
101
102#define SRST_CPUSYS_H 18
103#define SRST_BUSSYS_H 19
104#define SRST_SPDIF 20
105#define SRST_INTMEM 21
106#define SRST_ROM 22
107#define SRST_OTG_ADP 23
108#define SRST_I2S0 24
109#define SRST_I2S1 25
110#define SRST_I2S2 26
111#define SRST_ACODEC_P 27
112#define SRST_DFIMON 28
113#define SRST_MSCH 29
114#define SRST_EFUSE1024 30
115#define SRST_EFUSE256 31
116
117#define SRST_GPIO0 32
118#define SRST_GPIO1 33
119#define SRST_GPIO2 34
120#define SRST_GPIO3 35
121#define SRST_PERIPH_NOC_A 36
122#define SRST_PERIPH_NOC_BUS_H 37
123#define SRST_PERIPH_NOC_P 38
124#define SRST_UART0 39
125#define SRST_UART1 40
126#define SRST_UART2 41
127#define SRST_PHYNOC 42
128#define SRST_I2C0 43
129#define SRST_I2C1 44
130#define SRST_I2C2 45
131#define SRST_I2C3 46
132
133#define SRST_PWM 48
134#define SRST_A53_GIC 49
135#define SRST_DAP 51
136#define SRST_DAP_NOC 52
137#define SRST_CRYPTO 53
138#define SRST_SGRF 54
139#define SRST_GRF 55
140#define SRST_GMAC 56
141#define SRST_PERIPH_NOC_H 58
142#define SRST_MACPHY 63
143
144#define SRST_DMA 64
145#define SRST_NANDC 68
146#define SRST_USBOTG 69
147#define SRST_OTGC 70
148#define SRST_USBHOST0 71
149#define SRST_HOST_CTRL0 72
150#define SRST_USBHOST1 73
151#define SRST_HOST_CTRL1 74
152#define SRST_USBHOST2 75
153#define SRST_HOST_CTRL2 76
154#define SRST_USBPOR0 77
155#define SRST_USBPOR1 78
156#define SRST_DDRMSCH 79
157
158#define SRST_SMART_CARD 80
159#define SRST_SDMMC 81
160#define SRST_SDIO 82
161#define SRST_EMMC 83
162#define SRST_SPI 84
163#define SRST_TSP_H 85
164#define SRST_TSP 86
165#define SRST_TSADC 87
166#define SRST_DDRPHY 88
167#define SRST_DDRPHY_P 89
168#define SRST_DDRCTRL 90
169#define SRST_DDRCTRL_P 91
170#define SRST_HOST0_ECHI 92
171#define SRST_HOST1_ECHI 93
172#define SRST_HOST2_ECHI 94
173#define SRST_VOP_NOC_A 95
174
175#define SRST_HDMI_P 96
176#define SRST_VIO_ARBI_H 97
177#define SRST_IEP_NOC_A 98
178#define SRST_VIO_NOC_H 99
179#define SRST_VOP_A 100
180#define SRST_VOP_H 101
181#define SRST_VOP_D 102
182#define SRST_UTMI0 103
183#define SRST_UTMI1 104
184#define SRST_UTMI2 105
185#define SRST_UTMI3 106
186#define SRST_RGA 107
187#define SRST_RGA_NOC_A 108
188#define SRST_RGA_A 109
189#define SRST_RGA_H 110
190#define SRST_HDCP_A 111
191
192#define SRST_VPU_A 112
193#define SRST_VPU_H 113
194#define SRST_VPU_NOC_A 116
195#define SRST_VPU_NOC_H 117
196#define SRST_RKVDEC_A 118
197#define SRST_RKVDEC_NOC_A 119
198#define SRST_RKVDEC_H 120
199#define SRST_RKVDEC_NOC_H 121
200#define SRST_RKVDEC_CORE 122
201#define SRST_RKVDEC_CABAC 123
202#define SRST_IEP_A 124
203#define SRST_IEP_H 125
204#define SRST_GPU_A 126
205#define SRST_GPU_NOC_A 127
206
207#define SRST_CORE_DBG 128
208#define SRST_DBG_P 129
209#define SRST_TIMER0 130
210#define SRST_TIMER1 131
211#define SRST_TIMER2 132
212#define SRST_TIMER3 133
213#define SRST_TIMER4 134
214#define SRST_TIMER5 135
215#define SRST_VIO_H2P 136
216#define SRST_HDMIPHY 139
217#define SRST_VDAC 140
218#define SRST_TIMER_6CH_P 141
219
220#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index c719aacef14f..9a586e2d9c91 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -86,6 +86,8 @@
86#define SCLK_USBPHY480M_SRC 122 86#define SCLK_USBPHY480M_SRC 122
87#define SCLK_PVTM_CORE 123 87#define SCLK_PVTM_CORE 123
88#define SCLK_PVTM_GPU 124 88#define SCLK_PVTM_GPU 124
89#define SCLK_CRYPTO 125
90#define SCLK_MIPIDSI_24M 126
89 91
90#define SCLK_MAC 151 92#define SCLK_MAC 151
91#define SCLK_MACREF_OUT 152 93#define SCLK_MACREF_OUT 152
@@ -164,6 +166,8 @@
164#define PCLK_DDRUPCTL1 366 166#define PCLK_DDRUPCTL1 366
165#define PCLK_PUBL1 367 167#define PCLK_PUBL1 367
166#define PCLK_WDT 368 168#define PCLK_WDT 368
169#define PCLK_EFUSE256 369
170#define PCLK_EFUSE1024 370
167 171
168/* hclk gates */ 172/* hclk gates */
169#define HCLK_GPS 448 173#define HCLK_GPS 448
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 00:59:50 -0400