diff options
author | Rick Chen <rickchen36@gmail.com> | 2017-12-12 00:12:21 -0500 |
---|---|---|
committer | Greentime Hu <greentime@andestech.com> | 2018-02-21 21:44:36 -0500 |
commit | ea4625c3860ba002c83b1dffc528e1a4f0a89cf5 (patch) | |
tree | 9d3ffbbbb47f114d1b53af9e238658013a86e1bd | |
parent | 35dbb74aa752cff90e8dac1a24ed2a452aed0251 (diff) |
clocksource/drivers/atcpit100: VDSO support
VDSO needs real-time cycle count to ensure the time accuracy.
Unlike others, nds32 architecture does not define clock source,
hence VDSO needs atcpit100 offering real-time cycle count
to derive the correct time.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
-rw-r--r-- | drivers/clocksource/timer-atcpit100.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/clocksource/timer-atcpit100.c b/drivers/clocksource/timer-atcpit100.c index 2190096cffa3..5e23d7b4a722 100644 --- a/drivers/clocksource/timer-atcpit100.c +++ b/drivers/clocksource/timer-atcpit100.c | |||
@@ -18,6 +18,9 @@ | |||
18 | #include <linux/of_irq.h> | 18 | #include <linux/of_irq.h> |
19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
20 | #include "timer-of.h" | 20 | #include "timer-of.h" |
21 | #ifdef CONFIG_NDS32 | ||
22 | #include <asm/vdso_timer_info.h> | ||
23 | #endif | ||
21 | 24 | ||
22 | /* | 25 | /* |
23 | * Definition of register offsets | 26 | * Definition of register offsets |
@@ -204,6 +207,17 @@ static u64 notrace atcpit100_timer_sched_read(void) | |||
204 | return ~readl(timer_of_base(&to) + CH1_CNT); | 207 | return ~readl(timer_of_base(&to) + CH1_CNT); |
205 | } | 208 | } |
206 | 209 | ||
210 | #ifdef CONFIG_NDS32 | ||
211 | static void fill_vdso_need_info(struct device_node *node) | ||
212 | { | ||
213 | struct resource timer_res; | ||
214 | of_address_to_resource(node, 0, &timer_res); | ||
215 | timer_info.mapping_base = (unsigned long)timer_res.start; | ||
216 | timer_info.cycle_count_down = true; | ||
217 | timer_info.cycle_count_reg_offset = CH1_CNT; | ||
218 | } | ||
219 | #endif | ||
220 | |||
207 | static int __init atcpit100_timer_init(struct device_node *node) | 221 | static int __init atcpit100_timer_init(struct device_node *node) |
208 | { | 222 | { |
209 | int ret; | 223 | int ret; |
@@ -242,6 +256,10 @@ static int __init atcpit100_timer_init(struct device_node *node) | |||
242 | val = readl(base + INT_EN); | 256 | val = readl(base + INT_EN); |
243 | writel(val | CH0INT0EN, base + INT_EN); | 257 | writel(val | CH0INT0EN, base + INT_EN); |
244 | 258 | ||
259 | #ifdef CONFIG_NDS32 | ||
260 | fill_vdso_need_info(node); | ||
261 | #endif | ||
262 | |||
245 | return ret; | 263 | return ret; |
246 | } | 264 | } |
247 | 265 | ||