diff options
author | Javier Martinez Canillas <javier.martinez@collabora.co.uk> | 2015-01-23 23:25:35 -0500 |
---|---|---|
committer | Kukjin Kim <kgene@kernel.org> | 2015-01-28 18:52:23 -0500 |
commit | ea08de16eb1ba2052ce2db4b58b62a2ec33357a3 (patch) | |
tree | 03f35d04221655f6289313418bf27243a9e01293 | |
parent | 8856010029985ba4d63a8942deb7f9e780285dd2 (diff) |
ARM: dts: Add DISP1 power domain for exynos5420
The DISP1 power domain on Exynos5420 SoC includes the FIMD1, MIXER
and HDMI modules. Add a device node for this power domain and mark
these modules as consumer of the DISP1 power domain.
When a power domain is powered on and off, the input clocks of the
devices attached to it are reparented. So a reference to the input
and parent clocks of the devices are needed to manage that.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
-rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 03ef2481c640..a0a3b2829208 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi | |||
@@ -274,6 +274,20 @@ | |||
274 | #power-domain-cells = <0>; | 274 | #power-domain-cells = <0>; |
275 | }; | 275 | }; |
276 | 276 | ||
277 | disp_pd: power-domain@100440C0 { | ||
278 | compatible = "samsung,exynos4210-pd"; | ||
279 | reg = <0x100440C0 0x20>; | ||
280 | #power-domain-cells = <0>; | ||
281 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>, | ||
282 | <&clock CLK_MOUT_USER_ACLK200_DISP1>, | ||
283 | <&clock CLK_MOUT_SW_ACLK300>, | ||
284 | <&clock CLK_MOUT_USER_ACLK300_DISP1>, | ||
285 | <&clock CLK_MOUT_SW_ACLK400>, | ||
286 | <&clock CLK_MOUT_USER_ACLK400_DISP1>; | ||
287 | clock-names = "oscclk", "pclk0", "clk0", | ||
288 | "pclk1", "clk1", "pclk2", "clk2"; | ||
289 | }; | ||
290 | |||
277 | pinctrl_0: pinctrl@13400000 { | 291 | pinctrl_0: pinctrl@13400000 { |
278 | compatible = "samsung,exynos5420-pinctrl"; | 292 | compatible = "samsung,exynos5420-pinctrl"; |
279 | reg = <0x13400000 0x1000>; | 293 | reg = <0x13400000 0x1000>; |
@@ -541,6 +555,7 @@ | |||
541 | fimd: fimd@14400000 { | 555 | fimd: fimd@14400000 { |
542 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; | 556 | clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; |
543 | clock-names = "sclk_fimd", "fimd"; | 557 | clock-names = "sclk_fimd", "fimd"; |
558 | power-domains = <&disp_pd>; | ||
544 | }; | 559 | }; |
545 | 560 | ||
546 | adc: adc@12D10000 { | 561 | adc: adc@12D10000 { |
@@ -714,6 +729,7 @@ | |||
714 | phy = <&hdmiphy>; | 729 | phy = <&hdmiphy>; |
715 | samsung,syscon-phandle = <&pmu_system_controller>; | 730 | samsung,syscon-phandle = <&pmu_system_controller>; |
716 | status = "disabled"; | 731 | status = "disabled"; |
732 | power-domains = <&disp_pd>; | ||
717 | }; | 733 | }; |
718 | 734 | ||
719 | hdmiphy: hdmiphy@145D0000 { | 735 | hdmiphy: hdmiphy@145D0000 { |
@@ -726,6 +742,7 @@ | |||
726 | interrupts = <0 94 0>; | 742 | interrupts = <0 94 0>; |
727 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; | 743 | clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>; |
728 | clock-names = "mixer", "sclk_hdmi"; | 744 | clock-names = "mixer", "sclk_hdmi"; |
745 | power-domains = <&disp_pd>; | ||
729 | }; | 746 | }; |
730 | 747 | ||
731 | gsc_0: video-scaler@13e00000 { | 748 | gsc_0: video-scaler@13e00000 { |