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authorEmily Deng <Emily.Deng@amd.com>2016-08-07 23:36:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-08-08 14:33:22 -0400
commite9ed3a67cd1bfd8d0d0dc4968a36f6ea4db2d45a (patch)
tree482fbe507fc3537a91ed67bef6df08a730c82a57
parent048a5b76d2ba40adedb98a987bb15a9cc1f0a62b (diff)
drm/amdgpu: Define virtual display ip blocks.
For virtual display feature, define virtual display ip blocks, and set dce_virtual_ip_funcs to DCE block. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c341
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c282
2 files changed, 623 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 4efc901f658c..edcc14287d2d 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -67,6 +67,7 @@
67 67
68#include "amdgpu_amdkfd.h" 68#include "amdgpu_amdkfd.h"
69#include "amdgpu_powerplay.h" 69#include "amdgpu_powerplay.h"
70#include "dce_virtual.h"
70 71
71/* 72/*
72 * Indirect registers accessor 73 * Indirect registers accessor
@@ -1708,6 +1709,74 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
1708 }, 1709 },
1709}; 1710};
1710 1711
1712static const struct amdgpu_ip_block_version bonaire_ip_blocks_vd[] =
1713{
1714 /* ORDER MATTERS! */
1715 {
1716 .type = AMD_IP_BLOCK_TYPE_COMMON,
1717 .major = 1,
1718 .minor = 0,
1719 .rev = 0,
1720 .funcs = &cik_common_ip_funcs,
1721 },
1722 {
1723 .type = AMD_IP_BLOCK_TYPE_GMC,
1724 .major = 7,
1725 .minor = 0,
1726 .rev = 0,
1727 .funcs = &gmc_v7_0_ip_funcs,
1728 },
1729 {
1730 .type = AMD_IP_BLOCK_TYPE_IH,
1731 .major = 2,
1732 .minor = 0,
1733 .rev = 0,
1734 .funcs = &cik_ih_ip_funcs,
1735 },
1736 {
1737 .type = AMD_IP_BLOCK_TYPE_SMC,
1738 .major = 7,
1739 .minor = 0,
1740 .rev = 0,
1741 .funcs = &amdgpu_pp_ip_funcs,
1742 },
1743 {
1744 .type = AMD_IP_BLOCK_TYPE_DCE,
1745 .major = 8,
1746 .minor = 2,
1747 .rev = 0,
1748 .funcs = &dce_virtual_ip_funcs,
1749 },
1750 {
1751 .type = AMD_IP_BLOCK_TYPE_GFX,
1752 .major = 7,
1753 .minor = 2,
1754 .rev = 0,
1755 .funcs = &gfx_v7_0_ip_funcs,
1756 },
1757 {
1758 .type = AMD_IP_BLOCK_TYPE_SDMA,
1759 .major = 2,
1760 .minor = 0,
1761 .rev = 0,
1762 .funcs = &cik_sdma_ip_funcs,
1763 },
1764 {
1765 .type = AMD_IP_BLOCK_TYPE_UVD,
1766 .major = 4,
1767 .minor = 2,
1768 .rev = 0,
1769 .funcs = &uvd_v4_2_ip_funcs,
1770 },
1771 {
1772 .type = AMD_IP_BLOCK_TYPE_VCE,
1773 .major = 2,
1774 .minor = 0,
1775 .rev = 0,
1776 .funcs = &vce_v2_0_ip_funcs,
1777 },
1778};
1779
1711static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = 1780static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
1712{ 1781{
1713 /* ORDER MATTERS! */ 1782 /* ORDER MATTERS! */
@@ -1776,6 +1845,74 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
1776 }, 1845 },
1777}; 1846};
1778 1847
1848static const struct amdgpu_ip_block_version hawaii_ip_blocks_vd[] =
1849{
1850 /* ORDER MATTERS! */
1851 {
1852 .type = AMD_IP_BLOCK_TYPE_COMMON,
1853 .major = 1,
1854 .minor = 0,
1855 .rev = 0,
1856 .funcs = &cik_common_ip_funcs,
1857 },
1858 {
1859 .type = AMD_IP_BLOCK_TYPE_GMC,
1860 .major = 7,
1861 .minor = 0,
1862 .rev = 0,
1863 .funcs = &gmc_v7_0_ip_funcs,
1864 },
1865 {
1866 .type = AMD_IP_BLOCK_TYPE_IH,
1867 .major = 2,
1868 .minor = 0,
1869 .rev = 0,
1870 .funcs = &cik_ih_ip_funcs,
1871 },
1872 {
1873 .type = AMD_IP_BLOCK_TYPE_SMC,
1874 .major = 7,
1875 .minor = 0,
1876 .rev = 0,
1877 .funcs = &amdgpu_pp_ip_funcs,
1878 },
1879 {
1880 .type = AMD_IP_BLOCK_TYPE_DCE,
1881 .major = 8,
1882 .minor = 5,
1883 .rev = 0,
1884 .funcs = &dce_virtual_ip_funcs,
1885 },
1886 {
1887 .type = AMD_IP_BLOCK_TYPE_GFX,
1888 .major = 7,
1889 .minor = 3,
1890 .rev = 0,
1891 .funcs = &gfx_v7_0_ip_funcs,
1892 },
1893 {
1894 .type = AMD_IP_BLOCK_TYPE_SDMA,
1895 .major = 2,
1896 .minor = 0,
1897 .rev = 0,
1898 .funcs = &cik_sdma_ip_funcs,
1899 },
1900 {
1901 .type = AMD_IP_BLOCK_TYPE_UVD,
1902 .major = 4,
1903 .minor = 2,
1904 .rev = 0,
1905 .funcs = &uvd_v4_2_ip_funcs,
1906 },
1907 {
1908 .type = AMD_IP_BLOCK_TYPE_VCE,
1909 .major = 2,
1910 .minor = 0,
1911 .rev = 0,
1912 .funcs = &vce_v2_0_ip_funcs,
1913 },
1914};
1915
1779static const struct amdgpu_ip_block_version kabini_ip_blocks[] = 1916static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
1780{ 1917{
1781 /* ORDER MATTERS! */ 1918 /* ORDER MATTERS! */
@@ -1844,6 +1981,74 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
1844 }, 1981 },
1845}; 1982};
1846 1983
1984static const struct amdgpu_ip_block_version kabini_ip_blocks_vd[] =
1985{
1986 /* ORDER MATTERS! */
1987 {
1988 .type = AMD_IP_BLOCK_TYPE_COMMON,
1989 .major = 1,
1990 .minor = 0,
1991 .rev = 0,
1992 .funcs = &cik_common_ip_funcs,
1993 },
1994 {
1995 .type = AMD_IP_BLOCK_TYPE_GMC,
1996 .major = 7,
1997 .minor = 0,
1998 .rev = 0,
1999 .funcs = &gmc_v7_0_ip_funcs,
2000 },
2001 {
2002 .type = AMD_IP_BLOCK_TYPE_IH,
2003 .major = 2,
2004 .minor = 0,
2005 .rev = 0,
2006 .funcs = &cik_ih_ip_funcs,
2007 },
2008 {
2009 .type = AMD_IP_BLOCK_TYPE_SMC,
2010 .major = 7,
2011 .minor = 0,
2012 .rev = 0,
2013 .funcs = &amdgpu_pp_ip_funcs,
2014 },
2015 {
2016 .type = AMD_IP_BLOCK_TYPE_DCE,
2017 .major = 8,
2018 .minor = 3,
2019 .rev = 0,
2020 .funcs = &dce_virtual_ip_funcs,
2021 },
2022 {
2023 .type = AMD_IP_BLOCK_TYPE_GFX,
2024 .major = 7,
2025 .minor = 2,
2026 .rev = 0,
2027 .funcs = &gfx_v7_0_ip_funcs,
2028 },
2029 {
2030 .type = AMD_IP_BLOCK_TYPE_SDMA,
2031 .major = 2,
2032 .minor = 0,
2033 .rev = 0,
2034 .funcs = &cik_sdma_ip_funcs,
2035 },
2036 {
2037 .type = AMD_IP_BLOCK_TYPE_UVD,
2038 .major = 4,
2039 .minor = 2,
2040 .rev = 0,
2041 .funcs = &uvd_v4_2_ip_funcs,
2042 },
2043 {
2044 .type = AMD_IP_BLOCK_TYPE_VCE,
2045 .major = 2,
2046 .minor = 0,
2047 .rev = 0,
2048 .funcs = &vce_v2_0_ip_funcs,
2049 },
2050};
2051
1847static const struct amdgpu_ip_block_version mullins_ip_blocks[] = 2052static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
1848{ 2053{
1849 /* ORDER MATTERS! */ 2054 /* ORDER MATTERS! */
@@ -1912,6 +2117,74 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
1912 }, 2117 },
1913}; 2118};
1914 2119
2120static const struct amdgpu_ip_block_version mullins_ip_blocks_vd[] =
2121{
2122 /* ORDER MATTERS! */
2123 {
2124 .type = AMD_IP_BLOCK_TYPE_COMMON,
2125 .major = 1,
2126 .minor = 0,
2127 .rev = 0,
2128 .funcs = &cik_common_ip_funcs,
2129 },
2130 {
2131 .type = AMD_IP_BLOCK_TYPE_GMC,
2132 .major = 7,
2133 .minor = 0,
2134 .rev = 0,
2135 .funcs = &gmc_v7_0_ip_funcs,
2136 },
2137 {
2138 .type = AMD_IP_BLOCK_TYPE_IH,
2139 .major = 2,
2140 .minor = 0,
2141 .rev = 0,
2142 .funcs = &cik_ih_ip_funcs,
2143 },
2144 {
2145 .type = AMD_IP_BLOCK_TYPE_SMC,
2146 .major = 7,
2147 .minor = 0,
2148 .rev = 0,
2149 .funcs = &amdgpu_pp_ip_funcs,
2150 },
2151 {
2152 .type = AMD_IP_BLOCK_TYPE_DCE,
2153 .major = 8,
2154 .minor = 3,
2155 .rev = 0,
2156 .funcs = &dce_virtual_ip_funcs,
2157 },
2158 {
2159 .type = AMD_IP_BLOCK_TYPE_GFX,
2160 .major = 7,
2161 .minor = 2,
2162 .rev = 0,
2163 .funcs = &gfx_v7_0_ip_funcs,
2164 },
2165 {
2166 .type = AMD_IP_BLOCK_TYPE_SDMA,
2167 .major = 2,
2168 .minor = 0,
2169 .rev = 0,
2170 .funcs = &cik_sdma_ip_funcs,
2171 },
2172 {
2173 .type = AMD_IP_BLOCK_TYPE_UVD,
2174 .major = 4,
2175 .minor = 2,
2176 .rev = 0,
2177 .funcs = &uvd_v4_2_ip_funcs,
2178 },
2179 {
2180 .type = AMD_IP_BLOCK_TYPE_VCE,
2181 .major = 2,
2182 .minor = 0,
2183 .rev = 0,
2184 .funcs = &vce_v2_0_ip_funcs,
2185 },
2186};
2187
1915static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = 2188static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
1916{ 2189{
1917 /* ORDER MATTERS! */ 2190 /* ORDER MATTERS! */
@@ -1980,6 +2253,74 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
1980 }, 2253 },
1981}; 2254};
1982 2255
2256static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
2257{
2258 /* ORDER MATTERS! */
2259 {
2260 .type = AMD_IP_BLOCK_TYPE_COMMON,
2261 .major = 1,
2262 .minor = 0,
2263 .rev = 0,
2264 .funcs = &cik_common_ip_funcs,
2265 },
2266 {
2267 .type = AMD_IP_BLOCK_TYPE_GMC,
2268 .major = 7,
2269 .minor = 0,
2270 .rev = 0,
2271 .funcs = &gmc_v7_0_ip_funcs,
2272 },
2273 {
2274 .type = AMD_IP_BLOCK_TYPE_IH,
2275 .major = 2,
2276 .minor = 0,
2277 .rev = 0,
2278 .funcs = &cik_ih_ip_funcs,
2279 },
2280 {
2281 .type = AMD_IP_BLOCK_TYPE_SMC,
2282 .major = 7,
2283 .minor = 0,
2284 .rev = 0,
2285 .funcs = &amdgpu_pp_ip_funcs,
2286 },
2287 {
2288 .type = AMD_IP_BLOCK_TYPE_DCE,
2289 .major = 8,
2290 .minor = 1,
2291 .rev = 0,
2292 .funcs = &dce_virtual_ip_funcs,
2293 },
2294 {
2295 .type = AMD_IP_BLOCK_TYPE_GFX,
2296 .major = 7,
2297 .minor = 1,
2298 .rev = 0,
2299 .funcs = &gfx_v7_0_ip_funcs,
2300 },
2301 {
2302 .type = AMD_IP_BLOCK_TYPE_SDMA,
2303 .major = 2,
2304 .minor = 0,
2305 .rev = 0,
2306 .funcs = &cik_sdma_ip_funcs,
2307 },
2308 {
2309 .type = AMD_IP_BLOCK_TYPE_UVD,
2310 .major = 4,
2311 .minor = 2,
2312 .rev = 0,
2313 .funcs = &uvd_v4_2_ip_funcs,
2314 },
2315 {
2316 .type = AMD_IP_BLOCK_TYPE_VCE,
2317 .major = 2,
2318 .minor = 0,
2319 .rev = 0,
2320 .funcs = &vce_v2_0_ip_funcs,
2321 },
2322};
2323
1983int cik_set_ip_blocks(struct amdgpu_device *adev) 2324int cik_set_ip_blocks(struct amdgpu_device *adev)
1984{ 2325{
1985 switch (adev->asic_type) { 2326 switch (adev->asic_type) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 8f37066adcee..ff78b5a36143 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -77,6 +77,7 @@
77#if defined(CONFIG_DRM_AMD_ACP) 77#if defined(CONFIG_DRM_AMD_ACP)
78#include "amdgpu_acp.h" 78#include "amdgpu_acp.h"
79#endif 79#endif
80#include "dce_virtual.h"
80 81
81MODULE_FIRMWARE("amdgpu/polaris10_smc.bin"); 82MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
82MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin"); 83MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
@@ -890,6 +891,74 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
890 }, 891 },
891}; 892};
892 893
894static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] =
895{
896 /* ORDER MATTERS! */
897 {
898 .type = AMD_IP_BLOCK_TYPE_COMMON,
899 .major = 2,
900 .minor = 0,
901 .rev = 0,
902 .funcs = &vi_common_ip_funcs,
903 },
904 {
905 .type = AMD_IP_BLOCK_TYPE_GMC,
906 .major = 8,
907 .minor = 0,
908 .rev = 0,
909 .funcs = &gmc_v8_0_ip_funcs,
910 },
911 {
912 .type = AMD_IP_BLOCK_TYPE_IH,
913 .major = 3,
914 .minor = 0,
915 .rev = 0,
916 .funcs = &tonga_ih_ip_funcs,
917 },
918 {
919 .type = AMD_IP_BLOCK_TYPE_SMC,
920 .major = 7,
921 .minor = 1,
922 .rev = 0,
923 .funcs = &amdgpu_pp_ip_funcs,
924 },
925 {
926 .type = AMD_IP_BLOCK_TYPE_DCE,
927 .major = 10,
928 .minor = 0,
929 .rev = 0,
930 .funcs = &dce_virtual_ip_funcs,
931 },
932 {
933 .type = AMD_IP_BLOCK_TYPE_GFX,
934 .major = 8,
935 .minor = 0,
936 .rev = 0,
937 .funcs = &gfx_v8_0_ip_funcs,
938 },
939 {
940 .type = AMD_IP_BLOCK_TYPE_SDMA,
941 .major = 3,
942 .minor = 0,
943 .rev = 0,
944 .funcs = &sdma_v3_0_ip_funcs,
945 },
946 {
947 .type = AMD_IP_BLOCK_TYPE_UVD,
948 .major = 5,
949 .minor = 0,
950 .rev = 0,
951 .funcs = &uvd_v5_0_ip_funcs,
952 },
953 {
954 .type = AMD_IP_BLOCK_TYPE_VCE,
955 .major = 3,
956 .minor = 0,
957 .rev = 0,
958 .funcs = &vce_v3_0_ip_funcs,
959 },
960};
961
893static const struct amdgpu_ip_block_version fiji_ip_blocks[] = 962static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
894{ 963{
895 /* ORDER MATTERS! */ 964 /* ORDER MATTERS! */
@@ -958,6 +1027,74 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
958 }, 1027 },
959}; 1028};
960 1029
1030static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] =
1031{
1032 /* ORDER MATTERS! */
1033 {
1034 .type = AMD_IP_BLOCK_TYPE_COMMON,
1035 .major = 2,
1036 .minor = 0,
1037 .rev = 0,
1038 .funcs = &vi_common_ip_funcs,
1039 },
1040 {
1041 .type = AMD_IP_BLOCK_TYPE_GMC,
1042 .major = 8,
1043 .minor = 5,
1044 .rev = 0,
1045 .funcs = &gmc_v8_0_ip_funcs,
1046 },
1047 {
1048 .type = AMD_IP_BLOCK_TYPE_IH,
1049 .major = 3,
1050 .minor = 0,
1051 .rev = 0,
1052 .funcs = &tonga_ih_ip_funcs,
1053 },
1054 {
1055 .type = AMD_IP_BLOCK_TYPE_SMC,
1056 .major = 7,
1057 .minor = 1,
1058 .rev = 0,
1059 .funcs = &amdgpu_pp_ip_funcs,
1060 },
1061 {
1062 .type = AMD_IP_BLOCK_TYPE_DCE,
1063 .major = 10,
1064 .minor = 1,
1065 .rev = 0,
1066 .funcs = &dce_virtual_ip_funcs,
1067 },
1068 {
1069 .type = AMD_IP_BLOCK_TYPE_GFX,
1070 .major = 8,
1071 .minor = 0,
1072 .rev = 0,
1073 .funcs = &gfx_v8_0_ip_funcs,
1074 },
1075 {
1076 .type = AMD_IP_BLOCK_TYPE_SDMA,
1077 .major = 3,
1078 .minor = 0,
1079 .rev = 0,
1080 .funcs = &sdma_v3_0_ip_funcs,
1081 },
1082 {
1083 .type = AMD_IP_BLOCK_TYPE_UVD,
1084 .major = 6,
1085 .minor = 0,
1086 .rev = 0,
1087 .funcs = &uvd_v6_0_ip_funcs,
1088 },
1089 {
1090 .type = AMD_IP_BLOCK_TYPE_VCE,
1091 .major = 3,
1092 .minor = 0,
1093 .rev = 0,
1094 .funcs = &vce_v3_0_ip_funcs,
1095 },
1096};
1097
961static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = 1098static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
962{ 1099{
963 /* ORDER MATTERS! */ 1100 /* ORDER MATTERS! */
@@ -1026,6 +1163,74 @@ static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
1026 }, 1163 },
1027}; 1164};
1028 1165
1166static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] =
1167{
1168 /* ORDER MATTERS! */
1169 {
1170 .type = AMD_IP_BLOCK_TYPE_COMMON,
1171 .major = 2,
1172 .minor = 0,
1173 .rev = 0,
1174 .funcs = &vi_common_ip_funcs,
1175 },
1176 {
1177 .type = AMD_IP_BLOCK_TYPE_GMC,
1178 .major = 8,
1179 .minor = 1,
1180 .rev = 0,
1181 .funcs = &gmc_v8_0_ip_funcs,
1182 },
1183 {
1184 .type = AMD_IP_BLOCK_TYPE_IH,
1185 .major = 3,
1186 .minor = 1,
1187 .rev = 0,
1188 .funcs = &tonga_ih_ip_funcs,
1189 },
1190 {
1191 .type = AMD_IP_BLOCK_TYPE_SMC,
1192 .major = 7,
1193 .minor = 2,
1194 .rev = 0,
1195 .funcs = &amdgpu_pp_ip_funcs,
1196 },
1197 {
1198 .type = AMD_IP_BLOCK_TYPE_DCE,
1199 .major = 11,
1200 .minor = 2,
1201 .rev = 0,
1202 .funcs = &dce_virtual_ip_funcs,
1203 },
1204 {
1205 .type = AMD_IP_BLOCK_TYPE_GFX,
1206 .major = 8,
1207 .minor = 0,
1208 .rev = 0,
1209 .funcs = &gfx_v8_0_ip_funcs,
1210 },
1211 {
1212 .type = AMD_IP_BLOCK_TYPE_SDMA,
1213 .major = 3,
1214 .minor = 1,
1215 .rev = 0,
1216 .funcs = &sdma_v3_0_ip_funcs,
1217 },
1218 {
1219 .type = AMD_IP_BLOCK_TYPE_UVD,
1220 .major = 6,
1221 .minor = 3,
1222 .rev = 0,
1223 .funcs = &uvd_v6_0_ip_funcs,
1224 },
1225 {
1226 .type = AMD_IP_BLOCK_TYPE_VCE,
1227 .major = 3,
1228 .minor = 4,
1229 .rev = 0,
1230 .funcs = &vce_v3_0_ip_funcs,
1231 },
1232};
1233
1029static const struct amdgpu_ip_block_version cz_ip_blocks[] = 1234static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1030{ 1235{
1031 /* ORDER MATTERS! */ 1236 /* ORDER MATTERS! */
@@ -1103,6 +1308,83 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1103#endif 1308#endif
1104}; 1309};
1105 1310
1311static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =
1312{
1313 /* ORDER MATTERS! */
1314 {
1315 .type = AMD_IP_BLOCK_TYPE_COMMON,
1316 .major = 2,
1317 .minor = 0,
1318 .rev = 0,
1319 .funcs = &vi_common_ip_funcs,
1320 },
1321 {
1322 .type = AMD_IP_BLOCK_TYPE_GMC,
1323 .major = 8,
1324 .minor = 0,
1325 .rev = 0,
1326 .funcs = &gmc_v8_0_ip_funcs,
1327 },
1328 {
1329 .type = AMD_IP_BLOCK_TYPE_IH,
1330 .major = 3,
1331 .minor = 0,
1332 .rev = 0,
1333 .funcs = &cz_ih_ip_funcs,
1334 },
1335 {
1336 .type = AMD_IP_BLOCK_TYPE_SMC,
1337 .major = 8,
1338 .minor = 0,
1339 .rev = 0,
1340 .funcs = &amdgpu_pp_ip_funcs
1341 },
1342 {
1343 .type = AMD_IP_BLOCK_TYPE_DCE,
1344 .major = 11,
1345 .minor = 0,
1346 .rev = 0,
1347 .funcs = &dce_virtual_ip_funcs,
1348 },
1349 {
1350 .type = AMD_IP_BLOCK_TYPE_GFX,
1351 .major = 8,
1352 .minor = 0,
1353 .rev = 0,
1354 .funcs = &gfx_v8_0_ip_funcs,
1355 },
1356 {
1357 .type = AMD_IP_BLOCK_TYPE_SDMA,
1358 .major = 3,
1359 .minor = 0,
1360 .rev = 0,
1361 .funcs = &sdma_v3_0_ip_funcs,
1362 },
1363 {
1364 .type = AMD_IP_BLOCK_TYPE_UVD,
1365 .major = 6,
1366 .minor = 0,
1367 .rev = 0,
1368 .funcs = &uvd_v6_0_ip_funcs,
1369 },
1370 {
1371 .type = AMD_IP_BLOCK_TYPE_VCE,
1372 .major = 3,
1373 .minor = 0,
1374 .rev = 0,
1375 .funcs = &vce_v3_0_ip_funcs,
1376 },
1377#if defined(CONFIG_DRM_AMD_ACP)
1378 {
1379 .type = AMD_IP_BLOCK_TYPE_ACP,
1380 .major = 2,
1381 .minor = 2,
1382 .rev = 0,
1383 .funcs = &acp_ip_funcs,
1384 },
1385#endif
1386};
1387
1106int vi_set_ip_blocks(struct amdgpu_device *adev) 1388int vi_set_ip_blocks(struct amdgpu_device *adev)
1107{ 1389{
1108 switch (adev->asic_type) { 1390 switch (adev->asic_type) {
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