diff options
author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-04-29 09:25:42 -0400 |
---|---|---|
committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-05-01 04:32:39 -0400 |
commit | e99833448c5fa198a120db6d7087dd17149dc273 (patch) | |
tree | f8bc547c1e6947cee2d20c1069e8694079f11e93 | |
parent | 11a6f6abd74ab80865023200ca33515f6db43d63 (diff) |
powerpc/mm/radix: Add partition table format & callback
Add structs and #defines related to the radix MMU partition table
format. We also add a ppc_md callback for updating a partition table
entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r-- | arch/powerpc/include/asm/book3s/64/mmu.h | 31 | ||||
-rw-r--r-- | arch/powerpc/include/asm/machdep.h | 1 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 1 |
3 files changed, 31 insertions, 2 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h index aadb0bbc5c71..b86786f2521c 100644 --- a/arch/powerpc/include/asm/book3s/64/mmu.h +++ b/arch/powerpc/include/asm/book3s/64/mmu.h | |||
@@ -21,12 +21,39 @@ struct mmu_psize_def { | |||
21 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | 21 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; |
22 | #endif /* __ASSEMBLY__ */ | 22 | #endif /* __ASSEMBLY__ */ |
23 | 23 | ||
24 | #ifdef CONFIG_PPC_STD_MMU_64 | ||
25 | /* 64-bit classic hash table MMU */ | 24 | /* 64-bit classic hash table MMU */ |
26 | #include <asm/book3s/64/mmu-hash.h> | 25 | #include <asm/book3s/64/mmu-hash.h> |
27 | #endif | ||
28 | 26 | ||
29 | #ifndef __ASSEMBLY__ | 27 | #ifndef __ASSEMBLY__ |
28 | /* | ||
29 | * ISA 3.0 partiton and process table entry format | ||
30 | */ | ||
31 | struct prtb_entry { | ||
32 | __be64 prtb0; | ||
33 | __be64 prtb1; | ||
34 | }; | ||
35 | extern struct prtb_entry *process_tb; | ||
36 | |||
37 | struct patb_entry { | ||
38 | __be64 patb0; | ||
39 | __be64 patb1; | ||
40 | }; | ||
41 | extern struct patb_entry *partition_tb; | ||
42 | |||
43 | #define PATB_HR (1UL << 63) | ||
44 | #define PATB_GR (1UL << 63) | ||
45 | #define RPDB_MASK 0x0ffffffffffff00fUL | ||
46 | #define RPDB_SHIFT (1UL << 8) | ||
47 | /* | ||
48 | * Limit process table to PAGE_SIZE table. This | ||
49 | * also limit the max pid we can support. | ||
50 | * MAX_USER_CONTEXT * 16 bytes of space. | ||
51 | */ | ||
52 | #define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4) | ||
53 | /* | ||
54 | * Power9 currently only support 64K partition table size. | ||
55 | */ | ||
56 | #define PATB_SIZE_SHIFT 16 | ||
30 | 57 | ||
31 | typedef unsigned long mm_context_id_t; | 58 | typedef unsigned long mm_context_id_t; |
32 | struct spinlock; | 59 | struct spinlock; |
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index fd22442d30a9..6bdcd0da9e21 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h | |||
@@ -256,6 +256,7 @@ struct machdep_calls { | |||
256 | #ifdef CONFIG_ARCH_RANDOM | 256 | #ifdef CONFIG_ARCH_RANDOM |
257 | int (*get_random_seed)(unsigned long *v); | 257 | int (*get_random_seed)(unsigned long *v); |
258 | #endif | 258 | #endif |
259 | int (*update_partition_table)(u64); | ||
259 | }; | 260 | }; |
260 | 261 | ||
261 | extern void e500_idle(void); | 262 | extern void e500_idle(void); |
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index cf09c6eb5ee7..47082bcbf1e5 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -587,6 +587,7 @@ | |||
587 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ | 587 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ |
588 | #endif | 588 | #endif |
589 | #define SPRN_TIR 0x1BE /* Thread Identification Register */ | 589 | #define SPRN_TIR 0x1BE /* Thread Identification Register */ |
590 | #define SPRN_PTCR 0x1D0 /* Partition table control Register */ | ||
590 | #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */ | 591 | #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */ |
591 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ | 592 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ |
592 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ | 593 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ |