drm/i915: Fix 66 MHz LVDS SSC freq for gen2

Store the SSC refclock frequency in kHz to get more accuracy. Currently
we're pretending that 66 MHz is ~66000 kHz, when in fact it is actually
~66667 kHz. By storing the less rounded kHz value we get a much better
accuracy for out pixel clock calculations.

Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 10 insertions, 11 deletions

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index e4fba39631a5..f88e5079a3f5 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -327,12 +327,12 @@ static int intel_bios_ssc_frequency(struct drm_device *dev,
 {
         switch (INTEL_INFO(dev)->gen) {
         case 2:
-                return alternate ? 66 : 48;
+                return alternate ? 66667 : 48000;
         case 3:
         case 4:
-                return alternate ? 100 : 96;
+                return alternate ? 100000 : 96000;
         default:
-                return alternate ? 100 : 120;
+                return alternate ? 100000 : 120000;
         }
 }
 
@@ -796,7 +796,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
          */
         dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
                         !HAS_PCH_SPLIT(dev));
-        DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);
+        DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
 
         for (port = PORT_A; port < I915_MAX_PORTS; port++) {
                 struct ddi_vbt_port_info *info =
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 14e0b80c5641..9404b50ee8c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4761,9 +4761,8 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
                 refclk = 100000;
         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
-                refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
-                DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
-                              refclk / 1000);
+                refclk = dev_priv->vbt.lvds_ssc_freq;
+                DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
         } else if (!IS_GEN2(dev)) {
                 refclk = 96000;
         } else {
@@ -5909,9 +5908,9 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
         }
 
         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
-                DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
+                DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
                               dev_priv->vbt.lvds_ssc_freq);
-                return dev_priv->vbt.lvds_ssc_freq * 1000;
+                return dev_priv->vbt.lvds_ssc_freq;
         }
 
         return 120000;
@@ -6173,7 +6172,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
         factor = 21;
         if (is_lvds) {
                 if ((intel_panel_use_ssc(dev_priv) &&
-                     dev_priv->vbt.lvds_ssc_freq == 100) ||
+                     dev_priv->vbt.lvds_ssc_freq == 100000) ||
                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
                         factor = 25;
         } else if (intel_crtc->config.sdvo_tv_clock)
@@ -7888,7 +7887,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
         u32 dpll = pipe_config->dpll_hw_state.dpll;
 
         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
-                return dev_priv->vbt.lvds_ssc_freq * 1000;
+                return dev_priv->vbt.lvds_ssc_freq;
         else if (HAS_PCH_SPLIT(dev))
                 return 120000;
         else if (!IS_GEN2(dev))