Merge branch 'pci/misc' into next

* pci/misc:
  PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
  PCI: exynos: Add I/O access wrappers
  PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()

3 files changed, 184 insertions, 173 deletions

diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index ce04eb28e029..d3874f425653 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -378,6 +378,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
         struct acpi_pci_root *root;
         u32 flags, base_flags;
         acpi_handle handle = device->handle;
+        bool no_aspm = false, clear_aspm = false;
 
         root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
         if (!root)
@@ -437,27 +438,6 @@ static int acpi_pci_root_add(struct acpi_device *device,
         flags = base_flags = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
         acpi_pci_osc_support(root, flags);
 
-        /*
-         * TBD: Need PCI interface for enumeration/configuration of roots.
-         */
-
-        /*
-         * Scan the Root Bridge
-         * --------------------
-         * Must do this prior to any attempt to bind the root device, as the
-         * PCI namespace does not get created until this call is made (and
-         * thus the root bridge's pci_dev does not exist).
-         */
-        root->bus = pci_acpi_scan_root(root);
-        if (!root->bus) {
-                dev_err(&device->dev,
-                        "Bus %04x:%02x not present in PCI namespace\n",
-                        root->segment, (unsigned int)root->secondary.start);
-                result = -ENODEV;
-                goto end;
-        }
-
-        /* Indicate support for various _OSC capabilities. */
         if (pci_ext_cfg_avail())
                 flags |= OSC_EXT_PCI_CONFIG_SUPPORT;
         if (pcie_aspm_support_enabled()) {
@@ -471,7 +451,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
                 if (ACPI_FAILURE(status)) {
                         dev_info(&device->dev, "ACPI _OSC support "
                                 "notification failed, disabling PCIe ASPM\n");
-                        pcie_no_aspm();
+                        no_aspm = true;
                         flags = base_flags;
                 }
         }
@@ -503,7 +483,7 @@ static int acpi_pci_root_add(struct acpi_device *device,
                                  * We have ASPM control, but the FADT indicates
                                  * that it's unsupported. Clear it.
                                  */
-                                pcie_clear_aspm(root->bus);
+                                clear_aspm = true;
                         }
                 } else {
                         dev_info(&device->dev,
@@ -512,7 +492,14 @@ static int acpi_pci_root_add(struct acpi_device *device,
                                 acpi_format_exception(status), flags);
                         dev_info(&device->dev,
                                  "ACPI _OSC control for PCIe not granted, disabling ASPM\n");
-                        pcie_no_aspm();
+                        /*
+                         * We want to disable ASPM here, but aspm_disabled
+                         * needs to remain in its state from boot so that we
+                         * properly handle PCIe 1.1 devices.  So we set this
+                         * flag here, to defer the action until after the ACPI
+                         * root scan.
+                         */
+                        no_aspm = true;
                 }
         } else {
                 dev_info(&device->dev,
@@ -520,6 +507,33 @@ static int acpi_pci_root_add(struct acpi_device *device,
                          "(_OSC support mask: 0x%02x)\n", flags);
         }
 
+        /*
+         * TBD: Need PCI interface for enumeration/configuration of roots.
+         */
+
+        /*
+         * Scan the Root Bridge
+         * --------------------
+         * Must do this prior to any attempt to bind the root device, as the
+         * PCI namespace does not get created until this call is made (and
+         * thus the root bridge's pci_dev does not exist).
+         */
+        root->bus = pci_acpi_scan_root(root);
+        if (!root->bus) {
+                dev_err(&device->dev,
+                        "Bus %04x:%02x not present in PCI namespace\n",
+                        root->segment, (unsigned int)root->secondary.start);
+                result = -ENODEV;
+                goto end;
+        }
+
+        if (clear_aspm) {
+                dev_info(&device->dev, "Disabling ASPM (FADT indicates it is unsupported)\n");
+                pcie_clear_aspm(root->bus);
+        }
+        if (no_aspm)
+                pcie_no_aspm();
+
         pci_acpi_add_bus_pm_notifier(device, root->bus);
         if (device->wakeup.flags.run_wake)
                 device_set_run_wake(root->bus->bridge, true);
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 012ca8aec71a..94e096bb2d0a 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -91,19 +91,49 @@ struct exynos_pcie {
 #define PCIE_PHY_TRSV3_RXCDR            0x2ec
 #define PCIE_PHY_TRSV3_LVCC             0x31c
 
+static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
+{
+        writel(val, pcie->elbi_base + reg);
+}
+
+static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
+{
+        return readl(pcie->elbi_base + reg);
+}
+
+static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
+{
+        writel(val, pcie->phy_base + reg);
+}
+
+static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
+{
+        return readl(pcie->phy_base + reg);
+}
+
+static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
+{
+        writel(val, pcie->block_base + reg);
+}
+
+static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
+{
+        return readl(pcie->block_base + reg);
+}
+
 static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
 {
         u32 val;
         struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
 
         if (on) {
-                val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
+                val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
                 val |= PCIE_ELBI_SLV_DBI_ENABLE;
-                writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
+                exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
         } else {
-                val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
+                val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
                 val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
-                writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
+                exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
         }
 }
 
@@ -113,13 +143,13 @@ static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
         struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
 
         if (on) {
-                val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
+                val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
                 val |= PCIE_ELBI_SLV_DBI_ENABLE;
-                writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
+                exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
         } else {
-                val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
+                val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
                 val &= ~PCIE_ELBI_SLV_DBI_ENABLE;