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authorThierry Reding <treding@nvidia.com>2016-02-11 12:10:48 -0500
committerThierry Reding <treding@nvidia.com>2016-04-29 10:48:58 -0400
commite84fce0f8837496a48d11086829bdbe170358b7a (patch)
treee54feac1f7daf229b66025da6f9954b58c5fd377
parent16108f04799d24b6f2e1a8500db9f7df824f616e (diff)
usb: xhci: Add NVIDIA Tegra XUSB controller driver
Add support for the on-chip XUSB controller present on Tegra SoCs. This controller, when loaded with external firmware, exposes an interface compliant with xHCI. This driver loads the firmware, starts the controller, and is able to service host-specific messages sent by the controller's firmware. The controller also supports USB device mode as well as powergating of the SuperSpeed and host-controller logic when not in use, but support for these is not yet implemented. Based on work by: Ajay Gupta <ajayg@nvidia.com> Bharath Yadav <byadav@nvidia.com> Andrew Bresticker <abrestic@chromium.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat
-rw-r--r--drivers/usb/host/Kconfig9
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/xhci-tegra.c1288
3 files changed, 1298 insertions, 0 deletions
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 3050b18b2447..6acac6201af0 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -69,6 +69,15 @@ config USB_XHCI_RCAR
69 Say 'Y' to enable the support for the xHCI host controller 69 Say 'Y' to enable the support for the xHCI host controller
70 found in Renesas R-Car ARM SoCs. 70 found in Renesas R-Car ARM SoCs.
71 71
72config USB_XHCI_TEGRA
73 tristate "xHCI support for NVIDIA Tegra SoCs"
74 depends on PHY_TEGRA_XUSB
75 depends on RESET_CONTROLLER
76 select FW_LOADER
77 ---help---
78 Say 'Y' to enable the support for the xHCI host controller
79 found in NVIDIA Tegra124 and later SoCs.
80
72endif # USB_XHCI_HCD 81endif # USB_XHCI_HCD
73 82
74config USB_EHCI_HCD 83config USB_EHCI_HCD
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index a9ddd3c9ec94..6ef785b0ea8f 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_USB_XHCI_HCD) += xhci-hcd.o
68obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o 68obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
69obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o 69obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
70obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o 70obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
71obj-$(CONFIG_USB_XHCI_TEGRA) += xhci-tegra.o
71obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o 72obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o
72obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o 73obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
73obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o 74obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
new file mode 100644
index 000000000000..2860a454e30a
--- /dev/null
+++ b/drivers/usb/host/xhci-tegra.c
@@ -0,0 +1,1288 @@
1/*
2 * NVIDIA Tegra xHCI host controller driver
3 *
4 * Copyright (C) 2014 NVIDIA Corporation
5 * Copyright (C) 2014 Google, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/firmware.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/phy/phy.h>
21#include <linux/phy/tegra/xusb.h>
22#include <linux/platform_device.h>
23#include <linux/pm.h>
24#include <linux/regulator/consumer.h>
25#include <linux/reset.h>
26#include <linux/slab.h>
27
28#include "xhci.h"
29
30#define TEGRA_XHCI_SS_HIGH_SPEED 120000000
31#define TEGRA_XHCI_SS_LOW_SPEED 12000000
32
33/* FPCI CFG registers */
34#define XUSB_CFG_1 0x004
35#define XUSB_IO_SPACE_EN BIT(0)
36#define XUSB_MEM_SPACE_EN BIT(1)
37#define XUSB_BUS_MASTER_EN BIT(2)
38#define XUSB_CFG_4 0x010
39#define XUSB_BASE_ADDR_SHIFT 15
40#define XUSB_BASE_ADDR_MASK 0x1ffff
41#define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
42#define XUSB_CFG_CSB_BASE_ADDR 0x800
43
44/* FPCI mailbox registers */
45#define XUSB_CFG_ARU_MBOX_CMD 0x0e4
46#define MBOX_DEST_FALC BIT(27)
47#define MBOX_DEST_PME BIT(28)
48#define MBOX_DEST_SMI BIT(29)
49#define MBOX_DEST_XHCI BIT(30)
50#define MBOX_INT_EN BIT(31)
51#define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8
52#define CMD_DATA_SHIFT 0
53#define CMD_DATA_MASK 0xffffff
54#define CMD_TYPE_SHIFT 24
55#define CMD_TYPE_MASK 0xff
56#define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec
57#define XUSB_CFG_ARU_MBOX_OWNER 0x0f0
58#define MBOX_OWNER_NONE 0
59#define MBOX_OWNER_FW 1
60#define MBOX_OWNER_SW 2
61#define XUSB_CFG_ARU_SMI_INTR 0x428
62#define MBOX_SMI_INTR_FW_HANG BIT(1)
63#define MBOX_SMI_INTR_EN BIT(3)
64
65/* IPFS registers */
66#define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
67#define IPFS_EN_FPCI BIT(0)
68#define IPFS_XUSB_HOST_INTR_MASK_0 0x188
69#define IPFS_IP_INT_MASK BIT(16)
70#define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
71
72#define CSB_PAGE_SELECT_MASK 0x7fffff
73#define CSB_PAGE_SELECT_SHIFT 9
74#define CSB_PAGE_OFFSET_MASK 0x1ff
75#define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
76 CSB_PAGE_SELECT_MASK)
77#define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
78
79/* Falcon CSB registers */
80#define XUSB_FALC_CPUCTL 0x100
81#define CPUCTL_STARTCPU BIT(1)
82#define CPUCTL_STATE_HALTED BIT(4)
83#define CPUCTL_STATE_STOPPED BIT(5)
84#define XUSB_FALC_BOOTVEC 0x104
85#define XUSB_FALC_DMACTL 0x10c
86#define XUSB_FALC_IMFILLRNG1 0x154
87#define IMFILLRNG1_TAG_MASK 0xffff
88#define IMFILLRNG1_TAG_LO_SHIFT 0
89#define IMFILLRNG1_TAG_HI_SHIFT 16
90#define XUSB_FALC_IMFILLCTL 0x158
91
92/* MP CSB registers */
93#define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
94#define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
95#define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
96#define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
97#define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
98#define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
99#define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
100#define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
101#define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
102#define L2IMEMOP_ACTION_SHIFT 24
103#define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
104#define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
105#define XUSB_CSB_MP_APMAP 0x10181c
106#define APMAP_BOOTPATH BIT(31)
107
108#define IMEM_BLOCK_SIZE 256
109
110struct tegra_xusb_fw_header {
111 u32 boot_loadaddr_in_imem;
112 u32 boot_codedfi_offset;
113 u32 boot_codetag;
114 u32 boot_codesize;
115 u32 phys_memaddr;
116 u16 reqphys_memsize;
117 u16 alloc_phys_memsize;
118 u32 rodata_img_offset;
119 u32 rodata_section_start;
120 u32 rodata_section_end;
121 u32 main_fnaddr;
122 u32 fwimg_cksum;
123 u32 fwimg_created_time;
124 u32 imem_resident_start;
125 u32 imem_resident_end;
126 u32 idirect_start;
127 u32 idirect_end;
128 u32 l2_imem_start;
129 u32 l2_imem_end;
130 u32 version_id;
131 u8 init_ddirect;
132 u8 reserved[3];
133 u32 phys_addr_log_buffer;
134 u32 total_log_entries;
135 u32 dequeue_ptr;
136 u32 dummy_var[2];
137 u32 fwimg_len;
138 u8 magic[8];
139 u32 ss_low_power_entry_timeout;
140 u8 num_hsic_port;
141 u8 padding[139]; /* Pad to 256 bytes */
142};
143
144struct tegra_xusb_phy_type {
145 const char *name;
146 unsigned int num;
147};
148
149struct tegra_xusb_soc {
150 const char *firmware;
151 const char * const *supply_names;
152 unsigned int num_supplies;
153 const struct tegra_xusb_phy_type *phy_types;
154 unsigned int num_types;
155
156 struct {
157 struct {
158 unsigned int offset;
159 unsigned int count;
160 } usb2, ulpi, hsic, usb3;
161 } ports;
162};
163
164struct tegra_xusb {
165 struct device *dev;
166 void __iomem *regs;
167 struct usb_hcd *hcd;
168
169 struct mutex lock;
170
171 int xhci_irq;
172 int mbox_irq;
173
174 void __iomem *ipfs_base;
175 void __iomem *fpci_base;
176
177 const struct tegra_xusb_soc *soc;
178
179 struct regulator_bulk_data *supplies;
180
181 struct tegra_xusb_padctl *padctl;
182
183 struct clk *host_clk;
184 struct clk *falcon_clk;
185 struct clk *ss_clk;
186 struct clk *ss_src_clk;
187 struct clk *hs_src_clk;
188 struct clk *fs_src_clk;
189 struct clk *pll_u_480m;
190 struct clk *clk_m;
191 struct clk *pll_e;
192
193 struct reset_control *host_rst;
194 struct reset_control *ss_rst;
195
196 struct phy **phys;
197 unsigned int num_phys;
198
199 /* Firmware loading related */
200 struct {
201 size_t size;
202 void *virt;
203 dma_addr_t phys;
204 } fw;
205};
206
207static struct hc_driver __read_mostly tegra_xhci_hc_driver;
208
209static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
210{
211 return readl(tegra->fpci_base + offset);
212}
213
214static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
215 unsigned int offset)
216{
217 writel(value, tegra->fpci_base + offset);
218}
219
220static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
221{
222 return readl(tegra->ipfs_base + offset);
223}
224
225static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
226 unsigned int offset)
227{
228 writel(value, tegra->ipfs_base + offset);
229}
230
231static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
232{
233 u32 page = CSB_PAGE_SELECT(offset);
234 u32 ofs = CSB_PAGE_OFFSET(offset);
235
236 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
237
238 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
239}
240
241static void csb_writel(struct tegra_xusb *tegra, u32 value,
242 unsigned int offset)
243{
244 u32 page = CSB_PAGE_SELECT(offset);
245 u32 ofs = CSB_PAGE_OFFSET(offset);
246
247 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
248 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
249}
250
251static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
252 unsigned long rate)
253{
254 unsigned long new_parent_rate, old_parent_rate;
255 struct clk *clk = tegra->ss_src_clk;
256 unsigned int div;
257 int err;
258
259 if (clk_get_rate(clk) == rate)
260 return 0;
261
262 switch (rate) {
263 case TEGRA_XHCI_SS_HIGH_SPEED:
264 /*
265 * Reparent to PLLU_480M. Set divider first to avoid
266 * overclocking.
267 */
268 old_parent_rate = clk_get_rate(clk_get_parent(clk));
269 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
270 div = new_parent_rate / rate;
271
272 err = clk_set_rate(clk, old_parent_rate / div);
273 if (err)
274 return err;
275
276 err = clk_set_parent(clk, tegra->pll_u_480m);
277 if (err)
278 return err;
279
280 /*
281 * The rate should already be correct, but set it again just
282 * to be sure.
283 */
284 err = clk_set_rate(clk, rate);
285 if (err)
286 return err;
287
288 break;
289
290 case TEGRA_XHCI_SS_LOW_SPEED:
291 /* Reparent to CLK_M */
292 err = clk_set_parent(clk, tegra->clk_m);
293 if (err)
294 return err;
295
296 err = clk_set_rate(clk, rate);
297 if (err)
298 return err;
299
300 break;
301
302 default:
303 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
304 return -EINVAL;
305 }
306
307 if (clk_get_rate(clk) != rate) {
308 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
309 return -EINVAL;
310 }
311
312 return 0;
313}
314
315static unsigned long extract_field(u32 value, unsigned int start,
316 unsigned int count)
317{
318 return (value >> start) & ((1 << count) - 1);
319}
320
321/* Command requests from the firmware */
322enum tegra_xusb_mbox_cmd {
323 MBOX_CMD_MSG_ENABLED = 1,
324 MBOX_CMD_INC_FALC_CLOCK,
325 MBOX_CMD_DEC_FALC_CLOCK,
326 MBOX_CMD_INC_SSPI_CLOCK,
327 MBOX_CMD_DEC_SSPI_CLOCK,
328 MBOX_CMD_SET_BW, /* no ACK/NAK required */
329 MBOX_CMD_SET_SS_PWR_GATING,
330 MBOX_CMD_SET_SS_PWR_UNGATING,
331 MBOX_CMD_SAVE_DFE_CTLE_CTX,
332 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
333 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
334 MBOX_CMD_START_HSIC_IDLE,
335 MBOX_CMD_STOP_HSIC_IDLE,
336 MBOX_CMD_DBC_WAKE_STACK, /* unused */
337 MBOX_CMD_HSIC_PRETEND_CONNECT,
338 MBOX_CMD_RESET_SSPI,
339 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
340 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
341
342 MBOX_CMD_MAX,
343
344 /* Response message to above commands */
345 MBOX_CMD_ACK = 128,
346 MBOX_CMD_NAK
347};
348
349static const char * const mbox_cmd_name[] = {
350 [ 1] = "MSG_ENABLE",
351 [ 2] = "INC_FALCON_CLOCK",
352 [ 3] = "DEC_FALCON_CLOCK",
353 [ 4] = "INC_SSPI_CLOCK",
354 [ 5] = "DEC_SSPI_CLOCK",
355 [ 6] = "SET_BW",
356 [ 7] = "SET_SS_PWR_GATING",
357 [ 8] = "SET_SS_PWR_UNGATING",
358 [ 9] = "SAVE_DFE_CTLE_CTX",
359 [ 10] = "AIRPLANE_MODE_ENABLED",
360 [ 11] = "AIRPLANE_MODE_DISABLED",
361 [ 12] = "START_HSIC_IDLE",
362 [ 13] = "STOP_HSIC_IDLE",
363 [ 14] = "DBC_WAKE_STACK",
364 [ 15] = "HSIC_PRETEND_CONNECT",
365 [ 16] = "RESET_SSPI",
366 [ 17] = "DISABLE_SS_LFPS_DETECTION",
367 [ 18] = "ENABLE_SS_LFPS_DETECTION",
368 [128] = "ACK",
369 [129] = "NAK",
370};
371
372struct tegra_xusb_mbox_msg {
373 u32 cmd;
374 u32 data;
375};
376
377static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
378{
379 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
380 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
381}
382static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
383 u32 value)
384{
385 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
386 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
387}
388
389static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
390{
391 switch (cmd) {
392 case MBOX_CMD_SET_BW:
393 case MBOX_CMD_ACK:
394 case MBOX_CMD_NAK:
395 return false;
396
397 default:
398 return true;
399 }
400}
401
402static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
403 const struct tegra_xusb_mbox_msg *msg)
404{
405 bool wait_for_idle = false;
406 u32 value;
407
408 /*
409 * Acquire the mailbox. The firmware still owns the mailbox for
410 * ACK/NAK messages.
411 */
412 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
413 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
414 if (value != MBOX_OWNER_NONE) {
415 dev_err(tegra->dev, "mailbox is busy\n");
416 return -EBUSY;
417 }
418
419 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
420
421 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
422 if (value != MBOX_OWNER_SW) {
423 dev_err(tegra->dev, "failed to acquire mailbox\n");
424 return -EBUSY;
425 }
426
427 wait_for_idle = true;
428 }
429
430 value = tegra_xusb_mbox_pack(msg);
431 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
432
433 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
434 value |= MBOX_INT_EN | MBOX_DEST_FALC;
435 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
436
437 if (wait_for_idle) {
438 unsigned long timeout = jiffies + msecs_to_jiffies(250);
439
440 while (time_before(jiffies, timeout)) {
441 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
442 if (value == MBOX_OWNER_NONE)
443 break;
444
445 usleep_range(10, 20);
446 }
447
448 if (time_after(jiffies, timeout))
449 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
450
451 if (value != MBOX_OWNER_NONE)
452 return -ETIMEDOUT;
453 }
454
455 return 0;
456}
457
458static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
459{
460 struct tegra_xusb *tegra = data;
461 u32 value;
462
463 /* clear mailbox interrupts */
464 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
465 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
466
467 if (value & MBOX_SMI_INTR_FW_HANG)
468 dev_err(tegra->dev, "controller firmware hang\n");
469
470 return IRQ_WAKE_THREAD;
471}
472
473static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
474 const struct tegra_xusb_mbox_msg *msg)
475{
476 struct tegra_xusb_padctl *padctl = tegra->padctl;
477 const struct tegra_xusb_soc *soc = tegra->soc;
478 struct device *dev = tegra->dev;
479 struct tegra_xusb_mbox_msg rsp;
480 unsigned long mask;
481 unsigned int port;
482 bool idle, enable;
483 int err;
484
485 memset(&rsp, 0, sizeof(rsp));
486
487 switch (msg->cmd) {
488 case MBOX_CMD_INC_FALC_CLOCK:
489 case MBOX_CMD_DEC_FALC_CLOCK:
490 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
491 if (rsp.data != msg->data)
492 rsp.cmd = MBOX_CMD_NAK;
493 else
494 rsp.cmd = MBOX_CMD_ACK;
495
496 break;
497
498 case MBOX_CMD_INC_SSPI_CLOCK:
499 case MBOX_CMD_DEC_SSPI_CLOCK:
500 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
501 if (err < 0)
502 rsp.cmd = MBOX_CMD_NAK;
503 else
504 rsp.cmd = MBOX_CMD_ACK;
505
506 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
507 break;
508
509 case MBOX_CMD_SET_BW:
510 /*
511 * TODO: Request bandwidth once EMC scaling is supported.
512 * Ignore for now since ACK/NAK is not required for SET_BW
513 * messages.
514 */
515 break;
516
517 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
518 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
519 if (err < 0) {
520 dev_err(dev, "failed to save context for USB3#%u: %d\n",
521 msg->data, err);
522 rsp.cmd = MBOX_CMD_NAK;
523 } else {
524 rsp.cmd = MBOX_CMD_ACK;
525 }
526
527 rsp.data = msg->data;
528 break;
529
530 case MBOX_CMD_START_HSIC_IDLE:
531 case MBOX_CMD_STOP_HSIC_IDLE:
532 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
533 idle = false;
534 else
535 idle = true;
536
537 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
538 soc->ports.hsic.count);
539
540 for_each_set_bit(port, &mask, 32) {
541 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
542 idle);
543 if (err < 0)
544 break;
545 }
546
547 if (err < 0) {
548 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
549 idle ? "idle" : "busy", err);
550 rsp.cmd = MBOX_CMD_NAK;
551 } else {
552 rsp.cmd = MBOX_CMD_ACK;
553 }
554
555 rsp.data = msg->data;
556 break;
557
558 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
559 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
560 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
561 enable = false;
562 else
563 enable = true;
564
565 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
566 soc->ports.usb3.count);
567
568 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
569 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
570 port,
571 enable);
572 if (err < 0)
573 break;
574 }
575
576 if (err < 0) {
577 dev_err(dev,
578 "failed to %s LFPS detection on USB3#%u: %d\n",
579 enable ? "enable" : "disable", port, err);
580 rsp.cmd = MBOX_CMD_NAK;
581 } else {
582 rsp.cmd = MBOX_CMD_ACK;
583 }
584
585 rsp.data = msg->data;
586 break;
587
588 default:
589 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
590 break;
591 }
592
593 if (rsp.cmd) {
594 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
595
596 err = tegra_xusb_mbox_send(tegra, &rsp);
597 if (err < 0)
598 dev_err(dev, "failed to send %s: %d\n", cmd, err);
599 }
600}
601
602static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
603{
604 struct tegra_xusb *tegra = data;
605 struct tegra_xusb_mbox_msg msg;
606 u32 value;
607
608 mutex_lock(&tegra->lock);
609
610 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
611 tegra_xusb_mbox_unpack(&msg, value);
612
613 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
614 value &= ~MBOX_DEST_SMI;
615 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
616
617 /* clear mailbox owner if no ACK/NAK is required */
618 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
619 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
620
621 tegra_xusb_mbox_handle(tegra, &msg);
622
623 mutex_unlock(&tegra->lock);
624 return IRQ_HANDLED;
625}
626
627static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
628 struct resource *regs)
629{
630 u32 value;
631
632 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
633 value |= IPFS_EN_FPCI;
634 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
635
636 usleep_range(10, 20);
637
638 /* Program BAR0 space */
639 value = fpci_readl(tegra, XUSB_CFG_4);
640 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
641 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
642 fpci_writel(tegra, value, XUSB_CFG_4);
643
644 usleep_range(100, 200);
645
646 /* Enable bus master */
647 value = fpci_readl(tegra, XUSB_CFG_1);
648 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
649 fpci_writel(tegra, value, XUSB_CFG_1);
650
651 /* Enable interrupt assertion */
652 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
653 value |= IPFS_IP_INT_MASK;
654 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
655
656 /* Set hysteresis */
657 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
658}
659
660static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
661{
662 int err;
663
664 err = clk_prepare_enable(tegra->pll_e);
665 if (err < 0)
666 return err;
667
668 err = clk_prepare_enable(tegra->host_clk);
669 if (err < 0)
670 goto disable_plle;
671
672 err = clk_prepare_enable(tegra->ss_clk);
673 if (err < 0)
674 goto disable_host;
675
676 err = clk_prepare_enable(tegra->falcon_clk);
677 if (err < 0)
678 goto disable_ss;
679
680 err = clk_prepare_enable(tegra->fs_src_clk);
681 if (err < 0)
682 goto disable_falc;
683
684 err = clk_prepare_enable(tegra->hs_src_clk);
685 if (err < 0)
686 goto disable_fs_src;
687
688 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
689 if (err < 0)
690 goto disable_hs_src;
691
692 return 0;
693
694disable_hs_src:
695 clk_disable_unprepare(tegra->hs_src_clk);
696disable_fs_src:
697 clk_disable_unprepare(tegra->fs_src_clk);
698disable_falc:
699 clk_disable_unprepare(tegra->falcon_clk);
700disable_ss:
701 clk_disable_unprepare(tegra->ss_clk);
702disable_host:
703 clk_disable_unprepare(tegra->host_clk);
704disable_plle:
705 clk_disable_unprepare(tegra->pll_e);
706 return err;
707}
708
709static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
710{
711 clk_disable_unprepare(tegra->pll_e);
712 clk_disable_unprepare(tegra->host_clk);
713 clk_disable_unprepare(tegra->ss_clk);
714 clk_disable_unprepare(tegra->falcon_clk);
715 clk_disable_unprepare(tegra->fs_src_clk);
716 clk_disable_unprepare(tegra->hs_src_clk);
717}
718
719static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
720{
721 unsigned int i;
722 int err;
723
724 for (i = 0; i < tegra->num_phys; i++) {
725 err = phy_init(tegra->phys[i]);
726 if (err)
727 goto disable_phy;
728
729 err = phy_power_on(tegra->phys[i]);
730 if (err) {
731 phy_exit(tegra->phys[i]);
732 goto disable_phy;
733 }
734 }
735
736 return 0;
737
738disable_phy:
739 while (i--) {
740 phy_power_off(tegra->phys[i]);
741 phy_exit(tegra->phys[i]);
742 }
743
744 return err;
745}
746
747static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
748{
749 unsigned int i;
750
751 for (i = 0; i < tegra->num_phys; i++) {
752 phy_power_off(tegra->phys[i]);
753 phy_exit(tegra->phys[i]);
754 }
755}
756
757static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
758{
759 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
760 struct tegra_xusb_fw_header *header;
761 struct device *dev = tegra->dev;
762 const struct firmware *fw;
763 unsigned long timeout;
764 time_t timestamp;
765 struct tm time;
766 u64 address;
767 u32 value;
768 int err;
769
770 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
771 if (err < 0) {
772 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
773 return err;
774 }
775
776 /* Load Falcon controller with its firmware. */
777 header = (struct tegra_xusb_fw_header *)fw->data;
778 tegra->fw.size = le32_to_cpu(header->fwimg_len);
779
780 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
781 &tegra->fw.phys, GFP_KERNEL);
782 if (!tegra->fw.virt) {
783 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
784 release_firmware(fw);
785 return -ENOMEM;
786 }
787
788 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
789 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
790 release_firmware(fw);
791
792 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
793 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
794 csb_readl(tegra, XUSB_FALC_CPUCTL));
795 return 0;
796 }
797
798 /* Program the size of DFI into ILOAD_ATTR. */
799 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
800
801 /*
802 * Boot code of the firmware reads the ILOAD_BASE registers
803 * to get to the start of the DFI in system memory.
804 */
805 address = tegra->fw.phys + sizeof(*header);
806 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
807 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
808
809 /* Set BOOTPATH to 1 in APMAP. */
810 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
811
812 /* Invalidate L2IMEM. */
813 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
814
815 /*
816 * Initiate fetch of bootcode from system memory into L2IMEM.
817 * Program bootcode location and size in system memory.
818 */
819 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
820 IMEM_BLOCK_SIZE);
821 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
822 IMEM_BLOCK_SIZE);
823 code_blocks = code_tag_blocks + code_size_blocks;
824
825 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
826 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
827 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
828 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
829 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
830
831 /* Trigger L2IMEM load operation. */
832 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
833 XUSB_CSB_MP_L2IMEMOP_TRIG);
834
835 /* Setup Falcon auto-fill. */
836 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
837
838 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
839 IMFILLRNG1_TAG_LO_SHIFT) |
840 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
841 IMFILLRNG1_TAG_HI_SHIFT);
842 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
843
844 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
845
846 msleep(50);
847
848 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
849 XUSB_FALC_BOOTVEC);
850
851 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
852 timeout = jiffies + msecs_to_jiffies(5);
853
854 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
855
856 while (time_before(jiffies, timeout)) {
857 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
858 break;
859
860 usleep_range(100, 200);
861 }
862
863 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
864 dev_err(dev, "Falcon failed to start, state: %#x\n",
865 csb_readl(tegra, XUSB_FALC_CPUCTL));
866 return -EIO;
867 }
868
869 timestamp = le32_to_cpu(header->fwimg_created_time);
870 time_to_tm(timestamp, 0, &time);
871
872 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
873 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
874 time.tm_hour, time.tm_min, time.tm_sec);
875
876 return 0;
877}
878
879static int tegra_xusb_probe(struct platform_device *pdev)
880{
881 struct tegra_xusb_mbox_msg msg;
882 struct resource *res, *regs;
883 struct tegra_xusb *tegra;
884 struct xhci_hcd *xhci;
885 unsigned int i, j, k;
886 struct phy *phy;
887 int err;
888
889 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
890
891 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
892 if (!tegra)
893 return -ENOMEM;
894
895 tegra->soc = of_device_get_match_data(&pdev->dev);
896 mutex_init(&tegra->lock);
897 tegra->dev = &pdev->dev;
898
899 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
900 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
901 if (IS_ERR(tegra->regs))
902 return PTR_ERR(tegra->regs);
903
904 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
905 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
906 if (IS_ERR(tegra->fpci_base))
907 return PTR_ERR(tegra->fpci_base);
908
909 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
910 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
911 if (IS_ERR(tegra->ipfs_base))
912 return PTR_ERR(tegra->ipfs_base);
913
914 tegra->xhci_irq = platform_get_irq(pdev, 0);
915 if (tegra->xhci_irq < 0)
916 return tegra->xhci_irq;
917
918 tegra->mbox_irq = platform_get_irq(pdev, 1);
919 if (tegra->mbox_irq < 0)
920 return tegra->mbox_irq;
921
922 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
923 if (IS_ERR(tegra->padctl))
924 return PTR_ERR(tegra->padctl);
925
926 tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host");
927 if (IS_ERR(tegra->host_rst)) {
928 err = PTR_ERR(tegra->host_rst);
929 dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err);
930 goto put_padctl;
931 }
932
933 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
934 if (IS_ERR(tegra->ss_rst)) {
935 err = PTR_ERR(tegra->ss_rst);
936 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err);
937 goto put_padctl;
938 }
939
940 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
941 if (IS_ERR(tegra->host_clk)) {
942 err = PTR_ERR(tegra->host_clk);
943 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
944 goto put_padctl;
945 }
946
947 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
948 if (IS_ERR(tegra->falcon_clk)) {
949 err = PTR_ERR(tegra->falcon_clk);
950 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
951 goto put_padctl;
952 }
953
954 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
955 if (IS_ERR(tegra->ss_clk)) {
956 err = PTR_ERR(tegra->ss_clk);
957 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
958 goto put_padctl;
959 }
960
961 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
962 if (IS_ERR(tegra->ss_src_clk)) {
963 err = PTR_ERR(tegra->ss_src_clk);
964 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
965 goto put_padctl;
966 }
967
968 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
969 if (IS_ERR(tegra->hs_src_clk)) {
970 err = PTR_ERR(tegra->hs_src_clk);
971 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
972 goto put_padctl;
973 }
974
975 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
976 if (IS_ERR(tegra->fs_src_clk)) {
977 err = PTR_ERR(tegra->fs_src_clk);
978 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
979 goto put_padctl;
980 }
981
982 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
983 if (IS_ERR(tegra->pll_u_480m)) {
984 err = PTR_ERR(tegra->pll_u_480m);
985 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
986 goto put_padctl;
987 }
988
989 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
990 if (IS_ERR(tegra->clk_m)) {
991 err = PTR_ERR(tegra->clk_m);
992 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
993 goto put_padctl;
994 }
995
996 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
997 if (IS_ERR(tegra->pll_e)) {
998 err = PTR_ERR(tegra->pll_e);
999 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1000 goto put_padctl;
1001 }
1002
1003 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1004 sizeof(*tegra->supplies), GFP_KERNEL);
1005 if (!tegra->supplies) {
1006 err = -ENOMEM;
1007 goto put_padctl;
1008 }
1009
1010 for (i = 0; i < tegra->soc->num_supplies; i++)
1011 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1012
1013 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1014 tegra->supplies);
1015 if (err) {
1016 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1017 goto put_padctl;
1018 }
1019
1020 for (i = 0; i < tegra->soc->num_types; i++)
1021 tegra->num_phys += tegra->soc->phy_types[i].num;
1022
1023 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1024 sizeof(*tegra->phys), GFP_KERNEL);
1025 if (!tegra->phys) {
1026 dev_err(&pdev->dev, "failed to allocate PHY array\n");
1027 err = -ENOMEM;
1028 goto put_padctl;
1029 }
1030
1031 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1032 char prop[8];
1033
1034 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1035 snprintf(prop, sizeof(prop), "%s-%d",
1036 tegra->soc->phy_types[i].name, j);
1037
1038 phy = devm_phy_optional_get(&pdev->dev, prop);
1039 if (IS_ERR(phy)) {
1040 dev_err(&pdev->dev,
1041 "failed to get PHY %s: %ld\n", prop,
1042 PTR_ERR(phy));
1043 err = PTR_ERR(phy);
1044 goto put_padctl;
1045 }
1046
1047 tegra->phys[k++] = phy;
1048 }
1049 }
1050
1051 err = tegra_xusb_clk_enable(tegra);
1052 if (err) {
1053 dev_err(&pdev->dev, "failed to enable clocks: %d\n", err);
1054 goto put_padctl;
1055 }
1056
1057 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1058 if (err) {
1059 dev_err(&pdev->dev, "failed to enable regulators: %d\n", err);
1060 goto disable_clk;
1061 }
1062
1063 err = tegra_xusb_phy_enable(tegra);
1064 if (err < 0) {
1065 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1066 goto disable_regulator;
1067 }
1068
1069 tegra_xusb_ipfs_config(tegra, regs);
1070
1071 err = tegra_xusb_load_firmware(tegra);
1072 if (err < 0) {
1073 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1074 goto disable_phy;
1075 }
1076
1077 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1078 dev_name(&pdev->dev));
1079 if (!tegra->hcd) {
1080 err = -ENOMEM;
1081 goto disable_phy;
1082 }
1083
1084 /*
1085 * This must happen after usb_create_hcd(), because usb_create_hcd()
1086 * will overwrite the drvdata of the device with the hcd it creates.
1087 */
1088 platform_set_drvdata(pdev, tegra);
1089
1090 tegra->hcd->regs = tegra->regs;
1091 tegra->hcd->rsrc_start = regs->start;
1092 tegra->hcd->rsrc_len = resource_size(regs);
1093
1094 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1095 if (err < 0) {
1096 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1097 goto put_usb2;
1098 }
1099
1100 device_wakeup_enable(tegra->hcd->self.controller);
1101
1102 xhci = hcd_to_xhci(tegra->hcd);
1103
1104 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1105 &pdev->dev,
1106 dev_name(&pdev->dev),
1107 tegra->hcd);
1108 if (!xhci->shared_hcd) {
1109 dev_err(&pdev->dev, "failed to create shared HCD\n");
1110 goto remove_usb2;
1111 }
1112
1113 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1114 if (err < 0) {
1115 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1116 goto put_usb3;
1117 }
1118
1119 mutex_lock(&tegra->lock);
1120
1121 /* Enable firmware messages from controller. */
1122 msg.cmd = MBOX_CMD_MSG_ENABLED;
1123 msg.data = 0;
1124
1125 err = tegra_xusb_mbox_send(tegra, &msg);
1126 if (err < 0) {
1127 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1128 mutex_unlock(&tegra->lock);
1129 goto remove_usb3;
1130 }
1131
1132 mutex_unlock(&tegra->lock);
1133
1134 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1135 tegra_xusb_mbox_irq,
1136 tegra_xusb_mbox_thread, 0,
1137 dev_name(&pdev->dev), tegra);
1138 if (err < 0) {
1139 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1140 goto remove_usb3;
1141 }
1142
1143 return 0;
1144
1145remove_usb3:
1146 usb_remove_hcd(xhci->shared_hcd);
1147put_usb3:
1148 usb_put_hcd(xhci->shared_hcd);
1149remove_usb2:
1150 usb_remove_hcd(tegra->hcd);
1151put_usb2:
1152 usb_put_hcd(tegra->hcd);
1153disable_phy:
1154 tegra_xusb_phy_disable(tegra);
1155disable_regulator:
1156 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1157disable_clk:
1158 tegra_xusb_clk_disable(tegra);
1159put_padctl:
1160 tegra_xusb_padctl_put(tegra->padctl);
1161 return err;
1162}
1163
1164static int tegra_xusb_remove(struct platform_device *pdev)
1165{
1166 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1167 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1168
1169 usb_remove_hcd(xhci->shared_hcd);
1170 usb_put_hcd(xhci->shared_hcd);
1171 usb_remove_hcd(tegra->hcd);
1172 usb_put_hcd(tegra->hcd);
1173
1174 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1175 tegra->fw.phys);
1176
1177 tegra_xusb_phy_disable(tegra);
1178 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1179 tegra_xusb_clk_disable(tegra);
1180
1181 tegra_xusb_padctl_put(tegra->padctl);
1182
1183 return 0;
1184}
1185
1186#ifdef CONFIG_PM_SLEEP
1187static int tegra_xusb_suspend(struct device *dev)
1188{
1189 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1190 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1191 bool wakeup = device_may_wakeup(dev);
1192
1193 /* TODO: Powergate controller across suspend/resume. */
1194 return xhci_suspend(xhci, wakeup);
1195}
1196
1197static int tegra_xusb_resume(struct device *dev)
1198{
1199 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1200 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1201
1202 return xhci_resume(xhci, 0);
1203}
1204#endif
1205
1206static const struct dev_pm_ops tegra_xusb_pm_ops = {
1207 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1208};
1209
1210static const char * const tegra124_supply_names[] = {
1211 "avddio-pex",
1212 "dvddio-pex",
1213 "avdd-usb",
1214 "avdd-pll-utmip",
1215 "avdd-pll-erefe",
1216 "avdd-usb-ss-pll",
1217 "hvdd-usb-ss",
1218 "hvdd-usb-ss-pll-e",
1219};
1220
1221static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1222 { .name = "usb3", .num = 2, },
1223 { .name = "usb2", .num = 3, },
1224 { .name = "hsic", .num = 2, },
1225};
1226
1227static const struct tegra_xusb_soc tegra124_soc = {
1228 .firmware = "nvidia/tegra124/xusb.bin",
1229 .supply_names = tegra124_supply_names,
1230 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1231 .phy_types = tegra124_phy_types,
1232 .num_types = ARRAY_SIZE(tegra124_phy_types),
1233 .ports = {
1234 .usb2 = { .offset = 4, .count = 4, },
1235 .hsic = { .offset = 6, .count = 2, },
1236 .usb3 = { .offset = 0, .count = 2, },
1237 },
1238};
1239MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1240
1241static const struct of_device_id tegra_xusb_of_match[] = {
1242 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1243 { },
1244};
1245MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1246
1247static struct platform_driver tegra_xusb_driver = {
1248 .probe = tegra_xusb_probe,
1249 .remove = tegra_xusb_remove,
1250 .driver = {
1251 .name = "tegra-xusb",
1252 .pm = &tegra_xusb_pm_ops,
1253 .of_match_table = tegra_xusb_of_match,
1254 },
1255};
1256
1257static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1258{
1259 xhci->quirks |= XHCI_PLAT;
1260}
1261
1262static int tegra_xhci_setup(struct usb_hcd *hcd)
1263{
1264 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1265}
1266
1267static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1268 .extra_priv_size = sizeof(struct xhci_hcd),
1269 .reset = tegra_xhci_setup,
1270};
1271
1272static int __init tegra_xusb_init(void)
1273{
1274 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1275
1276 return platform_driver_register(&tegra_xusb_driver);
1277}
1278module_init(tegra_xusb_init);
1279
1280static void __exit tegra_xusb_exit(void)
1281{
1282 platform_driver_unregister(&tegra_xusb_driver);
1283}
1284module_exit(tegra_xusb_exit);
1285
1286MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1287MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1288MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 12:26:36 -0400