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authorGeert Uytterhoeven <geert+renesas@glider.be>2017-03-13 06:28:33 -0400
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-03-30 07:43:51 -0400
commite7ad4d3c1dd9dd6881d4470dd6586d5cc84b8e0c (patch)
treea7ed9520a18534bfbb44ad72303b30c3eeaca7fa
parentb205914c8f822ef2464b741c64e892823d685ad6 (diff)
pinctrl: sh-pfc: r8a7795: Add SCIF support
Add pins, groups, and functions for all SCIF serial ports on R-Car H3 ES2.0. Extracted from a big patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Diffstat
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c275
1 files changed, 275 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 6caaed53938c..996cacee99c3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1576,10 +1576,285 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), 1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1577}; 1577};
1578 1578
1579/* - SCIF0 ------------------------------------------------------------------ */
1580static const unsigned int scif0_data_pins[] = {
1581 /* RX, TX */
1582 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1583};
1584static const unsigned int scif0_data_mux[] = {
1585 RX0_MARK, TX0_MARK,
1586};
1587static const unsigned int scif0_clk_pins[] = {
1588 /* SCK */
1589 RCAR_GP_PIN(5, 0),
1590};
1591static const unsigned int scif0_clk_mux[] = {
1592 SCK0_MARK,
1593};
1594static const unsigned int scif0_ctrl_pins[] = {
1595 /* RTS, CTS */
1596 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1597};
1598static const unsigned int scif0_ctrl_mux[] = {
1599 RTS0_N_TANS_MARK, CTS0_N_MARK,
1600};
1601/* - SCIF1 ------------------------------------------------------------------ */
1602static const unsigned int scif1_data_a_pins[] = {
1603 /* RX, TX */
1604 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1605};
1606static const unsigned int scif1_data_a_mux[] = {
1607 RX1_A_MARK, TX1_A_MARK,
1608};
1609static const unsigned int scif1_clk_pins[] = {
1610 /* SCK */
1611 RCAR_GP_PIN(6, 21),
1612};
1613static const unsigned int scif1_clk_mux[] = {
1614 SCK1_MARK,
1615};
1616static const unsigned int scif1_ctrl_pins[] = {
1617 /* RTS, CTS */
1618 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1619};
1620static const unsigned int scif1_ctrl_mux[] = {
1621 RTS1_N_TANS_MARK, CTS1_N_MARK,
1622};
1623
1624static const unsigned int scif1_data_b_pins[] = {
1625 /* RX, TX */
1626 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1627};
1628static const unsigned int scif1_data_b_mux[] = {
1629 RX1_B_MARK, TX1_B_MARK,
1630};
1631/* - SCIF2 ------------------------------------------------------------------ */
1632static const unsigned int scif2_data_a_pins[] = {
1633 /* RX, TX */
1634 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1635};
1636static const unsigned int scif2_data_a_mux[] = {
1637 RX2_A_MARK, TX2_A_MARK,
1638};
1639static const unsigned int scif2_clk_pins[] = {
1640 /* SCK */
1641 RCAR_GP_PIN(5, 9),
1642};
1643static const unsigned int scif2_clk_mux[] = {
1644 SCK2_MARK,
1645};
1646static const unsigned int scif2_data_b_pins[] = {
1647 /* RX, TX */
1648 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1649};
1650static const unsigned int scif2_data_b_mux[] = {
1651 RX2_B_MARK, TX2_B_MARK,
1652};
1653/* - SCIF3 ------------------------------------------------------------------ */
1654static const unsigned int scif3_data_a_pins[] = {
1655 /* RX, TX */
1656 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1657};
1658static const unsigned int scif3_data_a_mux[] = {
1659 RX3_A_MARK, TX3_A_MARK,
1660};
1661static const unsigned int scif3_clk_pins[] = {
1662 /* SCK */
1663 RCAR_GP_PIN(1, 22),
1664};
1665static const unsigned int scif3_clk_mux[] = {
1666 SCK3_MARK,
1667};
1668static const unsigned int scif3_ctrl_pins[] = {
1669 /* RTS, CTS */
1670 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1671};
1672static const unsigned int scif3_ctrl_mux[] = {
1673 RTS3_N_TANS_MARK, CTS3_N_MARK,
1674};
1675static const unsigned int scif3_data_b_pins[] = {
1676 /* RX, TX */
1677 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1678};
1679static const unsigned int scif3_data_b_mux[] = {
1680 RX3_B_MARK, TX3_B_MARK,
1681};
1682/* - SCIF4 ------------------------------------------------------------------ */
1683static const unsigned int scif4_data_a_pins[] = {
1684 /* RX, TX */
1685 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1686};
1687static const unsigned int scif4_data_a_mux[] = {
1688 RX4_A_MARK, TX4_A_MARK,
1689};
1690static const unsigned int scif4_clk_a_pins[] = {
1691 /* SCK */
1692 RCAR_GP_PIN(2, 10),
1693};
1694static const unsigned int scif4_clk_a_mux[] = {
1695 SCK4_A_MARK,
1696};
1697static const unsigned int scif4_ctrl_a_pins[] = {
1698 /* RTS, CTS */
1699 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1700};
1701static const unsigned int scif4_ctrl_a_mux[] = {
1702 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1703};
1704static const unsigned int scif4_data_b_pins[] = {
1705 /* RX, TX */
1706 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1707};
1708static const unsigned int scif4_data_b_mux[] = {
1709 RX4_B_MARK, TX4_B_MARK,
1710};
1711static const unsigned int scif4_clk_b_pins[] = {
1712 /* SCK */
1713 RCAR_GP_PIN(1, 5),
1714};
1715static const unsigned int scif4_clk_b_mux[] = {
1716 SCK4_B_MARK,
1717};
1718static const unsigned int scif4_ctrl_b_pins[] = {
1719 /* RTS, CTS */
1720 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1721};
1722static const unsigned int scif4_ctrl_b_mux[] = {
1723 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1724};
1725static const unsigned int scif4_data_c_pins[] = {
1726 /* RX, TX */
1727 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1728};
1729static const unsigned int scif4_data_c_mux[] = {
1730 RX4_C_MARK, TX4_C_MARK,
1731};
1732static const unsigned int scif4_clk_c_pins[] = {
1733 /* SCK */
1734 RCAR_GP_PIN(0, 8),
1735};
1736static const unsigned int scif4_clk_c_mux[] = {
1737 SCK4_C_MARK,
1738};
1739static const unsigned int scif4_ctrl_c_pins[] = {
1740 /* RTS, CTS */
1741 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1742};
1743static const unsigned int scif4_ctrl_c_mux[] = {
1744 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1745};
1746/* - SCIF5 ------------------------------------------------------------------ */
1747static const unsigned int scif5_data_a_pins[] = {
1748 /* RX, TX */
1749 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1750};
1751static const unsigned int scif5_data_a_mux[] = {
1752 RX5_A_MARK, TX5_A_MARK,
1753};
1754static const unsigned int scif5_clk_a_pins[] = {
1755 /* SCK */
1756 RCAR_GP_PIN(6, 21),
1757};
1758static const unsigned int scif5_clk_a_mux[] = {
1759 SCK5_A_MARK,
1760};
1761static const unsigned int scif5_data_b_pins[] = {
1762 /* RX, TX */
1763 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
1764};
1765static const unsigned int scif5_data_b_mux[] = {
1766 RX5_B_MARK, TX5_B_MARK,
1767};
1768static const unsigned int scif5_clk_b_pins[] = {
1769 /* SCK */
1770 RCAR_GP_PIN(5, 0),
1771};
1772static const unsigned int scif5_clk_b_mux[] = {
1773 SCK5_B_MARK,
1774};
1775
1579static const struct sh_pfc_pin_group pinmux_groups[] = { 1776static const struct sh_pfc_pin_group pinmux_groups[] = {
1777 SH_PFC_PIN_GROUP(scif0_data),
1778 SH_PFC_PIN_GROUP(scif0_clk),
1779 SH_PFC_PIN_GROUP(scif0_ctrl),
1780 SH_PFC_PIN_GROUP(scif1_data_a),
1781 SH_PFC_PIN_GROUP(scif1_clk),
1782 SH_PFC_PIN_GROUP(scif1_ctrl),
1783 SH_PFC_PIN_GROUP(scif1_data_b),
1784 SH_PFC_PIN_GROUP(scif2_data_a),
1785 SH_PFC_PIN_GROUP(scif2_clk),
1786 SH_PFC_PIN_GROUP(scif2_data_b),
1787 SH_PFC_PIN_GROUP(scif3_data_a),
1788 SH_PFC_PIN_GROUP(scif3_clk),
1789 SH_PFC_PIN_GROUP(scif3_ctrl),
1790 SH_PFC_PIN_GROUP(scif3_data_b),
1791 SH_PFC_PIN_GROUP(scif4_data_a),
1792 SH_PFC_PIN_GROUP(scif4_clk_a),
1793 SH_PFC_PIN_GROUP(scif4_ctrl_a),
1794 SH_PFC_PIN_GROUP(scif4_data_b),
1795 SH_PFC_PIN_GROUP(scif4_clk_b),
1796 SH_PFC_PIN_GROUP(scif4_ctrl_b),
1797 SH_PFC_PIN_GROUP(scif4_data_c),
1798 SH_PFC_PIN_GROUP(scif4_clk_c),
1799 SH_PFC_PIN_GROUP(scif4_ctrl_c),
1800 SH_PFC_PIN_GROUP(scif5_data_a),
1801 SH_PFC_PIN_GROUP(scif5_clk_a),
1802 SH_PFC_PIN_GROUP(scif5_data_b),
1803 SH_PFC_PIN_GROUP(scif5_clk_b),
1804};
1805
1806static const char * const scif0_groups[] = {
1807 "scif0_data",
1808 "scif0_clk",
1809 "scif0_ctrl",
1810};
1811
1812static const char * const scif1_groups[] = {
1813 "scif1_data_a",
1814 "scif1_clk",
1815 "scif1_ctrl",
1816 "scif1_data_b",
1817};
1818
1819static const char * const scif2_groups[] = {
1820 "scif2_data_a",
1821 "scif2_clk",
1822 "scif2_data_b",
1823};
1824
1825static const char * const scif3_groups[] = {
1826 "scif3_data_a",
1827 "scif3_clk",
1828 "scif3_ctrl",
1829 "scif3_data_b",
1830};
1831
1832static const char * const scif4_groups[] = {
1833 "scif4_data_a",
1834 "scif4_clk_a",
1835 "scif4_ctrl_a",
1836 "scif4_data_b",
1837 "scif4_clk_b",
1838 "scif4_ctrl_b",
1839 "scif4_data_c",
1840 "scif4_clk_c",
1841 "scif4_ctrl_c",
1842};
1843
1844static const char * const scif5_groups[] = {
1845 "scif5_data_a",
1846 "scif5_clk_a",
1847 "scif5_data_b",
1848 "scif5_clk_b",
1580}; 1849};
1581 1850
1582static const struct sh_pfc_function pinmux_functions[] = { 1851static const struct sh_pfc_function pinmux_functions[] = {
1852 SH_PFC_FUNCTION(scif0),
1853 SH_PFC_FUNCTION(scif1),
1854 SH_PFC_FUNCTION(scif2),
1855 SH_PFC_FUNCTION(scif3),
1856 SH_PFC_FUNCTION(scif4),
1857 SH_PFC_FUNCTION(scif5),
1583}; 1858};
1584 1859
1585static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1860static const struct pinmux_cfg_reg pinmux_config_regs[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 18:35:26 -0400