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authorTristram Ha <Tristram.Ha@microchip.com>2019-07-29 13:49:47 -0400
committerDavid S. Miller <davem@davemloft.net>2019-07-30 18:12:50 -0400
commite66f840c08a237acfbb981592047b53e7411012f (patch)
tree67cbf1203dff60205bf764322adb9b39a3666e3b
parent016e43a26bab0126e33c9682f9d9d05eca9f0386 (diff)
net: dsa: ksz: Add Microchip KSZ8795 DSA driver
Add Microchip KSZ8795 DSA driver. Signed-off-by: Tristram Ha <Tristram.Ha@microchip.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: David S. Miller <davem@davemloft.net> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Tristram Ha <Tristram.Ha@microchip.com> Cc: Vivien Didelot <vivien.didelot@gmail.com> Cc: Woojung Huh <woojung.huh@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/dsa/microchip/Kconfig17
-rw-r--r--drivers/net/dsa/microchip/Makefile2
-rw-r--r--drivers/net/dsa/microchip/ksz8795.c1311
-rw-r--r--drivers/net/dsa/microchip/ksz8795_reg.h1004
-rw-r--r--drivers/net/dsa/microchip/ksz8795_spi.c104
-rw-r--r--drivers/net/dsa/microchip/ksz_common.c3
-rw-r--r--drivers/net/dsa/microchip/ksz_common.h28
-rw-r--r--drivers/net/dsa/microchip/ksz_priv.h1
8 files changed, 2469 insertions, 1 deletions
diff --git a/drivers/net/dsa/microchip/Kconfig b/drivers/net/dsa/microchip/Kconfig
index fe0a13b79c4b..5e4f74286ea3 100644
--- a/drivers/net/dsa/microchip/Kconfig
+++ b/drivers/net/dsa/microchip/Kconfig
@@ -16,3 +16,20 @@ config NET_DSA_MICROCHIP_KSZ9477_SPI
16 select REGMAP_SPI 16 select REGMAP_SPI
17 help 17 help
18 Select to enable support for registering switches configured through SPI. 18 Select to enable support for registering switches configured through SPI.
19
20menuconfig NET_DSA_MICROCHIP_KSZ8795
21 tristate "Microchip KSZ8795 series switch support"
22 depends on NET_DSA
23 select NET_DSA_MICROCHIP_KSZ_COMMON
24 help
25 This driver adds support for Microchip KSZ8795 switch chips.
26
27config NET_DSA_MICROCHIP_KSZ8795_SPI
28 tristate "KSZ8795 series SPI connected switch driver"
29 depends on NET_DSA_MICROCHIP_KSZ8795 && SPI
30 select REGMAP_SPI
31 help
32 This driver accesses KSZ8795 chip through SPI.
33
34 It is required to use the KSZ8795 switch driver as the only access
35 is through SPI.
diff --git a/drivers/net/dsa/microchip/Makefile b/drivers/net/dsa/microchip/Makefile
index 68451b02f775..e3d799b95d7d 100644
--- a/drivers/net/dsa/microchip/Makefile
+++ b/drivers/net/dsa/microchip/Makefile
@@ -2,3 +2,5 @@
2obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON) += ksz_common.o 2obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON) += ksz_common.o
3obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ9477) += ksz9477.o 3obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ9477) += ksz9477.o
4obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI) += ksz9477_spi.o 4obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI) += ksz9477_spi.o
5obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ8795) += ksz8795.o
6obj-$(CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI) += ksz8795_spi.o
diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c
new file mode 100644
index 000000000000..ae80b3c6dea2
--- /dev/null
+++ b/drivers/net/dsa/microchip/ksz8795.c
@@ -0,0 +1,1311 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/export.h>
11#include <linux/gpio.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_data/microchip-ksz.h>
15#include <linux/phy.h>
16#include <linux/etherdevice.h>
17#include <linux/if_bridge.h>
18#include <net/dsa.h>
19#include <net/switchdev.h>
20
21#include "ksz_priv.h"
22#include "ksz_common.h"
23#include "ksz8795_reg.h"
24
25static const struct {
26 char string[ETH_GSTRING_LEN];
27} mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
28 { "rx_hi" },
29 { "rx_undersize" },
30 { "rx_fragments" },
31 { "rx_oversize" },
32 { "rx_jabbers" },
33 { "rx_symbol_err" },
34 { "rx_crc_err" },
35 { "rx_align_err" },
36 { "rx_mac_ctrl" },
37 { "rx_pause" },
38 { "rx_bcast" },
39 { "rx_mcast" },
40 { "rx_ucast" },
41 { "rx_64_or_less" },
42 { "rx_65_127" },
43 { "rx_128_255" },
44 { "rx_256_511" },
45 { "rx_512_1023" },
46 { "rx_1024_1522" },
47 { "rx_1523_2000" },
48 { "rx_2001" },
49 { "tx_hi" },
50 { "tx_late_col" },
51 { "tx_pause" },
52 { "tx_bcast" },
53 { "tx_mcast" },
54 { "tx_ucast" },
55 { "tx_deferred" },
56 { "tx_total_col" },
57 { "tx_exc_col" },
58 { "tx_single_col" },
59 { "tx_mult_col" },
60 { "rx_total" },
61 { "tx_total" },
62 { "rx_discards" },
63 { "tx_discards" },
64};
65
66static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
67{
68 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
69}
70
71static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
72 bool set)
73{
74 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
75 bits, set ? bits : 0);
76}
77
78static int ksz8795_reset_switch(struct ksz_device *dev)
79{
80 /* reset switch */
81 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
82 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
83 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
84
85 return 0;
86}
87
88static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
89{
90 u8 hi, lo;
91
92 /* Number of queues can only be 1, 2, or 4. */
93 switch (queue) {
94 case 4:
95 case 3:
96 queue = PORT_QUEUE_SPLIT_4;
97 break;
98 case 2:
99 queue = PORT_QUEUE_SPLIT_2;
100 break;
101 default:
102 queue = PORT_QUEUE_SPLIT_1;
103 }
104 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
105 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
106 lo &= ~PORT_QUEUE_SPLIT_L;
107 if (queue & PORT_QUEUE_SPLIT_2)
108 lo |= PORT_QUEUE_SPLIT_L;
109 hi &= ~PORT_QUEUE_SPLIT_H;
110 if (queue & PORT_QUEUE_SPLIT_4)
111 hi |= PORT_QUEUE_SPLIT_H;
112 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
113 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
114
115 /* Default is port based for egress rate limit. */
116 if (queue != PORT_QUEUE_SPLIT_1)
117 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
118 true);
119}
120
121static void ksz8795_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
122 u64 *cnt)
123{
124 u16 ctrl_addr;
125 u32 data;
126 u8 check;
127 int loop;
128
129 ctrl_addr = addr + SWITCH_COUNTER_NUM * port;
130 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
131
132 mutex_lock(&dev->alu_mutex);
133 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
134
135 /* It is almost guaranteed to always read the valid bit because of
136 * slow SPI speed.
137 */
138 for (loop = 2; loop > 0; loop--) {
139 ksz_read8(dev, REG_IND_MIB_CHECK, &check);
140
141 if (check & MIB_COUNTER_VALID) {
142 ksz_read32(dev, REG_IND_DATA_LO, &data);
143 if (check & MIB_COUNTER_OVERFLOW)
144 *cnt += MIB_COUNTER_VALUE + 1;
145 *cnt += data & MIB_COUNTER_VALUE;
146 break;
147 }
148 }
149 mutex_unlock(&dev->alu_mutex);
150}
151
152static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
153 u64 *dropped, u64 *cnt)
154{
155 u16 ctrl_addr;
156 u32 data;
157 u8 check;
158 int loop;
159
160 addr -= SWITCH_COUNTER_NUM;
161 ctrl_addr = (KS_MIB_TOTAL_RX_1 - KS_MIB_TOTAL_RX_0) * port;
162 ctrl_addr += addr + KS_MIB_TOTAL_RX_0;
163 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
164
165 mutex_lock(&dev->alu_mutex);
166 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
167
168 /* It is almost guaranteed to always read the valid bit because of
169 * slow SPI speed.
170 */
171 for (loop = 2; loop > 0; loop--) {
172 ksz_read8(dev, REG_IND_MIB_CHECK, &check);
173
174 if (check & MIB_COUNTER_VALID) {
175 ksz_read32(dev, REG_IND_DATA_LO, &data);
176 if (addr < 2) {
177 u64 total;
178
179 total = check & MIB_TOTAL_BYTES_H;
180 total <<= 32;
181 *cnt += total;
182 *cnt += data;
183 if (check & MIB_COUNTER_OVERFLOW) {
184 total = MIB_TOTAL_BYTES_H + 1;
185 total <<= 32;
186 *cnt += total;
187 }
188 } else {
189 if (check & MIB_COUNTER_OVERFLOW)
190 *cnt += MIB_PACKET_DROPPED + 1;
191 *cnt += data & MIB_PACKET_DROPPED;
192 }
193 break;
194 }
195 }
196 mutex_unlock(&dev->alu_mutex);
197}
198
199static void ksz8795_freeze_mib(struct ksz_device *dev, int port, bool freeze)
200{
201 /* enable the port for flush/freeze function */
202 if (freeze)
203 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
204 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
205
206 /* disable the port after freeze is done */
207 if (!freeze)
208 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
209}
210
211static void ksz8795_port_init_cnt(struct ksz_device *dev, int port)
212{
213 struct ksz_port_mib *mib = &dev->ports[port].mib;
214
215 /* flush all enabled port MIB counters */
216 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
217 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
218 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
219
220 mib->cnt_ptr = 0;
221
222 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
223 while (mib->cnt_ptr < dev->reg_mib_cnt) {
224 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
225 &mib->counters[mib->cnt_ptr]);
226 ++mib->cnt_ptr;
227 }
228
229 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
230 while (mib->cnt_ptr < dev->mib_cnt) {
231 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
232 NULL, &mib->counters[mib->cnt_ptr]);
233 ++mib->cnt_ptr;
234 }
235 mib->cnt_ptr = 0;
236 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
237}
238
239static void ksz8795_r_table(struct ksz_device *dev, int table, u16 addr,
240 u64 *data)
241{
242 u16 ctrl_addr;
243
244 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
245
246 mutex_lock(&dev->alu_mutex);
247 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
248 ksz_read64(dev, REG_IND_DATA_HI, data);
249 mutex_unlock(&dev->alu_mutex);
250}
251
252static void ksz8795_w_table(struct ksz_device *dev, int table, u16 addr,
253 u64 data)
254{
255 u16 ctrl_addr;
256
257 ctrl_addr = IND_ACC_TABLE(table) | addr;
258
259 mutex_lock(&dev->alu_mutex);
260 ksz_write64(dev, REG_IND_DATA_HI, data);
261 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
262 mutex_unlock(&dev->alu_mutex);
263}
264
265static int ksz8795_valid_dyn_entry(struct ksz_device *dev, u8 *data)
266{
267 int timeout = 100;
268
269 do {
270 ksz_read8(dev, REG_IND_DATA_CHECK, data);
271 timeout--;
272 } while ((*data & DYNAMIC_MAC_TABLE_NOT_READY) && timeout);
273
274 /* Entry is not ready for accessing. */
275 if (*data & DYNAMIC_MAC_TABLE_NOT_READY) {
276 return -EAGAIN;
277 /* Entry is ready for accessing. */
278 } else {
279 ksz_read8(dev, REG_IND_DATA_8, data);
280
281 /* There is no valid entry in the table. */
282 if (*data & DYNAMIC_MAC_TABLE_MAC_EMPTY)
283 return -ENXIO;
284 }
285 return 0;
286}
287
288static int ksz8795_r_dyn_mac_table(struct ksz_device *dev, u16 addr,
289 u8 *mac_addr, u8 *fid, u8 *src_port,
290 u8 *timestamp, u16 *entries)
291{
292 u32 data_hi, data_lo;
293 u16 ctrl_addr;
294 u8 data;
295 int rc;
296
297 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
298
299 mutex_lock(&dev->alu_mutex);
300 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
301
302 rc = ksz8795_valid_dyn_entry(dev, &data);
303 if (rc == -EAGAIN) {
304 if (addr == 0)
305 *entries = 0;
306 } else if (rc == -ENXIO) {
307 *entries = 0;
308 /* At least one valid entry in the table. */
309 } else {
310 u64 buf = 0;
311 int cnt;
312
313 ksz_read64(dev, REG_IND_DATA_HI, &buf);
314 data_hi = (u32)(buf >> 32);
315 data_lo = (u32)buf;
316
317 /* Check out how many valid entry in the table. */
318 cnt = data & DYNAMIC_MAC_TABLE_ENTRIES_H;
319 cnt <<= DYNAMIC_MAC_ENTRIES_H_S;
320 cnt |= (data_hi & DYNAMIC_MAC_TABLE_ENTRIES) >>
321 DYNAMIC_MAC_ENTRIES_S;
322 *entries = cnt + 1;
323
324 *fid = (data_hi & DYNAMIC_MAC_TABLE_FID) >>
325 DYNAMIC_MAC_FID_S;
326 *src_port = (data_hi & DYNAMIC_MAC_TABLE_SRC_PORT) >>
327 DYNAMIC_MAC_SRC_PORT_S;
328 *timestamp = (data_hi & DYNAMIC_MAC_TABLE_TIMESTAMP) >>
329 DYNAMIC_MAC_TIMESTAMP_S;
330
331 mac_addr[5] = (u8)data_lo;
332 mac_addr[4] = (u8)(data_lo >> 8);
333 mac_addr[3] = (u8)(data_lo >> 16);
334 mac_addr[2] = (u8)(data_lo >> 24);
335
336 mac_addr[1] = (u8)data_hi;
337 mac_addr[0] = (u8)(data_hi >> 8);
338 rc = 0;
339 }
340 mutex_unlock(&dev->alu_mutex);
341
342 return rc;
343}
344
345static int ksz8795_r_sta_mac_table(struct ksz_device *dev, u16 addr,
346 struct alu_struct *alu)
347{
348 u32 data_hi, data_lo;
349 u64 data;
350
351 ksz8795_r_table(dev, TABLE_STATIC_MAC, addr, &data);
352 data_hi = data >> 32;
353 data_lo = (u32)data;
354 if (data_hi & (STATIC_MAC_TABLE_VALID | STATIC_MAC_TABLE_OVERRIDE)) {
355 alu->mac[5] = (u8)data_lo;
356 alu->mac[4] = (u8)(data_lo >> 8);
357 alu->mac[3] = (u8)(data_lo >> 16);
358 alu->mac[2] = (u8)(data_lo >> 24);
359 alu->mac[1] = (u8)data_hi;
360 alu->mac[0] = (u8)(data_hi >> 8);
361 alu->port_forward = (data_hi & STATIC_MAC_TABLE_FWD_PORTS) >>
362 STATIC_MAC_FWD_PORTS_S;
363 alu->is_override =
364 (data_hi & STATIC_MAC_TABLE_OVERRIDE) ? 1 : 0;
365 data_hi >>= 1;
366 alu->is_use_fid = (data_hi & STATIC_MAC_TABLE_USE_FID) ? 1 : 0;
367 alu->fid = (data_hi & STATIC_MAC_TABLE_FID) >>
368 STATIC_MAC_FID_S;
369 return 0;
370 }
371 return -ENXIO;
372}
373
374static void ksz8795_w_sta_mac_table(struct ksz_device *dev, u16 addr,
375 struct alu_struct *alu)
376{
377 u32 data_hi, data_lo;
378 u64 data;
379
380 data_lo = ((u32)alu->mac[2] << 24) |
381 ((u32)alu->mac[3] << 16) |
382 ((u32)alu->mac[4] << 8) | alu->mac[5];
383 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
384 data_hi |= (u32)alu->port_forward << STATIC_MAC_FWD_PORTS_S;
385
386 if (alu->is_override)
387 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
388 if (alu->is_use_fid) {
389 data_hi |= STATIC_MAC_TABLE_USE_FID;
390 data_hi |= (u32)alu->fid << STATIC_MAC_FID_S;
391 }
392 if (alu->is_static)
393 data_hi |= STATIC_MAC_TABLE_VALID;
394 else
395 data_hi &= ~STATIC_MAC_TABLE_OVERRIDE;
396
397 data = (u64)data_hi << 32 | data_lo;
398 ksz8795_w_table(dev, TABLE_STATIC_MAC, addr, data);
399}
400
401static void ksz8795_from_vlan(u16 vlan, u8 *fid, u8 *member, u8 *valid)
402{
403 *fid = vlan & VLAN_TABLE_FID;
404 *member = (vlan & VLAN_TABLE_MEMBERSHIP) >> VLAN_TABLE_MEMBERSHIP_S;
405 *valid = !!(vlan & VLAN_TABLE_VALID);
406}
407
408static void ksz8795_to_vlan(u8 fid, u8 member, u8 valid, u16 *vlan)
409{
410 *vlan = fid;
411 *vlan |= (u16)member << VLAN_TABLE_MEMBERSHIP_S;
412 if (valid)
413 *vlan |= VLAN_TABLE_VALID;
414}
415
416static void ksz8795_r_vlan_entries(struct ksz_device *dev, u16 addr)
417{
418 u64 data;
419 int i;
420
421 ksz8795_r_table(dev, TABLE_VLAN, addr, &data);
422 addr *= 4;
423 for (i = 0; i < 4; i++) {
424 dev->vlan_cache[addr + i].table[0] = (u16)data;
425 data >>= VLAN_TABLE_S;
426 }
427}
428
429static void ksz8795_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
430{
431 int index;
432 u16 *data;
433 u16 addr;
434 u64 buf;
435
436 data = (u16 *)&buf;
437 addr = vid / 4;
438 index = vid & 3;
439 ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
440 *vlan = data[index];
441}
442
443static void ksz8795_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
444{
445 int index;
446 u16 *data;
447 u16 addr;
448 u64 buf;
449
450 data = (u16 *)&buf;
451 addr = vid / 4;
452 index = vid & 3;
453 ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
454 data[index] = vlan;
455 dev->vlan_cache[vid].table[0] = vlan;
456 ksz8795_w_table(dev, TABLE_VLAN, addr, buf);
457}
458
459static void ksz8795_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
460{
461 u8 restart, speed, ctrl, link;
462 int processed = true;
463 u16 data = 0;
464 u8 p = phy;
465
466 switch (reg) {
467 case PHY_REG_CTRL:
468 ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
469 ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
470 ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
471 if (restart & PORT_PHY_LOOPBACK)
472 data |= PHY_LOOPBACK;
473 if (ctrl & PORT_FORCE_100_MBIT)
474 data |= PHY_SPEED_100MBIT;
475 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
476 data |= PHY_AUTO_NEG_ENABLE;
477 if (restart & PORT_POWER_DOWN)
478 data |= PHY_POWER_DOWN;
479 if (restart & PORT_AUTO_NEG_RESTART)
480 data |= PHY_AUTO_NEG_RESTART;
481 if (ctrl & PORT_FORCE_FULL_DUPLEX)
482 data |= PHY_FULL_DUPLEX;
483 if (speed & PORT_HP_MDIX)
484 data |= PHY_HP_MDIX;
485 if (restart & PORT_FORCE_MDIX)
486 data |= PHY_FORCE_MDIX;
487 if (restart & PORT_AUTO_MDIX_DISABLE)
488 data |= PHY_AUTO_MDIX_DISABLE;
489 if (restart & PORT_TX_DISABLE)
490 data |= PHY_TRANSMIT_DISABLE;
491 if (restart & PORT_LED_OFF)
492 data |= PHY_LED_DISABLE;
493 break;
494 case PHY_REG_STATUS:
495 ksz_pread8(dev, p, P_LINK_STATUS, &link);
496 data = PHY_100BTX_FD_CAPABLE |
497 PHY_100BTX_CAPABLE |
498 PHY_10BT_FD_CAPABLE |
499 PHY_10BT_CAPABLE |
500 PHY_AUTO_NEG_CAPABLE;
501 if (link & PORT_AUTO_NEG_COMPLETE)
502 data |= PHY_AUTO_NEG_ACKNOWLEDGE;
503 if (link & PORT_STAT_LINK_GOOD)
504 data |= PHY_LINK_STATUS;
505 break;
506 case PHY_REG_ID_1:
507 data = KSZ8795_ID_HI;
508 break;
509 case PHY_REG_ID_2:
510 data = KSZ8795_ID_LO;
511 break;
512 case PHY_REG_AUTO_NEGOTIATION:
513 ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
514 data = PHY_AUTO_NEG_802_3;
515 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
516 data |= PHY_AUTO_NEG_SYM_PAUSE;
517 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
518 data |= PHY_AUTO_NEG_100BTX_FD;
519 if (ctrl & PORT_AUTO_NEG_100BTX)
520 data |= PHY_AUTO_NEG_100BTX;
521 if (ctrl & PORT_AUTO_NEG_10BT_FD)
522 data |= PHY_AUTO_NEG_10BT_FD;
523 if (ctrl & PORT_AUTO_NEG_10BT)
524 data |= PHY_AUTO_NEG_10BT;
525 break;
526 case PHY_REG_REMOTE_CAPABILITY:
527 ksz_pread8(dev, p, P_REMOTE_STATUS, &link);
528 data = PHY_AUTO_NEG_802_3;
529 if (link & PORT_REMOTE_SYM_PAUSE)
530 data |= PHY_AUTO_NEG_SYM_PAUSE;
531 if (link & PORT_REMOTE_100BTX_FD)
532 data |= PHY_AUTO_NEG_100BTX_FD;
533 if (link & PORT_REMOTE_100BTX)
534 data |= PHY_AUTO_NEG_100BTX;
535 if (link & PORT_REMOTE_10BT_FD)
536 data |= PHY_AUTO_NEG_10BT_FD;
537 if (link & PORT_REMOTE_10BT)
538 data |= PHY_AUTO_NEG_10BT;
539 if (data & ~PHY_AUTO_NEG_802_3)
540 data |= PHY_REMOTE_ACKNOWLEDGE_NOT;
541 break;
542 default:
543 processed = false;
544 break;
545 }
546 if (processed)
547 *val = data;
548}
549
550static void ksz8795_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
551{
552 u8 p = phy;
553 u8 restart, speed, ctrl, data;
554
555 switch (reg) {
556 case PHY_REG_CTRL:
557
558 /* Do not support PHY reset function. */
559 if (val & PHY_RESET)
560 break;
561 ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
562 data = speed;
563 if (val & PHY_HP_MDIX)
564 data |= PORT_HP_MDIX;
565 else
566 data &= ~PORT_HP_MDIX;
567 if (data != speed)
568 ksz_pwrite8(dev, p, P_SPEED_STATUS, data);
569 ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
570 data = ctrl;
571 if (!(val & PHY_AUTO_NEG_ENABLE))
572 data |= PORT_AUTO_NEG_DISABLE;
573 else
574 data &= ~PORT_AUTO_NEG_DISABLE;
575
576 /* Fiber port does not support auto-negotiation. */
577 if (dev->ports[p].fiber)
578 data |= PORT_AUTO_NEG_DISABLE;
579 if (val & PHY_SPEED_100MBIT)
580 data |= PORT_FORCE_100_MBIT;
581 else
582 data &= ~PORT_FORCE_100_MBIT;
583 if (val & PHY_FULL_DUPLEX)
584 data |= PORT_FORCE_FULL_DUPLEX;
585 else
586 data &= ~PORT_FORCE_FULL_DUPLEX;
587 if (data != ctrl)
588 ksz_pwrite8(dev, p, P_FORCE_CTRL, data);
589 ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
590 data = restart;
591 if (val & PHY_LED_DISABLE)
592 data |= PORT_LED_OFF;
593 else
594 data &= ~PORT_LED_OFF;
595 if (val & PHY_TRANSMIT_DISABLE)
596 data |= PORT_TX_DISABLE;
597 else
598 data &= ~PORT_TX_DISABLE;
599 if (val & PHY_AUTO_NEG_RESTART)
600 data |= PORT_AUTO_NEG_RESTART;
601 else
602 data &= ~(PORT_AUTO_NEG_RESTART);
603 if (val & PHY_POWER_DOWN)
604 data |= PORT_POWER_DOWN;
605 else
606 data &= ~PORT_POWER_DOWN;
607 if (val & PHY_AUTO_MDIX_DISABLE)
608 data |= PORT_AUTO_MDIX_DISABLE;
609 else
610 data &= ~PORT_AUTO_MDIX_DISABLE;
611 if (val & PHY_FORCE_MDIX)
612 data |= PORT_FORCE_MDIX;
613 else
614 data &= ~PORT_FORCE_MDIX;
615 if (val & PHY_LOOPBACK)
616 data |= PORT_PHY_LOOPBACK;
617 else
618 data &= ~PORT_PHY_LOOPBACK;
619 if (data != restart)
620 ksz_pwrite8(dev, p, P_NEG_RESTART_CTRL, data);
621 break;
622 case PHY_REG_AUTO_NEGOTIATION:
623 ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
624 data = ctrl;
625 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
626 PORT_AUTO_NEG_100BTX_FD |
627 PORT_AUTO_NEG_100BTX |
628 PORT_AUTO_NEG_10BT_FD |
629 PORT_AUTO_NEG_10BT);
630 if (val & PHY_AUTO_NEG_SYM_PAUSE)
631 data |= PORT_AUTO_NEG_SYM_PAUSE;
632 if (val & PHY_AUTO_NEG_100BTX_FD)
633 data |= PORT_AUTO_NEG_100BTX_FD;
634 if (val & PHY_AUTO_NEG_100BTX)
635 data |= PORT_AUTO_NEG_100BTX;
636 if (val & PHY_AUTO_NEG_10BT_FD)
637 data |= PORT_AUTO_NEG_10BT_FD;
638 if (val & PHY_AUTO_NEG_10BT)
639 data |= PORT_AUTO_NEG_10BT;
640 if (data != ctrl)
641 ksz_pwrite8(dev, p, P_LOCAL_CTRL, data);
642 break;
643 default:
644 break;
645 }
646}
647
648static enum dsa_tag_protocol ksz8795_get_tag_protocol(struct dsa_switch *ds,
649 int port)
650{
651 return DSA_TAG_PROTO_KSZ8795;
652}
653
654static void ksz8795_get_strings(struct dsa_switch *ds, int port,
655 u32 stringset, uint8_t *buf)
656{
657 int i;
658
659 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
660 memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string,
661 ETH_GSTRING_LEN);
662 }
663}
664
665static void ksz8795_cfg_port_member(struct ksz_device *dev, int port,
666 u8 member)
667{
668 u8 data;
669
670 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
671 data &= ~PORT_VLAN_MEMBERSHIP;
672 data |= (member & dev->port_mask);
673 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
674 dev->ports[port].member = member;
675}
676
677static void ksz8795_port_stp_state_set(struct dsa_switch *ds, int port,
678 u8 state)
679{
680 struct ksz_device *dev = ds->priv;
681 int forward = dev->member;
682 struct ksz_port *p;
683 int member = -1;
684 u8 data;
685
686 p = &dev->ports[port];
687
688 ksz_pread8(dev, port, P_STP_CTRL, &data);
689 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
690
691 switch (state) {
692 case BR_STATE_DISABLED:
693 data |= PORT_LEARN_DISABLE;
694 if (port < SWITCH_PORT_NUM)
695 member = 0;
696 break;
697 case BR_STATE_LISTENING:
698 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
699 if (port < SWITCH_PORT_NUM &&
700 p->stp_state == BR_STATE_DISABLED)
701 member = dev->host_mask | p->vid_member;
702 break;
703 case BR_STATE_LEARNING:
704 data |= PORT_RX_ENABLE;
705 break;
706 case BR_STATE_FORWARDING:
707 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
708
709 /* This function is also used internally. */
710 if (port == dev->cpu_port)
711 break;
712
713 /* Port is a member of a bridge. */
714 if (dev->br_member & BIT(port)) {
715 dev->member |= BIT(port);
716 member = dev->member;
717 } else {
718 member = dev->host_mask | p->vid_member;
719 }
720 break;
721 case BR_STATE_BLOCKING:
722 data |= PORT_LEARN_DISABLE;
723 if (port < SWITCH_PORT_NUM &&
724 p->stp_state == BR_STATE_DISABLED)
725 member = dev->host_mask | p->vid_member;
726 break;
727 default:
728 dev_err(ds->dev, "invalid STP state: %d\n", state);
729 return;
730 }
731
732 ksz_pwrite8(dev, port, P_STP_CTRL, data);
733 p->stp_state = state;
734 if (data & PORT_RX_ENABLE)
735 dev->rx_ports |= BIT(port);
736 else
737 dev->rx_ports &= ~BIT(port);
738 if (data & PORT_TX_ENABLE)
739 dev->tx_ports |= BIT(port);
740 else
741 dev->tx_ports &= ~BIT(port);
742
743 /* Port membership may share register with STP state. */
744 if (member >= 0 && member != p->member)
745 ksz8795_cfg_port_member(dev, port, (u8)member);
746
747 /* Check if forwarding needs to be updated. */
748 if (state != BR_STATE_FORWARDING) {
749 if (dev->br_member & BIT(port))
750 dev->member &= ~BIT(port);
751 }
752
753 /* When topology has changed the function ksz_update_port_member
754 * should be called to modify port forwarding behavior.
755 */
756 if (forward != dev->member)
757 ksz_update_port_member(dev, port);
758}
759
760static void ksz8795_flush_dyn_mac_table(struct ksz_device *dev, int port)
761{
762 u8 learn[TOTAL_PORT_NUM];
763 int first, index, cnt;
764 struct ksz_port *p;
765
766 if ((uint)port < TOTAL_PORT_NUM) {
767 first = port;
768 cnt = port + 1;
769 } else {
770 /* Flush all ports. */
771 first = 0;
772 cnt = dev->mib_port_cnt;
773 }
774 for (index = first; index < cnt; index++) {
775 p = &dev->ports[index];
776 if (!p->on)
777 continue;
778 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
779 if (!(learn[index] & PORT_LEARN_DISABLE))
780 ksz_pwrite8(dev, index, P_STP_CTRL,
781 learn[index] | PORT_LEARN_DISABLE);
782 }
783 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
784 for (index = first; index < cnt; index++) {
785 p = &dev->ports[index];
786 if (!p->on)
787 continue;
788 if (!(learn[index] & PORT_LEARN_DISABLE))
789 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
790 }
791}
792
793static int ksz8795_port_vlan_filtering(struct dsa_switch *ds, int port,
794 bool flag)
795{
796 struct ksz_device *dev = ds->priv;
797
798 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
799
800 return 0;
801}
802
803static void ksz8795_port_vlan_add(struct dsa_switch *ds, int port,
804 const struct switchdev_obj_port_vlan *vlan)
805{
806 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
807 struct ksz_device *dev = ds->priv;
808 u16 data, vid, new_pvid = 0;
809 u8 fid, member, valid;
810
811 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
812
813 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
814 ksz8795_r_vlan_table(dev, vid, &data);
815 ksz8795_from_vlan(data, &fid, &member, &valid);
816
817 /* First time to setup the VLAN entry. */
818 if (!valid) {
819 /* Need to find a way to map VID to FID. */
820 fid = 1;
821 valid = 1;
822 }
823 member |= BIT(port);
824
825 ksz8795_to_vlan(fid, member, valid, &data);
826 ksz8795_w_vlan_table(dev, vid, data);
827
828 /* change PVID */
829 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
830 new_pvid = vid;
831 }
832
833 if (new_pvid) {
834 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
835 vid &= 0xfff;
836 vid |= new_pvid;
837 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
838 }
839}
840
841static int ksz8795_port_vlan_del(struct dsa_switch *ds, int port,
842 const struct switchdev_obj_port_vlan *vlan)
843{
844 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
845 struct ksz_device *dev = ds->priv;
846 u16 data, vid, pvid, new_pvid = 0;
847 u8 fid, member, valid;
848
849 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
850 pvid = pvid & 0xFFF;
851
852 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
853
854 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
855 ksz8795_r_vlan_table(dev, vid, &data);
856 ksz8795_from_vlan(data, &fid, &member, &valid);
857
858 member &= ~BIT(port);
859
860 /* Invalidate the entry if no more member. */
861 if (!member) {
862 fid = 0;
863 valid = 0;
864 }
865
866 if (pvid == vid)
867 new_pvid = 1;
868
869 ksz8795_to_vlan(fid, member, valid, &data);
870 ksz8795_w_vlan_table(dev, vid, data);
871 }
872
873 if (new_pvid != pvid)
874 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, pvid);
875
876 return 0;
877}
878
879static int ksz8795_port_mirror_add(struct dsa_switch *ds, int port,
880 struct dsa_mall_mirror_tc_entry *mirror,
881 bool ingress)
882{
883 struct ksz_device *dev = ds->priv;
884
885 if (ingress) {
886 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
887 dev->mirror_rx |= BIT(port);
888 } else {
889 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
890 dev->mirror_tx |= BIT(port);
891 }
892
893 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
894
895 /* configure mirror port */
896 if (dev->mirror_rx || dev->mirror_tx)
897 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
898 PORT_MIRROR_SNIFFER, true);
899
900 return 0;
901}
902
903static void ksz8795_port_mirror_del(struct dsa_switch *ds, int port,
904 struct dsa_mall_mirror_tc_entry *mirror)
905{
906 struct ksz_device *dev = ds->priv;
907 u8 data;
908
909 if (mirror->ingress) {
910 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
911 dev->mirror_rx &= ~BIT(port);
912 } else {
913 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
914 dev->mirror_tx &= ~BIT(port);
915 }
916
917 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
918
919 if (!dev->mirror_rx && !dev->mirror_tx)
920 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
921 PORT_MIRROR_SNIFFER, false);
922}
923
924static void ksz8795_port_setup(struct ksz_device *dev, int port, bool cpu_port)
925{
926 struct ksz_port *p = &dev->ports[port];
927 u8 data8, member;
928
929 /* enable broadcast storm limit */
930 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
931
932 ksz8795_set_prio_queue(dev, port, 4);
933
934 /* disable DiffServ priority */
935 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
936
937 /* replace priority */
938 ksz_port_cfg(dev, port, P_802_1P_CTRL, PORT_802_1P_REMAPPING, false);
939
940 /* enable 802.1p priority */
941 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
942
943 if (cpu_port) {
944 /* Configure MII interface for proper network communication. */
945 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
946 data8 &= ~PORT_INTERFACE_TYPE;
947 data8 &= ~PORT_GMII_1GPS_MODE;
948 switch (dev->interface) {
949 case PHY_INTERFACE_MODE_MII:
950 p->phydev.speed = SPEED_100;
951 break;
952 case PHY_INTERFACE_MODE_RMII:
953 data8 |= PORT_INTERFACE_RMII;
954 p->phydev.speed = SPEED_100;
955 break;
956 case PHY_INTERFACE_MODE_GMII:
957 data8 |= PORT_GMII_1GPS_MODE;
958 data8 |= PORT_INTERFACE_GMII;
959 p->phydev.speed = SPEED_1000;
960 break;
961 default:
962 data8 &= ~PORT_RGMII_ID_IN_ENABLE;
963 data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
964 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
965 dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
966 data8 |= PORT_RGMII_ID_IN_ENABLE;
967 if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
968 dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
969 data8 |= PORT_RGMII_ID_OUT_ENABLE;
970 data8 |= PORT_GMII_1GPS_MODE;
971 data8 |= PORT_INTERFACE_RGMII;
972 p->phydev.speed = SPEED_1000;
973 break;
974 }
975 ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
976 p->phydev.duplex = 1;
977
978 member = dev->port_mask;
979 dev->on_ports = dev->host_mask;
980 dev->live_ports = dev->host_mask;
981 } else {
982 member = dev->host_mask | p->vid_member;
983 dev->on_ports |= BIT(port);
984
985 /* Link was detected before port is enabled. */
986 if (p->phydev.link)
987 dev->live_ports |= BIT(port);
988 }
989 ksz8795_cfg_port_member(dev, port, member);
990}
991
992static void ksz8795_config_cpu_port(struct dsa_switch *ds)
993{
994 struct ksz_device *dev = ds->priv;
995 struct ksz_port *p;
996 u8 remote;
997 int i;
998
999 ds->num_ports = dev->port_cnt + 1;
1000
1001 /* Switch marks the maximum frame with extra byte as oversize. */
1002 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1003 ksz_cfg(dev, S_TAIL_TAG_CTRL, SW_TAIL_TAG_ENABLE, true);
1004
1005 p = &dev->ports[dev->cpu_port];
1006 p->vid_member = dev->port_mask;
1007 p->on = 1;
1008
1009 ksz8795_port_setup(dev, dev->cpu_port, true);
1010 dev->member = dev->host_mask;
1011
1012 for (i = 0; i < SWITCH_PORT_NUM; i++) {
1013 p = &dev->ports[i];
1014
1015 /* Initialize to non-zero so that ksz_cfg_port_member() will
1016 * be called.
1017 */
1018 p->vid_member = BIT(i);
1019 p->member = dev->port_mask;
1020 ksz8795_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1021
1022 /* Last port may be disabled. */
1023 if (i == dev->port_cnt)
1024 break;
1025 p->on = 1;
1026 p->phy = 1;
1027 }
1028 for (i = 0; i < dev->phy_port_cnt; i++) {
1029 p = &dev->ports[i];
1030 if (!p->on)
1031 continue;
1032 ksz_pread8(dev, i, P_REMOTE_STATUS, &remote);
1033 if (remote & PORT_FIBER_MODE)
1034 p->fiber = 1;
1035 if (p->fiber)
1036 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1037 true);
1038 else
1039 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1040 false);
1041 }
1042}
1043
1044static int ksz8795_setup(struct dsa_switch *ds)
1045{
1046 struct ksz_device *dev = ds->priv;
1047 struct alu_struct alu;
1048 int i, ret = 0;
1049
1050 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1051 dev->num_vlans, GFP_KERNEL);
1052 if (!dev->vlan_cache)
1053 return -ENOMEM;
1054
1055 ret = ksz8795_reset_switch(dev);
1056 if (ret) {
1057 dev_err(ds->dev, "failed to reset switch\n");
1058 return ret;
1059 }
1060
1061 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1062
1063 /* Enable automatic fast aging when link changed detected. */
1064 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1065
1066 /* Enable aggressive back off algorithm in half duplex mode. */
1067 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1068 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1069
1070 /*
1071 * Make sure unicast VLAN boundary is set as default and
1072 * enable no excessive collision drop.
1073 */
1074 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1075 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1076 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1077
1078 ksz8795_config_cpu_port(ds);
1079
1080 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true);
1081
1082 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1083
1084 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1085
1086 /* set broadcast storm protection 10% rate */
1087 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL,
1088 BROADCAST_STORM_RATE,
1089 (BROADCAST_STORM_VALUE *
1090 BROADCAST_STORM_PROT_RATE) / 100);
1091
1092 for (i = 0; i < VLAN_TABLE_ENTRIES; i++)
1093 ksz8795_r_vlan_entries(dev, i);
1094
1095 /* Setup STP address for STP operation. */
1096 memset(&alu, 0, sizeof(alu));
1097 ether_addr_copy(alu.mac, eth_stp_addr);
1098 alu.is_static = true;
1099 alu.is_override = true;
1100 alu.port_forward = dev->host_mask;
1101
1102 ksz8795_w_sta_mac_table(dev, 0, &alu);
1103
1104 ksz_init_mib_timer(dev);
1105
1106 return 0;
1107}
1108
1109static const struct dsa_switch_ops ksz8795_switch_ops = {
1110 .get_tag_protocol = ksz8795_get_tag_protocol,
1111 .setup = ksz8795_setup,
1112 .phy_read = ksz_phy_read16,
1113 .phy_write = ksz_phy_write16,
1114 .adjust_link = ksz_adjust_link,
1115 .port_enable = ksz_enable_port,
1116 .port_disable = ksz_disable_port,
1117 .get_strings = ksz8795_get_strings,
1118 .get_ethtool_stats = ksz_get_ethtool_stats,
1119 .get_sset_count = ksz_sset_count,
1120 .port_bridge_join = ksz_port_bridge_join,
1121 .port_bridge_leave = ksz_port_bridge_leave,
1122 .port_stp_state_set = ksz8795_port_stp_state_set,
1123 .port_fast_age = ksz_port_fast_age,
1124 .port_vlan_filtering = ksz8795_port_vlan_filtering,
1125 .port_vlan_prepare = ksz_port_vlan_prepare,
1126 .port_vlan_add = ksz8795_port_vlan_add,
1127 .port_vlan_del = ksz8795_port_vlan_del,
1128 .port_fdb_dump = ksz_port_fdb_dump,
1129 .port_mdb_prepare = ksz_port_mdb_prepare,
1130 .port_mdb_add = ksz_port_mdb_add,
1131 .port_mdb_del = ksz_port_mdb_del,
1132 .port_mirror_add = ksz8795_port_mirror_add,
1133 .port_mirror_del = ksz8795_port_mirror_del,
1134};
1135
1136static u32 ksz8795_get_port_addr(int port, int offset)
1137{
1138 return PORT_CTRL_ADDR(port, offset);
1139}
1140
1141static int ksz8795_switch_detect(struct ksz_device *dev)
1142{
1143 u8 id1, id2;
1144 u16 id16;
1145 int ret;
1146
1147 /* read chip id */
1148 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1149 if (ret)
1150 return ret;
1151
1152 id1 = id16 >> 8;
1153 id2 = id16 & SW_CHIP_ID_M;
1154 if (id1 != FAMILY_ID ||
1155 (id2 != CHIP_ID_94 && id2 != CHIP_ID_95))
1156 return -ENODEV;
1157
1158 dev->mib_port_cnt = TOTAL_PORT_NUM;
1159 dev->phy_port_cnt = SWITCH_PORT_NUM;
1160 dev->port_cnt = SWITCH_PORT_NUM;
1161
1162 if (id2 == CHIP_ID_95) {
1163 u8 val;
1164
1165 id2 = 0x95;
1166 ksz_read8(dev, REG_PORT_1_STATUS_0, &val);
1167 if (val & PORT_FIBER_MODE)
1168 id2 = 0x65;
1169 } else if (id2 == CHIP_ID_94) {
1170 dev->port_cnt--;
1171 dev->last_port = dev->port_cnt;
1172 id2 = 0x94;
1173 }
1174 id16 &= ~0xff;
1175 id16 |= id2;
1176 dev->chip_id = id16;
1177
1178 dev->cpu_port = dev->mib_port_cnt - 1;
1179 dev->host_mask = BIT(dev->cpu_port);
1180
1181 return 0;
1182}
1183
1184struct ksz_chip_data {
1185 u16 chip_id;
1186 const char *dev_name;
1187 int num_vlans;
1188 int num_alus;
1189 int num_statics;
1190 int cpu_ports;
1191 int port_cnt;
1192};
1193
1194static const struct ksz_chip_data ksz8795_switch_chips[] = {
1195 {
1196 .chip_id = 0x8795,
1197 .dev_name = "KSZ8795",
1198 .num_vlans = 4096,
1199 .num_alus = 0,
1200 .num_statics = 8,
1201 .cpu_ports = 0x10, /* can be configured as cpu port */
1202 .port_cnt = 4, /* total physical port count */
1203 },
1204 {
1205 .chip_id = 0x8794,
1206 .dev_name = "KSZ8794",
1207 .num_vlans = 4096,
1208 .num_alus = 0,
1209 .num_statics = 8,
1210 .cpu_ports = 0x10, /* can be configured as cpu port */
1211 .port_cnt = 3, /* total physical port count */
1212 },
1213 {
1214 .chip_id = 0x8765,
1215 .dev_name = "KSZ8765",
1216 .num_vlans = 4096,
1217 .num_alus = 0,
1218 .num_statics = 8,
1219 .cpu_ports = 0x10, /* can be configured as cpu port */
1220 .port_cnt = 4, /* total physical port count */
1221 },
1222};
1223
1224static int ksz8795_switch_init(struct ksz_device *dev)
1225{
1226 int i;
1227
1228 mutex_init(&dev->stats_mutex);
1229 mutex_init(&dev->alu_mutex);
1230 mutex_init(&dev->vlan_mutex);
1231
1232 dev->ds->ops = &ksz8795_switch_ops;
1233
1234 for (i = 0; i < ARRAY_SIZE(ksz8795_switch_chips); i++) {
1235 const struct ksz_chip_data *chip = &ksz8795_switch_chips[i];
1236
1237 if (dev->chip_id == chip->chip_id) {
1238 dev->name = chip->dev_name;
1239 dev->num_vlans = chip->num_vlans;
1240 dev->num_alus = chip->num_alus;
1241 dev->num_statics = chip->num_statics;
1242 dev->port_cnt = chip->port_cnt;
1243 dev->cpu_ports = chip->cpu_ports;
1244
1245 break;
1246 }
1247 }
1248
1249 /* no switch found */
1250 if (!dev->cpu_ports)
1251 return -ENODEV;
1252
1253 dev->port_mask = BIT(dev->port_cnt) - 1;
1254 dev->port_mask |= dev->host_mask;
1255
1256 dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1257 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1258
1259 i = dev->mib_port_cnt;
1260 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1261 GFP_KERNEL);
1262 if (!dev->ports)
1263 return -ENOMEM;
1264 for (i = 0; i < dev->mib_port_cnt; i++) {
1265 mutex_init(&dev->ports[i].mib.cnt_mutex);
1266 dev->ports[i].mib.counters =
1267 devm_kzalloc(dev->dev,
1268 sizeof(u64) *
1269 (TOTAL_SWITCH_COUNTER_NUM + 1),
1270 GFP_KERNEL);
1271 if (!dev->ports[i].mib.counters)
1272 return -ENOMEM;
1273 }
1274
1275 return 0;
1276}
1277
1278static void ksz8795_switch_exit(struct ksz_device *dev)
1279{
1280 ksz8795_reset_switch(dev);
1281}
1282
1283static const struct ksz_dev_ops ksz8795_dev_ops = {
1284 .get_port_addr = ksz8795_get_port_addr,
1285 .cfg_port_member = ksz8795_cfg_port_member,
1286 .flush_dyn_mac_table = ksz8795_flush_dyn_mac_table,
1287 .port_setup = ksz8795_port_setup,
1288 .r_phy = ksz8795_r_phy,
1289 .w_phy = ksz8795_w_phy,
1290 .r_dyn_mac_table = ksz8795_r_dyn_mac_table,
1291 .r_sta_mac_table = ksz8795_r_sta_mac_table,
1292 .w_sta_mac_table = ksz8795_w_sta_mac_table,
1293 .r_mib_cnt = ksz8795_r_mib_cnt,
1294 .r_mib_pkt = ksz8795_r_mib_pkt,
1295 .freeze_mib = ksz8795_freeze_mib,
1296 .port_init_cnt = ksz8795_port_init_cnt,
1297 .shutdown = ksz8795_reset_switch,
1298 .detect = ksz8795_switch_detect,
1299 .init = ksz8795_switch_init,
1300 .exit = ksz8795_switch_exit,
1301};
1302
1303int ksz8795_switch_register(struct ksz_device *dev)
1304{
1305 return ksz_switch_register(dev, &ksz8795_dev_ops);
1306}
1307EXPORT_SYMBOL(ksz8795_switch_register);
1308
1309MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1310MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1311MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/microchip/ksz8795_reg.h b/drivers/net/dsa/microchip/ksz8795_reg.h
new file mode 100644
index 000000000000..3a50462df8fa
--- /dev/null
+++ b/drivers/net/dsa/microchip/ksz8795_reg.h
@@ -0,0 +1,1004 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Microchip KSZ8795 register definitions
4 *
5 * Copyright (c) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#ifndef __KSZ8795_REG_H
10#define __KSZ8795_REG_H
11
12#define KS_PORT_M 0x1F
13
14#define KS_PRIO_M 0x3
15#define KS_PRIO_S 2
16
17#define REG_CHIP_ID0 0x00
18
19#define FAMILY_ID 0x87
20
21#define REG_CHIP_ID1 0x01
22
23#define SW_CHIP_ID_M 0xF0
24#define SW_CHIP_ID_S 4
25#define SW_REVISION_M 0x0E
26#define SW_REVISION_S 1
27#define SW_START 0x01
28
29#define CHIP_ID_94 0x60
30#define CHIP_ID_95 0x90
31
32#define REG_SW_CTRL_0 0x02
33
34#define SW_NEW_BACKOFF BIT(7)
35#define SW_GLOBAL_RESET BIT(6)
36#define SW_FLUSH_DYN_MAC_TABLE BIT(5)
37#define SW_FLUSH_STA_MAC_TABLE BIT(4)
38#define SW_LINK_AUTO_AGING BIT(0)
39
40#define REG_SW_CTRL_1 0x03
41
42#define SW_HUGE_PACKET BIT(6)
43#define SW_TX_FLOW_CTRL_DISABLE BIT(5)
44#define SW_RX_FLOW_CTRL_DISABLE BIT(4)
45#define SW_CHECK_LENGTH BIT(3)
46#define SW_AGING_ENABLE BIT(2)
47#define SW_FAST_AGING BIT(1)
48#define SW_AGGR_BACKOFF BIT(0)
49
50#define REG_SW_CTRL_2 0x04
51
52#define UNICAST_VLAN_BOUNDARY BIT(7)
53#define MULTICAST_STORM_DISABLE BIT(6)
54#define SW_BACK_PRESSURE BIT(5)
55#define FAIR_FLOW_CTRL BIT(4)
56#define NO_EXC_COLLISION_DROP BIT(3)
57#define SW_LEGAL_PACKET_DISABLE BIT(1)
58
59#define REG_SW_CTRL_3 0x05
60 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3)
61
62#define SW_VLAN_ENABLE BIT(7)
63#define SW_IGMP_SNOOP BIT(6)
64#define SW_MIRROR_RX_TX BIT(0)
65
66#define REG_SW_CTRL_4 0x06
67
68#define SW_HALF_DUPLEX_FLOW_CTRL BIT(7)
69#define SW_HALF_DUPLEX BIT(6)
70#define SW_FLOW_CTRL BIT(5)
71#define SW_10_MBIT BIT(4)
72#define SW_REPLACE_VID BIT(3)
73#define BROADCAST_STORM_RATE_HI 0x07
74
75#define REG_SW_CTRL_5 0x07
76
77#define BROADCAST_STORM_RATE_LO 0xFF
78#define BROADCAST_STORM_RATE 0x07FF
79
80#define REG_SW_CTRL_6 0x08
81
82#define SW_MIB_COUNTER_FLUSH BIT(7)
83#define SW_MIB_COUNTER_FREEZE BIT(6)
84#define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M
85
86#define REG_SW_CTRL_9 0x0B
87
88#define SPI_CLK_125_MHZ 0x80
89#define SPI_CLK_62_5_MHZ 0x40
90#define SPI_CLK_31_25_MHZ 0x00
91
92#define SW_LED_MODE_M 0x3
93#define SW_LED_MODE_S 4
94#define SW_LED_LINK_ACT_SPEED 0
95#define SW_LED_LINK_ACT 1
96#define SW_LED_LINK_ACT_DUPLEX 2
97#define SW_LED_LINK_DUPLEX 3
98
99#define REG_SW_CTRL_10 0x0C
100
101#define SW_TAIL_TAG_ENABLE BIT(1)
102#define SW_PASS_PAUSE BIT(0)
103
104#define REG_SW_CTRL_11 0x0D
105
106#define REG_POWER_MANAGEMENT_1 0x0E
107
108#define SW_PLL_POWER_DOWN BIT(5)
109#define SW_POWER_MANAGEMENT_MODE_M 0x3
110#define SW_POWER_MANAGEMENT_MODE_S 3
111#define SW_POWER_NORMAL 0
112#define SW_ENERGY_DETECTION 1
113#define SW_SOFTWARE_POWER_DOWN 2
114
115#define REG_POWER_MANAGEMENT_2 0x0F
116
117#define REG_PORT_1_CTRL_0 0x10
118#define REG_PORT_2_CTRL_0 0x20
119#define REG_PORT_3_CTRL_0 0x30
120#define REG_PORT_4_CTRL_0 0x40
121#define REG_PORT_5_CTRL_0 0x50
122
123#define PORT_BROADCAST_STORM BIT(7)
124#define PORT_DIFFSERV_ENABLE BIT(6)
125#define PORT_802_1P_ENABLE BIT(5)
126#define PORT_BASED_PRIO_S 3
127#define PORT_BASED_PRIO_M KS_PRIO_M
128#define PORT_BASED_PRIO_0 0
129#define PORT_BASED_PRIO_1 1
130#define PORT_BASED_PRIO_2 2
131#define PORT_BASED_PRIO_3 3
132#define PORT_INSERT_TAG BIT(2)
133#define PORT_REMOVE_TAG BIT(1)
134#define PORT_QUEUE_SPLIT_L BIT(0)
135
136#define REG_PORT_1_CTRL_1 0x11
137#define REG_PORT_2_CTRL_1 0x21
138#define REG_PORT_3_CTRL_1 0x31
139#define REG_PORT_4_CTRL_1 0x41
140#define REG_PORT_5_CTRL_1 0x51
141
142#define PORT_MIRROR_SNIFFER BIT(7)
143#define PORT_MIRROR_RX BIT(6)
144#define PORT_MIRROR_TX BIT(5)
145#define PORT_VLAN_MEMBERSHIP KS_PORT_M
146
147#define REG_PORT_1_CTRL_2 0x12
148#define REG_PORT_2_CTRL_2 0x22
149#define REG_PORT_3_CTRL_2 0x32
150#define REG_PORT_4_CTRL_2 0x42
151#define REG_PORT_5_CTRL_2 0x52
152
153#define PORT_802_1P_REMAPPING BIT(7)
154#define PORT_INGRESS_FILTER BIT(6)
155#define PORT_DISCARD_NON_VID BIT(5)
156#define PORT_FORCE_FLOW_CTRL BIT(4)
157#define PORT_BACK_PRESSURE BIT(3)
158#define PORT_TX_ENABLE BIT(2)
159#define PORT_RX_ENABLE BIT(1)
160#define PORT_LEARN_DISABLE BIT(0)
161
162#define REG_PORT_1_CTRL_3 0x13
163#define REG_PORT_2_CTRL_3 0x23
164#define REG_PORT_3_CTRL_3 0x33
165#define REG_PORT_4_CTRL_3 0x43
166#define REG_PORT_5_CTRL_3 0x53
167#define REG_PORT_1_CTRL_4 0x14
168#define REG_PORT_2_CTRL_4 0x24
169#define REG_PORT_3_CTRL_4 0x34
170#define REG_PORT_4_CTRL_4 0x44
171#define REG_PORT_5_CTRL_4 0x54
172
173#define PORT_DEFAULT_VID 0x0001
174
175#define REG_PORT_1_CTRL_5 0x15
176#define REG_PORT_2_CTRL_5 0x25
177#define REG_PORT_3_CTRL_5 0x35
178#define REG_PORT_4_CTRL_5 0x45
179#define REG_PORT_5_CTRL_5 0x55
180
181#define PORT_ACL_ENABLE BIT(2)
182#define PORT_AUTHEN_MODE 0x3
183#define PORT_AUTHEN_PASS 0
184#define PORT_AUTHEN_BLOCK 1
185#define PORT_AUTHEN_TRAP 2
186
187#define REG_PORT_5_CTRL_6 0x56
188
189#define PORT_MII_INTERNAL_CLOCK BIT(7)
190#define PORT_GMII_1GPS_MODE BIT(6)
191#define PORT_RGMII_ID_IN_ENABLE BIT(4)
192#define PORT_RGMII_ID_OUT_ENABLE BIT(3)
193#define PORT_GMII_MAC_MODE BIT(2)
194#define PORT_INTERFACE_TYPE 0x3
195#define PORT_INTERFACE_MII 0
196#define PORT_INTERFACE_RMII 1
197#define PORT_INTERFACE_GMII 2
198#define PORT_INTERFACE_RGMII 3
199
200#define REG_PORT_1_CTRL_7 0x17
201#define REG_PORT_2_CTRL_7 0x27
202#define REG_PORT_3_CTRL_7 0x37
203#define REG_PORT_4_CTRL_7 0x47
204
205#define PORT_AUTO_NEG_ASYM_PAUSE BIT(5)
206#define PORT_AUTO_NEG_SYM_PAUSE BIT(4)
207#define PORT_AUTO_NEG_100BTX_FD BIT(3)
208#define PORT_AUTO_NEG_100BTX BIT(2)
209#define PORT_AUTO_NEG_10BT_FD BIT(1)
210#define PORT_AUTO_NEG_10BT BIT(0)
211
212#define REG_PORT_1_STATUS_0 0x18
213#define REG_PORT_2_STATUS_0 0x28
214#define REG_PORT_3_STATUS_0 0x38
215#define REG_PORT_4_STATUS_0 0x48
216
217/* For KSZ8765. */
218#define PORT_FIBER_MODE BIT(7)
219
220#define PORT_REMOTE_ASYM_PAUSE BIT(5)
221#define PORT_REMOTE_SYM_PAUSE BIT(4)
222#define PORT_REMOTE_100BTX_FD BIT(3)
223#define PORT_REMOTE_100BTX BIT(2)
224#define PORT_REMOTE_10BT_FD BIT(1)
225#define PORT_REMOTE_10BT BIT(0)
226
227#define REG_PORT_1_STATUS_1 0x19
228#define REG_PORT_2_STATUS_1 0x29
229#define REG_PORT_3_STATUS_1 0x39
230#define REG_PORT_4_STATUS_1 0x49
231
232#define PORT_HP_MDIX BIT(7)
233#define PORT_REVERSED_POLARITY BIT(5)
234#define PORT_TX_FLOW_CTRL BIT(4)
235#define PORT_RX_FLOW_CTRL BIT(3)
236#define PORT_STAT_SPEED_100MBIT BIT(2)
237#define PORT_STAT_FULL_DUPLEX BIT(1)
238
239#define PORT_REMOTE_FAULT BIT(0)
240
241#define REG_PORT_1_LINK_MD_CTRL 0x1A
242#define REG_PORT_2_LINK_MD_CTRL 0x2A
243#define REG_PORT_3_LINK_MD_CTRL 0x3A
244#define REG_PORT_4_LINK_MD_CTRL 0x4A
245
246#define PORT_CABLE_10M_SHORT BIT(7)
247#define PORT_CABLE_DIAG_RESULT_M 0x3
248#define PORT_CABLE_DIAG_RESULT_S 5
249#define PORT_CABLE_STAT_NORMAL 0
250#define PORT_CABLE_STAT_OPEN 1
251#define PORT_CABLE_STAT_SHORT 2
252#define PORT_CABLE_STAT_FAILED 3
253#define PORT_START_CABLE_DIAG BIT(4)
254#define PORT_FORCE_LINK BIT(3)
255#define PORT_POWER_SAVING BIT(2)
256#define PORT_PHY_REMOTE_LOOPBACK BIT(1)
257#define PORT_CABLE_FAULT_COUNTER_H 0x01
258
259#define REG_PORT_1_LINK_MD_RESULT 0x1B
260#define REG_PORT_2_LINK_MD_RESULT 0x2B
261#define REG_PORT_3_LINK_MD_RESULT 0x3B
262#define REG_PORT_4_LINK_MD_RESULT 0x4B
263
264#define PORT_CABLE_FAULT_COUNTER_L 0xFF
265#define PORT_CABLE_FAULT_COUNTER 0x1FF
266
267#define REG_PORT_1_CTRL_9 0x1C
268#define REG_PORT_2_CTRL_9 0x2C
269#define REG_PORT_3_CTRL_9 0x3C
270#define REG_PORT_4_CTRL_9 0x4C
271
272#define PORT_AUTO_NEG_DISABLE BIT(7)
273#define PORT_FORCE_100_MBIT BIT(6)
274#define PORT_FORCE_FULL_DUPLEX BIT(5)
275
276#define REG_PORT_1_CTRL_10 0x1D
277#define REG_PORT_2_CTRL_10 0x2D
278#define REG_PORT_3_CTRL_10 0x3D
279#define REG_PORT_4_CTRL_10 0x4D
280
281#define PORT_LED_OFF BIT(7)
282#define PORT_TX_DISABLE BIT(6)
283#define PORT_AUTO_NEG_RESTART BIT(5)
284#define PORT_POWER_DOWN BIT(3)
285#define PORT_AUTO_MDIX_DISABLE BIT(2)
286#define PORT_FORCE_MDIX BIT(1)
287#define PORT_MAC_LOOPBACK BIT(0)
288
289#define REG_PORT_1_STATUS_2 0x1E
290#define REG_PORT_2_STATUS_2 0x2E
291#define REG_PORT_3_STATUS_2 0x3E
292#define REG_PORT_4_STATUS_2 0x4E
293
294#define PORT_MDIX_STATUS BIT(7)
295#define PORT_AUTO_NEG_COMPLETE BIT(6)
296#define PORT_STAT_LINK_GOOD BIT(5)
297
298#define REG_PORT_1_STATUS_3 0x1F
299#define REG_PORT_2_STATUS_3 0x2F
300#define REG_PORT_3_STATUS_3 0x3F
301#define REG_PORT_4_STATUS_3 0x4F
302
303#define PORT_PHY_LOOPBACK BIT(7)
304#define PORT_PHY_ISOLATE BIT(5)
305#define PORT_PHY_SOFT_RESET BIT(4)
306#define PORT_PHY_FORCE_LINK BIT(3)
307#define PORT_PHY_MODE_M 0x7
308#define PHY_MODE_IN_AUTO_NEG 1
309#define PHY_MODE_10BT_HALF 2
310#define PHY_MODE_100BT_HALF 3
311#define PHY_MODE_10BT_FULL 5
312#define PHY_MODE_100BT_FULL 6
313#define PHY_MODE_ISOLDATE 7
314
315#define REG_PORT_CTRL_0 0x00
316#define REG_PORT_CTRL_1 0x01
317#define REG_PORT_CTRL_2 0x02
318#define REG_PORT_CTRL_VID 0x03
319
320#define REG_PORT_CTRL_5 0x05
321
322#define REG_PORT_CTRL_7 0x07
323#define REG_PORT_STATUS_0 0x08
324#define REG_PORT_STATUS_1 0x09
325#define REG_PORT_LINK_MD_CTRL 0x0A
326#define REG_PORT_LINK_MD_RESULT 0x0B
327#define REG_PORT_CTRL_9 0x0C
328#define REG_PORT_CTRL_10 0x0D
329#define REG_PORT_STATUS_2 0x0E
330#define REG_PORT_STATUS_3 0x0F
331
332#define REG_PORT_CTRL_12 0xA0
333#define REG_PORT_CTRL_13 0xA1
334#define REG_PORT_RATE_CTRL_3 0xA2
335#define REG_PORT_RATE_CTRL_2 0xA3
336#define REG_PORT_RATE_CTRL_1 0xA4
337#define REG_PORT_RATE_CTRL_0 0xA5
338#define REG_PORT_RATE_LIMIT 0xA6
339#define REG_PORT_IN_RATE_0 0xA7
340#define REG_PORT_IN_RATE_1 0xA8
341#define REG_PORT_IN_RATE_2 0xA9
342#define REG_PORT_IN_RATE_3 0xAA
343#define REG_PORT_OUT_RATE_0 0xAB
344#define REG_PORT_OUT_RATE_1 0xAC
345#define REG_PORT_OUT_RATE_2 0xAD
346#define REG_PORT_OUT_RATE_3 0xAE
347
348#define PORT_CTRL_ADDR(port, addr) \
349 ((addr) + REG_PORT_1_CTRL_0 + (port) * \
350 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))
351
352#define REG_SW_MAC_ADDR_0 0x68
353#define REG_SW_MAC_ADDR_1 0x69
354#define REG_SW_MAC_ADDR_2 0x6A
355#define REG_SW_MAC_ADDR_3 0x6B
356#define REG_SW_MAC_ADDR_4 0x6C
357#define REG_SW_MAC_ADDR_5 0x6D
358
359#define REG_IND_CTRL_0 0x6E
360
361#define TABLE_EXT_SELECT_S 5
362#define TABLE_EEE_V 1
363#define TABLE_ACL_V 2
364#define TABLE_PME_V 4
365#define TABLE_LINK_MD_V 5
366#define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S)
367#define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S)
368#define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S)
369#define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S)
370#define TABLE_READ BIT(4)
371#define TABLE_SELECT_S 2
372#define TABLE_STATIC_MAC_V 0
373#define TABLE_VLAN_V 1
374#define TABLE_DYNAMIC_MAC_V 2
375#define TABLE_MIB_V 3
376#define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S)
377#define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S)
378#define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S)
379#define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S)
380
381#define REG_IND_CTRL_1 0x6F
382
383#define TABLE_ENTRY_MASK 0x03FF
384#define TABLE_EXT_ENTRY_MASK 0x0FFF
385
386#define REG_IND_DATA_8 0x70
387#define REG_IND_DATA_7 0x71
388#define REG_IND_DATA_6 0x72
389#define REG_IND_DATA_5 0x73
390#define REG_IND_DATA_4 0x74
391#define REG_IND_DATA_3 0x75
392#define REG_IND_DATA_2 0x76
393#define REG_IND_DATA_1 0x77
394#define REG_IND_DATA_0 0x78
395
396#define REG_IND_DATA_PME_EEE_ACL 0xA0
397
398#define REG_IND_DATA_CHECK REG_IND_DATA_6
399#define REG_IND_MIB_CHECK REG_IND_DATA_4
400#define REG_IND_DATA_HI REG_IND_DATA_7
401#define REG_IND_DATA_LO REG_IND_DATA_3
402
403#define REG_INT_STATUS 0x7C
404#define REG_INT_ENABLE 0x7D
405
406#define INT_PME BIT(4)
407
408#define REG_ACL_INT_STATUS 0x7E
409#define REG_ACL_INT_ENABLE 0x7F
410
411#define INT_PORT_5 BIT(4)
412#define INT_PORT_4 BIT(3)
413#define INT_PORT_3 BIT(2)
414#define INT_PORT_2 BIT(1)
415#define INT_PORT_1 BIT(0)
416
417#define INT_PORT_ALL \
418 (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1)
419
420#define REG_SW_CTRL_12 0x80
421#define REG_SW_CTRL_13 0x81
422
423#define SWITCH_802_1P_MASK 3
424#define SWITCH_802_1P_BASE 3
425#define SWITCH_802_1P_SHIFT 2
426
427#define SW_802_1P_MAP_M KS_PRIO_M
428#define SW_802_1P_MAP_S KS_PRIO_S
429
430#define REG_SWITCH_CTRL_14 0x82
431
432#define SW_PRIO_MAPPING_M KS_PRIO_M
433#define SW_PRIO_MAPPING_S 6
434#define SW_PRIO_MAP_3_HI 0
435#define SW_PRIO_MAP_2_HI 2
436#define SW_PRIO_MAP_0_LO 3
437
438#define REG_SW_CTRL_15 0x83
439#define REG_SW_CTRL_16 0x84
440#define REG_SW_CTRL_17 0x85
441#define REG_SW_CTRL_18 0x86
442
443#define SW_SELF_ADDR_FILTER_ENABLE BIT(6)
444
445#define REG_SW_UNK_UCAST_CTRL 0x83
446#define REG_SW_UNK_MCAST_CTRL 0x84
447#define REG_SW_UNK_VID_CTRL 0x85
448#define REG_SW_UNK_IP_MCAST_CTRL 0x86
449
450#define SW_UNK_FWD_ENABLE BIT(5)
451#define SW_UNK_FWD_MAP KS_PORT_M
452
453#define REG_SW_CTRL_19 0x87
454
455#define SW_IN_RATE_LIMIT_PERIOD_M 0x3
456#define SW_IN_RATE_LIMIT_PERIOD_S 4
457#define SW_IN_RATE_LIMIT_16_MS 0
458#define SW_IN_RATE_LIMIT_64_MS 1
459#define SW_IN_RATE_LIMIT_256_MS 2
460#define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
461#define SW_INS_TAG_ENABLE BIT(2)
462
463#define REG_TOS_PRIO_CTRL_0 0x90
464#define REG_TOS_PRIO_CTRL_1 0x91
465#define REG_TOS_PRIO_CTRL_2 0x92
466#define REG_TOS_PRIO_CTRL_3 0x93
467#define REG_TOS_PRIO_CTRL_4 0x94
468#define REG_TOS_PRIO_CTRL_5 0x95
469#define REG_TOS_PRIO_CTRL_6 0x96
470#define REG_TOS_PRIO_CTRL_7 0x97
471#define REG_TOS_PRIO_CTRL_8 0x98
472#define REG_TOS_PRIO_CTRL_9 0x99
473#define REG_TOS_PRIO_CTRL_10 0x9A
474#define REG_TOS_PRIO_CTRL_11 0x9B
475#define REG_TOS_PRIO_CTRL_12 0x9C
476#define REG_TOS_PRIO_CTRL_13 0x9D
477#define REG_TOS_PRIO_CTRL_14 0x9E
478#define REG_TOS_PRIO_CTRL_15 0x9F
479
480#define TOS_PRIO_M KS_PRIO_M
481#define TOS_PRIO_S KS_PRIO_S
482
483#define REG_SW_CTRL_20 0xA3
484
485#define SW_GMII_DRIVE_STRENGTH_S 4
486#define SW_DRIVE_STRENGTH_M 0x7
487#define SW_DRIVE_STRENGTH_2MA 0
488#define SW_DRIVE_STRENGTH_4MA 1
489#define SW_DRIVE_STRENGTH_8MA 2
490#define SW_DRIVE_STRENGTH_12MA 3
491#define SW_DRIVE_STRENGTH_16MA 4
492#define SW_DRIVE_STRENGTH_20MA 5
493#define SW_DRIVE_STRENGTH_24MA 6
494#define SW_DRIVE_STRENGTH_28MA 7
495#define SW_MII_DRIVE_STRENGTH_S 0
496
497#define REG_SW_CTRL_21 0xA4
498
499#define SW_IPV6_MLD_OPTION BIT(3)
500#define SW_IPV6_MLD_SNOOP BIT(2)
501
502#define REG_PORT_1_CTRL_12 0xB0
503#define REG_PORT_2_CTRL_12 0xC0
504#define REG_PORT_3_CTRL_12 0xD0
505#define REG_PORT_4_CTRL_12 0xE0
506#define REG_PORT_5_CTRL_12 0xF0
507
508#define PORT_PASS_ALL BIT(6)
509#define PORT_INS_TAG_FOR_PORT_5_S 3
510#define PORT_INS_TAG_FOR_PORT_5 BIT(3)
511#define PORT_INS_TAG_FOR_PORT_4 BIT(2)
512#define PORT_INS_TAG_FOR_PORT_3 BIT(1)
513#define PORT_INS_TAG_FOR_PORT_2 BIT(0)
514
515#define REG_PORT_1_CTRL_13 0xB1
516#define REG_PORT_2_CTRL_13 0xC1
517#define REG_PORT_3_CTRL_13 0xD1
518#define REG_PORT_4_CTRL_13 0xE1
519#define REG_PORT_5_CTRL_13 0xF1
520
521#define PORT_QUEUE_SPLIT_H BIT(1)
522#define PORT_QUEUE_SPLIT_1 0
523#define PORT_QUEUE_SPLIT_2 1
524#define PORT_QUEUE_SPLIT_4 2
525#define PORT_DROP_TAG BIT(0)
526
527#define REG_PORT_1_CTRL_14 0xB2
528#define REG_PORT_2_CTRL_14 0xC2
529#define REG_PORT_3_CTRL_14 0xD2
530#define REG_PORT_4_CTRL_14 0xE2
531#define REG_PORT_5_CTRL_14 0xF2
532#define REG_PORT_1_CTRL_15 0xB3
533#define REG_PORT_2_CTRL_15 0xC3
534#define REG_PORT_3_CTRL_15 0xD3
535#define REG_PORT_4_CTRL_15 0xE3
536#define REG_PORT_5_CTRL_15 0xF3
537#define REG_PORT_1_CTRL_16 0xB4
538#define REG_PORT_2_CTRL_16 0xC4
539#define REG_PORT_3_CTRL_16 0xD4
540#define REG_PORT_4_CTRL_16 0xE4
541#define REG_PORT_5_CTRL_16 0xF4
542#define REG_PORT_1_CTRL_17 0xB5
543#define REG_PORT_2_CTRL_17 0xC5
544#define REG_PORT_3_CTRL_17 0xD5
545#define REG_PORT_4_CTRL_17 0xE5
546#define REG_PORT_5_CTRL_17 0xF5
547
548#define REG_PORT_1_RATE_CTRL_3 0xB2
549#define REG_PORT_1_RATE_CTRL_2 0xB3
550#define REG_PORT_1_RATE_CTRL_1 0xB4
551#define REG_PORT_1_RATE_CTRL_0 0xB5
552#define REG_PORT_2_RATE_CTRL_3 0xC2
553#define REG_PORT_2_RATE_CTRL_2 0xC3
554#define REG_PORT_2_RATE_CTRL_1 0xC4
555#define REG_PORT_2_RATE_CTRL_0 0xC5
556#define REG_PORT_3_RATE_CTRL_3 0xD2
557#define REG_PORT_3_RATE_CTRL_2 0xD3
558#define REG_PORT_3_RATE_CTRL_1 0xD4
559#define REG_PORT_3_RATE_CTRL_0 0xD5
560#define REG_PORT_4_RATE_CTRL_3 0xE2
561#define REG_PORT_4_RATE_CTRL_2 0xE3
562#define REG_PORT_4_RATE_CTRL_1 0xE4
563#define REG_PORT_4_RATE_CTRL_0 0xE5
564#define REG_PORT_5_RATE_CTRL_3 0xF2
565#define REG_PORT_5_RATE_CTRL_2 0xF3
566#define REG_PORT_5_RATE_CTRL_1 0xF4
567#define REG_PORT_5_RATE_CTRL_0 0xF5
568
569#define RATE_CTRL_ENABLE BIT(7)
570#define RATE_RATIO_M (BIT(7) - 1)
571
572#define PORT_OUT_RATE_ENABLE BIT(7)
573
574#define REG_PORT_1_RATE_LIMIT 0xB6
575#define REG_PORT_2_RATE_LIMIT 0xC6
576#define REG_PORT_3_RATE_LIMIT 0xD6
577#define REG_PORT_4_RATE_LIMIT 0xE6
578#define REG_PORT_5_RATE_LIMIT 0xF6
579
580#define PORT_IN_PORT_BASED_S 6
581#define PORT_RATE_PACKET_BASED_S 5
582#define PORT_IN_FLOW_CTRL_S 4
583#define PORT_IN_LIMIT_MODE_M 0x3
584#define PORT_IN_LIMIT_MODE_S 2
585#define PORT_COUNT_IFG_S 1
586#define PORT_COUNT_PREAMBLE_S 0
587#define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S)
588#define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S)
589#define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S)
590#define PORT_IN_ALL 0
591#define PORT_IN_UNICAST 1
592#define PORT_IN_MULTICAST 2
593#define PORT_IN_BROADCAST 3
594#define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S)
595#define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S)
596
597#define REG_PORT_1_IN_RATE_0 0xB7
598#define REG_PORT_2_IN_RATE_0 0xC7
599#define REG_PORT_3_IN_RATE_0 0xD7
600#define REG_PORT_4_IN_RATE_0 0xE7
601#define REG_PORT_5_IN_RATE_0 0xF7
602#define REG_PORT_1_IN_RATE_1 0xB8
603#define REG_PORT_2_IN_RATE_1 0xC8
604#define REG_PORT_3_IN_RATE_1 0xD8
605#define REG_PORT_4_IN_RATE_1 0xE8
606#define REG_PORT_5_IN_RATE_1 0xF8
607#define REG_PORT_1_IN_RATE_2 0xB9
608#define REG_PORT_2_IN_RATE_2 0xC9
609#define REG_PORT_3_IN_RATE_2 0xD9
610#define REG_PORT_4_IN_RATE_2 0xE9
611#define REG_PORT_5_IN_RATE_2 0xF9
612#define REG_PORT_1_IN_RATE_3 0xBA
613#define REG_PORT_2_IN_RATE_3 0xCA
614#define REG_PORT_3_IN_RATE_3 0xDA
615#define REG_PORT_4_IN_RATE_3 0xEA
616#define REG_PORT_5_IN_RATE_3 0xFA
617
618#define PORT_IN_RATE_ENABLE BIT(7)
619#define PORT_RATE_LIMIT_M (BIT(7) - 1)
620
621#define REG_PORT_1_OUT_RATE_0 0xBB
622#define REG_PORT_2_OUT_RATE_0 0xCB
623#define REG_PORT_3_OUT_RATE_0 0xDB
624#define REG_PORT_4_OUT_RATE_0 0xEB
625#define REG_PORT_5_OUT_RATE_0 0xFB
626#define REG_PORT_1_OUT_RATE_1 0xBC
627#define REG_PORT_2_OUT_RATE_1 0xCC
628#define REG_PORT_3_OUT_RATE_1 0xDC
629#define REG_PORT_4_OUT_RATE_1 0xEC
630#define REG_PORT_5_OUT_RATE_1 0xFC
631#define REG_PORT_1_OUT_RATE_2 0xBD
632#define REG_PORT_2_OUT_RATE_2 0xCD
633#define REG_PORT_3_OUT_RATE_2 0xDD
634#define REG_PORT_4_OUT_RATE_2 0xED
635#define REG_PORT_5_OUT_RATE_2 0xFD
636#define REG_PORT_1_OUT_RATE_3 0xBE
637#define REG_PORT_2_OUT_RATE_3 0xCE
638#define REG_PORT_3_OUT_RATE_3 0xDE
639#define REG_PORT_4_OUT_RATE_3 0xEE
640#define REG_PORT_5_OUT_RATE_3 0xFE
641
642/* PME */
643
644#define SW_PME_OUTPUT_ENABLE BIT(1)
645#define SW_PME_ACTIVE_HIGH BIT(0)
646
647#define PORT_MAGIC_PACKET_DETECT BIT(2)
648#define PORT_LINK_UP_DETECT BIT(1)
649#define PORT_ENERGY_DETECT BIT(0)
650
651/* ACL */
652
653#define ACL_FIRST_RULE_M 0xF
654
655#define ACL_MODE_M 0x3
656#define ACL_MODE_S 4
657#define ACL_MODE_DISABLE 0
658#define ACL_MODE_LAYER_2 1
659#define ACL_MODE_LAYER_3 2
660#define ACL_MODE_LAYER_4 3
661#define ACL_ENABLE_M 0x3
662#define ACL_ENABLE_S 2
663#define ACL_ENABLE_2_COUNT 0
664#define ACL_ENABLE_2_TYPE 1
665#define ACL_ENABLE_2_MAC 2
666#define ACL_ENABLE_2_BOTH 3
667#define ACL_ENABLE_3_IP 1
668#define ACL_ENABLE_3_SRC_DST_COMP 2
669#define ACL_ENABLE_4_PROTOCOL 0
670#define ACL_ENABLE_4_TCP_PORT_COMP 1
671#define ACL_ENABLE_4_UDP_PORT_COMP 2
672#define ACL_ENABLE_4_TCP_SEQN_COMP 3
673#define ACL_SRC BIT(1)
674#define ACL_EQUAL BIT(0)
675
676#define ACL_MAX_PORT 0xFFFF
677
678#define ACL_MIN_PORT 0xFFFF
679#define ACL_IP_ADDR 0xFFFFFFFF
680#define ACL_TCP_SEQNUM 0xFFFFFFFF
681
682#define ACL_RESERVED 0xF8
683#define ACL_PORT_MODE_M 0x3
684#define ACL_PORT_MODE_S 1
685#define ACL_PORT_MODE_DISABLE 0
686#define ACL_PORT_MODE_EITHER 1
687#define ACL_PORT_MODE_IN_RANGE 2
688#define ACL_PORT_MODE_OUT_OF_RANGE 3
689
690#define ACL_TCP_FLAG_ENABLE BIT(0)
691
692#define ACL_TCP_FLAG_M 0xFF
693
694#define ACL_TCP_FLAG 0xFF
695#define ACL_ETH_TYPE 0xFFFF
696#define ACL_IP_M 0xFFFFFFFF
697
698#define ACL_PRIO_MODE_M 0x3
699#define ACL_PRIO_MODE_S 6
700#define ACL_PRIO_MODE_DISABLE 0
701#define ACL_PRIO_MODE_HIGHER 1
702#define ACL_PRIO_MODE_LOWER 2
703#define ACL_PRIO_MODE_REPLACE 3
704#define ACL_PRIO_M 0x7
705#define ACL_PRIO_S 3
706#define ACL_VLAN_PRIO_REPLACE BIT(2)
707#define ACL_VLAN_PRIO_M 0x7
708#define ACL_VLAN_PRIO_HI_M 0x3
709
710#define ACL_VLAN_PRIO_LO_M 0x8
711#define ACL_VLAN_PRIO_S 7
712#define ACL_MAP_MODE_M 0x3
713#define ACL_MAP_MODE_S 5
714#define ACL_MAP_MODE_DISABLE 0
715#define ACL_MAP_MODE_OR 1
716#define ACL_MAP_MODE_AND 2
717#define ACL_MAP_MODE_REPLACE 3
718#define ACL_MAP_PORT_M 0x1F
719
720#define ACL_CNT_M (BIT(11) - 1)
721#define ACL_CNT_S 5
722#define ACL_MSEC_UNIT BIT(4)
723#define ACL_INTR_MODE BIT(3)
724
725#define REG_PORT_ACL_BYTE_EN_MSB 0x10
726
727#define ACL_BYTE_EN_MSB_M 0x3F
728
729#define REG_PORT_ACL_BYTE_EN_LSB 0x11
730
731#define ACL_ACTION_START 0xA
732#define ACL_ACTION_LEN 2
733#define ACL_INTR_CNT_START 0xB
734#define ACL_RULESET_START 0xC
735#define ACL_RULESET_LEN 2
736#define ACL_TABLE_LEN 14
737
738#define ACL_ACTION_ENABLE 0x000C
739#define ACL_MATCH_ENABLE 0x1FF0
740#define ACL_RULESET_ENABLE 0x2003
741#define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF)
742#define ACL_MODE_ENABLE (0x10 << 8)
743
744#define REG_PORT_ACL_CTRL_0 0x12
745
746#define PORT_ACL_WRITE_DONE BIT(6)
747#define PORT_ACL_READ_DONE BIT(5)
748#define PORT_ACL_WRITE BIT(4)
749#define PORT_ACL_INDEX_M 0xF
750
751#define REG_PORT_ACL_CTRL_1 0x13
752
753#define PORT_ACL_FORCE_DLR_MISS BIT(0)
754
755#ifndef PHY_REG_CTRL
756#define PHY_REG_CTRL 0
757
758#define PHY_RESET BIT(15)
759#define PHY_LOOPBACK BIT(14)
760#define PHY_SPEED_100MBIT BIT(13)
761#define PHY_AUTO_NEG_ENABLE BIT(12)
762#define PHY_POWER_DOWN BIT(11)
763#define PHY_MII_DISABLE BIT(10)
764#define PHY_AUTO_NEG_RESTART BIT(9)
765#define PHY_FULL_DUPLEX BIT(8)
766#define PHY_COLLISION_TEST_NOT BIT(7)
767#define PHY_HP_MDIX BIT(5)
768#define PHY_FORCE_MDIX BIT(4)
769#define PHY_AUTO_MDIX_DISABLE BIT(3)
770#define PHY_REMOTE_FAULT_DISABLE BIT(2)
771#define PHY_TRANSMIT_DISABLE BIT(1)
772#define PHY_LED_DISABLE BIT(0)
773
774#define PHY_REG_STATUS 1
775
776#define PHY_100BT4_CAPABLE BIT(15)
777#define PHY_100BTX_FD_CAPABLE BIT(14)
778#define PHY_100BTX_CAPABLE BIT(13)
779#define PHY_10BT_FD_CAPABLE BIT(12)
780#define PHY_10BT_CAPABLE BIT(11)
781#define PHY_MII_SUPPRESS_CAPABLE_NOT BIT(6)
782#define PHY_AUTO_NEG_ACKNOWLEDGE BIT(5)
783#define PHY_REMOTE_FAULT BIT(4)
784#define PHY_AUTO_NEG_CAPABLE BIT(3)
785#define PHY_LINK_STATUS BIT(2)
786#define PHY_JABBER_DETECT_NOT BIT(1)
787#define PHY_EXTENDED_CAPABILITY BIT(0)
788
789#define PHY_REG_ID_1 2
790#define PHY_REG_ID_2 3
791
792#define PHY_REG_AUTO_NEGOTIATION 4
793
794#define PHY_AUTO_NEG_NEXT_PAGE_NOT BIT(15)
795#define PHY_AUTO_NEG_REMOTE_FAULT_NOT BIT(13)
796#define PHY_AUTO_NEG_SYM_PAUSE BIT(10)
797#define PHY_AUTO_NEG_100BT4 BIT(9)
798#define PHY_AUTO_NEG_100BTX_FD BIT(8)
799#define PHY_AUTO_NEG_100BTX BIT(7)
800#define PHY_AUTO_NEG_10BT_FD BIT(6)
801#define PHY_AUTO_NEG_10BT BIT(5)
802#define PHY_AUTO_NEG_SELECTOR 0x001F
803#define PHY_AUTO_NEG_802_3 0x0001
804
805#define PHY_REG_REMOTE_CAPABILITY 5
806
807#define PHY_REMOTE_NEXT_PAGE_NOT BIT(15)
808#define PHY_REMOTE_ACKNOWLEDGE_NOT BIT(14)
809#define PHY_REMOTE_REMOTE_FAULT_NOT BIT(13)
810#define PHY_REMOTE_SYM_PAUSE BIT(10)
811#define PHY_REMOTE_100BTX_FD BIT(8)
812#define PHY_REMOTE_100BTX BIT(7)
813#define PHY_REMOTE_10BT_FD BIT(6)
814#define PHY_REMOTE_10BT BIT(5)
815#endif
816
817#define KSZ8795_ID_HI 0x0022
818#define KSZ8795_ID_LO 0x1550
819
820#define KSZ8795_SW_ID 0x8795
821
822#define PHY_REG_LINK_MD 0x1D
823
824#define PHY_START_CABLE_DIAG BIT(15)
825#define PHY_CABLE_DIAG_RESULT 0x6000
826#define PHY_CABLE_STAT_NORMAL 0x0000
827#define PHY_CABLE_STAT_OPEN 0x2000
828#define PHY_CABLE_STAT_SHORT 0x4000
829#define PHY_CABLE_STAT_FAILED 0x6000
830#define PHY_CABLE_10M_SHORT BIT(12)
831#define PHY_CABLE_FAULT_COUNTER 0x01FF
832
833#define PHY_REG_PHY_CTRL 0x1F
834
835#define PHY_MODE_M 0x7
836#define PHY_MODE_S 8
837#define PHY_STAT_REVERSED_POLARITY BIT(5)
838#define PHY_STAT_MDIX BIT(4)
839#define PHY_FORCE_LINK BIT(3)
840#define PHY_POWER_SAVING_ENABLE BIT(2)
841#define PHY_REMOTE_LOOPBACK BIT(1)
842
843/* Chip resource */
844
845#define PRIO_QUEUES 4
846
847#define KS_PRIO_IN_REG 4
848
849#define TOTAL_PORT_NUM 5
850
851/* Host port can only be last of them. */
852#define SWITCH_PORT_NUM (TOTAL_PORT_NUM - 1)
853
854#define KSZ8795_COUNTER_NUM 0x20
855#define TOTAL_KSZ8795_COUNTER_NUM (KSZ8795_COUNTER_NUM + 4)
856
857#define SWITCH_COUNTER_NUM KSZ8795_COUNTER_NUM
858#define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ8795_COUNTER_NUM
859
860/* Common names used by other drivers */
861
862#define P_BCAST_STORM_CTRL REG_PORT_CTRL_0
863#define P_PRIO_CTRL REG_PORT_CTRL_0
864#define P_TAG_CTRL REG_PORT_CTRL_0
865#define P_MIRROR_CTRL REG_PORT_CTRL_1
866#define P_802_1P_CTRL REG_PORT_CTRL_2
867#define P_STP_CTRL REG_PORT_CTRL_2
868#define P_LOCAL_CTRL REG_PORT_CTRL_7
869#define P_REMOTE_STATUS REG_PORT_STATUS_0
870#define P_FORCE_CTRL REG_PORT_CTRL_9
871#define P_NEG_RESTART_CTRL REG_PORT_CTRL_10
872#define P_SPEED_STATUS REG_PORT_STATUS_1
873#define P_LINK_STATUS REG_PORT_STATUS_2
874#define P_PASS_ALL_CTRL REG_PORT_CTRL_12
875#define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12
876#define P_DROP_TAG_CTRL REG_PORT_CTRL_13
877#define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT
878
879#define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12
880#define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID
881
882#define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0
883#define S_LINK_AGING_CTRL REG_SW_CTRL_0
884#define S_HUGE_PACKET_CTRL REG_SW_CTRL_1
885#define S_MIRROR_CTRL REG_SW_CTRL_3
886#define S_REPLACE_VID_CTRL REG_SW_CTRL_4
887#define S_PASS_PAUSE_CTRL REG_SW_CTRL_10
888#define S_TAIL_TAG_CTRL REG_SW_CTRL_10
889#define S_802_1P_PRIO_CTRL REG_SW_CTRL_12
890#define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0
891#define S_IPV6_MLD_CTRL REG_SW_CTRL_21
892
893#define IND_ACC_TABLE(table) ((table) << 8)
894
895/* Driver set switch broadcast storm protection at 10% rate. */
896#define BROADCAST_STORM_PROT_RATE 10
897
898/* 148,800 frames * 67 ms / 100 */
899#define BROADCAST_STORM_VALUE 9969
900
901/**
902 * STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
903 * STATIC_MAC_TABLE_FWD_PORTS 00-001F0000-00000000
904 * STATIC_MAC_TABLE_VALID 00-00200000-00000000
905 * STATIC_MAC_TABLE_OVERRIDE 00-00400000-00000000
906 * STATIC_MAC_TABLE_USE_FID 00-00800000-00000000
907 * STATIC_MAC_TABLE_FID 00-7F000000-00000000
908 */
909
910#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
911#define STATIC_MAC_TABLE_FWD_PORTS 0x001F0000
912#define STATIC_MAC_TABLE_VALID 0x00200000
913#define STATIC_MAC_TABLE_OVERRIDE 0x00400000
914#define STATIC_MAC_TABLE_USE_FID 0x00800000
915#define STATIC_MAC_TABLE_FID 0x7F000000
916
917#define STATIC_MAC_FWD_PORTS_S 16
918#define STATIC_MAC_FID_S 24
919
920/**
921 * VLAN_TABLE_FID 00-007F007F-007F007F
922 * VLAN_TABLE_MEMBERSHIP 00-0F800F80-0F800F80
923 * VLAN_TABLE_VALID 00-10001000-10001000
924 */
925
926#define VLAN_TABLE_FID 0x007F
927#define VLAN_TABLE_MEMBERSHIP 0x0F80
928#define VLAN_TABLE_VALID 0x1000
929
930#define VLAN_TABLE_MEMBERSHIP_S 7
931#define VLAN_TABLE_S 16
932
933/**
934 * DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
935 * DYNAMIC_MAC_TABLE_FID 00-007F0000-00000000
936 * DYNAMIC_MAC_TABLE_NOT_READY 00-00800000-00000000
937 * DYNAMIC_MAC_TABLE_SRC_PORT 00-07000000-00000000
938 * DYNAMIC_MAC_TABLE_TIMESTAMP 00-18000000-00000000
939 * DYNAMIC_MAC_TABLE_ENTRIES 7F-E0000000-00000000
940 * DYNAMIC_MAC_TABLE_MAC_EMPTY 80-00000000-00000000
941 */
942
943#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
944#define DYNAMIC_MAC_TABLE_FID 0x007F0000
945#define DYNAMIC_MAC_TABLE_SRC_PORT 0x07000000
946#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x18000000
947#define DYNAMIC_MAC_TABLE_ENTRIES 0xE0000000
948
949#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
950
951#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x7F
952#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x80
953
954#define DYNAMIC_MAC_FID_S 16
955#define DYNAMIC_MAC_SRC_PORT_S 24
956#define DYNAMIC_MAC_TIMESTAMP_S 27
957#define DYNAMIC_MAC_ENTRIES_S 29
958#define DYNAMIC_MAC_ENTRIES_H_S 3
959
960/**
961 * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
962 * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF
963 * MIB_PACKET_DROPPED 00-00000000-0000FFFF
964 * MIB_COUNTER_VALID 00-00000020-00000000
965 * MIB_COUNTER_OVERFLOW 00-00000040-00000000
966 */
967
968#define MIB_COUNTER_OVERFLOW BIT(6)
969#define MIB_COUNTER_VALID BIT(5)
970
971#define MIB_COUNTER_VALUE 0x3FFFFFFF
972
973#define KS_MIB_TOTAL_RX_0 0x100
974#define KS_MIB_TOTAL_TX_0 0x101
975#define KS_MIB_PACKET_DROPPED_RX_0 0x102
976#define KS_MIB_PACKET_DROPPED_TX_0 0x103
977#define KS_MIB_TOTAL_RX_1 0x104
978#define KS_MIB_TOTAL_TX_1 0x105
979#define KS_MIB_PACKET_DROPPED_TX_1 0x106
980#define KS_MIB_PACKET_DROPPED_RX_1 0x107
981#define KS_MIB_TOTAL_RX_2 0x108
982#define KS_MIB_TOTAL_TX_2 0x109
983#define KS_MIB_PACKET_DROPPED_TX_2 0x10A
984#define KS_MIB_PACKET_DROPPED_RX_2 0x10B
985#define KS_MIB_TOTAL_RX_3 0x10C
986#define KS_MIB_TOTAL_TX_3 0x10D
987#define KS_MIB_PACKET_DROPPED_TX_3 0x10E
988#define KS_MIB_PACKET_DROPPED_RX_3 0x10F
989#define KS_MIB_TOTAL_RX_4 0x110
990#define KS_MIB_TOTAL_TX_4 0x111
991#define KS_MIB_PACKET_DROPPED_TX_4 0x112
992#define KS_MIB_PACKET_DROPPED_RX_4 0x113
993
994#define MIB_PACKET_DROPPED 0x0000FFFF
995
996#define MIB_TOTAL_BYTES_H 0x0000000F
997
998#define TAIL_TAG_OVERRIDE BIT(6)
999#define TAIL_TAG_LOOKUP BIT(7)
1000
1001#define VLAN_TABLE_ENTRIES (4096 / 4)
1002#define FID_ENTRIES 128
1003
1004#endif
diff --git a/drivers/net/dsa/microchip/ksz8795_spi.c b/drivers/net/dsa/microchip/ksz8795_spi.c
new file mode 100644
index 000000000000..50aa0d24effb
--- /dev/null
+++ b/drivers/net/dsa/microchip/ksz8795_spi.c
@@ -0,0 +1,104 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Microchip KSZ8795 series register access through SPI
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <asm/unaligned.h>
10
11#include <linux/delay.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/regmap.h>
15#include <linux/spi/spi.h>
16
17#include "ksz_priv.h"
18#include "ksz_common.h"
19
20#define SPI_ADDR_SHIFT 12
21#define SPI_ADDR_ALIGN 3
22#define SPI_TURNAROUND_SHIFT 1
23
24KSZ_REGMAP_TABLE(ksz8795, 16, SPI_ADDR_SHIFT,
25 SPI_TURNAROUND_SHIFT, SPI_ADDR_ALIGN);
26
27static int ksz8795_spi_probe(struct spi_device *spi)
28{
29 struct ksz_device *dev;
30 int i, ret;
31
32 dev = ksz_switch_alloc(&spi->dev, spi);
33 if (!dev)
34 return -ENOMEM;
35
36 for (i = 0; i < ARRAY_SIZE(ksz8795_regmap_config); i++) {
37 dev->regmap[i] = devm_regmap_init_spi(spi,
38 &ksz8795_regmap_config
39 [i]);
40 if (IS_ERR(dev->regmap[i])) {
41 ret = PTR_ERR(dev->regmap[i]);
42 dev_err(&spi->dev,
43 "Failed to initialize regmap%i: %d\n",
44 ksz8795_regmap_config[i].val_bits, ret);
45 return ret;
46 }
47 }
48
49 if (spi->dev.platform_data)
50 dev->pdata = spi->dev.platform_data;
51
52 ret = ksz8795_switch_register(dev);
53
54 /* Main DSA driver may not be started yet. */
55 if (ret)
56 return ret;
57
58 spi_set_drvdata(spi, dev);
59
60 return 0;
61}
62
63static int ksz8795_spi_remove(struct spi_device *spi)
64{
65 struct ksz_device *dev = spi_get_drvdata(spi);
66
67 if (dev)
68 ksz_switch_remove(dev);
69
70 return 0;
71}
72
73static void ksz8795_spi_shutdown(struct spi_device *spi)
74{
75 struct ksz_device *dev = spi_get_drvdata(spi);
76
77 if (dev && dev->dev_ops->shutdown)
78 dev->dev_ops->shutdown(dev);
79}
80
81static const struct of_device_id ksz8795_dt_ids[] = {
82 { .compatible = "microchip,ksz8765" },
83 { .compatible = "microchip,ksz8794" },
84 { .compatible = "microchip,ksz8795" },
85 {},
86};
87MODULE_DEVICE_TABLE(of, ksz8795_dt_ids);
88
89static struct spi_driver ksz8795_spi_driver = {
90 .driver = {
91 .name = "ksz8795-switch",
92 .owner = THIS_MODULE,
93 .of_match_table = of_match_ptr(ksz8795_dt_ids),
94 },
95 .probe = ksz8795_spi_probe,
96 .remove = ksz8795_spi_remove,
97 .shutdown = ksz8795_spi_shutdown,
98};
99
100module_spi_driver(ksz8795_spi_driver);
101
102MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
103MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch SPI Driver");
104MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index a3d2d67894bd..ce20cc90f9ef 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -373,7 +373,8 @@ int ksz_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
373 373
374 /* setup slave port */ 374 /* setup slave port */
375 dev->dev_ops->port_setup(dev, port, false); 375 dev->dev_ops->port_setup(dev, port, false);
376 dev->dev_ops->phy_setup(dev, port, phy); 376 if (dev->dev_ops->phy_setup)
377 dev->dev_ops->phy_setup(dev, port, phy);
377 378
378 /* port_stp_state_set() will be called after to enable the port so 379 /* port_stp_state_set() will be called after to enable the port so
379 * there is no need to do anything. 380 * there is no need to do anything.
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index ee7096d8af07..84fed4a2578b 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -68,6 +68,22 @@ static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
68 return ret; 68 return ret;
69} 69}
70 70
71static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
72{
73 u32 value[2];
74 int ret;
75
76 ret = regmap_bulk_read(dev->regmap[2], reg, value, 2);
77 if (!ret) {
78 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
79 value[0] = swab32(value[0]);
80 value[1] = swab32(value[1]);
81 *val = swab64((u64)*value);
82 }
83
84 return ret;
85}
86
71static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 87static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
72{ 88{
73 return regmap_write(dev->regmap[0], reg, value); 89 return regmap_write(dev->regmap[0], reg, value);
@@ -83,6 +99,18 @@ static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
83 return regmap_write(dev->regmap[2], reg, value); 99 return regmap_write(dev->regmap[2], reg, value);
84} 100}
85 101
102static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
103{
104 u32 val[2];
105
106 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
107 value = swab64(value);
108 val[0] = swab32(value & 0xffffffffULL);
109 val[1] = swab32(value >> 32ULL);
110
111 return regmap_bulk_write(dev->regmap[2], reg, val, 2);
112}
113
86static inline void ksz_pread8(struct ksz_device *dev, int port, int offset, 114static inline void ksz_pread8(struct ksz_device *dev, int port, int offset,
87 u8 *data) 115 u8 *data)
88{ 116{
diff --git a/drivers/net/dsa/microchip/ksz_priv.h b/drivers/net/dsa/microchip/ksz_priv.h
index beacf0e40f42..44c16aaf775c 100644
--- a/drivers/net/dsa/microchip/ksz_priv.h
+++ b/drivers/net/dsa/microchip/ksz_priv.h
@@ -150,6 +150,7 @@ int ksz_switch_register(struct ksz_device *dev,
150 const struct ksz_dev_ops *ops); 150 const struct ksz_dev_ops *ops);
151void ksz_switch_remove(struct ksz_device *dev); 151void ksz_switch_remove(struct ksz_device *dev);
152 152
153int ksz8795_switch_register(struct ksz_device *dev);
153int ksz9477_switch_register(struct ksz_device *dev); 154int ksz9477_switch_register(struct ksz_device *dev);
154 155
155#endif 156#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 05:24:32 -0400