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authorQiao Zhou <zhouqiao@marvell.com>2014-09-10 04:40:48 -0400
committerVinod Koul <vinod.koul@intel.com>2014-09-11 01:17:44 -0400
commite6222263124daae6be4b38b856af352667d95929 (patch)
tree1d77847d2db9fab5e7c4f49efd1e7d26d8f899d4
parente34b731faa7d12d3681187968ef899747e4feb55 (diff)
dmaengine: mmp_tdma: add DMA_PREP_INTERRUPT flag support
add DMA_PREP_INTERRUPT flag to support no_period_wakeup, in which user space app doesn't want audio interrupt to wake up audio threads. Signed-off-by: Qiao Zhou <zhouqiao@marvell.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/mmp_tdma.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/drivers/dma/mmp_tdma.c b/drivers/dma/mmp_tdma.c
index 6ad30e2c5038..c6bd015b7165 100644
--- a/drivers/dma/mmp_tdma.c
+++ b/drivers/dma/mmp_tdma.c
@@ -148,10 +148,16 @@ static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
148 tdmac->reg_base + TDCR); 148 tdmac->reg_base + TDCR);
149} 149}
150 150
151static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
152{
153 if (enable)
154 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
155 else
156 writel(0, tdmac->reg_base + TDIMR);
157}
158
151static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) 159static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
152{ 160{
153 /* enable irq */
154 writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
155 /* enable dma chan */ 161 /* enable dma chan */
156 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, 162 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
157 tdmac->reg_base + TDCR); 163 tdmac->reg_base + TDCR);
@@ -163,9 +169,6 @@ static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
163 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, 169 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
164 tdmac->reg_base + TDCR); 170 tdmac->reg_base + TDCR);
165 171
166 /* disable irq */
167 writel(0, tdmac->reg_base + TDIMR);
168
169 tdmac->status = DMA_COMPLETE; 172 tdmac->status = DMA_COMPLETE;
170} 173}
171 174
@@ -434,6 +437,10 @@ static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
434 i++; 437 i++;
435 } 438 }
436 439
440 /* enable interrupt */
441 if (flags & DMA_PREP_INTERRUPT)
442 mmp_tdma_enable_irq(tdmac, true);
443
437 tdmac->buf_len = buf_len; 444 tdmac->buf_len = buf_len;
438 tdmac->period_len = period_len; 445 tdmac->period_len = period_len;
439 tdmac->pos = 0; 446 tdmac->pos = 0;
@@ -455,6 +462,8 @@ static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
455 switch (cmd) { 462 switch (cmd) {
456 case DMA_TERMINATE_ALL: 463 case DMA_TERMINATE_ALL:
457 mmp_tdma_disable_chan(tdmac); 464 mmp_tdma_disable_chan(tdmac);
465 /* disable interrupt */
466 mmp_tdma_enable_irq(tdmac, false);
458 break; 467 break;
459 case DMA_PAUSE: 468 case DMA_PAUSE:
460 mmp_tdma_pause_chan(tdmac); 469 mmp_tdma_pause_chan(tdmac);