soc/fsl/qe: only apply QE_General4 workaround on affected SoCs

The QE_General4 workaround is only valid for the MPC832x and MPC836x
SoCs. The other SoCs that embed a QUICC engine are not affected by this
hardware bug and thus can use the computed divisors (this was
successfully tested on the T1040).

Similalry to what was done in commit 8ce795cb0c6b ("i2c: mpc: assign the
correct prescaler from SVR") in order to avoid changes in
the device tree nodes of the QE (with maybe a variant of the compatible
property), the PVR reg is read out to find out if the workaround must be
applied or not.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Scott Wood <oss@buserror.net>

1 files changed, 6 insertions, 2 deletions

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 31a094573a9d..2ef6fc6487c1 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -200,6 +200,9 @@ unsigned int qe_get_brg_clk(void)
 }
 EXPORT_SYMBOL(qe_get_brg_clk);
 
+#define PVR_VER_836x    0x8083
+#define PVR_VER_832x    0x8084
+
 /* Program the BRG to the given sampling rate and multiplier
  *
  * @brg: the BRG, QE_BRG1 - QE_BRG16
@@ -226,8 +229,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
         /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
            that the BRG divisor must be even if you're not using divide-by-16
            mode. */
-        if (!div16 && (divisor & 1) && (divisor > 3))
-                divisor++;
+        if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+                if (!div16 && (divisor & 1) && (divisor > 3))
+                        divisor++;
 
         tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
                 QE_BRGC_ENABLE | div16;