arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.

This commit adds the basical DTSI file of it, including the clock
support and UART support.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

1 files changed, 175 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
new file mode 100644
index 000000000000..56563150d61a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0>;
+                        enable-method = "psci";
+                };
+
+                cpu1: cpu@1 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <1>;
+                        enable-method = "psci";
+                };
+
+                cpu2: cpu@2 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <2>;
+                        enable-method = "psci";
+                };
+
+                cpu3: cpu@3 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <3>;
+                        enable-method = "psci";
+                };
+        };
+
+        iosc: internal-osc-clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16000000>;
+                clock-accuracy = <300000000>;
+                clock-output-names = "iosc";
+        };
+
+        osc24M: osc24M_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "osc24M";
+        };
+
+        osc32k: osc32k_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+                clock-output-names = "osc32k";
+        };
+
+        psci {
+                compatible = "arm,psci-0.2";
+                method = "smc";
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 14
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 11
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 10
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                ccu: clock@3001000 {
+                        compatible = "allwinner,sun50i-h6-ccu";
+                        reg = <0x03001000 0x1000>;
+                        clocks = <&osc24M>, <&osc32k>, <&iosc>;
+                        clock-names = "hosc", "losc", "iosc";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+
+                gic: interrupt-controller@3021000 {
+                        compatible = "arm,gic-400";
+                        reg = <0x03021000 0x1000>,
+                              <0x03022000 0x2000>,
+                              <0x03024000 0x2000>,
+                              <0x03026000 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                };
+
+                pio: pinctrl@300b000 {
+                        compatible = "allwinner,sun50i-h6-pinctrl";
+                        reg = <0x0300b000 0x400>;
+                        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu 26>, <&osc24M>, <&osc32k>;
+                        clock-names = "apb", "hosc", "losc";
+                        gpio-controller;
+                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+
+                        uart0_ph_pins: uart0-ph {
+                                pins = "PH0", "PH1";
+                                function = "uart0";
+                        };
+                };
+
+                uart0: serial@5000000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000000 0x400>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 70>;
+                        resets = <&ccu 21>;
+                        status = "disabled";
+                };
+
+                uart1: serial@5000400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000400 0x400>;
+                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 71>;
+                        resets = <&ccu 22>;
+                        status = "disabled";
+                };
+
+                uart2: serial@5000800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000800 0x400>;
+                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 72>;
+                        resets = <&ccu 23>;
+                        status = "disabled";
+                };
+
+                uart3: serial@5000c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000c00 0x400>;
+                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 73>;
+                        resets = <&ccu 24>;
+                        status = "disabled";
+                };
+        };
+};