arm64: dts: exynos: Enable HDMI/TV path on Exynos5433-TM2

TV path consist of following interconnected components:
- DECON_TV - display controller,
- HDMI - video signal converter RGB / HDMI,
- MHL - video signal converter HDMI / MHL,
- DDC - i2c slave device for EDID reading (on hsi2c_11 bus).

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

1 files changed, 69 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index cc6701b3bce4..a5c866901e93 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -278,6 +278,22 @@
         };
 };
 
+&decon_tv {
+        status = "okay";
+
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+                        tv_to_hdmi: endpoint {
+                                remote-endpoint = <&hdmi_to_tv>;
+                        };
+                };
+        };
+};
+
 &dsi {
         status = "okay";
         vddcore-supply = <&ldo6_reg>;
@@ -301,6 +317,33 @@
         };
 };
 
+&hdmi {
+        hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+        vdd-supply = <&ldo6_reg>;
+        vdd_osc-supply = <&ldo7_reg>;
+        vdd_pll-supply = <&ldo6_reg>;
+
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+                        hdmi_to_tv: endpoint {
+                                remote-endpoint = <&tv_to_hdmi>;
+                        };
+                };
+
+                port@1 {
+                        reg = <1>;
+                        hdmi_to_mhl: endpoint {
+                                remote-endpoint = <&mhl_to_hdmi>;
+                        };
+                };
+        };
+};
+
 &hsi2c_0 {
         status = "okay";
         clock-frequency = <2500000>;
@@ -702,6 +745,28 @@
         };
 };
 
+&hsi2c_7 {
+        status = "okay";
+
+        sii8620@39 {
+                reg = <0x39>;
+                compatible = "sil,sii8620";
+                cvcc10-supply = <&ldo36_reg>;
+                iovcc18-supply = <&ldo34_reg>;
+                interrupt-parent = <&gpf0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+                reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "xtal";
+
+                port {
+                        mhl_to_hdmi: endpoint {
+                                remote-endpoint = <&hdmi_to_mhl>;
+                        };
+                };
+        };
+};
+
 &hsi2c_8 {
         status = "okay";
 
@@ -745,6 +810,10 @@
         };
 };
 
+&hsi2c_11 {
+        status = "okay";
+};
+
 &i2s0 {
         status = "okay";
 };