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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-05-03 05:06:15 -0400
committerGeert Uytterhoeven <geert+renesas@glider.be>2016-06-06 05:58:35 -0400
commite4e2d7c388350eba8b1dbc2569441ac9b545a8c4 (patch)
tree77cd4a785a4695ce48b9884009ea9097b7ae9c8d
parent5b1defde7054e66da5c0f6cba8b35cef29edede0 (diff)
clk: renesas: cpg-mssr: Add support for R-Car M3-W
Initial support for R-Car M3-W (r8a7796), including basic core clocks, and SCIF2 (console) and INTC-AP (GIC) module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat
-rw-r--r--drivers/clk/renesas/Kconfig1
-rw-r--r--drivers/clk/renesas/Makefile1
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c192
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c6
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h1
5 files changed, 201 insertions, 0 deletions
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 2115ce410cfb..fcad9ff090f5 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -1,6 +1,7 @@
1config CLK_RENESAS_CPG_MSSR 1config CLK_RENESAS_CPG_MSSR
2 bool 2 bool
3 default y if ARCH_R8A7795 3 default y if ARCH_R8A7795
4 default y if ARCH_R8A7796
4 5
5config CLK_RENESAS_CPG_MSTP 6config CLK_RENESAS_CPG_MSTP
6 bool 7 bool
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 88924c95808c..0b8d31b4909c 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-div6.o
9obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o 9obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-div6.o
10obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o 10obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-div6.o
11obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o rcar-gen3-cpg.o 11obj-$(CONFIG_ARCH_R8A7795) += r8a7795-cpg-mssr.o rcar-gen3-cpg.o
12obj-$(CONFIG_ARCH_R8A7796) += r8a7796-cpg-mssr.o rcar-gen3-cpg.o
12obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o 13obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-div6.o
13 14
14obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o 15obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o clk-div6.o
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
new file mode 100644
index 000000000000..c84b549c14d2
--- /dev/null
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -0,0 +1,192 @@
1/*
2 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * Based on r8a7795-cpg-mssr.c
7 *
8 * Copyright (C) 2015 Glider bvba
9 * Copyright (C) 2015 Renesas Electronics Corp.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 */
15
16#include <linux/device.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19
20#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
21
22#include "renesas-cpg-mssr.h"
23#include "rcar-gen3-cpg.h"
24
25enum clk_ids {
26 /* Core Clock Outputs exported to DT */
27 LAST_DT_CORE_CLK = R8A7796_CLK_OSC,
28
29 /* External Input Clocks */
30 CLK_EXTAL,
31 CLK_EXTALR,
32
33 /* Internal Core Clocks */
34 CLK_MAIN,
35 CLK_PLL0,
36 CLK_PLL1,
37 CLK_PLL2,
38 CLK_PLL3,
39 CLK_PLL4,
40 CLK_PLL1_DIV2,
41 CLK_PLL1_DIV4,
42 CLK_S0,
43 CLK_S1,
44 CLK_S2,
45 CLK_S3,
46 CLK_SDSRC,
47 CLK_SSPSRC,
48
49 /* Module Clocks */
50 MOD_CLK_BASE
51};
52
53static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
54 /* External Clock Inputs */
55 DEF_INPUT("extal", CLK_EXTAL),
56 DEF_INPUT("extalr", CLK_EXTALR),
57
58 /* Internal Core Clocks */
59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
60 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
62 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
63 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
64 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
65
66 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
67 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
68 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
69 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
70 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
71 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
72
73 /* Core Clock Outputs */
74 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
75 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
76 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
77 DEF_FIXED("zx", R8A7796_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
78 DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
79 DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
80 DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
81 DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
82 DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
83 DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
84 DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0, 12, 1),
85 DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
86 DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
87 DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
88 DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
89 DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
90 DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
91 DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
92 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
93 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
94
95 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
96 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
97};
98
99static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
100 DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
101 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
102};
103
104static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
105 MOD_CLK_ID(408), /* INTC-AP (GIC) */
106};
107
108
109/*
110 * CPG Clock Data
111 */
112
113/*
114 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
115 * 14 13 19 17 (MHz)
116 *-------------------------------------------------------------------
117 * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
118 * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
119 * 0 0 1 0 Prohibited setting
120 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
121 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
122 * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
123 * 0 1 1 0 Prohibited setting
124 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
125 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
126 * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
127 * 1 0 1 0 Prohibited setting
128 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
129 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
130 * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
131 * 1 1 1 0 Prohibited setting
132 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
133 */
134#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
135 (((md) & BIT(13)) >> 11) | \
136 (((md) & BIT(19)) >> 18) | \
137 (((md) & BIT(17)) >> 17))
138
139static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
140 /* EXTAL div PLL1 mult PLL3 mult */
141 { 1, 192, 192, },
142 { 1, 192, 128, },
143 { 0, /* Prohibited setting */ },
144 { 1, 192, 192, },
145 { 1, 160, 160, },
146 { 1, 160, 106, },
147 { 0, /* Prohibited setting */ },
148 { 1, 160, 160, },
149 { 1, 128, 128, },
150 { 1, 128, 84, },
151 { 0, /* Prohibited setting */ },
152 { 1, 128, 128, },
153 { 2, 192, 192, },
154 { 2, 192, 128, },
155 { 0, /* Prohibited setting */ },
156 { 2, 192, 192, },
157};
158
159static int __init r8a7796_cpg_mssr_init(struct device *dev)
160{
161 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
162 u32 cpg_mode = rcar_gen3_read_mode_pins();
163
164 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
165 if (!cpg_pll_config->extal_div) {
166 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
167 return -EINVAL;
168 }
169
170 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR);
171}
172
173const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {
174 /* Core Clocks */
175 .core_clks = r8a7796_core_clks,
176 .num_core_clks = ARRAY_SIZE(r8a7796_core_clks),
177 .last_dt_core_clk = LAST_DT_CORE_CLK,
178 .num_total_core_clks = MOD_CLK_BASE,
179
180 /* Module Clocks */
181 .mod_clks = r8a7796_mod_clks,
182 .num_mod_clks = ARRAY_SIZE(r8a7796_mod_clks),
183 .num_hw_mod_clks = 12 * 32,
184
185 /* Critical Module Clocks */
186 .crit_mod_clks = r8a7796_crit_mod_clks,
187 .num_crit_mod_clks = ARRAY_SIZE(r8a7796_crit_mod_clks),
188
189 /* Callbacks */
190 .init = r8a7796_cpg_mssr_init,
191 .cpg_clk_register = rcar_gen3_cpg_clk_register,
192};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 210cd744a7a9..e1365e7491ae 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -509,6 +509,12 @@ static const struct of_device_id cpg_mssr_match[] = {
509 .data = &r8a7795_cpg_mssr_info, 509 .data = &r8a7795_cpg_mssr_info,
510 }, 510 },
511#endif 511#endif
512#ifdef CONFIG_ARCH_R8A7796
513 {
514 .compatible = "renesas,r8a7796-cpg-mssr",
515 .data = &r8a7796_cpg_mssr_info,
516 },
517#endif
512 { /* sentinel */ } 518 { /* sentinel */ }
513}; 519};
514 520
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 0d1e3e811e79..ee7edfaf1408 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -131,4 +131,5 @@ struct cpg_mssr_info {
131}; 131};
132 132
133extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; 133extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
134extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
134#endif 135#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 10:02:05 -0400