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authorLABBE Corentin <clabbe.montjoie@gmail.com>2015-12-17 07:45:42 -0500
committerHerbert Xu <herbert@gondor.apana.org.au>2015-12-22 07:43:40 -0500
commite4ae86e22edc1647f0ee0c2ab12ec05fce17d782 (patch)
treeadbad6ff81b7690bd7e6ed58538b334c0f1721ab
parentbdd75064d2b2068007f4fc5e26ac726e8617a090 (diff)
crypto: ux500 - Use precalculated hash from headers
Precalculated hash for empty message are now present in hash headers. This patch just use them. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r--drivers/crypto/ux500/Kconfig2
-rw-r--r--drivers/crypto/ux500/hash/hash_core.c20
2 files changed, 4 insertions, 18 deletions
diff --git a/drivers/crypto/ux500/Kconfig b/drivers/crypto/ux500/Kconfig
index 30796441b0a6..0e338bf6dfb7 100644
--- a/drivers/crypto/ux500/Kconfig
+++ b/drivers/crypto/ux500/Kconfig
@@ -18,6 +18,8 @@ config CRYPTO_DEV_UX500_HASH
18 tristate "UX500 crypto driver for HASH block" 18 tristate "UX500 crypto driver for HASH block"
19 depends on CRYPTO_DEV_UX500 19 depends on CRYPTO_DEV_UX500
20 select CRYPTO_HASH 20 select CRYPTO_HASH
21 select CRYPTO_SHA1
22 select CRYPTO_SHA256
21 help 23 help
22 This selects the hash driver for the UX500_HASH hardware. 24 This selects the hash driver for the UX500_HASH hardware.
23 Depends on UX500/STM DMA if running in DMA mode. 25 Depends on UX500/STM DMA if running in DMA mode.
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index f47d112041b2..d6fdc583ce5d 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -41,22 +41,6 @@ static int hash_mode;
41module_param(hash_mode, int, 0); 41module_param(hash_mode, int, 0);
42MODULE_PARM_DESC(hash_mode, "CPU or DMA mode. CPU = 0 (default), DMA = 1"); 42MODULE_PARM_DESC(hash_mode, "CPU or DMA mode. CPU = 0 (default), DMA = 1");
43 43
44/**
45 * Pre-calculated empty message digests.
46 */
47static const u8 zero_message_hash_sha1[SHA1_DIGEST_SIZE] = {
48 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
49 0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90,
50 0xaf, 0xd8, 0x07, 0x09
51};
52
53static const u8 zero_message_hash_sha256[SHA256_DIGEST_SIZE] = {
54 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
55 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
56 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
57 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55
58};
59
60/* HMAC-SHA1, no key */ 44/* HMAC-SHA1, no key */
61static const u8 zero_message_hmac_sha1[SHA1_DIGEST_SIZE] = { 45static const u8 zero_message_hmac_sha1[SHA1_DIGEST_SIZE] = {
62 0xfb, 0xdb, 0x1d, 0x1b, 0x18, 0xaa, 0x6c, 0x08, 46 0xfb, 0xdb, 0x1d, 0x1b, 0x18, 0xaa, 0x6c, 0x08,
@@ -242,13 +226,13 @@ static int get_empty_message_digest(
242 226
243 if (HASH_OPER_MODE_HASH == ctx->config.oper_mode) { 227 if (HASH_OPER_MODE_HASH == ctx->config.oper_mode) {
244 if (HASH_ALGO_SHA1 == ctx->config.algorithm) { 228 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
245 memcpy(zero_hash, &zero_message_hash_sha1[0], 229 memcpy(zero_hash, &sha1_zero_message_hash[0],
246 SHA1_DIGEST_SIZE); 230 SHA1_DIGEST_SIZE);
247 *zero_hash_size = SHA1_DIGEST_SIZE; 231 *zero_hash_size = SHA1_DIGEST_SIZE;
248 *zero_digest = true; 232 *zero_digest = true;
249 } else if (HASH_ALGO_SHA256 == 233 } else if (HASH_ALGO_SHA256 ==
250 ctx->config.algorithm) { 234 ctx->config.algorithm) {
251 memcpy(zero_hash, &zero_message_hash_sha256[0], 235 memcpy(zero_hash, &sha256_zero_message_hash[0],
252 SHA256_DIGEST_SIZE); 236 SHA256_DIGEST_SIZE);
253 *zero_hash_size = SHA256_DIGEST_SIZE; 237 *zero_hash_size = SHA256_DIGEST_SIZE;
254 *zero_digest = true; 238 *zero_digest = true;