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authorMika Westerberg <mika.westerberg@linux.intel.com>2017-08-18 06:05:55 -0400
committerLinus Walleij <linus.walleij@linaro.org>2017-08-22 09:42:19 -0400
commite480b745386e3911c45e5b281f3471c7aff8cc3b (patch)
tree6afed1199034eaa0b8a7ca4add11bcacee1b949e
parenta663ccf0fea17609b92ecc066ce6e8dda559ca73 (diff)
pinctrl: intel: Add Intel Lewisburg GPIO support
Intel Lewisburg has the same GPIO hardware than Intel Sunrisepoint-H except few differences in register offsets and pin lists. Because of this we add a separate pinctrl driver for Lewisburg. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--drivers/pinctrl/intel/Kconfig8
-rw-r--r--drivers/pinctrl/intel/Makefile1
-rw-r--r--drivers/pinctrl/intel/pinctrl-lewisburg.c343
3 files changed, 352 insertions, 0 deletions
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 9613c2a9e2b3..f30720a752f3 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -81,6 +81,14 @@ config PINCTRL_GEMINILAKE
81 This pinctrl driver provides an interface that allows configuring 81 This pinctrl driver provides an interface that allows configuring
82 of Intel Gemini Lake SoC pins and using them as GPIOs. 82 of Intel Gemini Lake SoC pins and using them as GPIOs.
83 83
84config PINCTRL_LEWISBURG
85 tristate "Intel Lewisburg pinctrl and GPIO driver"
86 depends on ACPI
87 select PINCTRL_INTEL
88 help
89 This pinctrl driver provides an interface that allows configuring
90 of Intel Lewisburg pins and using them as GPIOs.
91
84config PINCTRL_SUNRISEPOINT 92config PINCTRL_SUNRISEPOINT
85 tristate "Intel Sunrisepoint pinctrl and GPIO driver" 93 tristate "Intel Sunrisepoint pinctrl and GPIO driver"
86 depends on ACPI 94 depends on ACPI
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index d9b31f7e2b1b..c12874da5992 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
8obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o 8obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
9obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o 9obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
10obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o 10obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
11obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
11obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o 12obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c
new file mode 100644
index 000000000000..14d56ea6cfdc
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c
@@ -0,0 +1,343 @@
1/*
2 * Intel Lewisburg pinctrl/GPIO driver
3 *
4 * Copyright (C) 2017, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/acpi.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/pm.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#include "pinctrl-intel.h"
19
20#define LBG_PAD_OWN 0x020
21#define LBG_PADCFGLOCK 0x060
22#define LBG_HOSTSW_OWN 0x080
23#define LBG_GPI_IE 0x110
24
25#define LBG_COMMUNITY(b, s, e) \
26 { \
27 .barno = (b), \
28 .padown_offset = LBG_PAD_OWN, \
29 .padcfglock_offset = LBG_PADCFGLOCK, \
30 .hostown_offset = LBG_HOSTSW_OWN, \
31 .ie_offset = LBG_GPI_IE, \
32 .gpp_size = 24, \
33 .pin_base = (s), \
34 .npins = ((e) - (s) + 1), \
35 }
36
37static const struct pinctrl_pin_desc lbg_pins[] = {
38 /* GPP_A */
39 PINCTRL_PIN(0, "RCINB"),
40 PINCTRL_PIN(1, "LAD_0"),
41 PINCTRL_PIN(2, "LAD_1"),
42 PINCTRL_PIN(3, "LAD_2"),
43 PINCTRL_PIN(4, "LAD_3"),
44 PINCTRL_PIN(5, "LFRAMEB"),
45 PINCTRL_PIN(6, "SERIRQ"),
46 PINCTRL_PIN(7, "PIRQAB"),
47 PINCTRL_PIN(8, "CLKRUNB"),
48 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
49 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
50 PINCTRL_PIN(11, "PMEB"),
51 PINCTRL_PIN(12, "BM_BUSYB"),
52 PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
53 PINCTRL_PIN(14, "ESPI_RESETB"),
54 PINCTRL_PIN(15, "SUSACKB"),
55 PINCTRL_PIN(16, "CLKOUT_LPC_2"),
56 PINCTRL_PIN(17, "GPP_A_17"),
57 PINCTRL_PIN(18, "GPP_A_18"),
58 PINCTRL_PIN(19, "GPP_A_19"),
59 PINCTRL_PIN(20, "GPP_A_20"),
60 PINCTRL_PIN(21, "GPP_A_21"),
61 PINCTRL_PIN(22, "GPP_A_22"),
62 PINCTRL_PIN(23, "GPP_A_23"),
63 /* GPP_B */
64 PINCTRL_PIN(24, "CORE_VID_0"),
65 PINCTRL_PIN(25, "CORE_VID_1"),
66 PINCTRL_PIN(26, "VRALERTB"),
67 PINCTRL_PIN(27, "CPU_GP_2"),
68 PINCTRL_PIN(28, "CPU_GP_3"),
69 PINCTRL_PIN(29, "SRCCLKREQB_0"),
70 PINCTRL_PIN(30, "SRCCLKREQB_1"),
71 PINCTRL_PIN(31, "SRCCLKREQB_2"),
72 PINCTRL_PIN(32, "SRCCLKREQB_3"),
73 PINCTRL_PIN(33, "SRCCLKREQB_4"),
74 PINCTRL_PIN(34, "SRCCLKREQB_5"),
75 PINCTRL_PIN(35, "GPP_B_11"),
76 PINCTRL_PIN(36, "GLB_RST_WARN_N"),
77 PINCTRL_PIN(37, "PLTRSTB"),
78 PINCTRL_PIN(38, "SPKR"),
79 PINCTRL_PIN(39, "GPP_B_15"),
80 PINCTRL_PIN(40, "GPP_B_16"),
81 PINCTRL_PIN(41, "GPP_B_17"),
82 PINCTRL_PIN(42, "GPP_B_18"),
83 PINCTRL_PIN(43, "GPP_B_19"),
84 PINCTRL_PIN(44, "GPP_B_20"),
85 PINCTRL_PIN(45, "GPP_B_21"),
86 PINCTRL_PIN(46, "GPP_B_22"),
87 PINCTRL_PIN(47, "SML1ALERTB"),
88 /* GPP_F */
89 PINCTRL_PIN(48, "SATAXPCIE_3"),
90 PINCTRL_PIN(49, "SATAXPCIE_4"),
91 PINCTRL_PIN(50, "SATAXPCIE_5"),
92 PINCTRL_PIN(51, "SATAXPCIE_6"),
93 PINCTRL_PIN(52, "SATAXPCIE_7"),
94 PINCTRL_PIN(53, "SATA_DEVSLP_3"),
95 PINCTRL_PIN(54, "SATA_DEVSLP_4"),
96 PINCTRL_PIN(55, "SATA_DEVSLP_5"),
97 PINCTRL_PIN(56, "SATA_DEVSLP_6"),
98 PINCTRL_PIN(57, "SATA_DEVSLP_7"),
99 PINCTRL_PIN(58, "SATA_SCLOCK"),
100 PINCTRL_PIN(59, "SATA_SLOAD"),
101 PINCTRL_PIN(60, "SATA_SDATAOUT1"),
102 PINCTRL_PIN(61, "SATA_SDATAOUT0"),
103 PINCTRL_PIN(62, "SSATA_LEDB"),
104 PINCTRL_PIN(63, "USB2_OCB_4"),
105 PINCTRL_PIN(64, "USB2_OCB_5"),
106 PINCTRL_PIN(65, "USB2_OCB_6"),
107 PINCTRL_PIN(66, "USB2_OCB_7"),
108 PINCTRL_PIN(67, "GBE_SMBUS_CLK"),
109 PINCTRL_PIN(68, "GBE_SMBDATA"),
110 PINCTRL_PIN(69, "GBE_SMBALRTN"),
111 PINCTRL_PIN(70, "SSATA_SCLOCK"),
112 PINCTRL_PIN(71, "SSATA_SLOAD"),
113 /* GPP_C */
114 PINCTRL_PIN(72, "SMBCLK"),
115 PINCTRL_PIN(73, "SMBDATA"),
116 PINCTRL_PIN(74, "SMBALERTB"),
117 PINCTRL_PIN(75, "SML0CLK"),
118 PINCTRL_PIN(76, "SML0DATA"),
119 PINCTRL_PIN(77, "SML0ALERTB"),
120 PINCTRL_PIN(78, "SML1CLK"),
121 PINCTRL_PIN(79, "SML1DATA"),
122 PINCTRL_PIN(80, "GPP_C_8"),
123 PINCTRL_PIN(81, "GPP_C_9"),
124 PINCTRL_PIN(82, "GPP_C_10"),
125 PINCTRL_PIN(83, "GPP_C_11"),
126 PINCTRL_PIN(84, "GPP_C_12"),
127 PINCTRL_PIN(85, "GPP_C_13"),
128 PINCTRL_PIN(86, "GPP_C_14"),
129 PINCTRL_PIN(87, "GPP_C_15"),
130 PINCTRL_PIN(88, "GPP_C_16"),
131 PINCTRL_PIN(89, "GPP_C_17"),
132 PINCTRL_PIN(90, "GPP_C_18"),
133 PINCTRL_PIN(91, "GPP_C_19"),
134 PINCTRL_PIN(92, "GPP_C_20"),
135 PINCTRL_PIN(93, "GPP_C_21"),
136 PINCTRL_PIN(94, "GPP_C_22"),
137 PINCTRL_PIN(95, "GPP_C_23"),
138 /* GPP_D */
139 PINCTRL_PIN(96, "GPP_D_0"),
140 PINCTRL_PIN(97, "GPP_D_1"),
141 PINCTRL_PIN(98, "GPP_D_2"),
142 PINCTRL_PIN(99, "GPP_D_3"),
143 PINCTRL_PIN(100, "GPP_D_4"),
144 PINCTRL_PIN(101, "SSP0_SFRM"),
145 PINCTRL_PIN(102, "SSP0_TXD"),
146 PINCTRL_PIN(103, "SSP0_RXD"),
147 PINCTRL_PIN(104, "SSP0_SCLK"),
148 PINCTRL_PIN(105, "SSATA_DEVSLP_3"),
149 PINCTRL_PIN(106, "SSATA_DEVSLP_4"),
150 PINCTRL_PIN(107, "SSATA_DEVSLP_5"),
151 PINCTRL_PIN(108, "SSATA_SDATAOUT1"),
152 PINCTRL_PIN(109, "SML0BCLK_SML0BCLKIE"),
153 PINCTRL_PIN(110, "SML0BDATA_SML0BDATAIE"),
154 PINCTRL_PIN(111, "SSATA_SDATAOUT0"),
155 PINCTRL_PIN(112, "SML0BALERTB_SML0BALERTBIE"),
156 PINCTRL_PIN(113, "DMIC_CLK_1"),
157 PINCTRL_PIN(114, "DMIC_DATA_1"),
158 PINCTRL_PIN(115, "DMIC_CLK_0"),
159 PINCTRL_PIN(116, "DMIC_DATA_0"),
160 PINCTRL_PIN(117, "IE_UART_RXD"),
161 PINCTRL_PIN(118, "IE_UART_TXD"),
162 PINCTRL_PIN(119, "GPP_D_23"),
163 /* GPP_E */
164 PINCTRL_PIN(120, "SATAXPCIE_0"),
165 PINCTRL_PIN(121, "SATAXPCIE_1"),
166 PINCTRL_PIN(122, "SATAXPCIE_2"),
167 PINCTRL_PIN(123, "CPU_GP_0"),
168 PINCTRL_PIN(124, "SATA_DEVSLP_0"),
169 PINCTRL_PIN(125, "SATA_DEVSLP_1"),
170 PINCTRL_PIN(126, "SATA_DEVSLP_2"),
171 PINCTRL_PIN(127, "CPU_GP_1"),
172 PINCTRL_PIN(128, "SATA_LEDB"),
173 PINCTRL_PIN(129, "USB2_OCB_0"),
174 PINCTRL_PIN(130, "USB2_OCB_1"),
175 PINCTRL_PIN(131, "USB2_OCB_2"),
176 PINCTRL_PIN(132, "USB2_OCB_3"),
177 /* GPP_I */
178 PINCTRL_PIN(133, "GBE_TDO"),
179 PINCTRL_PIN(134, "GBE_TCK"),
180 PINCTRL_PIN(135, "GBE_TMS"),
181 PINCTRL_PIN(136, "GBE_TDI"),
182 PINCTRL_PIN(137, "DO_RESET_INB"),
183 PINCTRL_PIN(138, "DO_RESET_OUTB"),
184 PINCTRL_PIN(139, "RESET_DONE"),
185 PINCTRL_PIN(140, "GBE_TRST_N"),
186 PINCTRL_PIN(141, "GBE_PCI_DIS"),
187 PINCTRL_PIN(142, "GBE_LAN_DIS"),
188 PINCTRL_PIN(143, "GPP_I_10"),
189 PINCTRL_PIN(144, "GPIO_RCOMP_3P3"),
190 /* GPP_J */
191 PINCTRL_PIN(145, "GBE_LED_0_0"),
192 PINCTRL_PIN(146, "GBE_LED_0_1"),
193 PINCTRL_PIN(147, "GBE_LED_1_0"),
194 PINCTRL_PIN(148, "GBE_LED_1_1"),
195 PINCTRL_PIN(149, "GBE_LED_2_0"),
196 PINCTRL_PIN(150, "GBE_LED_2_1"),
197 PINCTRL_PIN(151, "GBE_LED_3_0"),
198 PINCTRL_PIN(152, "GBE_LED_3_1"),
199 PINCTRL_PIN(153, "GBE_SCL_0"),
200 PINCTRL_PIN(154, "GBE_SDA_0"),
201 PINCTRL_PIN(155, "GBE_SCL_1"),
202 PINCTRL_PIN(156, "GBE_SDA_1"),
203 PINCTRL_PIN(157, "GBE_SCL_2"),
204 PINCTRL_PIN(158, "GBE_SDA_2"),
205 PINCTRL_PIN(159, "GBE_SCL_3"),
206 PINCTRL_PIN(160, "GBE_SDA_3"),
207 PINCTRL_PIN(161, "GBE_SDP_0_0"),
208 PINCTRL_PIN(162, "GBE_SDP_0_1"),
209 PINCTRL_PIN(163, "GBE_SDP_1_0"),
210 PINCTRL_PIN(164, "GBE_SDP_1_1"),
211 PINCTRL_PIN(165, "GBE_SDP_2_0"),
212 PINCTRL_PIN(166, "GBE_SDP_2_1"),
213 PINCTRL_PIN(167, "GBE_SDP_3_0"),
214 PINCTRL_PIN(168, "GBE_SDP_3_1"),
215 /* GPP_K */
216 PINCTRL_PIN(169, "GBE_RMIICLK"),
217 PINCTRL_PIN(170, "GBE_RMII_TXD_0"),
218 PINCTRL_PIN(171, "GBE_RMII_TXD_1"),
219 PINCTRL_PIN(172, "GBE_RMII_TX_EN"),
220 PINCTRL_PIN(173, "GBE_RMII_CRS_DV"),
221 PINCTRL_PIN(174, "GBE_RMII_RXD_0"),
222 PINCTRL_PIN(175, "GBE_RMII_RXD_1"),
223 PINCTRL_PIN(176, "GBE_RMII_RX_ER"),
224 PINCTRL_PIN(177, "GBE_RMII_ARBIN"),
225 PINCTRL_PIN(178, "GBE_RMII_ARB_OUT"),
226 PINCTRL_PIN(179, "PE_RST_N"),
227 PINCTRL_PIN(180, "GPIO_RCOMP_1P8_3P3"),
228 /* GPP_G */
229 PINCTRL_PIN(181, "FAN_TACH_0"),
230 PINCTRL_PIN(182, "FAN_TACH_1"),
231 PINCTRL_PIN(183, "FAN_TACH_2"),
232 PINCTRL_PIN(184, "FAN_TACH_3"),
233 PINCTRL_PIN(185, "FAN_TACH_4"),
234 PINCTRL_PIN(186, "FAN_TACH_5"),
235 PINCTRL_PIN(187, "FAN_TACH_6"),
236 PINCTRL_PIN(188, "FAN_TACH_7"),
237 PINCTRL_PIN(189, "FAN_PWM_0"),
238 PINCTRL_PIN(190, "FAN_PWM_1"),
239 PINCTRL_PIN(191, "FAN_PWM_2"),
240 PINCTRL_PIN(192, "FAN_PWM_3"),
241 PINCTRL_PIN(193, "GSXDOUT"),
242 PINCTRL_PIN(194, "GSXSLOAD"),
243 PINCTRL_PIN(195, "GSXDIN"),
244 PINCTRL_PIN(196, "GSXSRESETB"),
245 PINCTRL_PIN(197, "GSXCLK"),
246 PINCTRL_PIN(198, "ADR_COMPLETE"),
247 PINCTRL_PIN(199, "NMIB"),
248 PINCTRL_PIN(200, "SMIB"),
249 PINCTRL_PIN(201, "SSATA_DEVSLP_0"),
250 PINCTRL_PIN(202, "SSATA_DEVSLP_1"),
251 PINCTRL_PIN(203, "SSATA_DEVSLP_2"),
252 PINCTRL_PIN(204, "SSATAXPCIE0_SSATAGP0"),
253 /* GPP_H */
254 PINCTRL_PIN(205, "SRCCLKREQB_6"),
255 PINCTRL_PIN(206, "SRCCLKREQB_7"),
256 PINCTRL_PIN(207, "SRCCLKREQB_8"),
257 PINCTRL_PIN(208, "SRCCLKREQB_9"),
258 PINCTRL_PIN(209, "SRCCLKREQB_10"),
259 PINCTRL_PIN(210, "SRCCLKREQB_11"),
260 PINCTRL_PIN(211, "SRCCLKREQB_12"),
261 PINCTRL_PIN(212, "SRCCLKREQB_13"),
262 PINCTRL_PIN(213, "SRCCLKREQB_14"),
263 PINCTRL_PIN(214, "SRCCLKREQB_15"),
264 PINCTRL_PIN(215, "SML2CLK"),
265 PINCTRL_PIN(216, "SML2DATA"),
266 PINCTRL_PIN(217, "SML2ALERTB"),
267 PINCTRL_PIN(218, "SML3CLK"),
268 PINCTRL_PIN(219, "SML3DATA"),
269 PINCTRL_PIN(220, "SML3ALERTB"),
270 PINCTRL_PIN(221, "SML4CLK"),
271 PINCTRL_PIN(222, "SML4DATA"),
272 PINCTRL_PIN(223, "SML4ALERTB"),
273 PINCTRL_PIN(224, "SSATAXPCIE1_SSATAGP1"),
274 PINCTRL_PIN(225, "SSATAXPCIE2_SSATAGP2"),
275 PINCTRL_PIN(226, "SSATAXPCIE3_SSATAGP3"),
276 PINCTRL_PIN(227, "SSATAXPCIE4_SSATAGP4"),
277 PINCTRL_PIN(228, "SSATAXPCIE5_SSATAGP5"),
278 /* GPP_L */
279 PINCTRL_PIN(229, "VISA2CH0_D0"),
280 PINCTRL_PIN(230, "VISA2CH0_D1"),
281 PINCTRL_PIN(231, "VISA2CH0_D2"),
282 PINCTRL_PIN(232, "VISA2CH0_D3"),
283 PINCTRL_PIN(233, "VISA2CH0_D4"),
284 PINCTRL_PIN(234, "VISA2CH0_D5"),
285 PINCTRL_PIN(235, "VISA2CH0_D6"),
286 PINCTRL_PIN(236, "VISA2CH0_D7"),
287 PINCTRL_PIN(237, "VISA2CH0_CLK"),
288 PINCTRL_PIN(238, "VISA2CH1_D0"),
289 PINCTRL_PIN(239, "VISA2CH1_D1"),
290 PINCTRL_PIN(240, "VISA2CH1_D2"),
291 PINCTRL_PIN(241, "VISA2CH1_D3"),
292 PINCTRL_PIN(242, "VISA2CH1_D4"),
293 PINCTRL_PIN(243, "VISA2CH1_D5"),
294 PINCTRL_PIN(244, "VISA2CH1_D6"),
295 PINCTRL_PIN(245, "VISA2CH1_D7"),
296 PINCTRL_PIN(246, "VISA2CH1_CLK"),
297};
298
299static const struct intel_community lbg_communities[] = {
300 LBG_COMMUNITY(0, 0, 71),
301 LBG_COMMUNITY(1, 72, 132),
302 LBG_COMMUNITY(3, 133, 144),
303 LBG_COMMUNITY(4, 145, 180),
304 LBG_COMMUNITY(5, 181, 246),
305};
306
307static const struct intel_pinctrl_soc_data lbg_soc_data = {
308 .pins = lbg_pins,
309 .npins = ARRAY_SIZE(lbg_pins),
310 .communities = lbg_communities,
311 .ncommunities = ARRAY_SIZE(lbg_communities),
312};
313
314static int lbg_pinctrl_probe(struct platform_device *pdev)
315{
316 return intel_pinctrl_probe(pdev, &lbg_soc_data);
317}
318
319static const struct dev_pm_ops lbg_pinctrl_pm_ops = {
320 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
321 intel_pinctrl_resume)
322};
323
324static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
325 { "INT3536" },
326 { }
327};
328MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match);
329
330static struct platform_driver lbg_pinctrl_driver = {
331 .probe = lbg_pinctrl_probe,
332 .driver = {
333 .name = "lewisburg-pinctrl",
334 .acpi_match_table = lbg_pinctrl_acpi_match,
335 .pm = &lbg_pinctrl_pm_ops,
336 },
337};
338
339module_platform_driver(lbg_pinctrl_driver);
340
341MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
342MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver");
343MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 15:25:38 -0400