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authorAlex Deucher <alexander.deucher@amd.com>2017-12-08 17:02:24 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-13 17:28:08 -0500
commite466c2935fe196f4c9d512650f1224f194a00b51 (patch)
tree69e1b65e25d933f5924088644ff882a3978a1327
parent2dd744e0ce2a34cb6b77a80385eee827a6a1ee24 (diff)
drm/amdgpu: remove some old gc 9.x registers
Leftover from bring up. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h8
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h7
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h14
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h45
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h14
5 files changed, 4 insertions, 84 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
index 003a131bad47..567a904804bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
+++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
@@ -48,7 +48,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_1[] =
48 0x00000000, // DB_STENCIL_WRITE_BASE 48 0x00000000, // DB_STENCIL_WRITE_BASE
49 0x00000000, // DB_STENCIL_WRITE_BASE_HI 49 0x00000000, // DB_STENCIL_WRITE_BASE_HI
50 0x00000000, // DB_DFSM_CONTROL 50 0x00000000, // DB_DFSM_CONTROL
51 0x00000000, // DB_RENDER_FILTER 51 0, // HOLE
52 0x00000000, // DB_Z_INFO2 52 0x00000000, // DB_Z_INFO2
53 0x00000000, // DB_STENCIL_INFO2 53 0x00000000, // DB_STENCIL_INFO2
54 0, // HOLE 54 0, // HOLE
@@ -259,8 +259,8 @@ static const unsigned int gfx9_SECT_CONTEXT_def_2[] =
259 0x00000000, // PA_SC_RIGHT_VERT_GRID 259 0x00000000, // PA_SC_RIGHT_VERT_GRID
260 0x00000000, // PA_SC_LEFT_VERT_GRID 260 0x00000000, // PA_SC_LEFT_VERT_GRID
261 0x00000000, // PA_SC_HORIZ_GRID 261 0x00000000, // PA_SC_HORIZ_GRID
262 0x00000000, // PA_SC_FOV_WINDOW_LR 262 0, // HOLE
263 0x00000000, // PA_SC_FOV_WINDOW_TB 263 0, // HOLE
264 0, // HOLE 264 0, // HOLE
265 0, // HOLE 265 0, // HOLE
266 0, // HOLE 266 0, // HOLE
@@ -701,7 +701,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_7[] =
701{ 701{
702 0x00000000, // VGT_GS_MAX_PRIMS_PER_SUBGROUP 702 0x00000000, // VGT_GS_MAX_PRIMS_PER_SUBGROUP
703 0x00000000, // VGT_DRAW_PAYLOAD_CNTL 703 0x00000000, // VGT_DRAW_PAYLOAD_CNTL
704 0x00000000, // VGT_INDEX_PAYLOAD_CNTL 704 0, // HOLE
705 0x00000000, // VGT_INSTANCE_STEP_RATE_0 705 0x00000000, // VGT_INSTANCE_STEP_RATE_0
706 0x00000000, // VGT_INSTANCE_STEP_RATE_1 706 0x00000000, // VGT_INSTANCE_STEP_RATE_1
707 0, // HOLE 707 0, // HOLE
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
index 663d3af35baf..5bf84c6d0ec3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
@@ -436,7 +436,6 @@
436#define mmTA_CNTL_DEFAULT 0x8004d850 436#define mmTA_CNTL_DEFAULT 0x8004d850
437#define mmTA_CNTL_AUX_DEFAULT 0x00000000 437#define mmTA_CNTL_AUX_DEFAULT 0x00000000
438#define mmTA_RESERVED_010C_DEFAULT 0x00000000 438#define mmTA_RESERVED_010C_DEFAULT 0x00000000
439#define mmTA_GRAD_ADJ_DEFAULT 0x40000040
440#define mmTA_STATUS_DEFAULT 0x00000000 439#define mmTA_STATUS_DEFAULT 0x00000000
441#define mmTA_SCRATCH_DEFAULT 0x00000000 440#define mmTA_SCRATCH_DEFAULT 0x00000000
442 441
@@ -1700,7 +1699,6 @@
1700#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 1699#define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000
1701#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000 1700#define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000
1702#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000 1701#define mmDB_DFSM_CONTROL_DEFAULT 0x00000000
1703#define mmDB_RENDER_FILTER_DEFAULT 0x00000000
1704#define mmDB_Z_INFO2_DEFAULT 0x00000000 1702#define mmDB_Z_INFO2_DEFAULT 0x00000000
1705#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000 1703#define mmDB_STENCIL_INFO2_DEFAULT 0x00000000
1706#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000 1704#define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000
@@ -1806,8 +1804,6 @@
1806#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000 1804#define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000
1807#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000 1805#define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000
1808#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000 1806#define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000
1809#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000
1810#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000
1811#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000 1807#define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000
1812#define mmCB_BLEND_RED_DEFAULT 0x00000000 1808#define mmCB_BLEND_RED_DEFAULT 0x00000000
1813#define mmCB_BLEND_GREEN_DEFAULT 0x00000000 1809#define mmCB_BLEND_GREEN_DEFAULT 0x00000000
@@ -2072,7 +2068,6 @@
2072#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000 2068#define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000
2073#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000 2069#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000
2074#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000 2070#define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000
2075#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000
2076#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000 2071#define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000
2077#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000 2072#define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000
2078#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000 2073#define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000
@@ -2490,7 +2485,6 @@
2490#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000 2485#define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000
2491#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000 2486#define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000
2492#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff 2487#define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff
2493#define mmVGT_OBJECT_ID_DEFAULT 0x00000000
2494#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000 2488#define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000
2495#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000 2489#define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000
2496#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000 2490#define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000
@@ -2534,7 +2528,6 @@
2534#define mmSQC_WRITEBACK_DEFAULT 0x00000000 2528#define mmSQC_WRITEBACK_DEFAULT 0x00000000
2535#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000 2529#define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000
2536#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000 2530#define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000
2537#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040
2538#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000 2531#define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000
2539#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000 2532#define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000
2540#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000 2533#define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
index e6d6171aa8b9..4ce090db7ef7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
@@ -841,8 +841,6 @@
841#define mmTA_CNTL_AUX_BASE_IDX 0 841#define mmTA_CNTL_AUX_BASE_IDX 0
842#define mmTA_RESERVED_010C 0x0543 842#define mmTA_RESERVED_010C 0x0543
843#define mmTA_RESERVED_010C_BASE_IDX 0 843#define mmTA_RESERVED_010C_BASE_IDX 0
844#define mmTA_GRAD_ADJ 0x0544
845#define mmTA_GRAD_ADJ_BASE_IDX 0
846#define mmTA_STATUS 0x0548 844#define mmTA_STATUS 0x0548
847#define mmTA_STATUS_BASE_IDX 0 845#define mmTA_STATUS_BASE_IDX 0
848#define mmTA_SCRATCH 0x0564 846#define mmTA_SCRATCH 0x0564
@@ -3330,8 +3328,6 @@
3330#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 3328#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
3331#define mmDB_DFSM_CONTROL 0x0018 3329#define mmDB_DFSM_CONTROL 0x0018
3332#define mmDB_DFSM_CONTROL_BASE_IDX 1 3330#define mmDB_DFSM_CONTROL_BASE_IDX 1
3333#define mmDB_RENDER_FILTER 0x0019
3334#define mmDB_RENDER_FILTER_BASE_IDX 1
3335#define mmDB_Z_INFO2 0x001a 3331#define mmDB_Z_INFO2 0x001a
3336#define mmDB_Z_INFO2_BASE_IDX 1 3332#define mmDB_Z_INFO2_BASE_IDX 1
3337#define mmDB_STENCIL_INFO2 0x001b 3333#define mmDB_STENCIL_INFO2 0x001b
@@ -3542,10 +3538,6 @@
3542#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 3538#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
3543#define mmPA_SC_HORIZ_GRID 0x00ea 3539#define mmPA_SC_HORIZ_GRID 0x00ea
3544#define mmPA_SC_HORIZ_GRID_BASE_IDX 1 3540#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
3545#define mmPA_SC_FOV_WINDOW_LR 0x00eb
3546#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1
3547#define mmPA_SC_FOV_WINDOW_TB 0x00ec
3548#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1
3549#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 3541#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
3550#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 3542#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
3551#define mmCB_BLEND_RED 0x0105 3543#define mmCB_BLEND_RED 0x0105
@@ -4074,8 +4066,6 @@
4074#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 4066#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1
4075#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 4067#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6
4076#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 4068#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
4077#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7
4078#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1
4079#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 4069#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8
4080#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 4070#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
4081#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 4071#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9
@@ -4908,8 +4898,6 @@
4908#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 4898#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1
4909#define mmIA_MULTI_VGT_PARAM 0x2258 4899#define mmIA_MULTI_VGT_PARAM 0x2258
4910#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 4900#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1
4911#define mmVGT_OBJECT_ID 0x2259
4912#define mmVGT_OBJECT_ID_BASE_IDX 1
4913#define mmVGT_INSTANCE_BASE_ID 0x225a 4901#define mmVGT_INSTANCE_BASE_ID 0x225a
4914#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 4902#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1
4915#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 4903#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280
@@ -4996,8 +4984,6 @@
4996#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 4984#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1
4997#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 4985#define mmTA_CS_BC_BASE_ADDR_HI 0x2381
4998#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 4986#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1
4999#define mmTA_GRAD_ADJ_UCONFIG 0x2382
5000#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1
5001#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 4987#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0
5002#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 4988#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1
5003#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 4989#define mmDB_OCCLUSION_COUNT0_HI 0x23c1
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
index 5c5e9b445432..2e1214be67a2 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
@@ -4576,15 +4576,6 @@
4576//TA_RESERVED_010C 4576//TA_RESERVED_010C
4577#define TA_RESERVED_010C__Unused__SHIFT 0x0 4577#define TA_RESERVED_010C__Unused__SHIFT 0x0
4578#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL 4578#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
4579//TA_GRAD_ADJ
4580#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0
4581#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8
4582#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10
4583#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18
4584#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL
4585#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L
4586#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L
4587#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L
4588//TA_STATUS 4579//TA_STATUS
4589#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc 4580#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
4590#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd 4581#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
@@ -14459,9 +14450,6 @@
14459#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L 14450#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L
14460#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L 14451#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L
14461#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L 14452#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L
14462//DB_RENDER_FILTER
14463#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0
14464#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL
14465//DB_Z_INFO2 14453//DB_Z_INFO2
14466#define DB_Z_INFO2__EPITCH__SHIFT 0x0 14454#define DB_Z_INFO2__EPITCH__SHIFT 0x0
14467#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL 14455#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL
@@ -14959,11 +14947,9 @@
14959#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 14947#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0
14960#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 14948#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1
14961#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 14949#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5
14962#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8
14963#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L 14950#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L
14964#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L 14951#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L
14965#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L 14952#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L
14966#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L
14967//CP_PERFMON_CNTX_CNTL 14953//CP_PERFMON_CNTX_CNTL
14968#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f 14954#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
14969#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L 14955#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L
@@ -15003,20 +14989,6 @@
15003#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L 14989#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L
15004#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L 14990#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L
15005#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L 14991#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L
15006//PA_SC_FOV_WINDOW_LR
15007#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0
15008#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8
15009#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10
15010#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18
15011#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL
15012#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L
15013#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L
15014#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L
15015//PA_SC_FOV_WINDOW_TB
15016#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0
15017#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8
15018#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL
15019#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L
15020//VGT_MULTI_PRIM_IB_RESET_INDX 14992//VGT_MULTI_PRIM_IB_RESET_INDX
15021#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 14993#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
15022#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL 14994#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL
@@ -17010,13 +16982,11 @@
17010#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 16982#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2
17011#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 16983#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3
17012#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 16984#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4
17013#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5
17014#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L 16985#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L
17015#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L 16986#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L
17016#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L 16987#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L
17017#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L 16988#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L
17018#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L 16989#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L
17019#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L
17020//PA_CL_OBJPRIM_ID_CNTL 16990//PA_CL_OBJPRIM_ID_CNTL
17021#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 16991#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0
17022#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 16992#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1
@@ -17345,9 +17315,6 @@
17345#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L 17315#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L
17346#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L 17316#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L
17347#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L 17317#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L
17348//VGT_INDEX_PAYLOAD_CNTL
17349#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0
17350#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L
17351//VGT_INSTANCE_STEP_RATE_0 17318//VGT_INSTANCE_STEP_RATE_0
17352#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 17319#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
17353#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL 17320#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL
@@ -19849,9 +19816,6 @@
19849#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L 19816#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L
19850#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L 19817#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L
19851#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L 19818#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L
19852//VGT_OBJECT_ID
19853#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0
19854#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL
19855//VGT_INSTANCE_BASE_ID 19819//VGT_INSTANCE_BASE_ID
19856#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 19820#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0
19857#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL 19821#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL
@@ -20067,15 +20031,6 @@
20067//TA_CS_BC_BASE_ADDR_HI 20031//TA_CS_BC_BASE_ADDR_HI
20068#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 20032#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
20069#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL 20033#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL
20070//TA_GRAD_ADJ_UCONFIG
20071#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0
20072#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8
20073#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10
20074#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18
20075#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL
20076#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L
20077#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L
20078#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L
20079//DB_OCCLUSION_COUNT0_LOW 20034//DB_OCCLUSION_COUNT0_LOW
20080#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 20035#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
20081#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL 20036#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
index db7ef5ede0e5..030e0020902b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h
@@ -815,8 +815,6 @@
815#define mmTA_CNTL_AUX_BASE_IDX 0 815#define mmTA_CNTL_AUX_BASE_IDX 0
816#define mmTA_RESERVED_010C 0x0543 816#define mmTA_RESERVED_010C 0x0543
817#define mmTA_RESERVED_010C_BASE_IDX 0 817#define mmTA_RESERVED_010C_BASE_IDX 0
818#define mmTA_GRAD_ADJ 0x0544
819#define mmTA_GRAD_ADJ_BASE_IDX 0
820#define mmTA_STATUS 0x0548 818#define mmTA_STATUS 0x0548
821#define mmTA_STATUS_BASE_IDX 0 819#define mmTA_STATUS_BASE_IDX 0
822#define mmTA_SCRATCH 0x0564 820#define mmTA_SCRATCH 0x0564
@@ -3617,8 +3615,6 @@
3617#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 3615#define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1
3618#define mmDB_DFSM_CONTROL 0x0018 3616#define mmDB_DFSM_CONTROL 0x0018
3619#define mmDB_DFSM_CONTROL_BASE_IDX 1 3617#define mmDB_DFSM_CONTROL_BASE_IDX 1
3620#define mmDB_RENDER_FILTER 0x0019
3621#define mmDB_RENDER_FILTER_BASE_IDX 1
3622#define mmDB_Z_INFO2 0x001a 3618#define mmDB_Z_INFO2 0x001a
3623#define mmDB_Z_INFO2_BASE_IDX 1 3619#define mmDB_Z_INFO2_BASE_IDX 1
3624#define mmDB_STENCIL_INFO2 0x001b 3620#define mmDB_STENCIL_INFO2 0x001b
@@ -3829,10 +3825,6 @@
3829#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 3825#define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1
3830#define mmPA_SC_HORIZ_GRID 0x00ea 3826#define mmPA_SC_HORIZ_GRID 0x00ea
3831#define mmPA_SC_HORIZ_GRID_BASE_IDX 1 3827#define mmPA_SC_HORIZ_GRID_BASE_IDX 1
3832#define mmPA_SC_FOV_WINDOW_LR 0x00eb
3833#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1
3834#define mmPA_SC_FOV_WINDOW_TB 0x00ec
3835#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1
3836#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 3828#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103
3837#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 3829#define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1
3838#define mmCB_BLEND_RED 0x0105 3830#define mmCB_BLEND_RED 0x0105
@@ -4361,8 +4353,6 @@
4361#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 4353#define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1
4362#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 4354#define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6
4363#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 4355#define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1
4364#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7
4365#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1
4366#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 4356#define mmVGT_INSTANCE_STEP_RATE_0 0x02a8
4367#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 4357#define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1
4368#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 4358#define mmVGT_INSTANCE_STEP_RATE_1 0x02a9
@@ -5195,8 +5185,6 @@
5195#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 5185#define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1
5196#define mmIA_MULTI_VGT_PARAM 0x2258 5186#define mmIA_MULTI_VGT_PARAM 0x2258
5197#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 5187#define mmIA_MULTI_VGT_PARAM_BASE_IDX 1
5198#define mmVGT_OBJECT_ID 0x2259
5199#define mmVGT_OBJECT_ID_BASE_IDX 1
5200#define mmVGT_INSTANCE_BASE_ID 0x225a 5188#define mmVGT_INSTANCE_BASE_ID 0x225a
5201#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 5189#define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1
5202#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 5190#define mmPA_SU_LINE_STIPPLE_VALUE 0x2280
@@ -5283,8 +5271,6 @@
5283#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 5271#define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1
5284#define mmTA_CS_BC_BASE_ADDR_HI 0x2381 5272#define mmTA_CS_BC_BASE_ADDR_HI 0x2381
5285#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 5273#define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1
5286#define mmTA_GRAD_ADJ_UCONFIG 0x2382
5287#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1
5288#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 5274#define mmDB_OCCLUSION_COUNT0_LOW 0x23c0
5289#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 5275#define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1
5290#define mmDB_OCCLUSION_COUNT0_HI 0x23c1 5276#define mmDB_OCCLUSION_COUNT0_HI 0x23c1
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 18:06:28 -0400