Merge tag 'imx-dt64-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt

Pull "Freescale arm64 device tree updates for 4.15" from Shawn Guo:

 - Add GICv3 ITS node and PCIe devcies for LS1088A support.
 - Enable PCIe support for LS2088A SoC.
 - Add OP-TEE support for various Layerscape SoCs, LS1012A, LS1043A,
   LS1046A, LS1088A and LS208XA.
 - Update DPAA QBMan nodes to use constant defines in the interrupt
   description.
 - Add DSPI device to support SPI-NOR on LS1012A based boards.

* tag 'imx-dt64-4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: update the DPAA QBMan nodes
  arm64: dts: ls1088a: add PCIe controller DT nodes
  arm64: dts: ls1088a: add gicv3 ITS DT node
  arm64: dts: ls2088a: add pcie support
  arm64: dts: ls: Add optee node
  dt-bindings: mtd: add sst25wf040b and en25s64 to sip-nor list
  dt-bindings: spi: Add fsl,ls1012a-dspi compatible string
  arm64: dts: ls1012a: add the DTS node for DSPI support

9 files changed, 173 insertions, 4 deletions

diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
index 9ce35af8507c..4cab5d85cf6f 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.txt
@@ -13,6 +13,7 @@ Required properties:
                  at25df321a
                  at25df641
                  at26df081a
+                 en25s64
                  mr25h256
                  mr25h10
                  mr25h40
@@ -31,6 +32,7 @@ Required properties:
                  s25fl008k
                  s25fl064k
                  sst25vf040b
+                 sst25wf040b
                  m25p40
                  m25p80
                  m25p16
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index 13b1fcc8469e..dcc7eaada511 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -5,6 +5,7 @@ Required properties:
                 "fsl,ls2085a-dspi"
                 or
                 "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
+                "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain SPI controller interrupt
 - clocks: from common clock binding: handle to dspi clock.
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index 8c013b54db14..cdc4aee75227 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -93,6 +93,39 @@
         };
 };
 
+&dspi {
+        bus-num = <0>;
+        status = "okay";
+
+        flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "n25q128a11", "jedec,spi-nor";
+                reg = <0>;
+                spi-max-frequency = <10000000>;
+        };
+
+        flash@1 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "sst25wf040b", "jedec,spi-nor";
+                spi-cpol;
+                spi-cpha;
+                reg = <1>;
+                spi-max-frequency = <10000000>;
+        };
+
+        flash@2 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "en25s64", "jedec,spi-nor";
+                spi-cpol;
+                spi-cpha;
+                reg = <2>;
+                spi-max-frequency = <10000000>;
+        };
+};
+
 &duart0 {
         status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index df83915d6ea6..3b0b6e4fdc11 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -355,6 +355,19 @@
                         status = "disabled";
                 };
 
+                dspi: dspi@2100000 {
+                        compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2100000 0x0 0x10000>;
+                        interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "dspi";
+                        clocks = <&clockgen 4 0>;
+                        spi-num-chipselects = <5>;
+                        big-endian;
+                        status = "disabled";
+                };
+
                 duart0: serial@21c0500 {
                         compatible = "fsl,ns16550", "ns16550a";
                         reg = <0x00 0x21c0500 0x0 0x100>;
@@ -472,4 +485,11 @@
                         phy_type = "ulpi";
                 };
         };
+
+        firmware {
+                optee {
+                        compatible = "linaro,optee-tz";
+                        method = "smc";
+                };
+        };
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index d16b9cc1e825..380e7c713395 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -376,14 +376,14 @@
                 qman: qman@1880000 {
                         compatible = "fsl,qman";
                         reg = <0x0 0x1880000 0x0 0x10000>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         memory-region = <&qman_fqd &qman_pfdr>;
                 };
 
                 bman: bman@1890000 {
                         compatible = "fsl,bman";
                         reg = <0x0 0x1890000 0x0 0x10000>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         memory-region = <&bman_fbpr>;
                 };
 
@@ -749,6 +749,13 @@
                 };
         };
 
+        firmware {
+                optee {
+                        compatible = "linaro,optee-tz";
+                        method = "smc";
+                };
+        };
+
 };
 
 #include "qoriq-qman-portals.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index c8ff0baddf1d..3a07914175f0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -281,7 +281,7 @@
                 qman: qman@1880000 {
                         compatible = "fsl,qman";
                         reg = <0x0 0x1880000 0x0 0x10000>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         memory-region = <&qman_fqd &qman_pfdr>;
 
                 };
@@ -289,7 +289,7 @@
                 bman: bman@1890000 {
                         compatible = "fsl,bman";
                         reg = <0x0 0x1890000 0x0 0x10000>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         memory-region = <&bman_fbpr>;
 
                 };
@@ -689,6 +689,13 @@
                         no-map;
                 };
         };
+
+        firmware {
+                optee {
+                        compatible = "linaro,optee-tz";
+                        method = "smc";
+                };
+        };
 };
 
 #include "qoriq-qman-portals.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 33797b373674..bd80e9a2e67c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -147,6 +147,15 @@
                       <0x0 0x0c0d0000 0 0x1000>, /* GICH */
                       <0x0 0x0c0e0000 0 0x20000>; /* GICV */
                 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                its: gic-its@6020000 {
+                        compatible = "arm,gic-v3-its";
+                        msi-controller;
+                        reg = <0x0 0x6020000 0 0x20000>;
+                };
         };
 
         timer {
@@ -434,6 +443,85 @@
                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
                         };
                 };
+
+                pcie@3400000 {
+                        compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
+                        reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+                               0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+                        reg-names = "regs", "config";
+                        interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+                        interrupt-names = "aer";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        dma-coherent;
+                        num-lanes = <4>;
+                        bus-range = <0x0 0xff>;
+                        ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                        msi-parent = <&its>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                pcie@3500000 {
+                        compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
+                        reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+                               0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+                        reg-names = "regs", "config";
+                        interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+                        interrupt-names = "aer";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        dma-coherent;
+                        num-lanes = <4>;
+                        bus-range = <0x0 0xff>;
+                        ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                        msi-parent = <&its>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                pcie@3600000 {
+                        compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
+                        reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+                               0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+                        reg-names = "regs", "config";
+                        interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+                        interrupt-names = "aer";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        dma-coherent;
+                        num-lanes = <8>;
+                        bus-range = <0x0 0xff>;
+                        ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                        msi-parent = <&its>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
+                                        <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
+                };
+        };
+
+        firmware {
+                optee {
+                        compatible = "linaro,optee-tz";
+                        method = "smc";
+                };
         };
 
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index 6aa319dae396..aeaef01d375f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -151,6 +151,7 @@
 };
 
 &pcie1 {
+        compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
                0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -159,6 +160,7 @@
 };
 
 &pcie2 {
+        compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
                0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -167,6 +169,7 @@
 };
 
 &pcie3 {
+        compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
                0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -175,6 +178,7 @@
 };
 
 &pcie4 {
+        compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
         reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
                0x38 0x00000000 0x0 0x00002000>; /* configuration space */
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 4fb9a0966a84..f3a40af33af8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -786,4 +786,11 @@
                 interrupts = <0 18 0x4>;
                 little-endian;
         };
+
+        firmware {
+                optee {
+                        compatible = "linaro,optee-tz";
+                        method = "smc";
+                };
+        };
 };