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authorLinus Walleij <linus.walleij@linaro.org>2016-08-29 05:30:18 -0400
committerLinus Walleij <linus.walleij@linaro.org>2016-08-31 03:30:28 -0400
commite3f617602103ef674aec417d52f0cff145fc0599 (patch)
tree19bc665bd9e82ca1319acb4cd720b87b4178bfbd
parentb2da116cbe46f55d34bcac3ae69206aeda5f11e1 (diff)
ARM: integrator: move CP CLCD display to DTS
The Integrator/CP CLCD VGA display can now be registered fully from the device tree. Delete the board file code and add the display definition to the DTS. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--arch/arm/boot/dts/integratorcp.dts37
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c57
2 files changed, 36 insertions, 58 deletions
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index e8299590bb6a..03d8423d3a11 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -226,7 +226,42 @@
226 reg = <0xC0000000 0x1000>; 226 reg = <0xC0000000 0x1000>;
227 interrupts = <22>; 227 interrupts = <22>;
228 clocks = <&auxosc>, <&pclk>; 228 clocks = <&auxosc>, <&pclk>;
229 clock-names = "clcd", "apb_pclk"; 229 clock-names = "clcdclk", "apb_pclk";
230
231 port {
232 /*
233 * The VGA connected is implemented with a
234 * THS8134A triple DAC that can be run in 24bit
235 * or 16bit RGB mode.
236 */
237 clcd_pads: endpoint {
238 remote-endpoint = <&clcd_panel>;
239 arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
240 };
241 };
242
243 panel {
244 compatible = "panel-dpi";
245
246 port {
247 clcd_panel: endpoint {
248 remote-endpoint = <&clcd_pads>;
249 };
250 };
251
252 /* Standard 640x480 VGA timings */
253 panel-timing {
254 clock-frequency = <25175000>;
255 hactive = <640>;
256 hback-porch = <48>;
257 hfront-porch = <16>;
258 hsync-len = <96>;
259 vactive = <480>;
260 vback-porch = <33>;
261 vfront-porch = <10>;
262 vsync-len = <2>;
263 };
264 };
230 }; 265 };
231 }; 266 };
232}; 267};
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 825298349bf5..a9e3cb511fcb 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -17,8 +17,6 @@
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/amba/bus.h> 18#include <linux/amba/bus.h>
19#include <linux/amba/kmi.h> 19#include <linux/amba/kmi.h>
20#include <linux/amba/clcd.h>
21#include <linux/platform_data/video-clcd-versatile.h>
22#include <linux/amba/mmci.h> 20#include <linux/amba/mmci.h>
23#include <linux/io.h> 21#include <linux/io.h>
24#include <linux/irqchip.h> 22#include <linux/irqchip.h>
@@ -42,8 +40,6 @@
42/* Base address to the CP controller */ 40/* Base address to the CP controller */
43static void __iomem *intcp_con_base; 41static void __iomem *intcp_con_base;
44 42
45#define INTCP_PA_CLCD_BASE 0xc0000000
46
47/* 43/*
48 * Logical Physical 44 * Logical Physical
49 * f1000000 10000000 Core module registers 45 * f1000000 10000000 Core module registers
@@ -121,57 +117,6 @@ static struct mmci_platform_data mmc_data = {
121 .gpio_cd = -1, 117 .gpio_cd = -1,
122}; 118};
123 119
124/*
125 * CLCD support
126 */
127/*
128 * Ensure VGA is selected.
129 */
130static void cp_clcd_enable(struct clcd_fb *fb)
131{
132 struct fb_var_screeninfo *var = &fb->fb.var;
133 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
134 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
135
136 if (var->bits_per_pixel <= 8 ||
137 (var->bits_per_pixel == 16 && var->green.length == 5))
138 /* Pseudocolor, RGB555, BGR555 */
139 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
140 else if (fb->fb.var.bits_per_pixel <= 16)
141 /* truecolor RGB565 */
142 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
143 else
144 val = 0; /* no idea for this, don't trust the docs */
145
146 cm_control(CM_CTRL_LCDMUXSEL_MASK|
147 CM_CTRL_LCDEN0|
148 CM_CTRL_LCDEN1|
149 CM_CTRL_STATIC1|
150 CM_CTRL_STATIC2|
151 CM_CTRL_STATIC|
152 CM_CTRL_n24BITEN, val);
153}
154
155static int cp_clcd_setup(struct clcd_fb *fb)
156{
157 fb->panel = versatile_clcd_get_panel("VGA");
158 if (!fb->panel)
159 return -EINVAL;
160
161 return versatile_clcd_setup_dma(fb, SZ_1M);
162}
163
164static struct clcd_board clcd_data = {
165 .name = "Integrator/CP",
166 .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
167 .check = clcdfb_check,
168 .decode = clcdfb_decode,
169 .enable = cp_clcd_enable,
170 .setup = cp_clcd_setup,
171 .mmap = versatile_clcd_mmap_dma,
172 .remove = versatile_clcd_remove_dma,
173};
174
175#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28) 120#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
176 121
177static u64 notrace intcp_read_sched_clock(void) 122static u64 notrace intcp_read_sched_clock(void)
@@ -209,8 +154,6 @@ static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
209 "mmci", &mmc_data), 154 "mmci", &mmc_data),
210 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE, 155 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
211 "aaci", &mmc_data), 156 "aaci", &mmc_data),
212 OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
213 "clcd", &clcd_data),
214 { /* sentinel */ }, 157 { /* sentinel */ },
215}; 158};
216 159