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authorMarek Szyprowski <m.szyprowski@samsung.com>2017-10-11 05:25:14 -0400
committerKrzysztof Kozlowski <krzk@kernel.org>2017-12-04 11:45:43 -0500
commite3d30890f15f49ca0cb9f3300f39d7e5b53c9cf0 (patch)
treebd9a4fb5c48809e89a2a2c5175af24253f2391c8
parent1842713cc9fbc7b6fb62b08f752f6c481b067dcd (diff)
ARM: dts: exynos: Add Exynos4412 ISP clock controller
Exynos4412 ISP clock controller is located in the SOC area, which belongs to ISP power domain. This patch instantiates a separate clock driver for those clocks, updates all clients of ISP clocks and ensures that the driver is properly integrated in ISP power domin. This finally solves all the mysterious freezes in accessing ISP clocks when ISP power domain is disabled. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi71
1 files changed, 44 insertions, 27 deletions
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index b255ac55b1c1..282525ac7554 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -191,10 +191,19 @@
191 191
192 clock: clock-controller@10030000 { 192 clock: clock-controller@10030000 {
193 compatible = "samsung,exynos4412-clock"; 193 compatible = "samsung,exynos4412-clock";
194 reg = <0x10030000 0x20000>; 194 reg = <0x10030000 0x18000>;
195 #clock-cells = <1>; 195 #clock-cells = <1>;
196 }; 196 };
197 197
198 isp_clock: clock-controller@10048000 {
199 compatible = "samsung,exynos4412-isp-clock";
200 reg = <0x10048000 0x1000>;
201 #clock-cells = <1>;
202 power-domains = <&pd_isp>;
203 clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
204 clock-names = "aclk200", "aclk400_mcuisp";
205 };
206
198 mct@10050000 { 207 mct@10050000 {
199 compatible = "samsung,exynos4412-mct"; 208 compatible = "samsung,exynos4412-mct";
200 reg = <0x10050000 0x800>; 209 reg = <0x10050000 0x800>;
@@ -257,7 +266,7 @@
257 reg = <0x12390000 0x1000>; 266 reg = <0x12390000 0x1000>;
258 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 267 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
259 power-domains = <&pd_isp>; 268 power-domains = <&pd_isp>;
260 clocks = <&clock CLK_FIMC_LITE0>; 269 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
261 clock-names = "flite"; 270 clock-names = "flite";
262 iommus = <&sysmmu_fimc_lite0>; 271 iommus = <&sysmmu_fimc_lite0>;
263 status = "disabled"; 272 status = "disabled";
@@ -268,7 +277,7 @@
268 reg = <0x123A0000 0x1000>; 277 reg = <0x123A0000 0x1000>;
269 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 278 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
270 power-domains = <&pd_isp>; 279 power-domains = <&pd_isp>;
271 clocks = <&clock CLK_FIMC_LITE1>; 280 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
272 clock-names = "flite"; 281 clock-names = "flite";
273 iommus = <&sysmmu_fimc_lite1>; 282 iommus = <&sysmmu_fimc_lite1>;
274 status = "disabled"; 283 status = "disabled";
@@ -280,29 +289,35 @@
280 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 289 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 290 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
282 power-domains = <&pd_isp>; 291 power-domains = <&pd_isp>;
283 clocks = <&clock CLK_FIMC_LITE0>, 292 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
284 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, 293 <&isp_clock CLK_ISP_FIMC_LITE1>,
285 <&clock CLK_PPMUISPMX>, 294 <&isp_clock CLK_ISP_PPMUISPX>,
295 <&isp_clock CLK_ISP_PPMUISPMX>,
296 <&isp_clock CLK_ISP_FIMC_ISP>,
297 <&isp_clock CLK_ISP_FIMC_DRC>,
298 <&isp_clock CLK_ISP_FIMC_FD>,
299 <&isp_clock CLK_ISP_MCUISP>,
300 <&isp_clock CLK_ISP_GICISP>,
301 <&isp_clock CLK_ISP_MCUCTL_ISP>,
302 <&isp_clock CLK_ISP_PWM_ISP>,
303 <&isp_clock CLK_ISP_DIV_ISP0>,
304 <&isp_clock CLK_ISP_DIV_ISP1>,
305 <&isp_clock CLK_ISP_DIV_MCUISP0>,
306 <&isp_clock CLK_ISP_DIV_MCUISP1>,
286 <&clock CLK_MOUT_MPLL_USER_T>, 307 <&clock CLK_MOUT_MPLL_USER_T>,
287 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, 308 <&clock CLK_ACLK200>,
288 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
289 <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
290 <&clock CLK_PWM_ISP>,
291 <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
292 <&clock CLK_DIV_MCUISP0>,
293 <&clock CLK_DIV_MCUISP1>,
294 <&clock CLK_UART_ISP_SCLK>,
295 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
296 <&clock CLK_ACLK400_MCUISP>, 309 <&clock CLK_ACLK400_MCUISP>,
297 <&clock CLK_DIV_ACLK400_MCUISP>; 310 <&clock CLK_DIV_ACLK200>,
311 <&clock CLK_DIV_ACLK400_MCUISP>,
312 <&clock CLK_UART_ISP_SCLK>;
298 clock-names = "lite0", "lite1", "ppmuispx", 313 clock-names = "lite0", "lite1", "ppmuispx",
299 "ppmuispmx", "mpll", "isp", 314 "ppmuispmx", "isp",
300 "drc", "fd", "mcuisp", 315 "drc", "fd", "mcuisp",
301 "gicisp", "mcuctl_isp", "pwm_isp", 316 "gicisp", "mcuctl_isp", "pwm_isp",
302 "ispdiv0", "ispdiv1", "mcuispdiv0", 317 "ispdiv0", "ispdiv1", "mcuispdiv0",
303 "mcuispdiv1", "uart", "aclk200", 318 "mcuispdiv1", "mpll", "aclk200",
304 "div_aclk200", "aclk400mcuisp", 319 "aclk400mcuisp", "div_aclk200",
305 "div_aclk400mcuisp"; 320 "div_aclk400mcuisp", "uart";
306 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 321 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
307 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 322 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
308 iommu-names = "isp", "drc", "fd", "mcuctl"; 323 iommu-names = "isp", "drc", "fd", "mcuctl";
@@ -318,7 +333,7 @@
318 i2c1_isp: i2c-isp@12140000 { 333 i2c1_isp: i2c-isp@12140000 {
319 compatible = "samsung,exynos4212-i2c-isp"; 334 compatible = "samsung,exynos4212-i2c-isp";
320 reg = <0x12140000 0x100>; 335 reg = <0x12140000 0x100>;
321 clocks = <&clock CLK_I2C1_ISP>; 336 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
322 clock-names = "i2c_isp"; 337 clock-names = "i2c_isp";
323 #address-cells = <1>; 338 #address-cells = <1>;
324 #size-cells = <0>; 339 #size-cells = <0>;
@@ -355,7 +370,7 @@
355 interrupts = <16 2>; 370 interrupts = <16 2>;
356 power-domains = <&pd_isp>; 371 power-domains = <&pd_isp>;
357 clock-names = "sysmmu"; 372 clock-names = "sysmmu";
358 clocks = <&clock CLK_SMMU_ISP>; 373 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
359 #iommu-cells = <0>; 374 #iommu-cells = <0>;
360 }; 375 };
361 376
@@ -366,7 +381,7 @@
366 interrupts = <16 3>; 381 interrupts = <16 3>;
367 power-domains = <&pd_isp>; 382 power-domains = <&pd_isp>;
368 clock-names = "sysmmu"; 383 clock-names = "sysmmu";
369 clocks = <&clock CLK_SMMU_DRC>; 384 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
370 #iommu-cells = <0>; 385 #iommu-cells = <0>;
371 }; 386 };
372 387
@@ -377,7 +392,7 @@
377 interrupts = <16 4>; 392 interrupts = <16 4>;
378 power-domains = <&pd_isp>; 393 power-domains = <&pd_isp>;
379 clock-names = "sysmmu"; 394 clock-names = "sysmmu";
380 clocks = <&clock CLK_SMMU_FD>; 395 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
381 #iommu-cells = <0>; 396 #iommu-cells = <0>;
382 }; 397 };
383 398
@@ -388,7 +403,7 @@
388 interrupts = <16 5>; 403 interrupts = <16 5>;
389 power-domains = <&pd_isp>; 404 power-domains = <&pd_isp>;
390 clock-names = "sysmmu"; 405 clock-names = "sysmmu";
391 clocks = <&clock CLK_SMMU_ISPCX>; 406 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
392 #iommu-cells = <0>; 407 #iommu-cells = <0>;
393 }; 408 };
394 409
@@ -399,7 +414,8 @@
399 interrupts = <16 0>; 414 interrupts = <16 0>;
400 power-domains = <&pd_isp>; 415 power-domains = <&pd_isp>;
401 clock-names = "sysmmu", "master"; 416 clock-names = "sysmmu", "master";
402 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; 417 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
418 <&isp_clock CLK_ISP_FIMC_LITE0>;
403 #iommu-cells = <0>; 419 #iommu-cells = <0>;
404 }; 420 };
405 421
@@ -410,7 +426,8 @@
410 interrupts = <16 1>; 426 interrupts = <16 1>;
411 power-domains = <&pd_isp>; 427 power-domains = <&pd_isp>;
412 clock-names = "sysmmu", "master"; 428 clock-names = "sysmmu", "master";
413 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; 429 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
430 <&isp_clock CLK_ISP_FIMC_LITE1>;
414 #iommu-cells = <0>; 431 #iommu-cells = <0>;
415 }; 432 };
416 433