diff options
author | Mark Brown <broonie@kernel.org> | 2015-06-22 05:24:35 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2015-06-22 05:24:35 -0400 |
commit | e39f6bc7de3d7c60ecdb43e45814470a8f600679 (patch) | |
tree | 79322bf4b9f2d888e1bc26f1d13ae115acbb475e | |
parent | 6afff9e0607933afb948d9e60c684b669fe4928c (diff) | |
parent | 8604bc28365c0673d932b0bfa6e52abb5d4dd62c (diff) |
Merge remote-tracking branch 'asoc/topic/tas2552' into asoc-next
-rw-r--r-- | Documentation/devicetree/bindings/sound/tas2552.txt | 6 | ||||
-rw-r--r-- | sound/soc/codecs/tas2552.c | 182 | ||||
-rw-r--r-- | sound/soc/codecs/tas2552.h | 61 |
3 files changed, 158 insertions, 91 deletions
diff --git a/Documentation/devicetree/bindings/sound/tas2552.txt b/Documentation/devicetree/bindings/sound/tas2552.txt index 55e2a0af5645..c49992c0b62a 100644 --- a/Documentation/devicetree/bindings/sound/tas2552.txt +++ b/Documentation/devicetree/bindings/sound/tas2552.txt | |||
@@ -14,6 +14,12 @@ Required properties: | |||
14 | Optional properties: | 14 | Optional properties: |
15 | - enable-gpio - gpio pin to enable/disable the device | 15 | - enable-gpio - gpio pin to enable/disable the device |
16 | 16 | ||
17 | tas2552 can receive it's reference clock via MCLK, BCLK, IVCLKIN pin or use the | ||
18 | internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM | ||
19 | reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK. | ||
20 | For system integration the dt-bindings/sound/tas2552.h header file provides | ||
21 | defined values to selct and configure the PLL and PDM reference clocks. | ||
22 | |||
17 | Example: | 23 | Example: |
18 | 24 | ||
19 | tas2552: tas2552@41 { | 25 | tas2552: tas2552@41 { |
diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c index 891e2c529df3..4f25a7d0efa2 100644 --- a/sound/soc/codecs/tas2552.c +++ b/sound/soc/codecs/tas2552.c | |||
@@ -45,7 +45,7 @@ static struct reg_default tas2552_reg_defs[] = { | |||
45 | {TAS2552_OUTPUT_DATA, 0xc0}, | 45 | {TAS2552_OUTPUT_DATA, 0xc0}, |
46 | {TAS2552_PDM_CFG, 0x01}, | 46 | {TAS2552_PDM_CFG, 0x01}, |
47 | {TAS2552_PGA_GAIN, 0x00}, | 47 | {TAS2552_PGA_GAIN, 0x00}, |
48 | {TAS2552_BOOST_PT_CTRL, 0x0f}, | 48 | {TAS2552_BOOST_APT_CTRL, 0x0f}, |
49 | {TAS2552_RESERVED_0D, 0xbe}, | 49 | {TAS2552_RESERVED_0D, 0xbe}, |
50 | {TAS2552_LIMIT_RATE_HYS, 0x08}, | 50 | {TAS2552_LIMIT_RATE_HYS, 0x08}, |
51 | {TAS2552_CFG_2, 0xef}, | 51 | {TAS2552_CFG_2, 0xef}, |
@@ -77,7 +77,9 @@ struct tas2552_data { | |||
77 | struct gpio_desc *enable_gpio; | 77 | struct gpio_desc *enable_gpio; |
78 | unsigned char regs[TAS2552_VBAT_DATA]; | 78 | unsigned char regs[TAS2552_VBAT_DATA]; |
79 | unsigned int pll_clkin; | 79 | unsigned int pll_clkin; |
80 | int pll_clk_id; | ||
80 | unsigned int pdm_clk; | 81 | unsigned int pdm_clk; |
82 | int pdm_clk_id; | ||
81 | 83 | ||
82 | unsigned int dai_fmt; | 84 | unsigned int dai_fmt; |
83 | unsigned int tdm_delay; | 85 | unsigned int tdm_delay; |
@@ -143,31 +145,105 @@ static const struct snd_soc_dapm_route tas2552_audio_map[] = { | |||
143 | }; | 145 | }; |
144 | 146 | ||
145 | #ifdef CONFIG_PM | 147 | #ifdef CONFIG_PM |
146 | static void tas2552_sw_shutdown(struct tas2552_data *tas_data, int sw_shutdown) | 148 | static void tas2552_sw_shutdown(struct tas2552_data *tas2552, int sw_shutdown) |
147 | { | 149 | { |
148 | u8 cfg1_reg = 0; | 150 | u8 cfg1_reg = 0; |
149 | 151 | ||
150 | if (!tas_data->codec) | 152 | if (!tas2552->codec) |
151 | return; | 153 | return; |
152 | 154 | ||
153 | if (sw_shutdown) | 155 | if (sw_shutdown) |
154 | cfg1_reg = TAS2552_SWS; | 156 | cfg1_reg = TAS2552_SWS; |
155 | 157 | ||
156 | snd_soc_update_bits(tas_data->codec, TAS2552_CFG_1, TAS2552_SWS, | 158 | snd_soc_update_bits(tas2552->codec, TAS2552_CFG_1, TAS2552_SWS, |
157 | cfg1_reg); | 159 | cfg1_reg); |
158 | } | 160 | } |
159 | #endif | 161 | #endif |
160 | 162 | ||
163 | static int tas2552_setup_pll(struct snd_soc_codec *codec, | ||
164 | struct snd_pcm_hw_params *params) | ||
165 | { | ||
166 | struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev); | ||
167 | bool bypass_pll = false; | ||
168 | unsigned int pll_clk = params_rate(params) * 512; | ||
169 | unsigned int pll_clkin = tas2552->pll_clkin; | ||
170 | u8 pll_enable; | ||
171 | |||
172 | if (!pll_clkin) { | ||
173 | if (tas2552->pll_clk_id != TAS2552_PLL_CLKIN_BCLK) | ||
174 | return -EINVAL; | ||
175 | |||
176 | pll_clkin = snd_soc_params_to_bclk(params); | ||
177 | pll_clkin += tas2552->tdm_delay; | ||
178 | } | ||
179 | |||
180 | pll_enable = snd_soc_read(codec, TAS2552_CFG_2) & TAS2552_PLL_ENABLE; | ||
181 | snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0); | ||
182 | |||
183 | if (pll_clkin == pll_clk) | ||
184 | bypass_pll = true; | ||
185 | |||
186 | if (bypass_pll) { | ||
187 | /* By pass the PLL configuration */ | ||
188 | snd_soc_update_bits(codec, TAS2552_PLL_CTRL_2, | ||
189 | TAS2552_PLL_BYPASS, TAS2552_PLL_BYPASS); | ||
190 | } else { | ||
191 | /* Fill in the PLL control registers for J & D | ||
192 | * pll_clk = (.5 * pll_clkin * J.D) / 2^p | ||
193 | * Need to fill in J and D here based on incoming freq | ||
194 | */ | ||
195 | unsigned int d; | ||
196 | u8 j; | ||
197 | u8 pll_sel = (tas2552->pll_clk_id << 3) & TAS2552_PLL_SRC_MASK; | ||
198 | u8 p = snd_soc_read(codec, TAS2552_PLL_CTRL_1); | ||
199 | |||
200 | p = (p >> 7); | ||
201 | |||
202 | recalc: | ||
203 | j = (pll_clk * 2 * (1 << p)) / pll_clkin; | ||
204 | d = (pll_clk * 2 * (1 << p)) % pll_clkin; | ||
205 | d /= (pll_clkin / 10000); | ||
206 | |||
207 | if (d && (pll_clkin < 512000 || pll_clkin > 9200000)) { | ||
208 | if (tas2552->pll_clk_id == TAS2552_PLL_CLKIN_BCLK) { | ||
209 | pll_clkin = 1800000; | ||
210 | pll_sel = (TAS2552_PLL_CLKIN_1_8_FIXED << 3) & | ||
211 | TAS2552_PLL_SRC_MASK; | ||
212 | } else { | ||
213 | pll_clkin = snd_soc_params_to_bclk(params); | ||
214 | pll_clkin += tas2552->tdm_delay; | ||
215 | pll_sel = (TAS2552_PLL_CLKIN_BCLK << 3) & | ||
216 | TAS2552_PLL_SRC_MASK; | ||
217 | } | ||
218 | goto recalc; | ||
219 | } | ||
220 | |||
221 | snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_PLL_SRC_MASK, | ||
222 | pll_sel); | ||
223 | |||
224 | snd_soc_update_bits(codec, TAS2552_PLL_CTRL_1, | ||
225 | TAS2552_PLL_J_MASK, j); | ||
226 | /* Will clear the PLL_BYPASS bit */ | ||
227 | snd_soc_write(codec, TAS2552_PLL_CTRL_2, | ||
228 | TAS2552_PLL_D_UPPER(d)); | ||
229 | snd_soc_write(codec, TAS2552_PLL_CTRL_3, | ||
230 | TAS2552_PLL_D_LOWER(d)); | ||
231 | } | ||
232 | |||
233 | /* Restore PLL status */ | ||
234 | snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, | ||
235 | pll_enable); | ||
236 | |||
237 | return 0; | ||
238 | } | ||
239 | |||
161 | static int tas2552_hw_params(struct snd_pcm_substream *substream, | 240 | static int tas2552_hw_params(struct snd_pcm_substream *substream, |
162 | struct snd_pcm_hw_params *params, | 241 | struct snd_pcm_hw_params *params, |
163 | struct snd_soc_dai *dai) | 242 | struct snd_soc_dai *dai) |
164 | { | 243 | { |
165 | struct snd_soc_codec *codec = dai->codec; | 244 | struct snd_soc_codec *codec = dai->codec; |
166 | struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev); | 245 | struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev); |
167 | int sample_rate, pll_clk; | ||
168 | int d; | ||
169 | int cpf; | 246 | int cpf; |
170 | u8 p, j; | ||
171 | u8 ser_ctrl1_reg, wclk_rate; | 247 | u8 ser_ctrl1_reg, wclk_rate; |
172 | 248 | ||
173 | switch (params_width(params)) { | 249 | switch (params_width(params)) { |
@@ -245,49 +321,7 @@ static int tas2552_hw_params(struct snd_pcm_substream *substream, | |||
245 | snd_soc_update_bits(codec, TAS2552_CFG_3, TAS2552_WCLK_FREQ_MASK, | 321 | snd_soc_update_bits(codec, TAS2552_CFG_3, TAS2552_WCLK_FREQ_MASK, |
246 | wclk_rate); | 322 | wclk_rate); |
247 | 323 | ||
248 | if (!tas2552->pll_clkin) | 324 | return tas2552_setup_pll(codec, params); |
249 | return -EINVAL; | ||
250 | |||
251 | snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0); | ||
252 | |||
253 | if (tas2552->pll_clkin == TAS2552_245MHZ_CLK || | ||
254 | tas2552->pll_clkin == TAS2552_225MHZ_CLK) { | ||
255 | /* By pass the PLL configuration */ | ||
256 | snd_soc_update_bits(codec, TAS2552_PLL_CTRL_2, | ||
257 | TAS2552_PLL_BYPASS_MASK, | ||
258 | TAS2552_PLL_BYPASS); | ||
259 | } else { | ||
260 | /* Fill in the PLL control registers for J & D | ||
261 | * PLL_CLK = (.5 * freq * J.D) / 2^p | ||
262 | * Need to fill in J and D here based on incoming freq | ||
263 | */ | ||
264 | p = snd_soc_read(codec, TAS2552_PLL_CTRL_1); | ||
265 | p = (p >> 7); | ||
266 | sample_rate = params_rate(params); | ||
267 | |||
268 | if (sample_rate == 48000) | ||
269 | pll_clk = TAS2552_245MHZ_CLK; | ||
270 | else if (sample_rate == 44100) | ||
271 | pll_clk = TAS2552_225MHZ_CLK; | ||
272 | else { | ||
273 | dev_vdbg(codec->dev, "Substream sample rate is not found %i\n", | ||
274 | params_rate(params)); | ||
275 | return -EINVAL; | ||
276 | } | ||
277 | |||
278 | j = (pll_clk * 2 * (1 << p)) / tas2552->pll_clkin; | ||
279 | d = (pll_clk * 2 * (1 << p)) % tas2552->pll_clkin; | ||
280 | |||
281 | snd_soc_update_bits(codec, TAS2552_PLL_CTRL_1, | ||
282 | TAS2552_PLL_J_MASK, j); | ||
283 | snd_soc_write(codec, TAS2552_PLL_CTRL_2, | ||
284 | (d >> 7) & TAS2552_PLL_D_UPPER_MASK); | ||
285 | snd_soc_write(codec, TAS2552_PLL_CTRL_3, | ||
286 | d & TAS2552_PLL_D_LOWER_MASK); | ||
287 | |||
288 | } | ||
289 | |||
290 | return 0; | ||
291 | } | 325 | } |
292 | 326 | ||
293 | #define TAS2552_DAI_FMT_MASK (TAS2552_BCLKDIR | \ | 327 | #define TAS2552_DAI_FMT_MASK (TAS2552_BCLKDIR | \ |
@@ -370,12 +404,21 @@ static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, | |||
370 | 404 | ||
371 | switch (clk_id) { | 405 | switch (clk_id) { |
372 | case TAS2552_PLL_CLKIN_MCLK: | 406 | case TAS2552_PLL_CLKIN_MCLK: |
373 | case TAS2552_PLL_CLKIN_BCLK: | ||
374 | case TAS2552_PLL_CLKIN_IVCLKIN: | 407 | case TAS2552_PLL_CLKIN_IVCLKIN: |
408 | if (freq < 512000 || freq > 24576000) { | ||
409 | /* out of range PLL_CLKIN, fall back to use BCLK */ | ||
410 | dev_warn(codec->dev, "Out of range PLL_CLKIN: %u\n", | ||
411 | freq); | ||
412 | clk_id = TAS2552_PLL_CLKIN_BCLK; | ||
413 | freq = 0; | ||
414 | } | ||
415 | /* fall through */ | ||
416 | case TAS2552_PLL_CLKIN_BCLK: | ||
375 | case TAS2552_PLL_CLKIN_1_8_FIXED: | 417 | case TAS2552_PLL_CLKIN_1_8_FIXED: |
376 | mask = TAS2552_PLL_SRC_MASK; | 418 | mask = TAS2552_PLL_SRC_MASK; |
377 | val = (clk_id << 3) & mask; /* bit 4:5 in the register */ | 419 | val = (clk_id << 3) & mask; /* bit 4:5 in the register */ |
378 | reg = TAS2552_CFG_1; | 420 | reg = TAS2552_CFG_1; |
421 | tas2552->pll_clk_id = clk_id; | ||
379 | tas2552->pll_clkin = freq; | 422 | tas2552->pll_clkin = freq; |
380 | break; | 423 | break; |
381 | case TAS2552_PDM_CLK_PLL: | 424 | case TAS2552_PDM_CLK_PLL: |
@@ -385,6 +428,7 @@ static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, | |||
385 | mask = TAS2552_PDM_CLK_SEL_MASK; | 428 | mask = TAS2552_PDM_CLK_SEL_MASK; |
386 | val = (clk_id >> 1) & mask; /* bit 0:1 in the register */ | 429 | val = (clk_id >> 1) & mask; /* bit 0:1 in the register */ |
387 | reg = TAS2552_PDM_CFG; | 430 | reg = TAS2552_PDM_CFG; |
431 | tas2552->pdm_clk_id = clk_id; | ||
388 | tas2552->pdm_clk = freq; | 432 | tas2552->pdm_clk = freq; |
389 | break; | 433 | break; |
390 | default: | 434 | default: |
@@ -509,9 +553,20 @@ static struct snd_soc_dai_driver tas2552_dai[] = { | |||
509 | */ | 553 | */ |
510 | static DECLARE_TLV_DB_SCALE(dac_tlv, -7, 100, 0); | 554 | static DECLARE_TLV_DB_SCALE(dac_tlv, -7, 100, 0); |
511 | 555 | ||
556 | static const char * const tas2552_din_source_select[] = { | ||
557 | "Muted", | ||
558 | "Left", | ||
559 | "Right", | ||
560 | "Left + Right average", | ||
561 | }; | ||
562 | static SOC_ENUM_SINGLE_DECL(tas2552_din_source_enum, | ||
563 | TAS2552_CFG_3, 3, | ||
564 | tas2552_din_source_select); | ||
565 | |||
512 | static const struct snd_kcontrol_new tas2552_snd_controls[] = { | 566 | static const struct snd_kcontrol_new tas2552_snd_controls[] = { |
513 | SOC_SINGLE_TLV("Speaker Driver Playback Volume", | 567 | SOC_SINGLE_TLV("Speaker Driver Playback Volume", |
514 | TAS2552_PGA_GAIN, 0, 0x1f, 0, dac_tlv), | 568 | TAS2552_PGA_GAIN, 0, 0x1f, 0, dac_tlv), |
569 | SOC_ENUM("DIN source", tas2552_din_source_enum), | ||
515 | }; | 570 | }; |
516 | 571 | ||
517 | static int tas2552_codec_probe(struct snd_soc_codec *codec) | 572 | static int tas2552_codec_probe(struct snd_soc_codec *codec) |
@@ -543,13 +598,14 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec) | |||
543 | snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE, TAS2552_MUTE); | 598 | snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE, TAS2552_MUTE); |
544 | snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL | | 599 | snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL | |
545 | TAS2552_DIN_SRC_SEL_AVG_L_R); | 600 | TAS2552_DIN_SRC_SEL_AVG_L_R); |
546 | snd_soc_write(codec, TAS2552_DOUT, TAS2552_PDM_DATA_I); | 601 | snd_soc_write(codec, TAS2552_OUTPUT_DATA, |
547 | snd_soc_write(codec, TAS2552_OUTPUT_DATA, TAS2552_PDM_DATA_V_I | 0x8); | 602 | TAS2552_PDM_DATA_SEL_V_I | |
548 | snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, TAS2552_APT_DELAY_200 | | 603 | TAS2552_R_DATA_OUT(TAS2552_DATA_OUT_V_DATA)); |
549 | TAS2552_APT_THRESH_2_1_7); | 604 | snd_soc_write(codec, TAS2552_BOOST_APT_CTRL, TAS2552_APT_DELAY_200 | |
605 | TAS2552_APT_THRESH_20_17); | ||
550 | 606 | ||
551 | snd_soc_write(codec, TAS2552_CFG_2, TAS2552_BOOST_EN | | 607 | snd_soc_write(codec, TAS2552_CFG_2, TAS2552_BOOST_EN | TAS2552_APT_EN | |
552 | TAS2552_APT_EN | TAS2552_LIM_EN); | 608 | TAS2552_LIM_EN); |
553 | 609 | ||
554 | return 0; | 610 | return 0; |
555 | 611 | ||
@@ -647,13 +703,10 @@ static int tas2552_probe(struct i2c_client *client, | |||
647 | if (data == NULL) | 703 | if (data == NULL) |
648 | return -ENOMEM; | 704 | return -ENOMEM; |
649 | 705 | ||
650 | data->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); | 706 | data->enable_gpio = devm_gpiod_get_optional(dev, "enable", |
651 | if (IS_ERR(data->enable_gpio)) { | 707 | GPIOD_OUT_LOW); |
652 | if (PTR_ERR(data->enable_gpio) == -EPROBE_DEFER) | 708 | if (IS_ERR(data->enable_gpio)) |
653 | return -EPROBE_DEFER; | 709 | return PTR_ERR(data->enable_gpio); |
654 | |||
655 | data->enable_gpio = NULL;; | ||
656 | } | ||
657 | 710 | ||
658 | data->tas2552_client = client; | 711 | data->tas2552_client = client; |
659 | data->regmap = devm_regmap_init_i2c(client, &tas2552_regmap_config); | 712 | data->regmap = devm_regmap_init_i2c(client, &tas2552_regmap_config); |
@@ -695,6 +748,7 @@ static int tas2552_probe(struct i2c_client *client, | |||
695 | static int tas2552_i2c_remove(struct i2c_client *client) | 748 | static int tas2552_i2c_remove(struct i2c_client *client) |
696 | { | 749 | { |
697 | snd_soc_unregister_codec(&client->dev); | 750 | snd_soc_unregister_codec(&client->dev); |
751 | pm_runtime_disable(&client->dev); | ||
698 | return 0; | 752 | return 0; |
699 | } | 753 | } |
700 | 754 | ||
diff --git a/sound/soc/codecs/tas2552.h b/sound/soc/codecs/tas2552.h index bbb820495516..5746f8fd0afd 100644 --- a/sound/soc/codecs/tas2552.h +++ b/sound/soc/codecs/tas2552.h | |||
@@ -19,7 +19,7 @@ | |||
19 | #define __TAS2552_H__ | 19 | #define __TAS2552_H__ |
20 | 20 | ||
21 | /* Register Address Map */ | 21 | /* Register Address Map */ |
22 | #define TAS2552_DEVICE_STATUS 0x00 | 22 | #define TAS2552_DEVICE_STATUS 0x00 |
23 | #define TAS2552_CFG_1 0x01 | 23 | #define TAS2552_CFG_1 0x01 |
24 | #define TAS2552_CFG_2 0x02 | 24 | #define TAS2552_CFG_2 0x02 |
25 | #define TAS2552_CFG_3 0x03 | 25 | #define TAS2552_CFG_3 0x03 |
@@ -33,13 +33,13 @@ | |||
33 | #define TAS2552_BTIP 0x0b | 33 | #define TAS2552_BTIP 0x0b |
34 | #define TAS2552_BTS_CTRL 0x0c | 34 | #define TAS2552_BTS_CTRL 0x0c |
35 | #define TAS2552_RESERVED_0D 0x0d | 35 | #define TAS2552_RESERVED_0D 0x0d |
36 | #define TAS2552_LIMIT_RATE_HYS 0x0e | 36 | #define TAS2552_LIMIT_RATE_HYS 0x0e |
37 | #define TAS2552_LIMIT_RELEASE 0x0f | 37 | #define TAS2552_LIMIT_RELEASE 0x0f |
38 | #define TAS2552_LIMIT_INT_COUNT 0x10 | 38 | #define TAS2552_LIMIT_INT_COUNT 0x10 |
39 | #define TAS2552_PDM_CFG 0x11 | 39 | #define TAS2552_PDM_CFG 0x11 |
40 | #define TAS2552_PGA_GAIN 0x12 | 40 | #define TAS2552_PGA_GAIN 0x12 |
41 | #define TAS2552_EDGE_RATE_CTRL 0x13 | 41 | #define TAS2552_EDGE_RATE_CTRL 0x13 |
42 | #define TAS2552_BOOST_PT_CTRL 0x14 | 42 | #define TAS2552_BOOST_APT_CTRL 0x14 |
43 | #define TAS2552_VER_NUM 0x16 | 43 | #define TAS2552_VER_NUM 0x16 |
44 | #define TAS2552_VBAT_DATA 0x19 | 44 | #define TAS2552_VBAT_DATA 0x19 |
45 | #define TAS2552_MAX_REG 0x20 | 45 | #define TAS2552_MAX_REG 0x20 |
@@ -103,10 +103,21 @@ | |||
103 | #define TAS2552_WCLKDIR (1 << 7) | 103 | #define TAS2552_WCLKDIR (1 << 7) |
104 | 104 | ||
105 | /* OUTPUT_DATA register */ | 105 | /* OUTPUT_DATA register */ |
106 | #define TAS2552_PDM_DATA_I 0x00 | 106 | #define TAS2552_DATA_OUT_I_DATA (0x0) |
107 | #define TAS2552_PDM_DATA_V (1 << 6) | 107 | #define TAS2552_DATA_OUT_V_DATA (0x1) |
108 | #define TAS2552_PDM_DATA_I_V (1 << 7) | 108 | #define TAS2552_DATA_OUT_VBAT_DATA (0x2) |
109 | #define TAS2552_PDM_DATA_V_I (0x11 << 6) | 109 | #define TAS2552_DATA_OUT_VBOOST_DATA (0x3) |
110 | #define TAS2552_DATA_OUT_PGA_GAIN (0x4) | ||
111 | #define TAS2552_DATA_OUT_IV_DATA (0x5) | ||
112 | #define TAS2552_DATA_OUT_VBAT_VBOOST_GAIN (0x6) | ||
113 | #define TAS2552_DATA_OUT_DISABLED (0x7) | ||
114 | #define TAS2552_L_DATA_OUT(x) ((x) << 0) | ||
115 | #define TAS2552_R_DATA_OUT(x) ((x) << 3) | ||
116 | #define TAS2552_PDM_DATA_SEL_I (0x0 << 6) | ||
117 | #define TAS2552_PDM_DATA_SEL_V (0x1 << 6) | ||
118 | #define TAS2552_PDM_DATA_SEL_I_V (0x2 << 6) | ||
119 | #define TAS2552_PDM_DATA_SEL_V_I (0x3 << 6) | ||
120 | #define TAS2552_PDM_DATA_SEL_MASK TAS2552_PDM_DATA_SEL_V_I | ||
110 | 121 | ||
111 | /* PDM CFG Register */ | 122 | /* PDM CFG Register */ |
112 | #define TAS2552_PDM_CLK_SEL_PLL (0x0 << 0) | 123 | #define TAS2552_PDM_CLK_SEL_PLL (0x0 << 0) |
@@ -116,24 +127,20 @@ | |||
116 | #define TAS2552_PDM_CLK_SEL_MASK TAS2552_PDM_CLK_SEL_MCLK | 127 | #define TAS2552_PDM_CLK_SEL_MASK TAS2552_PDM_CLK_SEL_MCLK |
117 | #define TAS2552_PDM_DATA_ES (1 << 2) | 128 | #define TAS2552_PDM_DATA_ES (1 << 2) |
118 | 129 | ||
119 | /* Boost pass-through register */ | 130 | /* Boost Auto-pass through register */ |
120 | #define TAS2552_APT_DELAY_50 0x00 | 131 | #define TAS2552_APT_DELAY_50 (0x0 << 0) |
121 | #define TAS2552_APT_DELAY_75 (1 << 1) | 132 | #define TAS2552_APT_DELAY_75 (0x1 << 0) |
122 | #define TAS2552_APT_DELAY_125 (1 << 2) | 133 | #define TAS2552_APT_DELAY_125 (0x2 << 0) |
123 | #define TAS2552_APT_DELAY_200 (1 << 3) | 134 | #define TAS2552_APT_DELAY_200 (0x3 << 0) |
124 | 135 | #define TAS2552_APT_THRESH_05_02 (0x0 << 2) | |
125 | #define TAS2552_APT_THRESH_2_5 0x00 | 136 | #define TAS2552_APT_THRESH_10_07 (0x1 << 2) |
126 | #define TAS2552_APT_THRESH_1_7 (1 << 3) | 137 | #define TAS2552_APT_THRESH_14_11 (0x2 << 2) |
127 | #define TAS2552_APT_THRESH_1_4_1_1 (1 << 4) | 138 | #define TAS2552_APT_THRESH_20_17 (0x3 << 2) |
128 | #define TAS2552_APT_THRESH_2_1_7 (0x11 << 2) | ||
129 | 139 | ||
130 | /* PLL Control Register */ | 140 | /* PLL Control Register */ |
131 | #define TAS2552_245MHZ_CLK 24576000 | 141 | #define TAS2552_PLL_J_MASK 0x7f |
132 | #define TAS2552_225MHZ_CLK 22579200 | 142 | #define TAS2552_PLL_D_UPPER(x) (((x) >> 8) & 0x3f) |
133 | #define TAS2552_PLL_J_MASK 0x7f | 143 | #define TAS2552_PLL_D_LOWER(x) ((x) & 0xff) |
134 | #define TAS2552_PLL_D_UPPER_MASK 0x3f | 144 | #define TAS2552_PLL_BYPASS (1 << 7) |
135 | #define TAS2552_PLL_D_LOWER_MASK 0xff | ||
136 | #define TAS2552_PLL_BYPASS_MASK 0x80 | ||
137 | #define TAS2552_PLL_BYPASS 0x80 | ||
138 | 145 | ||
139 | #endif | 146 | #endif |