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authorAlexander Müller <serveralex@gmail.com>2016-08-27 13:40:54 -0400
committerMichael Turquette <mturquette@baylibre.com>2016-09-01 20:43:12 -0400
commite31a1900c1ff73d669408fc3243afb5c55863139 (patch)
treeea26b4b9a18151961ee49a64f1fc449a6f0120ac
parent7ba64d82b35890afa40e7cd6837e657b6185b389 (diff)
meson: clk: Add support for clock gates
This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other components. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-7-git-send-email-serveralex@gmail.com
Diffstat
-rw-r--r--drivers/clk/meson/meson8b.c249
-rw-r--r--drivers/clk/meson/meson8b.h5
2 files changed, 254 insertions, 0 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index f815d40149f7..e1d4aa145a03 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -313,6 +313,92 @@ struct clk_gate meson8b_clk81 = {
313 }, 313 },
314}; 314};
315 315
316/* Everything Else (EE) domain gates */
317
318static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
319static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
320static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
321static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
322static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
323static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
324static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
325static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
326static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
327static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
328static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
329static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
330static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
331static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
332static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
333static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
334static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
335static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
336static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
337
338static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
339static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
340static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
341static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
342static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
343static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
344static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
345static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
346static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
347static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
348static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
349static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
350static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
351static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
352static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
353static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
354static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
355static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
356static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
357static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
358static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
359static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
360static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
361static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
362static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
363
364static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
365static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
366static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
367static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
368static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
369static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
370static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
371static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
372static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
373static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
374static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
375static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
376static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
377
378static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
379static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
380static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
381static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
382static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
383static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
384static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
385static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
386static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
387static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
388static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
389static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
390static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
391static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
392static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
393static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
394
395/* Always On (AO) domain gates */
396
397static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
398static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
399static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
400static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
401
316static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 402static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
317 .hws = { 403 .hws = {
318 [CLKID_XTAL] = &meson8b_xtal.hw, 404 [CLKID_XTAL] = &meson8b_xtal.hw,
@@ -328,6 +414,83 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
328 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw, 414 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
329 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw, 415 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
330 [CLKID_CLK81] = &meson8b_clk81.hw, 416 [CLKID_CLK81] = &meson8b_clk81.hw,
417 [CLKID_DDR] = &meson8b_ddr.hw,
418 [CLKID_DOS] = &meson8b_dos.hw,
419 [CLKID_ISA] = &meson8b_isa.hw,
420 [CLKID_PL301] = &meson8b_pl301.hw,
421 [CLKID_PERIPHS] = &meson8b_periphs.hw,
422 [CLKID_SPICC] = &meson8b_spicc.hw,
423 [CLKID_I2C] = &meson8b_i2c.hw,
424 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
425 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
426 [CLKID_RNG0] = &meson8b_rng0.hw,
427 [CLKID_UART0] = &meson8b_uart0.hw,
428 [CLKID_SDHC] = &meson8b_sdhc.hw,
429 [CLKID_STREAM] = &meson8b_stream.hw,
430 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
431 [CLKID_SDIO] = &meson8b_sdio.hw,
432 [CLKID_ABUF] = &meson8b_abuf.hw,
433 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
434 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
435 [CLKID_SPI] = &meson8b_spi.hw,
436 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
437 [CLKID_ETH] = &meson8b_eth.hw,
438 [CLKID_DEMUX] = &meson8b_demux.hw,
439 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
440 [CLKID_IEC958] = &meson8b_iec958.hw,
441 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
442 [CLKID_AMCLK] = &meson8b_amclk.hw,
443 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
444 [CLKID_MIXER] = &meson8b_mixer.hw,
445 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
446 [CLKID_ADC] = &meson8b_adc.hw,
447 [CLKID_BLKMV] = &meson8b_blkmv.hw,
448 [CLKID_AIU] = &meson8b_aiu.hw,
449 [CLKID_UART1] = &meson8b_uart1.hw,
450 [CLKID_G2D] = &meson8b_g2d.hw,
451 [CLKID_USB0] = &meson8b_usb0.hw,
452 [CLKID_USB1] = &meson8b_usb1.hw,
453 [CLKID_RESET] = &meson8b_reset.hw,
454 [CLKID_NAND] = &meson8b_nand.hw,
455 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
456 [CLKID_USB] = &meson8b_usb.hw,
457 [CLKID_VDIN1] = &meson8b_vdin1.hw,
458 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
459 [CLKID_EFUSE] = &meson8b_efuse.hw,
460 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
461 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
462 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
463 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
464 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
465 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
466 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
467 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
468 [CLKID_DVIN] = &meson8b_dvin.hw,
469 [CLKID_UART2] = &meson8b_uart2.hw,
470 [CLKID_SANA] = &meson8b_sana.hw,
471 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
472 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
473 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
474 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
475 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
476 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
477 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
478 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
479 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw,
480 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
481 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
482 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
483 [CLKID_ENC480P] = &meson8b_enc480p.hw,
484 [CLKID_RNG1] = &meson8b_rng1.hw,
485 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
486 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
487 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
488 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
489 [CLKID_EDP] = &meson8b_edp.hw,
490 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
491 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
492 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
493 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
331 }, 494 },
332 .num = CLK_NR_CLKS, 495 .num = CLK_NR_CLKS,
333}; 496};
@@ -338,6 +501,87 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
338 &meson8b_sys_pll, 501 &meson8b_sys_pll,
339}; 502};
340 503
504static struct clk_gate *meson8b_clk_gates[] = {
505 &meson8b_clk81,
506 &meson8b_ddr,
507 &meson8b_dos,
508 &meson8b_isa,
509 &meson8b_pl301,
510 &meson8b_periphs,
511 &meson8b_spicc,
512 &meson8b_i2c,
513 &meson8b_sar_adc,
514 &meson8b_smart_card,
515 &meson8b_rng0,
516 &meson8b_uart0,
517 &meson8b_sdhc,
518 &meson8b_stream,
519 &meson8b_async_fifo,
520 &meson8b_sdio,
521 &meson8b_abuf,
522 &meson8b_hiu_iface,
523 &meson8b_assist_misc,
524 &meson8b_spi,
525 &meson8b_i2s_spdif,
526 &meson8b_eth,
527 &meson8b_demux,
528 &meson8b_aiu_glue,
529 &meson8b_iec958,
530 &meson8b_i2s_out,
531 &meson8b_amclk,
532 &meson8b_aififo2,
533 &meson8b_mixer,
534 &meson8b_mixer_iface,
535 &meson8b_adc,
536 &meson8b_blkmv,
537 &meson8b_aiu,
538 &meson8b_uart1,
539 &meson8b_g2d,
540 &meson8b_usb0,
541 &meson8b_usb1,
542 &meson8b_reset,
543 &meson8b_nand,
544 &meson8b_dos_parser,
545 &meson8b_usb,
546 &meson8b_vdin1,
547 &meson8b_ahb_arb0,
548 &meson8b_efuse,
549 &meson8b_boot_rom,
550 &meson8b_ahb_data_bus,
551 &meson8b_ahb_ctrl_bus,
552 &meson8b_hdmi_intr_sync,
553 &meson8b_hdmi_pclk,
554 &meson8b_usb1_ddr_bridge,
555 &meson8b_usb0_ddr_bridge,
556 &meson8b_mmc_pclk,
557 &meson8b_dvin,
558 &meson8b_uart2,
559 &meson8b_sana,
560 &meson8b_vpu_intr,
561 &meson8b_sec_ahb_ahb3_bridge,
562 &meson8b_clk81_a9,
563 &meson8b_vclk2_venci0,
564 &meson8b_vclk2_venci1,
565 &meson8b_vclk2_vencp0,
566 &meson8b_vclk2_vencp1,
567 &meson8b_gclk_venci_int,
568 &meson8b_gclk_vencp_int,
569 &meson8b_dac_clk,
570 &meson8b_aoclk_gate,
571 &meson8b_iec958_gate,
572 &meson8b_enc480p,
573 &meson8b_rng1,
574 &meson8b_gclk_vencl_int,
575 &meson8b_vclk2_venclmcc,
576 &meson8b_vclk2_vencl,
577 &meson8b_vclk2_other,
578 &meson8b_edp,
579 &meson8b_ao_media_cpu,
580 &meson8b_ao_ahb_sram,
581 &meson8b_ao_ahb_bus,
582 &meson8b_ao_iface,
583};
584
341static int meson8b_clkc_probe(struct platform_device *pdev) 585static int meson8b_clkc_probe(struct platform_device *pdev)
342{ 586{
343 void __iomem *clk_base; 587 void __iomem *clk_base;
@@ -365,6 +609,11 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
365 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; 609 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
366 meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg; 610 meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
367 611
612 /* Populate base address for gates */
613 for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
614 meson8b_clk_gates[i]->reg = clk_base +
615 (u32)meson8b_clk_gates[i]->reg;
616
368 /* 617 /*
369 * register all clks 618 * register all clks
370 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 619 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 86efe6a9c658..010e9582888d 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -30,6 +30,11 @@
30 * 30 *
31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 31 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
32 */ 32 */
33#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
34#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
35#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
36#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
37#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
33#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ 38#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
34#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ 39#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
35#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 40#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-25 02:15:00 -0400