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authorVaradarajan Narayanan <varada@codeaurora.org>2015-11-19 18:19:28 -0500
committerLinus Walleij <linus.walleij@linaro.org>2016-02-16 09:52:21 -0500
commite260d2bbc97e64bdc9e3d36b5828556b0490277b (patch)
tree7cb3f96c9fc8e65f38104026b53c59ec360cd301
parent740f5b08d48956fa9644f2048081f129058e205a (diff)
pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support
Add pinctrl driver support for IPQ4019 platform Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> [Dropped .owner assignment] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt74
-rw-r--r--drivers/pinctrl/qcom/Kconfig8
-rw-r--r--drivers/pinctrl/qcom/Makefile1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq4019.c453
4 files changed, 536 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
new file mode 100644
index 000000000000..cfb8500dd56b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
@@ -0,0 +1,74 @@
1Qualcomm Atheros IPQ4019 TLMM block
2
3This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
4platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
5
6Required properties:
7- compatible: "qcom,ipq4019-pinctrl"
8- reg: Should be the base address and length of the TLMM block.
9- interrupts: Should be the parent IRQ of the TLMM block.
10- interrupt-controller: Marks the device node as an interrupt controller.
11- #interrupt-cells: Should be two.
12- gpio-controller: Marks the device node as a GPIO controller.
13- #gpio-cells : Should be two.
14 The first cell is the gpio pin number and the
15 second cell is used for optional parameters.
16
17Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
18a general description of GPIO and interrupt bindings.
19
20Please refer to pinctrl-bindings.txt in this directory for details of the
21common pinctrl bindings used by client devices, including the meaning of the
22phrase "pin configuration node".
23
24The pin configuration nodes act as a container for an abitrary number of
25subnodes. Each of these subnodes represents some desired configuration for a
26pin, a group, or a list of pins or groups. This configuration can include the
27mux function to select on those pin(s)/group(s), and various pin configuration
28parameters, such as pull-up, drive strength, etc.
29
30The name of each subnode is not important; all subnodes should be enumerated
31and processed purely based on their content.
32
33Each subnode only affects those parameters that are explicitly listed. In
34other words, a subnode that lists a mux function but no pin configuration
35parameters implies no information about any pin configuration parameters.
36Similarly, a pin subnode that describes a pullup parameter implies no
37information about e.g. the mux function.
38
39
40The following generic properties as defined in pinctrl-bindings.txt are valid
41to specify in a pin configuration subnode:
42 pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
43
44Non-empty subnodes must specify the 'pins' property.
45Note that not all properties are valid for all pins.
46
47
48Valid values for qcom,pins are:
49 gpio0-gpio99
50 Supports mux, bias and drive-strength
51
52Valid values for qcom,function are:
53gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
54
55Example:
56
57 tlmm: pinctrl@1000000 {
58 compatible = "qcom,ipq4019-pinctrl";
59 reg = <0x1000000 0x300000>;
60
61 gpio-controller;
62 #gpio-cells = <2>;
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 interrupts = <0 208 0>;
66
67 serial_pins: serial_pinmux {
68 mux {
69 pins = "gpio60", "gpio61";
70 function = "blsp_uart0";
71 bias-disable;
72 };
73 };
74 };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index eeac8cba8a21..67bc70dcda64 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -23,6 +23,14 @@ config PINCTRL_APQ8084
23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
24 Qualcomm TLMM block found in the Qualcomm APQ8084 platform. 24 Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
25 25
26config PINCTRL_IPQ4019
27 tristate "Qualcomm IPQ4019 pin controller driver"
28 depends on GPIOLIB && OF
29 select PINCTRL_MSM
30 help
31 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
32 Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
33
26config PINCTRL_IPQ8064 34config PINCTRL_IPQ8064
27 tristate "Qualcomm IPQ8064 pin controller driver" 35 tristate "Qualcomm IPQ8064 pin controller driver"
28 depends on GPIOLIB && OF 36 depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index dfb50a9fe04a..c964a2c4b90a 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -2,6 +2,7 @@
2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o 2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o 3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
4obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o 4obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
5obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
5obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o 6obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
6obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o 7obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
7obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o 8obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
new file mode 100644
index 000000000000..b5d81ced6ce6
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -0,0 +1,453 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-msm.h"
20
21static const struct pinctrl_pin_desc ipq4019_pins[] = {
22 PINCTRL_PIN(0, "GPIO_0"),
23 PINCTRL_PIN(1, "GPIO_1"),
24 PINCTRL_PIN(2, "GPIO_2"),
25 PINCTRL_PIN(3, "GPIO_3"),
26 PINCTRL_PIN(4, "GPIO_4"),
27 PINCTRL_PIN(5, "GPIO_5"),
28 PINCTRL_PIN(6, "GPIO_6"),
29 PINCTRL_PIN(7, "GPIO_7"),
30 PINCTRL_PIN(8, "GPIO_8"),
31 PINCTRL_PIN(9, "GPIO_9"),
32 PINCTRL_PIN(10, "GPIO_10"),
33 PINCTRL_PIN(11, "GPIO_11"),
34 PINCTRL_PIN(12, "GPIO_12"),
35 PINCTRL_PIN(13, "GPIO_13"),
36 PINCTRL_PIN(14, "GPIO_14"),
37 PINCTRL_PIN(15, "GPIO_15"),
38 PINCTRL_PIN(16, "GPIO_16"),
39 PINCTRL_PIN(17, "GPIO_17"),
40 PINCTRL_PIN(18, "GPIO_18"),
41 PINCTRL_PIN(19, "GPIO_19"),
42 PINCTRL_PIN(20, "GPIO_20"),
43 PINCTRL_PIN(21, "GPIO_21"),
44 PINCTRL_PIN(22, "GPIO_22"),
45 PINCTRL_PIN(23, "GPIO_23"),
46 PINCTRL_PIN(24, "GPIO_24"),
47 PINCTRL_PIN(25, "GPIO_25"),
48 PINCTRL_PIN(26, "GPIO_26"),
49 PINCTRL_PIN(27, "GPIO_27"),
50 PINCTRL_PIN(28, "GPIO_28"),
51 PINCTRL_PIN(29, "GPIO_29"),
52 PINCTRL_PIN(30, "GPIO_30"),
53 PINCTRL_PIN(31, "GPIO_31"),
54 PINCTRL_PIN(32, "GPIO_32"),
55 PINCTRL_PIN(33, "GPIO_33"),
56 PINCTRL_PIN(34, "GPIO_34"),
57 PINCTRL_PIN(35, "GPIO_35"),
58 PINCTRL_PIN(36, "GPIO_36"),
59 PINCTRL_PIN(37, "GPIO_37"),
60 PINCTRL_PIN(38, "GPIO_38"),
61 PINCTRL_PIN(39, "GPIO_39"),
62 PINCTRL_PIN(40, "GPIO_40"),
63 PINCTRL_PIN(41, "GPIO_41"),
64 PINCTRL_PIN(42, "GPIO_42"),
65 PINCTRL_PIN(43, "GPIO_43"),
66 PINCTRL_PIN(44, "GPIO_44"),
67 PINCTRL_PIN(45, "GPIO_45"),
68 PINCTRL_PIN(46, "GPIO_46"),
69 PINCTRL_PIN(47, "GPIO_47"),
70 PINCTRL_PIN(48, "GPIO_48"),
71 PINCTRL_PIN(49, "GPIO_49"),
72 PINCTRL_PIN(50, "GPIO_50"),
73 PINCTRL_PIN(51, "GPIO_51"),
74 PINCTRL_PIN(52, "GPIO_52"),
75 PINCTRL_PIN(53, "GPIO_53"),
76 PINCTRL_PIN(54, "GPIO_54"),
77 PINCTRL_PIN(55, "GPIO_55"),
78 PINCTRL_PIN(56, "GPIO_56"),
79 PINCTRL_PIN(57, "GPIO_57"),
80 PINCTRL_PIN(58, "GPIO_58"),
81 PINCTRL_PIN(59, "GPIO_59"),
82 PINCTRL_PIN(60, "GPIO_60"),
83 PINCTRL_PIN(61, "GPIO_61"),
84 PINCTRL_PIN(62, "GPIO_62"),
85 PINCTRL_PIN(63, "GPIO_63"),
86 PINCTRL_PIN(64, "GPIO_64"),
87 PINCTRL_PIN(65, "GPIO_65"),
88 PINCTRL_PIN(66, "GPIO_66"),
89 PINCTRL_PIN(67, "GPIO_67"),
90 PINCTRL_PIN(68, "GPIO_68"),
91 PINCTRL_PIN(69, "GPIO_69"),
92 PINCTRL_PIN(70, "GPIO_70"),
93 PINCTRL_PIN(71, "GPIO_71"),
94 PINCTRL_PIN(72, "GPIO_72"),
95 PINCTRL_PIN(73, "GPIO_73"),
96 PINCTRL_PIN(74, "GPIO_74"),
97 PINCTRL_PIN(75, "GPIO_75"),
98 PINCTRL_PIN(76, "GPIO_76"),
99 PINCTRL_PIN(77, "GPIO_77"),
100 PINCTRL_PIN(78, "GPIO_78"),
101 PINCTRL_PIN(79, "GPIO_79"),
102 PINCTRL_PIN(80, "GPIO_80"),
103 PINCTRL_PIN(81, "GPIO_81"),
104 PINCTRL_PIN(82, "GPIO_82"),
105 PINCTRL_PIN(83, "GPIO_83"),
106 PINCTRL_PIN(84, "GPIO_84"),
107 PINCTRL_PIN(85, "GPIO_85"),
108 PINCTRL_PIN(86, "GPIO_86"),
109 PINCTRL_PIN(87, "GPIO_87"),
110 PINCTRL_PIN(88, "GPIO_88"),
111 PINCTRL_PIN(89, "GPIO_89"),
112 PINCTRL_PIN(90, "GPIO_90"),
113 PINCTRL_PIN(91, "GPIO_91"),
114 PINCTRL_PIN(92, "GPIO_92"),
115 PINCTRL_PIN(93, "GPIO_93"),
116 PINCTRL_PIN(94, "GPIO_94"),
117 PINCTRL_PIN(95, "GPIO_95"),
118 PINCTRL_PIN(96, "GPIO_96"),
119 PINCTRL_PIN(97, "GPIO_97"),
120 PINCTRL_PIN(98, "GPIO_98"),
121 PINCTRL_PIN(99, "GPIO_99"),
122};
123
124#define DECLARE_QCA_GPIO_PINS(pin) \
125 static const unsigned int gpio##pin##_pins[] = { pin }
126DECLARE_QCA_GPIO_PINS(0);
127DECLARE_QCA_GPIO_PINS(1);
128DECLARE_QCA_GPIO_PINS(2);
129DECLARE_QCA_GPIO_PINS(3);
130DECLARE_QCA_GPIO_PINS(4);
131DECLARE_QCA_GPIO_PINS(5);
132DECLARE_QCA_GPIO_PINS(6);
133DECLARE_QCA_GPIO_PINS(7);
134DECLARE_QCA_GPIO_PINS(8);
135DECLARE_QCA_GPIO_PINS(9);
136DECLARE_QCA_GPIO_PINS(10);
137DECLARE_QCA_GPIO_PINS(11);
138DECLARE_QCA_GPIO_PINS(12);
139DECLARE_QCA_GPIO_PINS(13);
140DECLARE_QCA_GPIO_PINS(14);
141DECLARE_QCA_GPIO_PINS(15);
142DECLARE_QCA_GPIO_PINS(16);
143DECLARE_QCA_GPIO_PINS(17);
144DECLARE_QCA_GPIO_PINS(18);
145DECLARE_QCA_GPIO_PINS(19);
146DECLARE_QCA_GPIO_PINS(20);
147DECLARE_QCA_GPIO_PINS(21);
148DECLARE_QCA_GPIO_PINS(22);
149DECLARE_QCA_GPIO_PINS(23);
150DECLARE_QCA_GPIO_PINS(24);
151DECLARE_QCA_GPIO_PINS(25);
152DECLARE_QCA_GPIO_PINS(26);
153DECLARE_QCA_GPIO_PINS(27);
154DECLARE_QCA_GPIO_PINS(28);
155DECLARE_QCA_GPIO_PINS(29);
156DECLARE_QCA_GPIO_PINS(30);
157DECLARE_QCA_GPIO_PINS(31);
158DECLARE_QCA_GPIO_PINS(32);
159DECLARE_QCA_GPIO_PINS(33);
160DECLARE_QCA_GPIO_PINS(34);
161DECLARE_QCA_GPIO_PINS(35);
162DECLARE_QCA_GPIO_PINS(36);
163DECLARE_QCA_GPIO_PINS(37);
164DECLARE_QCA_GPIO_PINS(38);
165DECLARE_QCA_GPIO_PINS(39);
166DECLARE_QCA_GPIO_PINS(40);
167DECLARE_QCA_GPIO_PINS(41);
168DECLARE_QCA_GPIO_PINS(42);
169DECLARE_QCA_GPIO_PINS(43);
170DECLARE_QCA_GPIO_PINS(44);
171DECLARE_QCA_GPIO_PINS(45);
172DECLARE_QCA_GPIO_PINS(46);
173DECLARE_QCA_GPIO_PINS(47);
174DECLARE_QCA_GPIO_PINS(48);
175DECLARE_QCA_GPIO_PINS(49);
176DECLARE_QCA_GPIO_PINS(50);
177DECLARE_QCA_GPIO_PINS(51);
178DECLARE_QCA_GPIO_PINS(52);
179DECLARE_QCA_GPIO_PINS(53);
180DECLARE_QCA_GPIO_PINS(54);
181DECLARE_QCA_GPIO_PINS(55);
182DECLARE_QCA_GPIO_PINS(56);
183DECLARE_QCA_GPIO_PINS(57);
184DECLARE_QCA_GPIO_PINS(58);
185DECLARE_QCA_GPIO_PINS(59);
186DECLARE_QCA_GPIO_PINS(60);
187DECLARE_QCA_GPIO_PINS(61);
188DECLARE_QCA_GPIO_PINS(62);
189DECLARE_QCA_GPIO_PINS(63);
190DECLARE_QCA_GPIO_PINS(64);
191DECLARE_QCA_GPIO_PINS(65);
192DECLARE_QCA_GPIO_PINS(66);
193DECLARE_QCA_GPIO_PINS(67);
194DECLARE_QCA_GPIO_PINS(68);
195DECLARE_QCA_GPIO_PINS(69);
196DECLARE_QCA_GPIO_PINS(70);
197DECLARE_QCA_GPIO_PINS(71);
198DECLARE_QCA_GPIO_PINS(72);
199DECLARE_QCA_GPIO_PINS(73);
200DECLARE_QCA_GPIO_PINS(74);
201DECLARE_QCA_GPIO_PINS(75);
202DECLARE_QCA_GPIO_PINS(76);
203DECLARE_QCA_GPIO_PINS(77);
204DECLARE_QCA_GPIO_PINS(78);
205DECLARE_QCA_GPIO_PINS(79);
206DECLARE_QCA_GPIO_PINS(80);
207DECLARE_QCA_GPIO_PINS(81);
208DECLARE_QCA_GPIO_PINS(82);
209DECLARE_QCA_GPIO_PINS(83);
210DECLARE_QCA_GPIO_PINS(84);
211DECLARE_QCA_GPIO_PINS(85);
212DECLARE_QCA_GPIO_PINS(86);
213DECLARE_QCA_GPIO_PINS(87);
214DECLARE_QCA_GPIO_PINS(88);
215DECLARE_QCA_GPIO_PINS(89);
216DECLARE_QCA_GPIO_PINS(90);
217DECLARE_QCA_GPIO_PINS(91);
218DECLARE_QCA_GPIO_PINS(92);
219DECLARE_QCA_GPIO_PINS(93);
220DECLARE_QCA_GPIO_PINS(94);
221DECLARE_QCA_GPIO_PINS(95);
222DECLARE_QCA_GPIO_PINS(96);
223DECLARE_QCA_GPIO_PINS(97);
224DECLARE_QCA_GPIO_PINS(98);
225DECLARE_QCA_GPIO_PINS(99);
226
227#define FUNCTION(fname) \
228 [qca_mux_##fname] = { \
229 .name = #fname, \
230 .groups = fname##_groups, \
231 .ngroups = ARRAY_SIZE(fname##_groups), \
232 }
233
234#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \
235 { \
236 .name = "gpio" #id, \
237 .pins = gpio##id##_pins, \
238 .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
239 .funcs = (int[]){ \
240 qca_mux_NA, /* gpio mode */ \
241 qca_mux_##f1, \
242 qca_mux_##f2, \
243 qca_mux_##f3, \
244 qca_mux_##f4, \
245 qca_mux_##f5, \
246 qca_mux_##f6, \
247 qca_mux_##f7, \
248 qca_mux_##f8, \
249 qca_mux_##f9, \
250 qca_mux_##f10, \
251 qca_mux_##f11, \
252 qca_mux_##f12, \
253 qca_mux_##f13, \
254 qca_mux_##f14 \
255 }, \
256 .nfuncs = 15, \
257 .ctl_reg = 0x1000 + 0x10 * id, \
258 .io_reg = 0x1004 + 0x10 * id, \
259 .intr_cfg_reg = 0x1008 + 0x10 * id, \
260 .intr_status_reg = 0x100c + 0x10 * id, \
261 .intr_target_reg = 0x400 + 0x4 * id, \
262 .mux_bit = 2, \
263 .pull_bit = 0, \
264 .drv_bit = 6, \
265 .oe_bit = 9, \
266 .in_bit = 0, \
267 .out_bit = 1, \
268 .intr_enable_bit = 0, \
269 .intr_status_bit = 0, \
270 .intr_target_bit = 5, \
271 .intr_raw_status_bit = 4, \
272 .intr_polarity_bit = 1, \
273 .intr_detection_bit = 2, \
274 .intr_detection_width = 2, \
275 }
276
277
278enum ipq4019_functions {
279 qca_mux_gpio,
280 qca_mux_blsp_uart1,
281 qca_mux_blsp_i2c0,
282 qca_mux_blsp_i2c1,
283 qca_mux_blsp_uart0,
284 qca_mux_blsp_spi1,
285 qca_mux_blsp_spi0,
286 qca_mux_NA,
287};
288
289static const char * const gpio_groups[] = {
290 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
291 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
292 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
293 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
294 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
295 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
296 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
297 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
298 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
299 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
300 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
301 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
302 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
303 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
304 "gpio99",
305};
306
307static const char * const blsp_uart1_groups[] = {
308 "gpio8", "gpio9", "gpio10", "gpio11",
309};
310static const char * const blsp_i2c0_groups[] = {
311 "gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
312};
313static const char * const blsp_spi0_groups[] = {
314 "gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
315 "gpio54", "gpio55", "gpio56", "gpio57",
316};
317static const char * const blsp_i2c1_groups[] = {
318 "gpio12", "gpio13", "gpio34", "gpio35",
319};
320static const char * const blsp_uart0_groups[] = {
321 "gpio16", "gpio17", "gpio60", "gpio61",
322};
323static const char * const blsp_spi1_groups[] = {
324 "gpio44", "gpio45", "gpio46", "gpio47",
325};
326
327static const struct msm_function ipq4019_functions[] = {
328 FUNCTION(gpio),
329 FUNCTION(blsp_uart1),
330 FUNCTION(blsp_i2c0),
331 FUNCTION(blsp_i2c1),
332 FUNCTION(blsp_uart0),
333 FUNCTION(blsp_spi1),
334 FUNCTION(blsp_spi0),
335};
336
337static const struct msm_pingroup ipq4019_groups[] = {
338 PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
339 PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
340 PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
341 PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
342 PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
343 PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
344 PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
345 PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
346 PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
347 PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
348 PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
349 PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
350 PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
351 PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
352 PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
353 PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
354 PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
355 PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
356 PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
357 PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
358 PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
359 PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
360 PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
361 PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
362 PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
363 PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
364 PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
365 PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
366 PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
367 PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
368 PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
369 PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
370 PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
371 PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
372 PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
373 PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
374 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
375 PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
376 PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
377 PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
378 PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
379 PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
380 PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
381 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
382 PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
383 PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
384 PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
385 PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
386 PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
387 PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
388 PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
389 PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
390 PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
391 PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
392 PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
393 PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
394 PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
395 PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
396 PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
397 PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
398 PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
399 PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
400 PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
401 PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
402 PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
403 PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
404 PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
405 PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
406 PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
407 PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
408};
409
410static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
411 .pins = ipq4019_pins,
412 .npins = ARRAY_SIZE(ipq4019_pins),
413 .functions = ipq4019_functions,
414 .nfunctions = ARRAY_SIZE(ipq4019_functions),
415 .groups = ipq4019_groups,
416 .ngroups = ARRAY_SIZE(ipq4019_groups),
417 .ngpios = 70,
418};
419
420static int ipq4019_pinctrl_probe(struct platform_device *pdev)
421{
422 return msm_pinctrl_probe(pdev, &ipq4019_pinctrl);
423}
424
425static const struct of_device_id ipq4019_pinctrl_of_match[] = {
426 { .compatible = "qcom,ipq4019-pinctrl", },
427 { },
428};
429
430static struct platform_driver ipq4019_pinctrl_driver = {
431 .driver = {
432 .name = "ipq4019-pinctrl",
433 .of_match_table = ipq4019_pinctrl_of_match,
434 },
435 .probe = ipq4019_pinctrl_probe,
436 .remove = msm_pinctrl_remove,
437};
438
439static int __init ipq4019_pinctrl_init(void)
440{
441 return platform_driver_register(&ipq4019_pinctrl_driver);
442}
443arch_initcall(ipq4019_pinctrl_init);
444
445static void __exit ipq4019_pinctrl_exit(void)
446{
447 platform_driver_unregister(&ipq4019_pinctrl_driver);
448}
449module_exit(ipq4019_pinctrl_exit);
450
451MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver");
452MODULE_LICENSE("GPL v2");
453MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 07:04:24 -0400