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authorLikun Gao <Likun.Gao@amd.com>2018-07-10 08:26:41 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-09-14 10:35:21 -0400
commite21f561ad52a6c909c64d2856a3ad03a4042a5df (patch)
tree2cc36a7cf57e016a5daf5533f0dbe3b076141501
parent79f3641cc03881ba98aa549a149b34c838b7d7fb (diff)
drm/amdgpu: add picasso support for gmc
Same as raven. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index b1c848937e42..55b11afec16e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -846,6 +846,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
846 adev->gmc.gart_size = 512ULL << 20; 846 adev->gmc.gart_size = 512ULL << 20;
847 break; 847 break;
848 case CHIP_RAVEN: /* DCE SG support */ 848 case CHIP_RAVEN: /* DCE SG support */
849 case CHIP_PICASSO: /* DCE SG support */
849 adev->gmc.gart_size = 1024ULL << 20; 850 adev->gmc.gart_size = 1024ULL << 20;
850 break; 851 break;
851 } 852 }
@@ -934,6 +935,7 @@ static int gmc_v9_0_sw_init(void *handle)
934 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 935 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
935 switch (adev->asic_type) { 936 switch (adev->asic_type) {
936 case CHIP_RAVEN: 937 case CHIP_RAVEN:
938 case CHIP_PICASSO:
937 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 939 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
938 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 940 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
939 } else { 941 } else {
@@ -1060,6 +1062,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1060 case CHIP_VEGA12: 1062 case CHIP_VEGA12:
1061 break; 1063 break;
1062 case CHIP_RAVEN: 1064 case CHIP_RAVEN:
1065 case CHIP_PICASSO:
1063 soc15_program_register_sequence(adev, 1066 soc15_program_register_sequence(adev,
1064 golden_settings_athub_1_0_0, 1067 golden_settings_athub_1_0_0,
1065 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1068 ARRAY_SIZE(golden_settings_athub_1_0_0));
@@ -1094,6 +1097,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1094 1097
1095 switch (adev->asic_type) { 1098 switch (adev->asic_type) {
1096 case CHIP_RAVEN: 1099 case CHIP_RAVEN:
1100 case CHIP_PICASSO:
1097 mmhub_v1_0_initialize_power_gating(adev); 1101 mmhub_v1_0_initialize_power_gating(adev);
1098 mmhub_v1_0_update_power_gating(adev, true); 1102 mmhub_v1_0_update_power_gating(adev, true);
1099 break; 1103 break;