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authorThierry Reding <treding@nvidia.com>2018-09-20 12:13:39 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-09-28 09:04:45 -0400
commite1c3c7e54ed3655c02248b4f1c7940aff4eecb56 (patch)
treeecd59d31b57ac7eaea4066f1de74d549e627d66a
parent2815ef7fe4d43072b9eda448d04fbc184f2aa513 (diff)
usb: xhci: tegra: Firmware header is little endian
The XUSB firmware header is in little endian byte order, so make the fields __le32 and __le16 instead of u32 and u16 to avoid warnings from sparse when the fields are used with the endian-aware __le32_to_cpu() and __le16_to_cpu() accessors, respectively. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/usb/host/xhci-tegra.c52
1 files changed, 26 insertions, 26 deletions
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index 4b463e5202a4..4ee510a51d64 100644
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -107,35 +107,35 @@
107#define IMEM_BLOCK_SIZE 256 107#define IMEM_BLOCK_SIZE 256
108 108
109struct tegra_xusb_fw_header { 109struct tegra_xusb_fw_header {
110 u32 boot_loadaddr_in_imem; 110 __le32 boot_loadaddr_in_imem;
111 u32 boot_codedfi_offset; 111 __le32 boot_codedfi_offset;
112 u32 boot_codetag; 112 __le32 boot_codetag;
113 u32 boot_codesize; 113 __le32 boot_codesize;
114 u32 phys_memaddr; 114 __le32 phys_memaddr;
115 u16 reqphys_memsize; 115 __le16 reqphys_memsize;
116 u16 alloc_phys_memsize; 116 __le16 alloc_phys_memsize;
117 u32 rodata_img_offset; 117 __le32 rodata_img_offset;
118 u32 rodata_section_start; 118 __le32 rodata_section_start;
119 u32 rodata_section_end; 119 __le32 rodata_section_end;
120 u32 main_fnaddr; 120 __le32 main_fnaddr;
121 u32 fwimg_cksum; 121 __le32 fwimg_cksum;
122 u32 fwimg_created_time; 122 __le32 fwimg_created_time;
123 u32 imem_resident_start; 123 __le32 imem_resident_start;
124 u32 imem_resident_end; 124 __le32 imem_resident_end;
125 u32 idirect_start; 125 __le32 idirect_start;
126 u32 idirect_end; 126 __le32 idirect_end;
127 u32 l2_imem_start; 127 __le32 l2_imem_start;
128 u32 l2_imem_end; 128 __le32 l2_imem_end;
129 u32 version_id; 129 __le32 version_id;
130 u8 init_ddirect; 130 u8 init_ddirect;
131 u8 reserved[3]; 131 u8 reserved[3];
132 u32 phys_addr_log_buffer; 132 __le32 phys_addr_log_buffer;
133 u32 total_log_entries; 133 __le32 total_log_entries;
134 u32 dequeue_ptr; 134 __le32 dequeue_ptr;
135 u32 dummy_var[2]; 135 __le32 dummy_var[2];
136 u32 fwimg_len; 136 __le32 fwimg_len;
137 u8 magic[8]; 137 u8 magic[8];
138 u32 ss_low_power_entry_timeout; 138 __le32 ss_low_power_entry_timeout;
139 u8 num_hsic_port; 139 u8 num_hsic_port;
140 u8 padding[139]; /* Pad to 256 bytes */ 140 u8 padding[139]; /* Pad to 256 bytes */
141}; 141};