Merge branch 'pci/jiang-pcie-cap' into next

* pci/jiang-pcie-cap: (40 commits) rtl8192e: Use PCI Express Capability accessors et131x: Use PCI Express Capability accessors rapdio/tsi721: Use PCI Express Capability accessors drm/radeon: Use PCI Express Capability accessors [SCSI] qla4xxx: Use PCI Express Capability accessors [SCSI] qla4xxx: Use PCI Express Capability accessors IB/qib: Use PCI Express Capability accessors IB/mthca: Use PCI Express Capability accessors rtlwifi: Use PCI Express Capability accessors iwlwifi: Use PCI Express Capability accessors iwlegacy: Use PCI Express Capability accessors ath9k: Use PCI Express Capability accessors atl1c: Use PCI Express Capability accessors cxgb4: Use PCI Express Capability accessors cxgb3: Use PCI Express Capability accessors myri10ge: Use PCI Express Capability accessors niu: Use PCI Express Capability accessors mlx4: Use PCI Express Capability accessors vxge: Use PCI Express Capability accessors igb: Use PCI Express Capability accessors ...
author: Bjorn Helgaas <bhelgaas@google.com> 2012-08-23 20:31:58 -0400
committer: Bjorn Helgaas <bhelgaas@google.com> 2012-08-23 20:31:58 -0400
commit: e1c171b86baaccab983ded5dfa1663c0981d2520 (patch)
tree: 648ad71d7bd2838678f66d055fcaae654b5e4ddc
parent: 0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (diff)
parent: 479e0d485eaab452cf248cd1a9520015023b35b2 (diff)
52 files changed, 591 insertions, 823 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index d3ad5150d660..c25a2a4f2e3d 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -367,17 +367,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
 /* Tegra PCIE requires relaxed ordering */
 static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
 {
-        u16 val16;
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
-        int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
-        if (pos <= 0) {
-                dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
-                return;
-        }
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
-        val16 |= PCI_EXP_DEVCTL_RELAX_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 52a1ba70b3b6..c5dfb2c87d44 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -117,16 +117,11 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
        }
        /* Enable the PCIe normal error reporting */
-        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+        config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
-        if (pos) {
+        config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
-                /* Update Device Control */
+        config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
-                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
+        config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
-                config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
-                config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
-                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
-        }
        /* Find the Advanced Error Reporting capability */
        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 9cda6a1ad0cf..b46e1dadc882 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -855,7 +855,7 @@ static void __devinit pnv_ioda_setup_PEs(struct pci_bus *bus)
                if (pe == NULL)
                        continue;
                /* Leaving the PCIe domain ... single PE# */
-                if (dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
+                if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
                        pnv_ioda_setup_bus_PE(dev, pe);
                else if (dev->subordinate)
                        pnv_ioda_setup_PEs(dev->subordinate);
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index 33c10864d2f7..d2292be6fb90 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -246,16 +246,13 @@ static void __devinit fixup_read_and_payload_sizes(void)
        /* Scan for the smallest maximum payload size. */
        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-                int pcie_caps_offset;
                u32 devcap;
                int max_payload;
-                pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
+                if (!pci_is_pcie(dev))
-                if (pcie_caps_offset == 0)
                        continue;
-                pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP,
+                pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap);
-                                      &devcap);
                max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD;
                if (max_payload < smallest_max_payload)
                        smallest_max_payload = max_payload;
@@ -263,21 +260,10 @@ static void __devinit fixup_read_and_payload_sizes(void)
        /* Now, set the max_payload_size for all devices to that value. */
        new_values = (max_read_size << 12) | (smallest_max_payload << 5);
-        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
-                int pcie_caps_offset;
+                pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
-                u16 devctl;
+                                PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
+                                new_values);
-                pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP);
-                if (pcie_caps_offset == 0)
-                        continue;
-                pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
-                                     &devctl);
-                devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ);
-                devctl |= new_values;
-                pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL,
-                                      devctl);
-        }
 }
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e585a3b947eb..b106c56c9af1 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -77,13 +77,9 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
 {
        u16 ctl, v;
-        int cap, err;
+        int err;
-        cap = pci_pcie_cap(rdev->pdev);
+        err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
-        if (!cap)
-                return;
-        err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
        if (err)
                return;
@@ -95,7 +91,7 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
        if ((v == 0) || (v == 6) || (v == 7)) {
                ctl &= ~PCI_EXP_DEVCTL_READRQ;
                ctl |= (2 << 12);
-                pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
+                pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
        }
 }
diff --git a/drivers/infiniband/hw/mthca/mthca_reset.c b/drivers/infiniband/hw/mthca/mthca_reset.c
index 4fa3534ec233..74c6a9426047 100644
--- a/drivers/infiniband/hw/mthca/mthca_reset.c
+++ b/drivers/infiniband/hw/mthca/mthca_reset.c
@@ -241,16 +241,16 @@ good:
        if (hca_pcie_cap) {
                devctl = hca_header[(hca_pcie_cap + PCI_EXP_DEVCTL) / 4];
-                if (pci_write_config_word(mdev->pdev, hca_pcie_cap + PCI_EXP_DEVCTL,
+                if (pcie_capability_write_word(mdev->pdev, PCI_EXP_DEVCTL,
-                                           devctl)) {
+                                               devctl)) {
                        err = -ENODEV;
                        mthca_err(mdev, "Couldn't restore HCA PCI Express "
                                  "Device Control register, aborting.\n");
                        goto out;
                }
                linkctl = hca_header[(hca_pcie_cap + PCI_EXP_LNKCTL) / 4];
-                if (pci_write_config_word(mdev->pdev, hca_pcie_cap + PCI_EXP_LNKCTL,
+                if (pcie_capability_write_word(mdev->pdev, PCI_EXP_LNKCTL,
-                                           linkctl)) {
+                                               linkctl)) {
                        err = -ENODEV;
                        mthca_err(mdev, "Couldn't restore HCA PCI Express "
                                  "Link control register, aborting.\n");
diff --git a/drivers/infiniband/hw/qib/qib_pcie.c b/drivers/infiniband/hw/qib/qib_pcie.c
index 062c301ebf53..900137173210 100644
--- a/drivers/infiniband/hw/qib/qib_pcie.c
+++ b/drivers/infiniband/hw/qib/qib_pcie.c
@@ -273,10 +273,9 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
                    struct qib_msix_entry *entry)
 {
        u16 linkstat, speed;
-        int pos = 0, pose, ret = 1;
+        int pos = 0, ret = 1;
-        pose = pci_pcie_cap(dd->pcidev);
+        if (!pci_is_pcie(dd->pcidev)) {
-        if (!pose) {
                qib_dev_err(dd, "Can't find PCI Express capability!\n");
                /* set up something... */
                dd->lbus_width = 1;
@@ -298,7 +297,7 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
        if (!pos)
                qib_enable_intx(dd->pcidev);
-        pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat);
+        pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
        /*
         * speed is bits 0-3, linkwidth is bits 4-8
         * no defines for them in headers
@@ -516,7 +515,6 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
 {
        int r;
        struct pci_dev *parent;
-        int ppos;
        u16 devid;
        u32 mask, bits, val;
@@ -529,8 +527,7 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
                qib_devinfo(dd->pcidev, "Parent not root\n");
                return 1;
        }
-        ppos = pci_pcie_cap(parent);
+        if (!pci_is_pcie(parent))
-        if (!ppos)
                return 1;
        if (parent->vendor != 0x8086)
                return 1;
@@ -587,7 +584,6 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
 {
        int ret = 1; /* Assume the worst */
        struct pci_dev *parent;
-        int ppos, epos;
        u16 pcaps, pctl, ecaps, ectl;
        int rc_sup, ep_sup;
        int rc_cur, ep_cur;
@@ -598,19 +594,15 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
                qib_devinfo(dd->pcidev, "Parent not root\n");
                goto bail;
        }
-        ppos = pci_pcie_cap(parent);
-        if (ppos) {
+        if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
-                pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps);
-                pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
-        } else
                goto bail;
+        pcie_capability_read_word(parent, PCI_EXP_DEVCAP, &pcaps);
+        pcie_capability_read_word(parent, PCI_EXP_DEVCTL, &pctl);
        /* Find out supported and configured values for endpoint (us) */
-        epos = pci_pcie_cap(dd->pcidev);
+        pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps);
-        if (epos) {
+        pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
-                pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps);
-                pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl);
-        } else
-                goto bail;
        ret = 0;
        /* Find max payload supported by root, endpoint */
        rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD);
@@ -629,14 +621,14 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
                rc_cur = rc_sup;
                pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
                        val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
-                pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
+                pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
        }
        /* If less than (allowed, supported), bump endpoint payload */
        if (rc_sup > ep_cur) {
                ep_cur = rc_sup;
                ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
                        val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
-                pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
+                pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
        }
        /*
@@ -654,13 +646,13 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
                rc_cur = rc_sup;
                pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
                        val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
-                pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
+                pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
        }
        if (rc_sup > ep_cur) {
                ep_cur = rc_sup;
                ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
                        val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
-                pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
+                pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
        }
 bail:
        return ret;
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 7469b5346643..8b5075d6dd5a 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -2350,7 +2350,7 @@ static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
                        return 0;
                if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
                        return 0;
-        } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
+        } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
                return 0;
        /* 
@@ -3545,10 +3545,10 @@ found:
                struct pci_dev *bridge = bus->self;
                if (!bridge || !pci_is_pcie(bridge) ||
-                    bridge->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
+                    pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
                        return 0;
-                if (bridge->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
+                if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
                        for (i = 0; i < atsru->devices_cnt; i++)
                                if (atsru->devices[i] == bridge)
                                        return 1;
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 1bf5bbfe778e..8892e2b64498 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -149,7 +149,7 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
        data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
        pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
        /* clear error status */
-        pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
+        pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
                        PCI_EXP_DEVSTA_NFED |
                        PCI_EXP_DEVSTA_FED |
                        PCI_EXP_DEVSTA_CED |
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index dd451c3dd83d..281cf3f7bc20 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -1162,14 +1162,9 @@ static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
 {
-        int pos;
        u16 status;
-        pos = pci_pcie_cap(dev);
+        pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
-        if (!pos)
-                return false;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
        return status & PCI_EXP_DEVSTA_TRPND;
 }
@@ -6149,8 +6144,7 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
        u16 devctl;
        int r_order, w_order;
-        pci_read_config_word(bp->pdev,
+        pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
-                             pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
        DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
        w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
        if (bp->mrrs == -1)
@@ -9386,15 +9380,10 @@ static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
 static bool __devinit bnx2x_can_flr(struct bnx2x *bp)
 {
-        int pos;
        u32 cap;
        struct pci_dev *dev = bp->pdev;
-        pos = pci_pcie_cap(dev);
+        pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
-        if (!pos)
-                return false;
-        pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
        if (!(cap & PCI_EXP_DEVCAP_FLR))
                return false;
@@ -9403,7 +9392,7 @@ static bool __devinit bnx2x_can_flr(struct bnx2x *bp)
 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
 {
-        int i, pos;
+        int i;
        u16 status;
        struct pci_dev *dev = bp->pdev;
@@ -9411,16 +9400,12 @@ static int __devinit bnx2x_do_flr(struct bnx2x *bp)
        if (bnx2x_can_flr(bp))
                return -ENOTTY;
-        pos = pci_pcie_cap(dev);
-        if (!pos)
-                return -ENOTTY;
        /* Wait for Transaction Pending bit clean */
        for (i = 0; i < 4; i++) {
                if (i)
                        msleep((1 << (i - 1)) * 100);
-                pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
+                pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
                if (!(status & PCI_EXP_DEVSTA_TRPND))
                        goto clear;
        }
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index bf906c51d82a..8325fd8d4e5b 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -3653,17 +3653,9 @@ static int tg3_power_down_prepare(struct tg3 *tp)
        tg3_enable_register_access(tp);
        /* Restore the CLKREQ setting. */
-        if (tg3_flag(tp, CLKREQ_BUG)) {
+        if (tg3_flag(tp, CLKREQ_BUG))
-                u16 lnkctl;
+                pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
+                                         PCI_EXP_LNKCTL_CLKREQ_EN);
-                pci_read_config_word(tp->pdev,
-                                     pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
-                                     &lnkctl);
-                lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
-                pci_write_config_word(tp->pdev,
-                                      pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
-                                      lnkctl);
-        }
        misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
        tw32(TG3PCI_MISC_HOST_CTRL,
@@ -4434,20 +4426,13 @@ relink:
        /* Prevent send BD corruption. */
        if (tg3_flag(tp, CLKREQ_BUG)) {
-                u16 oldlnkctl, newlnkctl;
-                pci_read_config_word(tp->pdev,
-                                     pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
-                                     &oldlnkctl);
                if (tp->link_config.active_speed == SPEED_100 ||
                    tp->link_config.active_speed == SPEED_10)
-                        newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
+                        pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
+                                                   PCI_EXP_LNKCTL_CLKREQ_EN);
                else
-                        newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
+                        pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
-                if (newlnkctl != oldlnkctl)
+                                                 PCI_EXP_LNKCTL_CLKREQ_EN);
-                        pci_write_config_word(tp->pdev,
-                                              pci_pcie_cap(tp->pdev) +
-                                              PCI_EXP_LNKCTL, newlnkctl);
        }
        if (current_link_up != netif_carrier_ok(tp->dev)) {
@@ -8054,7 +8039,7 @@ static int tg3_chip_reset(struct tg3 *tp)
        udelay(120);
-        if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
+        if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
                u16 val16;
                if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
@@ -8071,24 +8056,17 @@ static int tg3_chip_reset(struct tg3 *tp)
                }
                /* Clear the "no snoop" and "relaxed ordering" bits. */
-                pci_read_config_word(tp->pdev,
+                val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
-                                     pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
-                                     &val16);
-                val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
-                           PCI_EXP_DEVCTL_NOSNOOP_EN);
                /*
                 * Older PCIe devices only support the 128 byte
                 * MPS setting.  Enforce the restriction.
                 */
                if (!tg3_flag(tp, CPMU_PRESENT))
-                        val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
+                        val16 |= PCI_EXP_DEVCTL_PAYLOAD;
-                pci_write_config_word(tp->pdev,
+                pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
-                                      pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
-                                      val16);
                /* Clear error status */
-                pci_write_config_word(tp->pdev,
+                pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
-                                      pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
                                      PCI_EXP_DEVSTA_CED |
                                      PCI_EXP_DEVSTA_NFED |
                                      PCI_EXP_DEVSTA_FED |
@@ -14565,9 +14543,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                tg3_flag_set(tp, PCI_EXPRESS);
-                pci_read_config_word(tp->pdev,
+                pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
-                                     pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
-                                     &lnkctl);
                if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
                        if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
                            ASIC_REV_5906) {
diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
index bff8a3cdd3df..aef45d3113ba 100644
--- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
@@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap)
        unsigned int log2_width, pldsize;
        unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt;
-        pci_read_config_word(adap->pdev,
+        pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val);
-                             adap->pdev->pcie_cap + PCI_EXP_DEVCTL,
-                             &val);
        pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
        pci_read_config_word(adap->pdev, 0x2, &devid);
        if (devid == 0x37) {
-                pci_write_config_word(adap->pdev,
+                pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL,
-                                      adap->pdev->pcie_cap + PCI_EXP_DEVCTL,
+                                           val & ~PCI_EXP_DEVCTL_READRQ &
-                                      val & ~PCI_EXP_DEVCTL_READRQ &
+                                           ~PCI_EXP_DEVCTL_PAYLOAD);
-                                      ~PCI_EXP_DEVCTL_PAYLOAD);
                pldsize = 0;
        }
-        pci_read_config_word(adap->pdev, adap->pdev->pcie_cap + PCI_EXP_LNKCTL,
+        pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val);
-                             &val);
        fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
        fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
@@ -3425,15 +3421,13 @@ out_err:
 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
 {
        static unsigned short speed_map[] = { 33, 66, 100, 133 };
-        u32 pci_mode, pcie_cap;
+        u32 pci_mode;
-        pcie_cap = pci_pcie_cap(adapter->pdev);
+        if (pci_is_pcie(adapter->pdev)) {
-        if (pcie_cap) {
                u16 val;
                p->variant = PCI_VARIANT_PCIE;
-                pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
+                pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
-                                        &val);
                p->width = (val >> 4) & 0x3f;
                return;
        }
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 5ed49af23d6a..4a20821511e7 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -3694,15 +3694,7 @@ static void __devinit print_port_info(const struct net_device *dev)
 static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev)
 {
-        u16 v;
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
-        int pos;
-        pos = pci_pcie_cap(dev);
-        if (pos > 0) {
-                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &v);
-                v |= PCI_EXP_DEVCTL_RELAX_EN;
-                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, v);
-        }
 }
 /*
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index fa947dfa4c30..af1601323173 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -2741,11 +2741,9 @@ static void __devinit get_pci_mode(struct adapter *adapter,
                                   struct pci_params *p)
 {
        u16 val;
-        u32 pcie_cap = pci_pcie_cap(adapter->pdev);
-        if (pcie_cap) {
+        if (pci_is_pcie(adapter->pdev)) {
-                pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA,
+                pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
-                                     &val);
                p->speed = val & PCI_EXP_LNKSTA_CLS;
                p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
        }
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 95b245310f17..9f474b2cc819 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -5570,16 +5570,15 @@ static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
         */
        if (adapter->flags & FLAG_IS_QUAD_PORT) {
                struct pci_dev *us_dev = pdev->bus->self;
-                int pos = pci_pcie_cap(us_dev);
                u16 devctl;
-                pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
+                pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
-                pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
+                pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
-                                      (devctl & ~PCI_EXP_DEVCTL_CERE));
+                                           (devctl & ~PCI_EXP_DEVCTL_CERE));
                e1000_power_off(pdev, sleep, wake);
-                pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
+                pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
        } else {
                e1000_power_off(pdev, sleep, wake);
        }
@@ -5593,25 +5592,15 @@ static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
 #else
 static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
 {
-        int pos;
-        u16 reg16;
        /*
         * Both device and parent should have the same ASPM setting.
         * Disable ASPM in downstream component first and then upstream.
         */
-        pos = pci_pcie_cap(pdev);
+        pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
-        pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
-        reg16 &= ~state;
-        pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
-        if (!pdev->bus->self)
-                return;
-        pos = pci_pcie_cap(pdev->bus->self);
+        if (pdev->bus->self)
-        pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
+                pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
-        reg16 &= ~state;
+                                           state);
-        pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
 }
 #endif
 static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index b7c2d5050572..9a379d9c07fa 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -6539,28 +6539,20 @@ static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
 {
        struct igb_adapter *adapter = hw->back;
-        u16 cap_offset;
-        cap_offset = adapter->pdev->pcie_cap;
+        if (pcie_capability_read_word(adapter->pdev, reg, value))
-        if (!cap_offset)
                return -E1000_ERR_CONFIG;
-        pci_read_config_word(adapter->pdev, cap_offset + reg, value);
        return 0;
 }
 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
 {
        struct igb_adapter *adapter = hw->back;
-        u16 cap_offset;
-        cap_offset = adapter->pdev->pcie_cap;
+        if (pcie_capability_write_word(adapter->pdev, reg, *value))
-        if (!cap_offset)
                return -E1000_ERR_CONFIG;
-        pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
        return 0;
 }
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 4326f74f7137..976570d4c939 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -7527,7 +7527,7 @@ static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
                goto skip_bad_vf_detection;
        bdev = pdev->bus->self;
-        while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
+        while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
                bdev = bdev->bus->self;
        if (!bdev)
diff --git a/drivers/net/ethernet/mellanox/mlx4/reset.c b/drivers/net/ethernet/mellanox/mlx4/reset.c
index 11e7c1cb99bf..dd1b5093d8b1 100644
--- a/drivers/net/ethernet/mellanox/mlx4/reset.c
+++ b/drivers/net/ethernet/mellanox/mlx4/reset.c
@@ -141,16 +141,16 @@ int mlx4_reset(struct mlx4_dev *dev)
        /* Now restore the PCI headers */
        if (pcie_cap) {
                devctl = hca_header[(pcie_cap + PCI_EXP_DEVCTL) / 4];
-                if (pci_write_config_word(dev->pdev, pcie_cap + PCI_EXP_DEVCTL,
+                if (pcie_capability_write_word(dev->pdev, PCI_EXP_DEVCTL,
-                                           devctl)) {
+                                               devctl)) {
                        err = -ENODEV;
                        mlx4_err(dev, "Couldn't restore HCA PCI Express "
                                 "Device Control register, aborting.\n");
                        goto out;
                }
                linkctl = hca_header[(pcie_cap + PCI_EXP_LNKCTL) / 4];
-                if (pci_write_config_word(dev->pdev, pcie_cap + PCI_EXP_LNKCTL,
+                if (pcie_capability_write_word(dev->pdev, PCI_EXP_LNKCTL,
-                                           linkctl)) {
+                                               linkctl)) {
                        err = -ENODEV;
                        mlx4_err(dev, "Couldn't restore HCA PCI Express "
                                 "Link control register, aborting.\n");
diff --git a/drivers/net/ethernet/myricom/myri10ge/myri10ge.c b/drivers/net/ethernet/myricom/myri10ge/myri10ge.c
index fa85cf1353fd..83516e3369c9 100644
--- a/drivers/net/ethernet/myricom/myri10ge/myri10ge.c
+++ b/drivers/net/ethernet/myricom/myri10ge/myri10ge.c
@@ -1078,22 +1078,16 @@ static int myri10ge_reset(struct myri10ge_priv *mgp)
 #ifdef CONFIG_MYRI10GE_DCA
 static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
 {
-        int ret, cap, err;
+        int ret;
        u16 ctl;
-        cap = pci_pcie_cap(pdev);
+        pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &ctl);
-        if (!cap)
-                return 0;
-        err = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
-        if (err)
-                return 0;
        ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
        if (ret != on) {
                ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
                ctl |= (on << 4);
-                pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
+                pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, ctl);
        }
        return ret;
 }
@@ -3192,18 +3186,13 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
        struct device *dev = &mgp->pdev->dev;
        int cap;
        unsigned err_cap;
-        u16 val;
-        u8 ext_type;
        int ret;
        if (!myri10ge_ecrc_enable || !bridge)
                return;
        /* check that the bridge is a root port */
-        cap = pci_pcie_cap(bridge);
+        if (pci_pcie_type(bridge) != PCI_EXP_TYPE_ROOT_PORT) {
-        pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
-        ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
-        if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
                if (myri10ge_ecrc_enable > 1) {
                        struct pci_dev *prev_bridge, *old_bridge = bridge;
@@ -3218,11 +3207,8 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
                                                " to force ECRC\n");
                                        return;
                                }
-                                cap = pci_pcie_cap(bridge);
+                        } while (pci_pcie_type(bridge) !=
-                                pci_read_config_word(bridge,
+                                 PCI_EXP_TYPE_ROOT_PORT);
-                                                     cap + PCI_CAP_FLAGS, &val);
-                                ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
-                        } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
                        dev_info(dev,
                                 "Forcing ECRC on non-root port %s"
@@ -3335,11 +3321,10 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
        int overridden = 0;
        if (myri10ge_force_firmware == 0) {
-                int link_width, exp_cap;
+                int link_width;
                u16 lnk;
-                exp_cap = pci_pcie_cap(mgp->pdev);
+                pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
-                pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
                link_width = (lnk >> 4) & 0x3f;
                /* Check to see if Link is less than 8 or if the
diff --git a/drivers/net/ethernet/neterion/vxge/vxge-config.c b/drivers/net/ethernet/neterion/vxge/vxge-config.c
index 32d06824fe3e..c2e420a84d22 100644
--- a/drivers/net/ethernet/neterion/vxge/vxge-config.c
+++ b/drivers/net/ethernet/neterion/vxge/vxge-config.c
@@ -757,7 +757,7 @@ __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
        u16 lnk;
        /* Get the negotiated link width and speed from PCI config space */
-        pci_read_config_word(dev, dev->pcie_cap + PCI_EXP_LNKSTA, &lnk);
+        pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
        if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
                return VXGE_HW_ERR_INVALID_PCI_INFO;
@@ -1982,7 +1982,7 @@ u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
        struct pci_dev *dev = hldev->pdev;
        u16 lnk;
-        pci_read_config_word(dev, dev->pcie_cap + PCI_EXP_LNKSTA, &lnk);
+        pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
        return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
 }
diff --git a/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c b/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
index 342b3a79bd0f..01d6141cedd9 100644
--- a/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
+++ b/drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c
@@ -1382,7 +1382,7 @@ static void netxen_mask_aer_correctable(struct netxen_adapter *adapter)
                adapter->ahw.board_type != NETXEN_BRDTYPE_P3_10G_TP)
                return;
-        if (root->pcie_type != PCI_EXP_TYPE_ROOT_PORT)
+        if (pci_pcie_type(root) != PCI_EXP_TYPE_ROOT_PORT)
                return;
        aer_pos = pci_find_ext_capability(root, PCI_EXT_CAP_ID_ERR);
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index b47d5b35024e..a7cc56007b33 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -833,15 +833,8 @@ static void rtl_unlock_work(struct rtl8169_private *tp)
 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 {
-        int cap = pci_pcie_cap(pdev);
+        pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
+                                           PCI_EXP_DEVCTL_READRQ, force);
-        if (cap) {
-                u16 ctl;
-                pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
-                ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
-                pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
-        }
 }
 struct rtl_cond {
@@ -4739,28 +4732,14 @@ static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
 static void rtl_disable_clock_request(struct pci_dev *pdev)
 {
-        int cap = pci_pcie_cap(pdev);
+        pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
+                                   PCI_EXP_LNKCTL_CLKREQ_EN);
-        if (cap) {
-                u16 ctl;
-                pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
-                ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
-                pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
-        }
 }
 static void rtl_enable_clock_request(struct pci_dev *pdev)
 {
-        int cap = pci_pcie_cap(pdev);
+        pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
+                                 PCI_EXP_LNKCTL_CLKREQ_EN);
-        if (cap) {
-                u16 ctl;
-                pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
-                ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
-                pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
-        }
 }
 #define R8168_CPCMD_QUIRK_MASK (\
@@ -5405,14 +5384,9 @@ static void rtl_hw_start_8101(struct net_device *dev)
                tp->event_slow &= ~RxFIFOOver;
        if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
-            tp->mac_version == RTL_GIGA_MAC_VER_16) {
+            tp->mac_version == RTL_GIGA_MAC_VER_16)
-                int cap = pci_pcie_cap(pdev);
+                pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
+                                         PCI_EXP_DEVCTL_NOSNOOP_EN);
-                if (cap) {
-                        pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
-                                              PCI_EXP_DEVCTL_NOSNOOP_EN);
-                }
-        }
        RTL_W8(Cfg9346, Cfg9346_Unlock);
diff --git a/drivers/net/ethernet/sun/niu.c b/drivers/net/ethernet/sun/niu.c
index c2a0fe393267..3208dca66758 100644
--- a/drivers/net/ethernet/sun/niu.c
+++ b/drivers/net/ethernet/sun/niu.c
@@ -9762,9 +9762,8 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev,
        union niu_parent_id parent_id;
        struct net_device *dev;
        struct niu *np;
-        int err, pos;
+        int err;
        u64 dma_mask;
-        u16 val16;
        niu_driver_version();
@@ -9787,8 +9786,7 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev,
                goto err_out_disable_pdev;
        }
-        pos = pci_pcie_cap(pdev);
+        if (!pci_is_pcie(pdev)) {
-        if (pos <= 0) {
                dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
                goto err_out_free_res;
        }
@@ -9813,14 +9811,11 @@ static int __devinit niu_pci_init_one(struct pci_dev *pdev,
                goto err_out_free_dev;
        }
-        pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
+        pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
-        val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
+                PCI_EXP_DEVCTL_NOSNOOP_EN,
-        val16 |= (PCI_EXP_DEVCTL_CERE |
+                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
-                  PCI_EXP_DEVCTL_NFERE |
+                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE |
-                  PCI_EXP_DEVCTL_FERE |
+                PCI_EXP_DEVCTL_RELAX_EN);
-                  PCI_EXP_DEVCTL_URRE |
-                  PCI_EXP_DEVCTL_RELAX_EN);
-        pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
        dma_mask = DMA_BIT_MASK(44);
        err = pci_set_dma_mask(pdev, dma_mask);
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 87b89d55e637..f7fe104df372 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -112,41 +112,32 @@ static void ath_pci_aspm_init(struct ath_common *common)
        struct ath_hw *ah = sc->sc_ah;
        struct pci_dev *pdev = to_pci_dev(sc->dev);
        struct pci_dev *parent;
-        int pos;
+        u16 aspm;
-        u8 aspm;
        if (!ah->is_pciexpress)
                return;
-        pos = pci_pcie_cap(pdev);
-        if (!pos)
-                return;
        parent = pdev->bus->self;
        if (!parent)
                return;
        if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
                /* Bluetooth coexistance requires disabling ASPM. */
-                pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
+                pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
-                aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
+                        PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
-                pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
                /*
                 * Both upstream and downstream PCIe components should
                 * have the same ASPM settings.
                 */
-                pos = pci_pcie_cap(parent);
+                pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
-                pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
+                        PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
-                aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
-                pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
                ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
                return;
        }
-        pos = pci_pcie_cap(parent);
+        pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
-        pci_read_config_byte(parent, pos +  PCI_EXP_LNKCTL, &aspm);
        if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
                ah->aspm_enabled = true;
                /* Initialize PCIe PM and SERDES registers. */
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index 5f5017767b99..724682669060 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,10 +1832,8 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
 static inline u16
 il_pcie_link_ctl(struct il_priv *il)
 {
-        int pos;
        u16 pci_lnk_ctl;
-        pos = pci_pcie_cap(il->pci_dev);
+        pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &pci_lnk_ctl);
-        pci_read_config_word(il->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
        return pci_lnk_ctl;
 }
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 939c2f78df58..26bdbe3ff7cf 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -675,13 +675,10 @@ static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 {
        struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
-        int pos;
        u16 pci_lnk_ctl;
-        struct pci_dev *pci_dev = trans_pcie->pci_dev;
+        pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
+                                  &pci_lnk_ctl);
-        pos = pci_pcie_cap(pci_dev);
-        pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
        return pci_lnk_ctl;
 }
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 80f75d3ba84a..5983631a1b1a 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -372,13 +372,11 @@ static void rtl_pci_parse_configuration(struct pci_dev *pdev,
        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
        u8 tmp;
-        int pos;
+        u16 linkctrl_reg;
-        u8 linkctrl_reg;
        /*Link Control Register */
-        pos = pci_pcie_cap(pdev);
+        pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
-        pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
+        pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
-        pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
                 pcipriv->ndis_adapter.linkctrl_reg);
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index ba91a7e17519..3af0478c057b 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -469,3 +469,205 @@ void pci_cfg_access_unlock(struct pci_dev *dev)
        raw_spin_unlock_irqrestore(&pci_lock, flags);
 }
 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
+static inline int pcie_cap_version(const struct pci_dev *dev)
+{
+        return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
+}
+static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
+{
+        return true;
+}
+static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
+{
+        int type = pci_pcie_type(dev);
+        return pcie_cap_version(dev) > 1 ||
+               type == PCI_EXP_TYPE_ROOT_PORT ||
+               type == PCI_EXP_TYPE_ENDPOINT ||
+               type == PCI_EXP_TYPE_LEG_END;
+}
+static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
+{
+        int type = pci_pcie_type(dev);
+        return pcie_cap_version(dev) > 1 ||
+               type == PCI_EXP_TYPE_ROOT_PORT ||
+               (type == PCI_EXP_TYPE_DOWNSTREAM &&
+                dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
+}
+static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
+{
+        int type = pci_pcie_type(dev);
+        return pcie_cap_version(dev) > 1 ||
+               type == PCI_EXP_TYPE_ROOT_PORT ||
+               type == PCI_EXP_TYPE_RC_EC;
+}
+static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
+{
+        if (!pci_is_pcie(dev))
+                return false;
+        switch (pos) {
+        case PCI_EXP_FLAGS_TYPE:
+                return true;
+        case PCI_EXP_DEVCAP:
+        case PCI_EXP_DEVCTL:
+        case PCI_EXP_DEVSTA:
+                return pcie_cap_has_devctl(dev);
+        case PCI_EXP_LNKCAP:
+        case PCI_EXP_LNKCTL:
+        case PCI_EXP_LNKSTA:
+                return pcie_cap_has_lnkctl(dev);
+        case PCI_EXP_SLTCAP:
+        case PCI_EXP_SLTCTL:
+        case PCI_EXP_SLTSTA:
+                return pcie_cap_has_sltctl(dev);
+        case PCI_EXP_RTCTL:
+        case PCI_EXP_RTCAP:
+        case PCI_EXP_RTSTA:
+                return pcie_cap_has_rtctl(dev);
+        case PCI_EXP_DEVCAP2:
+        case PCI_EXP_DEVCTL2:
+        case PCI_EXP_LNKCAP2:
+        case PCI_EXP_LNKCTL2:
+        case PCI_EXP_LNKSTA2:
+                return pcie_cap_version(dev) > 1;
+        default:
+                return false;
+        }
+}
+/*
+ * Note that these accessor functions are only for the "PCI Express
+ * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
+ * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
+ */
+int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
+{
+        int ret;
+        *val = 0;
+        if (pos & 1)
+                return -EINVAL;
+        if (pcie_capability_reg_implemented(dev, pos)) {
+                ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
+                /*
+                 * Reset *val to 0 if pci_read_config_word() fails, it may
+                 * have been written as 0xFFFF if hardware error happens
+                 * during pci_read_config_word().
+                 */
+                if (ret)
+                        *val = 0;
+                return ret;
+        }
+        /*
+         * For Functions that do not implement the Slot Capabilities,
+         * Slot Status, and Slot Control registers, these spaces must
+         * be hardwired to 0b, with the exception of the Presence Detect
+         * State bit in the Slot Status register of Downstream Ports,
+         * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
+         */
+        if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
+                 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
+                *val = PCI_EXP_SLTSTA_PDS;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(pcie_capability_read_word);
+int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
+{
+        int ret;
+        *val = 0;
+        if (pos & 3)
+                return -EINVAL;
+        if (pcie_capability_reg_implemented(dev, pos)) {
+                ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
+                /*
+                 * Reset *val to 0 if pci_read_config_dword() fails, it may
+                 * have been written as 0xFFFFFFFF if hardware error happens
+                 * during pci_read_config_dword().
+                 */
+                if (ret)
+                        *val = 0;
+                return ret;
+        }
+        if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
+                 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
+                *val = PCI_EXP_SLTSTA_PDS;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(pcie_capability_read_dword);
+int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
+{
+        if (pos & 1)
+                return -EINVAL;
+        if (!pcie_capability_reg_implemented(dev, pos))
+                return 0;
+        return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
+}
+EXPORT_SYMBOL(pcie_capability_write_word);
+int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
+{
+        if (pos & 3)
+                return -EINVAL;
+        if (!pcie_capability_reg_implemented(dev, pos))
+                return 0;
+        return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
+}
+EXPORT_SYMBOL(pcie_capability_write_dword);
+int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
+                                       u16 clear, u16 set)
+{
+        int ret;
+        u16 val;
+        ret = pcie_capability_read_word(dev, pos, &val);
+        if (!ret) {
+                val &= ~clear;
+                val |= set;
+                ret = pcie_capability_write_word(dev, pos, val);
+        }
+        return ret;
+}
+EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
+int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
+                                        u32 clear, u32 set)
+{
+        int ret;
+        u32 val;
+        ret = pcie_capability_read_dword(dev, pos, &val);
+        if (!ret) {
+                val &= ~clear;
+                val |= set;
+                ret = pcie_capability_write_dword(dev, pos, val);
+        }
+        return ret;
+}
+EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
diff --git a/drivers/pci/hotplug/pciehp_acpi.c b/drivers/pci/hotplug/pciehp_acpi.c
index 376d70d17176..24d709b7388c 100644
--- a/drivers/pci/hotplug/pciehp_acpi.c
+++ b/drivers/pci/hotplug/pciehp_acpi.c
@@ -81,16 +81,12 @@ static struct list_head __initdata dummy_slots = LIST_HEAD_INIT(dummy_slots);
 /* Dummy driver for dumplicate name detection */
 static int __init dummy_probe(struct pcie_device *dev)
 {
-        int pos;
        u32 slot_cap;
        acpi_handle handle;
        struct dummy_slot *slot, *tmp;
        struct pci_dev *pdev = dev->port;
-        pos = pci_pcie_cap(pdev);
+        pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
-        if (!pos)
-                return -ENODEV;
-        pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &slot_cap);
        slot = kzalloc(sizeof(*slot), GFP_KERNEL);
        if (!slot)
                return -ENOMEM;
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 302451e8289d..13b2eaf7ba43 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -44,25 +44,25 @@
 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
 {
        struct pci_dev *dev = ctrl->pcie->port;
-        return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
+        return pcie_capability_read_word(dev, reg, value);
 }
 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
 {
        struct pci_dev *dev = ctrl->pcie->port;
-        return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
+        return pcie_capability_read_dword(dev, reg, value);
 }
 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
 {
        struct pci_dev *dev = ctrl->pcie->port;
-        return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
+        return pcie_capability_write_word(dev, reg, value);
 }
 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
 {
        struct pci_dev *dev = ctrl->pcie->port;
-        return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
+        return pcie_capability_write_dword(dev, reg, value);
 }
 /* Power Control Command */
@@ -855,10 +855,6 @@ struct controller *pcie_init(struct pcie_device *dev)
                goto abort;
        }
        ctrl->pcie = dev;
-        if (!pci_pcie_cap(pdev)) {
-                ctrl_err(ctrl, "Cannot find PCI Express capability\n");
-                goto abort_ctrl;
-        }
        if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
                ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
                goto abort_ctrl;
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c
index 8c05a18c9770..fec2d5b75440 100644
--- a/drivers/pci/hotplug/pcihp_slot.c
+++ b/drivers/pci/hotplug/pcihp_slot.c
@@ -96,17 +96,11 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
 {
        int pos;
-        u16 reg16;
        u32 reg32;
        if (!hpp)
                return;
-        /* Find PCI Express capability */
-        pos = pci_pcie_cap(dev);
-        if (!pos)
-                return;
        if (hpp->revision > 1) {
                dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
                         hpp->revision);
@@ -114,17 +108,13 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
        }
        /* Initialize Device Control Register */
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
+        pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
-        reg16 = (reg16 & hpp->pci_exp_devctl_and) | hpp->pci_exp_devctl_or;
+                        ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
        /* Initialize Link Control Register */
-        if (dev->subordinate) {
+        if (dev->subordinate)
-                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &reg16);
+                pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
-                reg16 = (reg16 & hpp->pci_exp_lnkctl_and)
+                        ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
-                        | hpp->pci_exp_lnkctl_or;
-                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, reg16);
-        }
        /* Find Advanced Error Reporting Enhanced Capability */
        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 74bbaf82638d..aeccc911abb8 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -433,8 +433,8 @@ static int sriov_init(struct pci_dev *dev, int pos)
        struct resource *res;
        struct pci_dev *pdev;
-        if (dev->pcie_type != PCI_EXP_TYPE_RC_END &&
+        if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END &&
-            dev->pcie_type != PCI_EXP_TYPE_ENDPOINT)
+            pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT)
                return -ENODEV;
        pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
@@ -503,7 +503,7 @@ found:
        iov->self = dev;
        pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
        pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
-        if (dev->pcie_type == PCI_EXP_TYPE_RC_END)
+        if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
                iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
        if (pdev)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index f3ea977a5b1b..fac08f508d09 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -254,38 +254,6 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
 }
 /**
- * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
- * @dev: PCI device to check
- *
- * Like pci_pcie_cap() but also checks that the PCIe capability version is
- * >= 2.  Note that v1 capability structures could be sparse in that not
- * all register fields were required.  v2 requires the entire structure to
- * be present size wise, while still allowing for non-implemented registers
- * to exist but they must be hardwired to 0.
- *
- * Due to the differences in the versions of capability structures, one
- * must be careful not to try and access non-existant registers that may
- * exist in early versions - v1 - of Express devices.
- *
- * Returns the offset of the PCIe capability structure as long as the
- * capability version is >= 2; otherwise 0 is returned.
- */
-static int pci_pcie_cap2(struct pci_dev *dev)
-{
-        u16 flags;
-        int pos;
-        pos = pci_pcie_cap(dev);
-        if (pos) {
-                pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
-                if ((flags & PCI_EXP_FLAGS_VERS) < 2)
-                        pos = 0;
-        }
-        return pos;
-}
-/**
 * pci_find_ext_capability - Find an extended capability
 * @dev: PCI device to query
 * @cap: capability code
@@ -854,21 +822,6 @@ EXPORT_SYMBOL(pci_choose_state);
 #define PCI_EXP_SAVE_REGS       7
-#define pcie_cap_has_devctl(type, flags)        1
-#define pcie_cap_has_lnkctl(type, flags)                \
-                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
-                 (type == PCI_EXP_TYPE_ROOT_PORT ||     \
-                  type == PCI_EXP_TYPE_ENDPOINT ||      \
-                  type == PCI_EXP_TYPE_LEG_END))
-#define pcie_cap_has_sltctl(type, flags)                \
-                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
-                 ((type == PCI_EXP_TYPE_ROOT_PORT) ||   \
-                  (type == PCI_EXP_TYPE_DOWNSTREAM &&   \
-                   (flags & PCI_EXP_FLAGS_SLOT))))
-#define pcie_cap_has_rtctl(type, flags)                 \
-                ((flags & PCI_EXP_FLAGS_VERS) > 1 ||    \
-                 (type == PCI_EXP_TYPE_ROOT_PORT ||     \
-                  type == PCI_EXP_TYPE_RC_EC))
 static struct pci_cap_saved_state *pci_find_saved_cap(
        struct pci_dev *pci_dev, char cap)
@@ -885,13 +838,11 @@ static struct pci_cap_saved_state *pci_find_saved_cap(
 static int pci_save_pcie_state(struct pci_dev *dev)
 {
-        int pos, i = 0;
+        int i = 0;
        struct pci_cap_saved_state *save_state;
        u16 *cap;
-        u16 flags;
-        pos = pci_pcie_cap(dev);
+        if (!pci_is_pcie(dev))
-        if (!pos)
                return 0;
        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
@@ -899,60 +850,37 @@ static int pci_save_pcie_state(struct pci_dev *dev)
                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
                return -ENOMEM;
        }
-        cap = (u16 *)&save_state->cap.data[0];
-        pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
-        if (pcie_cap_has_devctl(dev->pcie_type, flags))
+        cap = (u16 *)&save_state->cap.data[0];
-                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
+        pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
-        if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
+        pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
-                pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
+        pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
-        if (pcie_cap_has_sltctl(dev->pcie_type, flags))
+        pcie_capability_read_word(dev, PCI_EXP_RTCTL,  &cap[i++]);
-                pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
+        pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
-        if (pcie_cap_has_rtctl(dev->pcie_type, flags))
+        pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
-                pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
+        pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return 0;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
-        pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
-        pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
        return 0;
 }
 static void pci_restore_pcie_state(struct pci_dev *dev)
 {
-        int i = 0, pos;
+        int i = 0;
        struct pci_cap_saved_state *save_state;
        u16 *cap;
-        u16 flags;
        save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
-        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+        if (!save_state)
-        if (!save_state || pos <= 0)
-                return;
-        cap = (u16 *)&save_state->cap.data[0];
-        pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
-        if (pcie_cap_has_devctl(dev->pcie_type, flags))
-                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
-        if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
-                pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
-        if (pcie_cap_has_sltctl(dev->pcie_type, flags))
-                pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
-        if (pcie_cap_has_rtctl(dev->pcie_type, flags))
-                pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
                return;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
+        cap = (u16 *)&save_state->cap.data[0];
-        pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
+        pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
-        pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
+        pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
+        pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
+        pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
+        pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
+        pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
+        pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
 }
@@ -2066,35 +1994,24 @@ void pci_free_cap_save_buffers(struct pci_dev *dev)
 */
 void pci_enable_ari(struct pci_dev *dev)
 {
-        int pos;
        u32 cap;
-        u16 ctrl;
        struct pci_dev *bridge;
        if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
                return;
-        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
+        if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
-        if (!pos)
                return;
        bridge = dev->bus->self;
        if (!bridge)
                return;
-        /* ARI is a PCIe cap v2 feature */
+        pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
-        pos = pci_pcie_cap2(bridge);
-        if (!pos)
-                return;
-        pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
        if (!(cap & PCI_EXP_DEVCAP2_ARI))
                return;
-        pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
+        pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
-        ctrl |= PCI_EXP_DEVCTL2_ARI;
-        pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
        bridge->ari_enabled = 1;
 }
@@ -2109,20 +2026,14 @@ void pci_enable_ari(struct pci_dev *dev)
 */
 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
 {
-        int pos;
+        u16 ctrl = 0;
-        u16 ctrl;
-        /* ID-based Ordering is a PCIe cap v2 feature */
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
        if (type & PCI_EXP_IDO_REQUEST)
                ctrl |= PCI_EXP_IDO_REQ_EN;
        if (type & PCI_EXP_IDO_COMPLETION)
                ctrl |= PCI_EXP_IDO_CMP_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+        if (ctrl)
+                pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
 }
 EXPORT_SYMBOL(pci_enable_ido);
@@ -2133,20 +2044,14 @@ EXPORT_SYMBOL(pci_enable_ido);
 */
 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
 {
-        int pos;
+        u16 ctrl = 0;
-        u16 ctrl;
-        /* ID-based Ordering is a PCIe cap v2 feature */
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
        if (type & PCI_EXP_IDO_REQUEST)
-                ctrl &= ~PCI_EXP_IDO_REQ_EN;
+                ctrl |= PCI_EXP_IDO_REQ_EN;
        if (type & PCI_EXP_IDO_COMPLETION)
-                ctrl &= ~PCI_EXP_IDO_CMP_EN;
+                ctrl |= PCI_EXP_IDO_CMP_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+        if (ctrl)
+                pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
 }
 EXPORT_SYMBOL(pci_disable_ido);
@@ -2171,17 +2076,11 @@ EXPORT_SYMBOL(pci_disable_ido);
 */
 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
 {
-        int pos;
        u32 cap;
        u16 ctrl;
        int ret;
-        /* OBFF is a PCIe cap v2 feature */
+        pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return -ENOTSUPP;
-        pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
        if (!(cap & PCI_EXP_OBFF_MASK))
                return -ENOTSUPP; /* no OBFF support at all */
@@ -2192,7 +2091,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
                        return ret;
        }
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+        pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
        if (cap & PCI_EXP_OBFF_WAKE)
                ctrl |= PCI_EXP_OBFF_WAKE_EN;
        else {
@@ -2210,7 +2109,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
                        return -ENOTSUPP;
                }
        }
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+        pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
        return 0;
 }
@@ -2224,17 +2123,7 @@ EXPORT_SYMBOL(pci_enable_obff);
 */
 void pci_disable_obff(struct pci_dev *dev)
 {
-        int pos;
+        pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
-        u16 ctrl;
-        /* OBFF is a PCIe cap v2 feature */
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
-        ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
 }
 EXPORT_SYMBOL(pci_disable_obff);
@@ -2247,15 +2136,9 @@ EXPORT_SYMBOL(pci_disable_obff);
 */
 static bool pci_ltr_supported(struct pci_dev *dev)
 {
-        int pos;
        u32 cap;
-        /* LTR is a PCIe cap v2 feature */
+        pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return false;
-        pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
        return cap & PCI_EXP_DEVCAP2_LTR;
 }
@@ -2272,22 +2155,15 @@ static bool pci_ltr_supported(struct pci_dev *dev)
 */
 int pci_enable_ltr(struct pci_dev *dev)
 {
-        int pos;
-        u16 ctrl;
        int ret;
-        if (!pci_ltr_supported(dev))
-                return -ENOTSUPP;
-        /* LTR is a PCIe cap v2 feature */
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return -ENOTSUPP;
        /* Only primary function can enable/disable LTR */
        if (PCI_FUNC(dev->devfn) != 0)
                return -EINVAL;
+        if (!pci_ltr_supported(dev))
+                return -ENOTSUPP;
        /* Enable upstream ports first */
        if (dev->bus->self) {
                ret = pci_enable_ltr(dev->bus->self);
@@ -2295,11 +2171,7 @@ int pci_enable_ltr(struct pci_dev *dev)
                        return ret;
        }
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+        return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
-        ctrl |= PCI_EXP_LTR_EN;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
-        return 0;
 }
 EXPORT_SYMBOL(pci_enable_ltr);
@@ -2309,24 +2181,14 @@ EXPORT_SYMBOL(pci_enable_ltr);
 */
 void pci_disable_ltr(struct pci_dev *dev)
 {
-        int pos;
-        u16 ctrl;
-        if (!pci_ltr_supported(dev))
-                return;
-        /* LTR is a PCIe cap v2 feature */
-        pos = pci_pcie_cap2(dev);
-        if (!pos)
-                return;
        /* Only primary function can enable/disable LTR */
        if (PCI_FUNC(dev->devfn) != 0)
                return;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+        if (!pci_ltr_supported(dev))
-        ctrl &= ~PCI_EXP_LTR_EN;
+                return;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+        pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
 }
 EXPORT_SYMBOL(pci_disable_ltr);
@@ -2409,9 +2271,6 @@ void pci_enable_acs(struct pci_dev *dev)
        if (!pci_acs_enable)
                return;
-        if (!pci_is_pcie(dev))
-                return;
        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
        if (!pos)
                return;
@@ -2459,8 +2318,8 @@ bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
                acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
                              PCI_ACS_EC | PCI_ACS_DT);
-        if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM ||
+        if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM ||
-            pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+            pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
            pdev->multifunction) {
                pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
                if (!pos)
@@ -3176,15 +3035,10 @@ EXPORT_SYMBOL(pci_set_dma_seg_boundary);
 static int pcie_flr(struct pci_dev *dev, int probe)
 {
        int i;
-        int pos;
        u32 cap;
-        u16 status, control;
+        u16 status;
-        pos = pci_pcie_cap(dev);
-        if (!pos)
-                return -ENOTTY;
-        pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
+        pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
        if (!(cap & PCI_EXP_DEVCAP_FLR))
                return -ENOTTY;
@@ -3196,7 +3050,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
                if (i)
                        msleep((1 << (i - 1)) * 100);
-                pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
+                pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
                if (!(status & PCI_EXP_DEVSTA_TRPND))
                        goto clear;
        }
@@ -3205,9 +3059,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
                        "proceeding with reset anyway\n");
 clear:
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
-        control |= PCI_EXP_DEVCTL_BCR_FLR;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
        msleep(100);
@@ -3575,18 +3427,11 @@ EXPORT_SYMBOL(pcix_set_mmrbc);
 */
 int pcie_get_readrq(struct pci_dev *dev)
 {
-        int ret, cap;
        u16 ctl;
-        cap = pci_pcie_cap(dev);
+        pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
-        if (!cap)
-                return -EINVAL;
-        ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
-        if (!ret)
-                ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
-        return ret;
+        return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
 }
 EXPORT_SYMBOL(pcie_get_readrq);
@@ -3600,19 +3445,11 @@ EXPORT_SYMBOL(pcie_get_readrq);
 */
 int pcie_set_readrq(struct pci_dev *dev, int rq)
 {
-        int cap, err = -EINVAL;
+        u16 v;
-        u16 ctl, v;
        if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
-                goto out;
+                return -EINVAL;
-        cap = pci_pcie_cap(dev);
-        if (!cap)
-                goto out;
-        err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
-        if (err)
-                goto out;
        /*
         * If using the "performance" PCIe config, we clamp the
         * read rq size to the max packet size to prevent the
@@ -3630,14 +3467,8 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
        v = (ffs(rq) - 8) << 12;
-        if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
+        return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
-                ctl &= ~PCI_EXP_DEVCTL_READRQ;
+                                                  PCI_EXP_DEVCTL_READRQ, v);
-                ctl |= v;
-                err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
-        }
-out:
-        return err;
 }
 EXPORT_SYMBOL(pcie_set_readrq);
@@ -3650,18 +3481,11 @@ EXPORT_SYMBOL(pcie_set_readrq);
 */
 int pcie_get_mps(struct pci_dev *dev)
 {
-        int ret, cap;
        u16 ctl;
-        cap = pci_pcie_cap(dev);
+        pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
-        if (!cap)
-                return -EINVAL;
-        ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
-        if (!ret)
-                ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
-        return ret;
+        return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
 }
 /**
@@ -3674,32 +3498,18 @@ int pcie_get_mps(struct pci_dev *dev)
 */
 int pcie_set_mps(struct pci_dev *dev, int mps)
 {
-        int cap, err = -EINVAL;
+        u16 v;
-        u16 ctl, v;
        if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
-                goto out;
+                return -EINVAL;
        v = ffs(mps) - 8;
        if (v > dev->pcie_mpss) 
-                goto out;
+                return -EINVAL;
        v <<= 5;
-        cap = pci_pcie_cap(dev);
+        return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
-        if (!cap)
+                                                  PCI_EXP_DEVCTL_PAYLOAD, v);
-                goto out;
-        err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
-        if (err)
-                goto out;
-        if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
-                ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
-                ctl |= v;
-                err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
-        }
-out:
-        return err;
 }
 /**
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index 52229863e9fe..4e24cb8a94ae 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -288,7 +288,7 @@ static struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
        while (1) {
                if (!pci_is_pcie(dev))
                        break;
-                if (dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
+                if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
                        return dev;
                if (!dev->bus->self)
                        break;
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 58ad7917553c..c78778fc0cba 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -81,10 +81,11 @@ bool pci_aer_available(void)
 static int set_device_error_reporting(struct pci_dev *dev, void *data)
 {
        bool enable = *((bool *)data);
+        int type = pci_pcie_type(dev);
-        if ((dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||
+        if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
-            (dev->pcie_type == PCI_EXP_TYPE_UPSTREAM) ||
+            (type == PCI_EXP_TYPE_UPSTREAM) ||
-            (dev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)) {
+            (type == PCI_EXP_TYPE_DOWNSTREAM)) {
                if (enable)
                        pci_enable_pcie_error_reporting(dev);
                else
@@ -121,19 +122,17 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev,
 static void aer_enable_rootport(struct aer_rpc *rpc)
 {
        struct pci_dev *pdev = rpc->rpd->port;
-        int pos, aer_pos;
+        int aer_pos;
        u16 reg16;
        u32 reg32;
-        pos = pci_pcie_cap(pdev);
        /* Clear PCIe Capability's Device Status */
-        pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, &reg16);
+        pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, &reg16);
-        pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16);
+        pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
        /* Disable system error generation in response to error messages */
-        pci_read_config_word(pdev, pos + PCI_EXP_RTCTL, &reg16);
+        pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
-        reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK);
+                                   SYSTEM_ERROR_INTR_ON_MESG_MASK);
-        pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16);
        aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
        /* Clear error status */
@@ -395,9 +394,8 @@ static void aer_error_resume(struct pci_dev *dev)
        u16 reg16;
        /* Clean up Root device status */
-        pos = pci_pcie_cap(dev);
+        pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &reg16);
-        pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &reg16);
+        pcie_capability_write_word(dev, PCI_EXP_DEVSTA, reg16);
-        pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16);
        /* Clean AER Root Error Status */
        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c
index 124f20ff11b2..5194a7d41730 100644
--- a/drivers/pci/pcie/aer/aerdrv_acpi.c
+++ b/drivers/pci/pcie/aer/aerdrv_acpi.c
@@ -60,7 +60,7 @@ static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
        p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
        if (p->flags & ACPI_HEST_GLOBAL) {
                if ((pci_is_pcie(info->pci_dev) &&
-                     info->pci_dev->pcie_type == pcie_type) || bridge)
+                     pci_pcie_type(info->pci_dev) == pcie_type) || bridge)
                        ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
        } else
                if (hest_match_pci(p, info->pci_dev))
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 0ca053538146..cefc0ddcacf6 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -32,53 +32,28 @@ static bool nosourceid;
 module_param(forceload, bool, 0);
 module_param(nosourceid, bool, 0);
+#define PCI_EXP_AER_FLAGS       (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
+                                 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
 int pci_enable_pcie_error_reporting(struct pci_dev *dev)
 {
-        u16 reg16 = 0;
-        int pos;
        if (pcie_aer_get_firmware_first(dev))
                return -EIO;
-        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
+        if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))
-        if (!pos)
-                return -EIO;
-        pos = pci_pcie_cap(dev);
-        if (!pos)
                return -EIO;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
+        return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
-        reg16 |= (PCI_EXP_DEVCTL_CERE |
-                PCI_EXP_DEVCTL_NFERE |
-                PCI_EXP_DEVCTL_FERE |
-                PCI_EXP_DEVCTL_URRE);
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
-        return 0;
 }
 EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
 int pci_disable_pcie_error_reporting(struct pci_dev *dev)
 {
-        u16 reg16 = 0;
-        int pos;
        if (pcie_aer_get_firmware_first(dev))
                return -EIO;
-        pos = pci_pcie_cap(dev);
+        return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
-        if (!pos)
+                                          PCI_EXP_AER_FLAGS);
-                return -EIO;
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
-        reg16 &= ~(PCI_EXP_DEVCTL_CERE |
-                PCI_EXP_DEVCTL_NFERE |
-                PCI_EXP_DEVCTL_FERE |
-                PCI_EXP_DEVCTL_URRE);
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16);
-        return 0;
 }
 EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
@@ -151,18 +126,12 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
         */
        if (atomic_read(&dev->enable_cnt) == 0)
                return false;
-        pos = pci_pcie_cap(dev);
-        if (!pos)
-                return false;
        /* Check if AER is enabled */
-        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &reg16);
+        pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &reg16);
-        if (!(reg16 & (
+        if (!(reg16 & PCI_EXP_AER_FLAGS))
-                PCI_EXP_DEVCTL_CERE |
-                PCI_EXP_DEVCTL_NFERE |
-                PCI_EXP_DEVCTL_FERE |
-                PCI_EXP_DEVCTL_URRE)))
                return false;
        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
        if (!pos)
                return false;
@@ -465,7 +434,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
        if (driver && driver->reset_link) {
                status = driver->reset_link(udev);
-        } else if (udev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
+        } else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM) {
                status = default_downstream_reset_link(udev);
        } else {
                dev_printk(KERN_DEBUG, &dev->dev,
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index b500840a143b..213753b283a6 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -125,21 +125,16 @@ static int policy_to_clkpm_state(struct pcie_link_state *link)
 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
 {
-        int pos;
-        u16 reg16;
        struct pci_dev *child;
        struct pci_bus *linkbus = link->pdev->subordinate;
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-                pos = pci_pcie_cap(child);
-                if (!pos)
-                        return;
-                pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16);
                if (enable)
-                        reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
+                        pcie_capability_set_word(child, PCI_EXP_LNKCTL,
+                                                 PCI_EXP_LNKCTL_CLKREQ_EN);
                else
-                        reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
+                        pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
-                pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16);
+                                                   PCI_EXP_LNKCTL_CLKREQ_EN);
        }
        link->clkpm_enabled = !!enable;
 }
@@ -157,7 +152,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
 {
-        int pos, capable = 1, enabled = 1;
+        int capable = 1, enabled = 1;
        u32 reg32;
        u16 reg16;
        struct pci_dev *child;
@@ -165,16 +160,13 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
        /* All functions should have the same cap and state, take the worst */
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-                pos = pci_pcie_cap(child);
+                pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
-                if (!pos)
-                        return;
-                pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, &reg32);
                if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
                        capable = 0;
                        enabled = 0;
                        break;
                }
-                pci_read_config_word(child, pos + PCI_EXP_LNKCTL, &reg16);
+                pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
                if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
                        enabled = 0;
        }
@@ -190,7 +182,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
 */
 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
 {
-        int ppos, cpos, same_clock = 1;
+        int same_clock = 1;
        u16 reg16, parent_reg, child_reg[8];
        unsigned long start_jiffies;
        struct pci_dev *child, *parent = link->pdev;
@@ -203,46 +195,43 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
        BUG_ON(!pci_is_pcie(child));
        /* Check downstream component if bit Slot Clock Configuration is 1 */
-        cpos = pci_pcie_cap(child);
+        pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
-        pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, &reg16);
        if (!(reg16 & PCI_EXP_LNKSTA_SLC))
                same_clock = 0;
        /* Check upstream component if bit Slot Clock Configuration is 1 */
-        ppos = pci_pcie_cap(parent);
+        pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
-        pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16);
        if (!(reg16 & PCI_EXP_LNKSTA_SLC))
                same_clock = 0;
        /* Configure downstream component, all functions */
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-                cpos = pci_pcie_cap(child);
+                pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
-                pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, &reg16);
                child_reg[PCI_FUNC(child->devfn)] = reg16;
                if (same_clock)
                        reg16 |= PCI_EXP_LNKCTL_CCC;
                else
                        reg16 &= ~PCI_EXP_LNKCTL_CCC;
-                pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16);
+                pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
        }
        /* Configure upstream component */
-        pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, &reg16);
+        pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
        parent_reg = reg16;
        if (same_clock)
                reg16 |= PCI_EXP_LNKCTL_CCC;
        else
                reg16 &= ~PCI_EXP_LNKCTL_CCC;
-        pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
+        pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
        /* Retrain link */
        reg16 |= PCI_EXP_LNKCTL_RL;
-        pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16);
+        pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
        /* Wait for link training end. Break out after waiting for timeout */
        start_jiffies = jiffies;
        for (;;) {
-                pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, &reg16);
+                pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
                if (!(reg16 & PCI_EXP_LNKSTA_LT))
                        break;
                if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
@@ -255,12 +244,10 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
        /* Training failed. Restore common clock configurations */
        dev_printk(KERN_ERR, &parent->dev,
                   "ASPM: Could not configure common clock\n");
-        list_for_each_entry(child, &linkbus->devices, bus_list) {
+        list_for_each_entry(child, &linkbus->devices, bus_list)
-                cpos = pci_pcie_cap(child);
+                pcie_capability_write_word(child, PCI_EXP_LNKCTL,
-                pci_write_config_word(child, cpos + PCI_EXP_LNKCTL,
+                                           child_reg[PCI_FUNC(child->devfn)]);
-                                      child_reg[PCI_FUNC(child->devfn)]);
+        pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
-        }
-        pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg);
 }
 /* Convert L0s latency encoding to ns */
@@ -305,16 +292,14 @@ struct aspm_register_info {
 static void pcie_get_aspm_reg(struct pci_dev *pdev,
                              struct aspm_register_info *info)
 {
-        int pos;
        u16 reg16;
        u32 reg32;
-        pos = pci_pcie_cap(pdev);
+        pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32);
-        pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &reg32);
        info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
        info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
        info->latency_encoding_l1  = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
-        pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
+        pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &reg16);
        info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
 }
@@ -412,7 +397,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
         * do ASPM for now.
         */
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-                if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
+                if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
                        link->aspm_disable = ASPM_STATE_ALL;
                        break;
                }
@@ -420,17 +405,15 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
        /* Get and check endpoint acceptable latencies */
        list_for_each_entry(child, &linkbus->devices, bus_list) {
-                int pos;
                u32 reg32, encoding;
                struct aspm_latency *acceptable =
                        &link->acceptable[PCI_FUNC(child->devfn)];
-                if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
+                if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
-                    child->pcie_type != PCI_EXP_TYPE_LEG_END)
+                    pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
                        continue;
-                pos = pci_pcie_cap(child);
+                pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
-                pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32);
                /* Calculate endpoint L0s acceptable latency */
                encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
                acceptable->l0s = calc_l0s_acceptable(encoding);
@@ -444,13 +427,7 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
 {
-        u16 reg16;
+        pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, 0x3, val);
-        int pos = pci_pcie_cap(pdev);
-        pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
-        reg16 &= ~0x3;
-        reg16 |= val;
-        pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
 }
 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
@@ -505,7 +482,6 @@ static void free_link_state(struct pcie_link_state *link)
 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 {
        struct pci_dev *child;
-        int pos;
        u32 reg32;
        /*
@@ -513,8 +489,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
         * very strange. Disable ASPM for the whole slot
         */
        list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
-                pos = pci_pcie_cap(child);
+                if (!pci_is_pcie(child))
-                if (!pos)
                        return -EINVAL;
                /*
@@ -530,7 +505,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
                 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
                 * RBER bit to determine if a function is 1.1 version device
                 */
-                pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, &reg32);
+                pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
                if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
                        dev_printk(KERN_INFO, &child->dev, "disabling ASPM"
                                " on pre-1.1 PCIe device.  You can enable it"
@@ -552,7 +527,7 @@ static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
        INIT_LIST_HEAD(&link->children);
        INIT_LIST_HEAD(&link->link);
        link->pdev = pdev;
-        if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) {
+        if (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM) {
                struct pcie_link_state *parent;
                parent = pdev->bus->parent->self->link_state;
                if (!parent) {
@@ -585,12 +560,12 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
        if (!pci_is_pcie(pdev) || pdev->link_state)
                return;
-        if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+        if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
-            pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
+            pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
                return;
        /* VIA has a strange chipset, root port is under a bridge */
-        if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT &&
+        if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
            pdev->bus->self)
                return;
@@ -647,8 +622,8 @@ static void pcie_update_aspm_capable(struct pcie_link_state *root)
                if (link->root != root)
                        continue;
                list_for_each_entry(child, &linkbus->devices, bus_list) {
-                        if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) &&
+                        if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
-                            (child->pcie_type != PCI_EXP_TYPE_LEG_END))
+                            (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
                                continue;
                        pcie_aspm_check_latency(child);
                }
@@ -663,8 +638,8 @@ void pcie_aspm_exit_link_state(struct pci_dev *pdev)
        if (!pci_is_pcie(pdev) || !parent || !parent->link_state)
                return;
-        if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
+        if ((pci_pcie_type(parent) != PCI_EXP_TYPE_ROOT_PORT) &&
-            (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
+            (pci_pcie_type(parent) != PCI_EXP_TYPE_DOWNSTREAM))
                return;
        down_read(&pci_bus_sem);
@@ -704,8 +679,8 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev)
        if (aspm_disabled || !pci_is_pcie(pdev) || !link)
                return;
-        if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
+        if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
-            (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
+            (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
                return;
        /*
         * Devices changed PM state, we should recheck if latency
@@ -729,8 +704,8 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
        if (aspm_policy != POLICY_POWERSAVE)
                return;
-        if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
+        if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) &&
-            (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
+            (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
                return;
        down_read(&pci_bus_sem);
@@ -757,8 +732,8 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem,
        if (!pci_is_pcie(pdev))
                return;
-        if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
+        if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
-            pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
+            pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)
                parent = pdev;
        if (!parent || !parent->link_state)
                return;
@@ -933,8 +908,8 @@ void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
        struct pcie_link_state *link_state = pdev->link_state;
        if (!pci_is_pcie(pdev) ||
-            (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+            (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
-             pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
+             pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
                return;
        if (link_state->aspm_support)
@@ -950,8 +925,8 @@ void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
        struct pcie_link_state *link_state = pdev->link_state;
        if (!pci_is_pcie(pdev) ||
-            (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
+            (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
-             pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
+             pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) || !link_state)
                return;
        if (link_state->aspm_support)
diff --git a/drivers/pci/pcie/pme.c b/drivers/pci/pcie/pme.c
index 001f1b78f39c..9ca0dc9ffd84 100644
--- a/drivers/pci/pcie/pme.c
+++ b/drivers/pci/pcie/pme.c
@@ -57,17 +57,12 @@ struct pcie_pme_service_data {
 */
 void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable)
 {
-        int rtctl_pos;
-        u16 rtctl;
-        rtctl_pos = pci_pcie_cap(dev) + PCI_EXP_RTCTL;
-        pci_read_config_word(dev, rtctl_pos, &rtctl);
        if (enable)
-                rtctl |= PCI_EXP_RTCTL_PMEIE;
+                pcie_capability_set_word(dev, PCI_EXP_RTCTL,
+                                         PCI_EXP_RTCTL_PMEIE);
        else
-                rtctl &= ~PCI_EXP_RTCTL_PMEIE;
+                pcie_capability_clear_word(dev, PCI_EXP_RTCTL,
-        pci_write_config_word(dev, rtctl_pos, rtctl);
+                                           PCI_EXP_RTCTL_PMEIE);
 }
 /**
@@ -120,7 +115,7 @@ static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn)
        if (!dev)
                return false;
-        if (pci_is_pcie(dev) && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
+        if (pci_is_pcie(dev) && pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
                down_read(&pci_bus_sem);
                if (pcie_pme_walk_bus(bus))
                        found = true;
@@ -226,18 +221,15 @@ static void pcie_pme_work_fn(struct work_struct *work)
        struct pcie_pme_service_data *data =
                        container_of(work, struct pcie_pme_service_data, work);
        struct pci_dev *port = data->srv->port;
-        int rtsta_pos;
        u32 rtsta;
-        rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
        spin_lock_irq(&data->lock);
        for (;;) {
                if (data->noirq)
                        break;
-                pci_read_config_dword(port, rtsta_pos, &rtsta);
+                pcie_capability_read_dword(port, PCI_EXP_RTSTA, &rtsta);
                if (rtsta & PCI_EXP_RTSTA_PME) {
                        /*
                         * Clear PME status of the port.  If there are other
@@ -276,17 +268,14 @@ static irqreturn_t pcie_pme_irq(int irq, void *context)
 {
        struct pci_dev *port;
        struct pcie_pme_service_data *data;
-        int rtsta_pos;
        u32 rtsta;
        unsigned long flags;
        port = ((struct pcie_device *)context)->port;
        data = get_service_data((struct pcie_device *)context);
-        rtsta_pos = pci_pcie_cap(port) + PCI_EXP_RTSTA;
        spin_lock_irqsave(&data->lock, flags);
-        pci_read_config_dword(port, rtsta_pos, &rtsta);
+        pcie_capability_read_dword(port, PCI_EXP_RTSTA, &rtsta);
        if (!(rtsta & PCI_EXP_RTSTA_PME)) {
                spin_unlock_irqrestore(&data->lock, flags);
@@ -335,13 +324,13 @@ static void pcie_pme_mark_devices(struct pci_dev *port)
                struct pci_dev *dev;
                /* Check if this is a root port event collector. */
-                if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus)
+                if (pci_pcie_type(port) != PCI_EXP_TYPE_RC_EC || !bus)
                        return;
                down_read(&pci_bus_sem);
                list_for_each_entry(dev, &bus->devices, bus_list)
                        if (pci_is_pcie(dev)
-                            && dev->pcie_type == PCI_EXP_TYPE_RC_END)
+                            && pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)
                                pcie_pme_set_native(dev, NULL);
                up_read(&pci_bus_sem);
        }
diff --git a/drivers/pci/pcie/portdrv_bus.c b/drivers/pci/pcie/portdrv_bus.c
index 18bf90f748f6..67be55a7f260 100644
--- a/drivers/pci/pcie/portdrv_bus.c
+++ b/drivers/pci/pcie/portdrv_bus.c
@@ -38,7 +38,7 @@ static int pcie_port_bus_match(struct device *dev, struct device_driver *drv)
                return 0;
        if ((driver->port_type != PCIE_ANY_PORT) &&
-            (driver->port_type != pciedev->port->pcie_type))
+            (driver->port_type != pci_pcie_type(pciedev->port)))
                return 0;
        return 1;
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 75915b30ad19..aede99171e90 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -246,8 +246,7 @@ static void cleanup_service_irqs(struct pci_dev *dev)
 */
 static int get_port_device_capability(struct pci_dev *dev)
 {
-        int services = 0, pos;
+        int services = 0;
-        u16 reg16;
        u32 reg32;
        int cap_mask = 0;
        int err;
@@ -265,11 +264,9 @@ static int get_port_device_capability(struct pci_dev *dev)
                        return 0;
        }
-        pos = pci_pcie_cap(dev);
-        pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
        /* Hot-Plug Capable */
-        if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) {
+        if (cap_mask & PCIE_PORT_SERVICE_HP) {
-                pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, &reg32);
+                pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, &reg32);
                if (reg32 & PCI_EXP_SLTCAP_HPC) {
                        services |= PCIE_PORT_SERVICE_HP;
                        /*
@@ -277,10 +274,8 @@ static int get_port_device_capability(struct pci_dev *dev)
                         * enabled by the BIOS and the hot-plug service driver
                         * is not loaded.
                         */
-                        pos += PCI_EXP_SLTCTL;
+                        pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
-                        pci_read_config_word(dev, pos, &reg16);
+                                PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
-                        reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
-                        pci_write_config_word(dev, pos, reg16);
                }
        }
        /* AER capable */
@@ -298,7 +293,7 @@ static int get_port_device_capability(struct pci_dev *dev)
                services |= PCIE_PORT_SERVICE_VC;
        /* Root ports are capable of generating PME too */
        if ((cap_mask & PCIE_PORT_SERVICE_PME)
-            && dev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
+            && pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
                services |= PCIE_PORT_SERVICE_PME;
                /*
                 * Disable PME interrupt on this port in case it's been enabled
@@ -336,7 +331,7 @@ static int pcie_device_init(struct pci_dev *pdev, int service, int irq)
        device->release = release_pcie_device;  /* callback to free pcie dev */
        dev_set_name(device, "%s:pcie%02x",
                     pci_name(pdev),
-                     get_descriptor_id(pdev->pcie_type, service));
+                     get_descriptor_id(pci_pcie_type(pdev), service));
        device->parent = &pdev->dev;
        device_enable_async_suspend(device);
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 3a7eefcb270a..2360330e48f1 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -64,14 +64,7 @@ __setup("pcie_ports=", pcie_port_setup);
 */
 void pcie_clear_root_pme_status(struct pci_dev *dev)
 {
-        int rtsta_pos;
+        pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
-        u32 rtsta;
-        rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
-        pci_read_config_dword(dev, rtsta_pos, &rtsta);
-        rtsta |= PCI_EXP_RTSTA_PME;
-        pci_write_config_dword(dev, rtsta_pos, rtsta);
 }
 static int pcie_portdrv_restore_config(struct pci_dev *dev)
@@ -95,7 +88,7 @@ static int pcie_port_resume_noirq(struct device *dev)
         * which breaks ACPI-based runtime wakeup on PCI Express, so clear those
         * bits now just in case (shouldn't hurt).
         */
-        if(pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
+        if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
                pcie_clear_root_pme_status(pdev);
        return 0;
 }
@@ -186,9 +179,9 @@ static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
        int status;
        if (!pci_is_pcie(dev) ||
-            ((dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
+            ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
-             (dev->pcie_type != PCI_EXP_TYPE_UPSTREAM) &&
+             (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) &&
-             (dev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)))
+             (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
                return -ENODEV;
        if (!dev->irq && dev->pin) {
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 6c143b4497ca..d8f513bdf95c 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -603,10 +603,10 @@ static void pci_set_bus_speed(struct pci_bus *bus)
                u32 linkcap;
                u16 linksta;
-                pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
+                pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
                bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
-                pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
+                pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
                pcie_update_link_speed(bus, linksta);
        }
 }
@@ -929,24 +929,16 @@ void set_pcie_port_type(struct pci_dev *pdev)
        pdev->is_pcie = 1;
        pdev->pcie_cap = pos;
        pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
-        pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
+        pdev->pcie_flags_reg = reg16;
        pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
        pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
 }
 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
 {
-        int pos;
-        u16 reg16;
        u32 reg32;
-        pos = pci_pcie_cap(pdev);
+        pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
-        if (!pos)
-                return;
-        pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
-        if (!(reg16 & PCI_EXP_FLAGS_SLOT))
-                return;
-        pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
        if (reg32 & PCI_EXP_SLTCAP_HPC)
                pdev->is_hotplug_bridge = 1;
 }
@@ -1160,8 +1152,7 @@ int pci_cfg_space_size(struct pci_dev *dev)
        if (class == PCI_CLASS_BRIDGE_HOST)
                return pci_cfg_space_size_ext(dev);
-        pos = pci_pcie_cap(dev);
+        if (!pci_is_pcie(dev)) {
-        if (!pos) {
                pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
                if (!pos)
                        goto fail;
@@ -1383,9 +1374,9 @@ static int only_one_child(struct pci_bus *bus)
        if (!parent || !pci_is_pcie(parent))
                return 0;
-        if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
+        if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
                return 1;
-        if (parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM &&
+        if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
            !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
                return 1;
        return 0;
@@ -1462,7 +1453,7 @@ static int pcie_find_smpss(struct pci_dev *dev, void *data)
         */
        if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
             (dev->bus->self &&
-              dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
+              pci_pcie_type(dev->bus->self) != PCI_EXP_TYPE_ROOT_PORT)))
                *smpss = 0;
        if (*smpss > dev->pcie_mpss)
@@ -1478,7 +1469,8 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
        if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
                mps = 128 << dev->pcie_mpss;
-                if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
+                if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
+                    dev->bus->self)
                        /* For "Performance", the assumption is made that
                         * downstream communication will never be larger than
                         * the MRRS.  So, the MPS only needs to be configured
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 51553179e967..7a451ff56ecc 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3081,17 +3081,36 @@ static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
 {
-        int pos;
+        int i;
+        u16 status;
-        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+        /*
-        if (!pos)
+         * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
-                return -ENOTTY;
+         *
+         * The 82599 supports FLR on VFs, but FLR support is reported only
+         * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
+         * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
+         */
        if (probe)
                return 0;
-        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
+        /* Wait for Transaction Pending bit clean */
-                                PCI_EXP_DEVCTL_BCR_FLR);
+        for (i = 0; i < 4; i++) {
+                if (i)
+                        msleep((1 << (i - 1)) * 100);
+                pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
+                if (!(status & PCI_EXP_DEVSTA_TRPND))
+                        goto clear;
+        }
+        dev_err(&dev->dev, "transaction is not cleared; "
+                        "proceeding with reset anyway\n");
+clear:
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
        msleep(100);
        return 0;
diff --git a/drivers/pci/search.c b/drivers/pci/search.c
index 993d4a0a2469..621b162ceb69 100644
--- a/drivers/pci/search.c
+++ b/drivers/pci/search.c
@@ -41,7 +41,7 @@ pci_find_upstream_pcie_bridge(struct pci_dev *pdev)
                        continue;
                }
                /* PCI device should connect to a PCIe bridge */
-                if (pdev->pcie_type != PCI_EXP_TYPE_PCI_BRIDGE) {
+                if (pci_pcie_type(pdev) != PCI_EXP_TYPE_PCI_BRIDGE) {
                        /* Busted hardware? */
                        WARN_ON_ONCE(1);
                        return NULL;
diff --git a/drivers/rapidio/devices/tsi721.c b/drivers/rapidio/devices/tsi721.c
index 722246cf20ab..fc22b93e0924 100644
--- a/drivers/rapidio/devices/tsi721.c
+++ b/drivers/rapidio/devices/tsi721.c
@@ -2212,9 +2212,8 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
                                  const struct pci_device_id *id)
 {
        struct tsi721_device *priv;
-        int i, cap;
+        int i;
        int err;
-        u32 regval;
        priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL);
        if (priv == NULL) {
@@ -2320,20 +2319,16 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
                        dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
        }
-        cap = pci_pcie_cap(pdev);
+        BUG_ON(!pci_is_pcie(pdev));
-        BUG_ON(cap == 0);
        /* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
-        pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &regval);
+        pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
-        regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
+                PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
-                    PCI_EXP_DEVCTL_NOSNOOP_EN);
+                PCI_EXP_DEVCTL_NOSNOOP_EN,
-        regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT;
+                0x2 << MAX_READ_REQUEST_SZ_SHIFT);
-        pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval);
        /* Adjust PCIe completion timeout. */
-        pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, &regval);
+        pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2, 0xf, 0x2);
-        regval &= ~(0x0f);
-        pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2);
        /*
         * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c
index 9ce3a8f8754f..7cfdf2bd8edb 100644
--- a/drivers/scsi/qla2xxx/qla_nx.c
+++ b/drivers/scsi/qla2xxx/qla_nx.c
@@ -1615,13 +1615,11 @@ qla82xx_get_fw_offs(struct qla_hw_data *ha)
 char *
 qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str)
 {
-        int pcie_reg;
        struct qla_hw_data *ha = vha->hw;
        char lwstr[6];
        uint16_t lnk;
-        pcie_reg = pci_pcie_cap(ha->pdev);
+        pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
-        pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk);
        ha->link_width = (lnk >> 4) & 0x3f;
        strcpy(str, "PCIe (");
@@ -2497,7 +2495,6 @@ fw_load_failed:
 int
 qla82xx_start_firmware(scsi_qla_host_t *vha)
 {
-        int           pcie_cap;
        uint16_t      lnk;
        struct qla_hw_data *ha = vha->hw;
@@ -2528,8 +2525,7 @@ qla82xx_start_firmware(scsi_qla_host_t *vha)
        }
        /* Negotiated Link width */
-        pcie_cap = pci_pcie_cap(ha->pdev);
+        pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
-        pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
        ha->link_width = (lnk >> 4) & 0x3f;
        /* Synchronize with Receive peg */
diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c
index 939d7261c37a..807bf76f1b6a 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.c
+++ b/drivers/scsi/qla4xxx/ql4_nx.c
@@ -1566,7 +1566,6 @@ qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
 static int
 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
 {
-        int pcie_cap;
        uint16_t lnk;
        /* scrub dma mask expansion register */
@@ -1590,8 +1589,7 @@ qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
        }
        /* Negotiated Link width */
-        pcie_cap = pci_pcie_cap(ha->pdev);
+        pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
-        pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
        ha->link_width = (lnk >> 4) & 0x3f;
        /* Synchronize with Receive peg */
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 029725c89e58..49553f88c7b3 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -3995,16 +3995,14 @@ static void et131x_hwaddr_init(struct et131x_adapter *adapter)
 static int et131x_pci_init(struct et131x_adapter *adapter,
                                                struct pci_dev *pdev)
 {
-        int cap = pci_pcie_cap(pdev);
        u16 max_payload;
-        u16 ctl;
        int i, rc;
        rc = et131x_init_eeprom(adapter);
        if (rc < 0)
                goto out;
-        if (!cap) {
+        if (!pci_is_pcie(pdev)) {
                dev_err(&pdev->dev, "Missing PCIe capabilities\n");
                goto err_out;
        }
@@ -4012,7 +4010,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
        /* Let's set up the PORT LOGIC Register.  First we need to know what
         * the max_payload_size is
         */
-        if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCAP, &max_payload)) {
+        if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
                dev_err(&pdev->dev,
                    "Could not read PCI config space for Max Payload Size\n");
                goto err_out;
@@ -4049,17 +4047,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
        }
        /* Change the max read size to 2k */
-        if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl)) {
+        if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
+                                PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
                dev_err(&pdev->dev,
-                        "Could not read PCI config space for Max read size\n");
+                        "Couldn't change PCI config space for Max read size\n");
-                goto err_out;
-        }
-        ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | (0x04 << 12);
-        if (pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl)) {
-                dev_err(&pdev->dev,
-                      "Could not write PCI config space for Max read size\n");
                goto err_out;
        }
diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c
index ddadcc3e4e7c..5abbee37cdca 100644
--- a/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c
+++ b/drivers/staging/rtl8192e/rtl8192e/rtl_pci.c
@@ -31,12 +31,10 @@ static void rtl8192_parse_pci_configuration(struct pci_dev *pdev,
        struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
        u8 tmp;
-        int pos;
+        u16 LinkCtrlReg;
-        u8 LinkCtrlReg;
-        pos = pci_find_capability(priv->pdev, PCI_CAP_ID_EXP);
+        pcie_capability_read_word(priv->pdev, PCI_EXP_LNKCTL, &LinkCtrlReg);
-        pci_read_config_byte(priv->pdev, pos + PCI_EXP_LNKCTL, &LinkCtrlReg);
+        priv->NdisAdapter.LinkCtrlReg = (u8)LinkCtrlReg;
-        priv->NdisAdapter.LinkCtrlReg = LinkCtrlReg;
        RT_TRACE(COMP_INIT, "Link Control Register =%x\n",
                 priv->NdisAdapter.LinkCtrlReg);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 5faa8310eec9..b8667e0548e0 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -254,10 +254,10 @@ struct pci_dev {
        u8              revision;       /* PCI revision, low byte of class word */
        u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
        u8              pcie_cap;       /* PCI-E capability offset */
-        u8              pcie_type:4;    /* PCI-E device/port type */
        u8              pcie_mpss:3;    /* PCI-E Max Payload Size Supported */
        u8              rom_base_reg;   /* which config register controls the ROM */
        u8              pin;            /* which interrupt pin this device uses */
+        u16             pcie_flags_reg; /* cached PCI-E Capabilities Register */
        struct pci_driver *driver;      /* which driver has allocated this device */
        u64             dma_mask;       /* Mask of the bits of bus address this
@@ -816,6 +816,39 @@ static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
        return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
 }
+int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
+int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
+int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
+int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
+int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
+                                       u16 clear, u16 set);
+int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
+                                        u32 clear, u32 set);
+static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
+                                           u16 set)
+{
+        return pcie_capability_clear_and_set_word(dev, pos, 0, set);
+}
+static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
+                                            u32 set)
+{
+        return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
+}
+static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
+                                             u16 clear)
+{
+        return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
+}
+static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
+                                              u32 clear)
+{
+        return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
+}
 /* user-space driven config access */
 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
@@ -1650,6 +1683,15 @@ static inline bool pci_is_pcie(struct pci_dev *dev)
        return !!pci_pcie_cap(dev);
 }
+/**
+ * pci_pcie_type - get the PCIe device/port type
+ * @dev: PCI device
+ */
+static inline int pci_pcie_type(const struct pci_dev *dev)
+{
+        return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
+}
 void pci_request_acs(void);
 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
 bool pci_acs_path_enabled(struct pci_dev *start,
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 7fb75b143755..3958f70f3202 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -549,6 +549,7 @@
 #define  PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
 #define  PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
 #define PCI_EXP_LNKCTL2         48      /* Link Control 2 */
+#define PCI_EXP_LNKSTA2         50      /* Link Status 2 */
 #define PCI_EXP_SLTCTL2         56      /* Slot Control 2 */
 /* Extended Capabilities (PCI-X 2.0 and Express) */
author	Bjorn Helgaas <bhelgaas@google.com>	2012-08-23 20:31:58 -0400
committer	Bjorn Helgaas <bhelgaas@google.com>	2012-08-23 20:31:58 -0400
commit	e1c171b86baaccab983ded5dfa1663c0981d2520 (patch)
tree	648ad71d7bd2838678f66d055fcaae654b5e4ddc
parent	0d7614f09c1ebdbaa1599a5aba7593f147bf96ee (diff)
parent	479e0d485eaab452cf248cd1a9520015023b35b2 (diff)