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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-10-09 12:37:15 -0400
committerJani Nikula <jani.nikula@intel.com>2014-10-16 07:58:44 -0400
commite17ac6db2ef99388b750b2141c11974dc5742913 (patch)
tree2febcd0c30a88a3e2f78b9903442e092f7b5af3b
parent1180e20606fd7c5d76dc5b2a1594fa51ba5a0f31 (diff)
drm/i915: Don't trust the DP_DETECT bit for eDP ports on CHV
On CHV the display DDC pins may be muxed to an alternate function if there's no need for DDC on a specific port, which is the case for eDP ports since there's no way to plug in a DP++ HDMI dongle. This causes problems when trying to determine if the port is present since the the DP_DETECTED bit is the latched state of the DDC SDA pin at boot. If the DDC pins are muxed to an alternate function the bit may indicate that the port isn't present. To work around this look at the VBT as well as the DP_DETECTED bit to determine if we should attempt registering an eDP port. Do this only for ports B and C since port D doesn't support eDP (no PPS/BLC). In theory someone could also wire up a normal DP port w/o DDC lines. That would just mean that simple DP++ HDMI dongles wouldn't work on such a port. With this change we would still fail to register such DP ports. But let's hope no one wires their board in such a way, and if they do we can extend the VBT checks to cover normal DP ports as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84265 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c33
1 files changed, 21 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6a0cc367934d..c9e220963a78 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12354,27 +12354,36 @@ static void intel_setup_outputs(struct drm_device *dev)
12354 if (I915_READ(PCH_DP_D) & DP_DETECTED) 12354 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12355 intel_dp_init(dev, PCH_DP_D, PORT_D); 12355 intel_dp_init(dev, PCH_DP_D, PORT_D);
12356 } else if (IS_VALLEYVIEW(dev)) { 12356 } else if (IS_VALLEYVIEW(dev)) {
12357 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { 12357 /*
12358 * The DP_DETECTED bit is the latched state of the DDC
12359 * SDA pin at boot. However since eDP doesn't require DDC
12360 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12361 * eDP ports may have been muxed to an alternate function.
12362 * Thus we can't rely on the DP_DETECTED bit alone to detect
12363 * eDP ports. Consult the VBT as well as DP_DETECTED to
12364 * detect eDP ports.
12365 */
12366 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12358 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, 12367 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12359 PORT_B); 12368 PORT_B);
12360 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) 12369 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12361 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); 12370 intel_dp_is_edp(dev, PORT_B))
12362 } 12371 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12363 12372
12364 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { 12373 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12365 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, 12374 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12366 PORT_C); 12375 PORT_C);
12367 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) 12376 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12368 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); 12377 intel_dp_is_edp(dev, PORT_C))
12369 } 12378 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12370 12379
12371 if (IS_CHERRYVIEW(dev)) { 12380 if (IS_CHERRYVIEW(dev)) {
12372 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { 12381 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12373 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, 12382 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12374 PORT_D); 12383 PORT_D);
12375 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) 12384 /* eDP not supported on port D, so don't check VBT */
12376 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); 12385 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12377 } 12386 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12378 } 12387 }
12379 12388
12380 intel_dsi_init(dev); 12389 intel_dsi_init(dev);