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authorMaruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>2015-12-04 18:40:32 -0500
committerMark Brown <broonie@kernel.org>2015-12-07 14:52:02 -0500
commite164835a0270cc01c93794536027cc70cd00d0ff (patch)
tree013e6b1801609cad415e69c20ed3988967d0de99
parentf48303122d2fd94b719e546cf8a39d412c7eee69 (diff)
ASoC: dwc: add quirk for different register offset
DWC in ACP 2.x IP has different offsets for I2S_COMP_PARAM_* registers. Added a quirk to support the same. Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--include/sound/designware_i2s.h5
-rw-r--r--sound/soc/dwc/designware_i2s.c17
2 files changed, 19 insertions, 3 deletions
diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h
index 8966ba7c9629..e0bb45807f29 100644
--- a/include/sound/designware_i2s.h
+++ b/include/sound/designware_i2s.h
@@ -45,6 +45,11 @@ struct i2s_platform_data {
45 u32 snd_fmts; 45 u32 snd_fmts;
46 u32 snd_rates; 46 u32 snd_rates;
47 47
48 #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0)
49 unsigned int quirks;
50 unsigned int i2s_reg_comp1;
51 unsigned int i2s_reg_comp2;
52
48 void *play_dma_data; 53 void *play_dma_data;
49 void *capture_dma_data; 54 void *capture_dma_data;
50 bool (*filter)(struct dma_chan *chan, void *slave); 55 bool (*filter)(struct dma_chan *chan, void *slave);
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c
index 3d7754c115ec..940c88136a34 100644
--- a/sound/soc/dwc/designware_i2s.c
+++ b/sound/soc/dwc/designware_i2s.c
@@ -94,6 +94,9 @@ struct dw_i2s_dev {
94 struct clk *clk; 94 struct clk *clk;
95 int active; 95 int active;
96 unsigned int capability; 96 unsigned int capability;
97 unsigned int quirks;
98 unsigned int i2s_reg_comp1;
99 unsigned int i2s_reg_comp2;
97 struct device *dev; 100 struct device *dev;
98 101
99 /* data related to DMA transfers b/w i2s and DMAC */ 102 /* data related to DMA transfers b/w i2s and DMAC */
@@ -477,8 +480,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev,
477 * Read component parameter registers to extract 480 * Read component parameter registers to extract
478 * the I2S block's configuration. 481 * the I2S block's configuration.
479 */ 482 */
480 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); 483 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
481 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 484 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
482 u32 idx; 485 u32 idx;
483 486
484 if (COMP1_TX_ENABLED(comp1)) { 487 if (COMP1_TX_ENABLED(comp1)) {
@@ -521,7 +524,7 @@ static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
521 struct resource *res, 524 struct resource *res,
522 const struct i2s_platform_data *pdata) 525 const struct i2s_platform_data *pdata)
523{ 526{
524 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); 527 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
525 u32 idx = COMP1_APB_DATA_WIDTH(comp1); 528 u32 idx = COMP1_APB_DATA_WIDTH(comp1);
526 int ret; 529 int ret;
527 530
@@ -625,6 +628,14 @@ static int dw_i2s_probe(struct platform_device *pdev)
625 if (pdata) { 628 if (pdata) {
626 dev->capability = pdata->cap; 629 dev->capability = pdata->cap;
627 clk_id = NULL; 630 clk_id = NULL;
631 dev->quirks = pdata->quirks;
632 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
633 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
634 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
635 } else {
636 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
637 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
638 }
628 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); 639 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
629 } else { 640 } else {
630 clk_id = "i2sclk"; 641 clk_id = "i2sclk";