drm/i915/gvt: Align render mmio list to cacheline

Make the global mmio list be cacheline aligned to improve performance.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index e24e57afc45e..679411fe653f 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -44,7 +44,7 @@ struct render_mmio {
         u32 value;
 };
 
-static struct render_mmio gen8_render_mmio_list[] = {
+static struct render_mmio gen8_render_mmio_list[] __cacheline_aligned = {
         {RCS, _MMIO(0x229c), 0xffff, false},
         {RCS, _MMIO(0x2248), 0x0, false},
         {RCS, _MMIO(0x2098), 0x0, false},
@@ -75,7 +75,7 @@ static struct render_mmio gen8_render_mmio_list[] = {
         {BCS, _MMIO(0x22028), 0x0, false},
 };
 
-static struct render_mmio gen9_render_mmio_list[] = {
+static struct render_mmio gen9_render_mmio_list[] __cacheline_aligned = {
         {RCS, _MMIO(0x229c), 0xffff, false},
         {RCS, _MMIO(0x2248), 0x0, false},
         {RCS, _MMIO(0x2098), 0x0, false},