Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-next

New stuff for 5.1.
amdgpu:
- DC bandwidth formula updates
- Support for DCC on scanout surfaces
- Support for multiple IH rings on soc15 asics
- Fix xgmi locking
- Add sysfs interface to get pcie usage stats
- Simplify DC i2c/aux code
- Initial support for BACO on vega10/20
- New runtime SMU feature debug interface
- Expand existing sysfs power interfaces to new clock domains
- Handle kexec properly
- Simplify IH programming
- Rework doorbell handling across asics
- Drop old CI DPM implementation
- DC page flipping fixes
- Misc SR-IOV fixes

amdkfd:
- Simplify the interfaces between amdkfd and amdgpu

ttm:
- Add a callback to notify the driver when the lru changes

sched:
- Refactor mirror list handling
- Rework hw fence processing

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190125231517.26268-1-alexander.deucher@amd.com

253 files changed, 6565 insertions, 18723 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index f76bcb9c45e4..466da5954a68 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -57,7 +57,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
 
 # add asic specific block
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
-        ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
+        dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o
 
 amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bcef6ea4bcf9..9efa681d0878 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -542,6 +542,11 @@ struct amdgpu_asic_funcs {
         bool (*need_full_reset)(struct amdgpu_device *adev);
         /* initialize doorbell layout for specific asic*/
         void (*init_doorbell_index)(struct amdgpu_device *adev);
+        /* PCIe bandwidth usage */
+        void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
+                               uint64_t *count1);
+        /* do we need to reset the asic at init time (e.g., kexec) */
+        bool (*need_reset_on_init)(struct amdgpu_device *adev);
 };
 
 /*
@@ -634,7 +639,7 @@ struct amdgpu_nbio_funcs {
         void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
         u32 (*get_memsize)(struct amdgpu_device *adev);
         void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
-                                    bool use_doorbell, int doorbell_index);
+                        bool use_doorbell, int doorbell_index, int doorbell_size);
         void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
                                          bool enable);
         void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
@@ -1042,6 +1047,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
+#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
+#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
 
 /* Common functions */
 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 2dfaf158ef07..e957e42c539a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -28,8 +28,6 @@
 #include <linux/module.h>
 #include <linux/dma-buf.h>
 
-const struct kgd2kfd_calls *kgd2kfd;
-
 static const unsigned int compute_vmid_bitmap = 0xFF00;
 
 /* Total memory size in system memory and all GPU VRAM. Used to
@@ -47,12 +45,9 @@ int amdgpu_amdkfd_init(void)
         amdgpu_amdkfd_total_mem_size *= si.mem_unit;
 
 #ifdef CONFIG_HSA_AMD
-        ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
-        if (ret)
-                kgd2kfd = NULL;
+        ret = kgd2kfd_init();
         amdgpu_amdkfd_gpuvm_init_mem_limits();
 #else
-        kgd2kfd = NULL;
         ret = -ENOENT;
 #endif
 
@@ -61,17 +56,13 @@ int amdgpu_amdkfd_init(void)
 
 void amdgpu_amdkfd_fini(void)
 {
-        if (kgd2kfd)
-                kgd2kfd->exit();
+        kgd2kfd_exit();
 }
 
 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
 {
         const struct kfd2kgd_calls *kfd2kgd;
 
-        if (!kgd2kfd)
-                return;
-
         switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
         case CHIP_KAVERI:
@@ -98,8 +89,8 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
                 return;
         }
 
-        adev->kfd.dev = kgd2kfd->probe((struct kgd_dev *)adev,
-                                       adev->pdev, kfd2kgd);
+        adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
+                                      adev->pdev, kfd2kgd);
 
         if (adev->kfd.dev)
                 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
@@ -182,7 +173,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                                 &gpu_resources.doorbell_start_offset);
 
                 if (adev->asic_type < CHIP_VEGA10) {
-                        kgd2kfd->device_init(adev->kfd.dev, &gpu_resources);
+                        kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
                         return;
                 }
 
@@ -197,13 +188,13 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                          * can use each doorbell assignment twice.
                          */
                         gpu_resources.sdma_doorbell[0][i] =
-                                adev->doorbell_index.sdma_engine0 + (i >> 1);
+                                adev->doorbell_index.sdma_engine[0] + (i >> 1);
                         gpu_resources.sdma_doorbell[0][i+1] =
-                                adev->doorbell_index.sdma_engine0 + 0x200 + (i >> 1);
+                                adev->doorbell_index.sdma_engine[0] + 0x200 + (i >> 1);
                         gpu_resources.sdma_doorbell[1][i] =
-                                adev->doorbell_index.sdma_engine1 + (i >> 1);
+                                adev->doorbell_index.sdma_engine[1] + (i >> 1);
                         gpu_resources.sdma_doorbell[1][i+1] =
-                                adev->doorbell_index.sdma_engine1 + 0x200 + (i >> 1);
+                                adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
                 }
                 /* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
                  * SDMA, IH and VCN. So don't use them for the CP.
@@ -211,14 +202,14 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                 gpu_resources.reserved_doorbell_mask = 0x1e0;
                 gpu_resources.reserved_doorbell_val  = 0x0e0;
 
-                kgd2kfd->device_init(adev->kfd.dev, &gpu_resources);
+                kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
         }
 }
 
 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
 {
         if (adev->kfd.dev) {
-                kgd2kfd->device_exit(adev->kfd.dev);
+                kgd2kfd_device_exit(adev->kfd.dev);
                 adev->kfd.dev = NULL;
         }
 }
@@ -227,13 +218,13 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
                 const void *ih_ring_entry)
 {
         if (adev->kfd.dev)
-                kgd2kfd->interrupt(adev->kfd.dev, ih_ring_entry);
+                kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
 }
 
 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
 {
         if (adev->kfd.dev)
-                kgd2kfd->suspend(adev->kfd.dev);
+                kgd2kfd_suspend(adev->kfd.dev);
 }
 
 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
@@ -241,7 +232,7 @@ int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
         int r = 0;
 
         if (adev->kfd.dev)
-                r = kgd2kfd->resume(adev->kfd.dev);
+                r = kgd2kfd_resume(adev->kfd.dev);
 
         return r;
 }
@@ -251,7 +242,7 @@ int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
         int r = 0;
 
         if (adev->kfd.dev)
-                r = kgd2kfd->pre_reset(adev->kfd.dev);
+                r = kgd2kfd_pre_reset(adev->kfd.dev);
 
         return r;
 }
@@ -261,7 +252,7 @@ int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
         int r = 0;
 
         if (adev->kfd.dev)
-                r = kgd2kfd->post_reset(adev->kfd.dev);
+                r = kgd2kfd_post_reset(adev->kfd.dev);
 
         return r;
 }
@@ -619,4 +610,47 @@ struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
 {
         return NULL;
 }
+
+struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+                              const struct kfd2kgd_calls *f2g)
+{
+        return NULL;
+}
+
+bool kgd2kfd_device_init(struct kfd_dev *kfd,
+                         const struct kgd2kfd_shared_resources *gpu_resources)
+{
+        return false;
+}
+
+void kgd2kfd_device_exit(struct kfd_dev *kfd)
+{
+}
+
+void kgd2kfd_exit(void)
+{
+}
+
+void kgd2kfd_suspend(struct kfd_dev *kfd)
+{
+}
+
+int kgd2kfd_resume(struct kfd_dev *kfd)
+{
+        return 0;
+}
+
+int kgd2kfd_pre_reset(struct kfd_dev *kfd)
+{
+        return 0;
+}
+
+int kgd2kfd_post_reset(struct kfd_dev *kfd)
+{
+        return 0;
+}
+
+void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
+{
+}
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 70429f7aa9a8..0b31a1859023 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -33,7 +33,6 @@
 #include "amdgpu_sync.h"
 #include "amdgpu_vm.h"
 
-extern const struct kgd2kfd_calls *kgd2kfd;
 extern uint64_t amdgpu_amdkfd_total_mem_size;
 
 struct amdgpu_device;
@@ -214,4 +213,22 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
 
+/* KGD2KFD callbacks */
+int kgd2kfd_init(void);
+void kgd2kfd_exit(void);
+struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
+                              const struct kfd2kgd_calls *f2g);
+bool kgd2kfd_device_init(struct kfd_dev *kfd,
+                         const struct kgd2kfd_shared_resources *gpu_resources);
+void kgd2kfd_device_exit(struct kfd_dev *kfd);
+void kgd2kfd_suspend(struct kfd_dev *kfd);
+int kgd2kfd_resume(struct kfd_dev *kfd);
+int kgd2kfd_pre_reset(struct kfd_dev *kfd);
+int kgd2kfd_post_reset(struct kfd_dev *kfd);
+void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
+int kgd2kfd_quiesce_mm(struct mm_struct *mm);
+int kgd2kfd_resume_mm(struct mm_struct *mm);
+int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
+                                               struct dma_fence *fence);
+
 #endif /* AMDGPU_AMDKFD_H_INCLUDED */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
index 574c1181ae9a..3107b9575929 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
@@ -122,7 +122,7 @@ static bool amdkfd_fence_enable_signaling(struct dma_fence *f)
         if (dma_fence_is_signaled(f))
                 return true;
 
-        if (!kgd2kfd->schedule_evict_and_restore_process(fence->mm, f))
+        if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, f))
                 return true;
 
         return false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index be1ab43473c6..d7b10d79f1de 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1790,7 +1790,7 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem,
         evicted_bos = atomic_inc_return(&process_info->evicted_bos);
         if (evicted_bos == 1) {
                 /* First eviction, stop the queues */
-                r = kgd2kfd->quiesce_mm(mm);
+                r = kgd2kfd_quiesce_mm(mm);
                 if (r)
                         pr_err("Failed to quiesce KFD\n");
                 schedule_delayed_work(&process_info->restore_userptr_work,
@@ -2082,7 +2082,7 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
             evicted_bos)
                 goto unlock_out;
         evicted_bos = 0;
-        if (kgd2kfd->resume_mm(mm)) {
+        if (kgd2kfd_resume_mm(mm)) {
                 pr_err("%s: Failed to resume KFD\n", __func__);
                 /* No recovery from this failure. Probably the CP is
                  * hanging. No point trying again.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index a028661d9e20..92b11de19581 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -576,6 +576,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
         { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
+        { 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0, 0, 0, 0, 0 },
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 28bccceaa363..c898b19f335a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1645,7 +1645,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                 if (r) {
                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
                                   adev->ip_blocks[i].version->funcs->name, r);
-                        return r;
+                        goto init_failed;
                 }
                 adev->ip_blocks[i].status.sw = true;
 
@@ -1654,17 +1654,17 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                         r = amdgpu_device_vram_scratch_init(adev);
                         if (r) {
                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
-                                return r;
+                                goto init_failed;
                         }
                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
                         if (r) {
                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
-                                return r;
+                                goto init_failed;
                         }
                         r = amdgpu_device_wb_init(adev);
                         if (r) {
                                 DRM_ERROR("amdgpu_device_wb_init failed %d\n", r);
-                                return r;
+                                goto init_failed;
                         }
                         adev->ip_blocks[i].status.hw = true;
 
@@ -1675,7 +1675,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
                                                                 AMDGPU_CSA_SIZE);
                                 if (r) {
                                         DRM_ERROR("allocate CSA failed %d\n", r);
-                                        return r;
+                                        goto init_failed;
                                 }
                         }
                 }
@@ -1683,28 +1683,32 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
 
         r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
         if (r)
-                return r;
+                goto init_failed;
 
         r = amdgpu_device_ip_hw_init_phase1(adev);
         if (r)
-                return r;
+                goto init_failed;
 
         r = amdgpu_device_fw_loading(adev);
         if (r)
-                return r;
+                goto init_failed;
 
         r = amdgpu_device_ip_hw_init_phase2(adev);
         if (r)
-                return r;
+                goto init_failed;
 
         if (adev->gmc.xgmi.num_physical_nodes > 1)
                 amdgpu_xgmi_add_device(adev);
         amdgpu_amdkfd_device_init(adev);
 
-        if (amdgpu_sriov_vf(adev))
+init_failed:
+        if (amdgpu_sriov_vf(adev)) {
+                if (!r)
+                        amdgpu_virt_init_data_exchange(adev);
                 amdgpu_virt_release_full_gpu(adev, true);
+        }
 
-        return 0;
+        return r;
 }
 
 /**
@@ -2131,7 +2135,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
                                 continue;
 
                         r = block->version->funcs->hw_init(adev);
-                        DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+                        DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
                         if (r)
                                 return r;
                 }
@@ -2165,7 +2169,7 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)
                                 continue;
 
                         r = block->version->funcs->hw_init(adev);
-                        DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
+                        DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
                         if (r)
                                 return r;
                 }
@@ -2546,6 +2550,17 @@ int amdgpu_device_init(struct amdgpu_device *adev,
         /* detect if we are with an SRIOV vbios */
         amdgpu_device_detect_sriov_bios(adev);
 
+        /* check if we need to reset the asic
+         *  E.g., driver was not cleanly unloaded previously, etc.
+         */
+        if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) {
+                r = amdgpu_asic_reset(adev);
+                if (r) {
+                        dev_err(adev->dev, "asic reset on init failed\n");
+                        goto failed;
+                }
+        }
+
         /* Post card if necessary */
         if (amdgpu_device_need_post(adev)) {
                 if (!adev->bios) {
@@ -2610,6 +2625,8 @@ fence_driver_init:
                 }
                 dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
+                if (amdgpu_virt_request_full_gpu(adev, false))
+                        amdgpu_virt_release_full_gpu(adev, false);
                 goto failed;
         }
 
@@ -2632,9 +2649,6 @@ fence_driver_init:
                 goto failed;
         }
 
-        if (amdgpu_sriov_vf(adev))
-                amdgpu_virt_init_data_exchange(adev);
-
         amdgpu_fbdev_init(adev);
 
         r = amdgpu_pm_sysfs_init(adev);
@@ -2798,7 +2812,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
                         struct drm_framebuffer *fb = crtc->primary->fb;
                         struct amdgpu_bo *robj;
 
-                        if (amdgpu_crtc->cursor_bo) {
+                        if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
                                 r = amdgpu_bo_reserve(aobj, true);
                                 if (r == 0) {
@@ -2906,7 +2920,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 
-                        if (amdgpu_crtc->cursor_bo) {
+                        if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {
                                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
                                 r = amdgpu_bo_reserve(aobj, true);
                                 if (r == 0) {
@@ -3226,6 +3240,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
         r = amdgpu_ib_ring_tests(adev);
 
 error:
+        amdgpu_virt_init_data_exchange(adev);
         amdgpu_virt_release_full_gpu(adev, true);
         if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
                 atomic_inc(&adev->vram_lost_counter);
@@ -3298,17 +3313,15 @@ static int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
                 if (!ring || !ring->sched.thread)
                         continue;
 
-                kthread_park(ring->sched.thread);
-
-                if (job && job->base.sched != &ring->sched)
-                        continue;
-
-                drm_sched_hw_job_reset(&ring->sched, job ? &job->base : NULL);
+                drm_sched_stop(&ring->sched);
 
                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
                 amdgpu_fence_driver_force_completion(ring);
         }
 
+        if(job)
+                drm_sched_increase_karma(&job->base);
+
 
 
         if (!amdgpu_sriov_vf(adev)) {
@@ -3454,14 +3467,10 @@ static void amdgpu_device_post_asic_reset(struct amdgpu_device *adev,
                 if (!ring || !ring->sched.thread)
                         continue;
 
-                /* only need recovery sched of the given job's ring
-                 * or all rings (in the case @job is NULL)
-                 * after above amdgpu_reset accomplished
-                 */
-                if ((!job || job->base.sched == &ring->sched) && !adev->asic_reset_res)
-                        drm_sched_job_recovery(&ring->sched);
+                if (!adev->asic_reset_res)
+                        drm_sched_resubmit_jobs(&ring->sched);
 
-                kthread_unpark(ring->sched.thread);
+                drm_sched_start(&ring->sched, !adev->asic_reset_res);
         }
 
         if (!amdgpu_device_has_dc_support(adev)) {
@@ -3521,9 +3530,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
          * by different nodes. No point also since the one node already executing
          * reset will also reset all the other nodes in the hive.
          */
-        hive = amdgpu_get_xgmi_hive(adev);
+        hive = amdgpu_get_xgmi_hive(adev, 0);
         if (hive && adev->gmc.xgmi.num_physical_nodes > 1 &&
-            !mutex_trylock(&hive->hive_lock))
+            !mutex_trylock(&hive->reset_lock))
                 return 0;
 
         /* Start with adev pre asic reset first for soft reset check.*/
@@ -3602,7 +3611,7 @@ retry:	/* Rest of adevs pre asic reset from XGMI hive. */
         }
 
         if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
-                mutex_unlock(&hive->hive_lock);
+                mutex_unlock(&hive->reset_lock);
 
         if (r)
                 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 15ce7e681d67..b083b219b1a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -188,10 +188,12 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
                 goto cleanup;
         }
 
-        r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
-        if (unlikely(r != 0)) {
-                DRM_ERROR("failed to pin new abo buffer before flip\n");
-                goto unreserve;
+        if (!adev->enable_virtual_display) {
+                r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
+                if (unlikely(r != 0)) {
+                        DRM_ERROR("failed to pin new abo buffer before flip\n");
+                        goto unreserve;
+                }
         }
 
         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
@@ -211,7 +213,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
         amdgpu_bo_unreserve(new_abo);
 
-        work->base = amdgpu_bo_gpu_offset(new_abo);
+        if (!adev->enable_virtual_display)
+                work->base = amdgpu_bo_gpu_offset(new_abo);
         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
                 amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
 
@@ -242,9 +245,10 @@ pflip_cleanup:
                 goto cleanup;
         }
 unpin:
-        if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) {
-                DRM_ERROR("failed to unpin new abo in error path\n");
-        }
+        if (!adev->enable_virtual_display)
+                if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
+                        DRM_ERROR("failed to unpin new abo in error path\n");
+
 unreserve:
         amdgpu_bo_unreserve(new_abo);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
index be620b29f4aa..1cfec06f81d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
@@ -51,14 +51,7 @@ struct amdgpu_doorbell_index {
         uint32_t userqueue_start;
         uint32_t userqueue_end;
         uint32_t gfx_ring0;
-        uint32_t sdma_engine0;
-        uint32_t sdma_engine1;
-        uint32_t sdma_engine2;
-        uint32_t sdma_engine3;
-        uint32_t sdma_engine4;
-        uint32_t sdma_engine5;
-        uint32_t sdma_engine6;
-        uint32_t sdma_engine7;
+        uint32_t sdma_engine[8];
         uint32_t ih;
         union {
                 struct {
@@ -79,6 +72,8 @@ struct amdgpu_doorbell_index {
                 } uvd_vce;
         };
         uint32_t max_assignment;
+        /* Per engine SDMA doorbell size in dword */
+        uint32_t sdma_doorbell_range;
 };
 
 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index f972cd156795..2f61e9edb1c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -364,6 +364,14 @@ enum amdgpu_pcie_gen {
                 ((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
                         (adev)->powerplay.pp_handle))
 
+#define amdgpu_dpm_get_ppfeature_status(adev, buf) \
+                ((adev)->powerplay.pp_funcs->get_ppfeature_status(\
+                        (adev)->powerplay.pp_handle, (buf)))
+
+#define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \
+                ((adev)->powerplay.pp_funcs->set_ppfeature_status(\
+                        (adev)->powerplay.pp_handle, (ppfeatures)))
+
 struct amdgpu_dpm {
         struct amdgpu_ps        *ps;
         /* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index c48207b377bc..0b8ef2d27d6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -202,12 +202,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                         amdgpu_asic_flush_hdp(adev, ring);
         }
 
+        if (need_ctx_switch)
+                status |= AMDGPU_HAVE_CTX_SWITCH;
+
         skip_preamble = ring->current_ctx == fence_ctx;
         if (job && ring->funcs->emit_cntxcntl) {
-                if (need_ctx_switch)
-                        status |= AMDGPU_HAVE_CTX_SWITCH;
                 status |= job->preamble_status;
-
                 amdgpu_ring_emit_cntxcntl(ring, status);
         }
 
@@ -221,8 +221,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                         !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
                         continue;
 
-                amdgpu_ring_emit_ib(ring, job, ib, need_ctx_switch);
-                need_ctx_switch = false;
+                amdgpu_ring_emit_ib(ring, job, ib, status);
+                status &= ~AMDGPU_HAVE_CTX_SWITCH;
         }
 
         if (ring->funcs->emit_tmz)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 8af67f649660..d0a5db777b6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -52,6 +52,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
         ih->use_bus_addr = use_bus_addr;
 
         if (use_bus_addr) {
+                dma_addr_t dma_addr;
+
                 if (ih->ring)
                         return 0;
 
@@ -59,21 +61,26 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                  * add them to the end of the ring allocation.
                  */
                 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8,
-                                              &ih->rb_dma_addr, GFP_KERNEL);
+                                              &dma_addr, GFP_KERNEL);
                 if (ih->ring == NULL)
                         return -ENOMEM;
 
                 memset((void *)ih->ring, 0, ih->ring_size + 8);
-                ih->wptr_offs = (ih->ring_size / 4) + 0;
-                ih->rptr_offs = (ih->ring_size / 4) + 1;
+                ih->gpu_addr = dma_addr;
+                ih->wptr_addr = dma_addr + ih->ring_size;
+                ih->wptr_cpu = &ih->ring[ih->ring_size / 4];
+                ih->rptr_addr = dma_addr + ih->ring_size + 4;
+                ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1];
         } else {
-                r = amdgpu_device_wb_get(adev, &ih->wptr_offs);
+                unsigned wptr_offs, rptr_offs;
+
+                r = amdgpu_device_wb_get(adev, &wptr_offs);
                 if (r)
                         return r;
 
-                r = amdgpu_device_wb_get(adev, &ih->rptr_offs);
+                r = amdgpu_device_wb_get(adev, &rptr_offs);
                 if (r) {
-                        amdgpu_device_wb_free(adev, ih->wptr_offs);
+                        amdgpu_device_wb_free(adev, wptr_offs);
                         return r;
                 }
 
@@ -82,10 +89,15 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                                             &ih->ring_obj, &ih->gpu_addr,
                                             (void **)&ih->ring);
                 if (r) {
-                        amdgpu_device_wb_free(adev, ih->rptr_offs);
-                        amdgpu_device_wb_free(adev, ih->wptr_offs);
+                        amdgpu_device_wb_free(adev, rptr_offs);
+                        amdgpu_device_wb_free(adev, wptr_offs);
                         return r;
                 }
+
+                ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
+                ih->wptr_cpu = &adev->wb.wb[wptr_offs];
+                ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
+                ih->rptr_cpu = &adev->wb.wb[rptr_offs];
         }
         return 0;
 }
@@ -109,13 +121,13 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
                  * add them to the end of the ring allocation.
                  */
                 dma_free_coherent(adev->dev, ih->ring_size + 8,
-                                  (void *)ih->ring, ih->rb_dma_addr);
+                                  (void *)ih->ring, ih->gpu_addr);
                 ih->ring = NULL;
         } else {
                 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
                                       (void **)&ih->ring);
-                amdgpu_device_wb_free(adev, ih->wptr_offs);
-                amdgpu_device_wb_free(adev, ih->rptr_offs);
+                amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
+                amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
         }
 }
 
@@ -137,7 +149,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
         if (!ih->enabled || adev->shutdown)
                 return IRQ_NONE;
 
-        wptr = amdgpu_ih_get_wptr(adev);
+        wptr = amdgpu_ih_get_wptr(adev, ih);
 
 restart_ih:
         /* is somebody else already processing irqs? */
@@ -154,11 +166,11 @@ restart_ih:
                 ih->rptr &= ih->ptr_mask;
         }
 
-        amdgpu_ih_set_rptr(adev);
+        amdgpu_ih_set_rptr(adev, ih);
         atomic_set(&ih->lock, 0);
 
         /* make sure wptr hasn't changed while processing */
-        wptr = amdgpu_ih_get_wptr(adev);
+        wptr = amdgpu_ih_get_wptr(adev, ih);
         if (wptr != ih->rptr)
                 goto restart_ih;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index f877bb78d10a..1ccb1831382a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -31,34 +31,40 @@ struct amdgpu_iv_entry;
  * R6xx+ IH ring
  */
 struct amdgpu_ih_ring {
-        struct amdgpu_bo        *ring_obj;
-        volatile uint32_t       *ring;
-        unsigned                rptr;
         unsigned                ring_size;
-        uint64_t                gpu_addr;
         uint32_t                ptr_mask;
-        atomic_t                lock;
-        bool                    enabled;
-        unsigned                wptr_offs;
-        unsigned                rptr_offs;
         u32                     doorbell_index;
         bool                    use_doorbell;
         bool                    use_bus_addr;
-        dma_addr_t              rb_dma_addr; /* only used when use_bus_addr = true */
+
+        struct amdgpu_bo        *ring_obj;
+        volatile uint32_t       *ring;
+        uint64_t                gpu_addr;
+
+        uint64_t                wptr_addr;
+        volatile uint32_t       *wptr_cpu;
+
+        uint64_t                rptr_addr;
+        volatile uint32_t       *rptr_cpu;
+
+        bool                    enabled;
+        unsigned                rptr;
+        atomic_t                lock;
 };
 
 /* provided by the ih block */
 struct amdgpu_ih_funcs {
         /* ring read/write ptr handling, called from interrupt context */
-        u32 (*get_wptr)(struct amdgpu_device *adev);
-        void (*decode_iv)(struct amdgpu_device *adev,
+        u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
+        void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                           struct amdgpu_iv_entry *entry);
-        void (*set_rptr)(struct amdgpu_device *adev);
+        void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
 };
 
-#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
-#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
-#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
+#define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
+#define amdgpu_ih_decode_iv(adev, iv) \
+        (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv))
+#define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih))
 
 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                         unsigned ring_size, bool use_bus_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index b7968f426862..8bfb3dab46f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -148,6 +148,8 @@ static void amdgpu_irq_callback(struct amdgpu_device *adev,
         entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
         amdgpu_ih_decode_iv(adev, &entry);
 
+        trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
+
         amdgpu_irq_dispatch(adev, &entry);
 }
 
@@ -175,6 +177,36 @@ irqreturn_t amdgpu_irq_handler(int irq, void *arg)
 }
 
 /**
+ * amdgpu_irq_handle_ih1 - kick of processing for IH1
+ *
+ * @work: work structure in struct amdgpu_irq
+ *
+ * Kick of processing IH ring 1.
+ */
+static void amdgpu_irq_handle_ih1(struct work_struct *work)
+{
+        struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+                                                  irq.ih1_work);
+
+        amdgpu_ih_process(adev, &adev->irq.ih1, amdgpu_irq_callback);
+}
+
+/**
+ * amdgpu_irq_handle_ih2 - kick of processing for IH2
+ *
+ * @work: work structure in struct amdgpu_irq
+ *
+ * Kick of processing IH ring 2.
+ */
+static void amdgpu_irq_handle_ih2(struct work_struct *work)
+{
+        struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
+                                                  irq.ih2_work);
+
+        amdgpu_ih_process(adev, &adev->irq.ih2, amdgpu_irq_callback);
+}
+
+/**
  * amdgpu_msi_ok - check whether MSI functionality is enabled
  *
  * @adev: amdgpu device pointer (unused)
@@ -238,6 +270,9 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
                                 amdgpu_hotplug_work_func);
         }
 
+        INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
+        INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
+
         adev->irq.installed = true;
         r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
         if (r) {
@@ -367,8 +402,6 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
         bool handled = false;
         int r;
 
-        trace_amdgpu_iv(entry);
-
         if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
                 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
index f6ce171cb8aa..c27decfda494 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
@@ -87,9 +87,11 @@ struct amdgpu_irq {
         /* status, etc. */
         bool                            msi_enabled; /* msi enabled */
 
-        /* interrupt ring */
-        struct amdgpu_ih_ring           ih;
-        const struct amdgpu_ih_funcs    *ih_funcs;
+        /* interrupt rings */
+        struct amdgpu_ih_ring           ih, ih1, ih2;
+        const struct amdgpu_ih_funcs    *ih_funcs;
+        struct work_struct              ih1_work, ih2_work;
+        struct amdgpu_irq_src           self_irq;
 
         /* gen irq stuff */
         struct irq_domain               *domain; /* GPU irq controller domain */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 1f61ed95727c..a7adb7b6bd98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -626,11 +626,71 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }
 
 /**
- * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
+ * DOC: ppfeatures
+ *
+ * The amdgpu driver provides a sysfs API for adjusting what powerplay
+ * features to be enabled. The file ppfeatures is used for this. And
+ * this is only available for Vega10 and later dGPUs.
+ *
+ * Reading back the file will show you the followings:
+ * - Current ppfeature masks
+ * - List of the all supported powerplay features with their naming,
+ *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
+ *
+ * To manually enable or disable a specific feature, just set or clear
+ * the corresponding bit from original ppfeature masks and input the
+ * new ppfeature masks.
+ */
+static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+                struct device_attribute *attr,
+                const char *buf,
+                size_t count)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+        uint64_t featuremask;
+        int ret;
+
+        ret = kstrtou64(buf, 0, &featuremask);
+        if (ret)
+                return -EINVAL;
+
+        pr_debug("featuremask = 0x%llx\n", featuremask);
+
+        if (adev->powerplay.pp_funcs->set_ppfeature_status) {
+                ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
+                if (ret)
+                        return -EINVAL;
+        }
+
+        return count;
+}
+
+static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+                struct device_attribute *attr,
+                char *buf)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+
+        if (adev->powerplay.pp_funcs->get_ppfeature_status)
+                return amdgpu_dpm_get_ppfeature_status(adev, buf);
+
+        return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+/**
+ * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk
+ * pp_dpm_pcie
  *
  * The amdgpu driver provides a sysfs API for adjusting what power levels
  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
- * and pp_dpm_pcie are used for this.
+ * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
+ * this.
+ *
+ * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
+ * Vega10 and later ASICs.
+ * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
  *
  * Reading back the files will show you the available power levels within
  * the power state and the clock information for those levels.
@@ -640,6 +700,8 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * Secondly,Enter a new value for each level by inputing a string that
  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
  * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.
+ *
+ * NOTE: change to the dcefclk max dpm level is not supported now
  */
 
 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
@@ -750,6 +812,114 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
         return count;
 }
 
+static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
+                struct device_attribute *attr,
+                char *buf)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+
+        if (adev->powerplay.pp_funcs->print_clock_levels)
+                return amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
+        else
+                return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
+                struct device_attribute *attr,
+                const char *buf,
+                size_t count)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+        int ret;
+        uint32_t mask = 0;
+
+        ret = amdgpu_read_mask(buf, count, &mask);
+        if (ret)
+                return ret;
+
+        if (adev->powerplay.pp_funcs->force_clock_level)
+                ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
+
+        if (ret)
+                return -EINVAL;
+
+        return count;
+}
+
+static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
+                struct device_attribute *attr,
+                char *buf)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+
+        if (adev->powerplay.pp_funcs->print_clock_levels)
+                return amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
+        else
+                return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
+                struct device_attribute *attr,
+                const char *buf,
+                size_t count)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+        int ret;
+        uint32_t mask = 0;
+
+        ret = amdgpu_read_mask(buf, count, &mask);
+        if (ret)
+                return ret;
+
+        if (adev->powerplay.pp_funcs->force_clock_level)
+                ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
+
+        if (ret)
+                return -EINVAL;
+
+        return count;
+}
+
+static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
+                struct device_attribute *attr,
+                char *buf)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+
+        if (adev->powerplay.pp_funcs->print_clock_levels)
+                return amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
+        else
+                return snprintf(buf, PAGE_SIZE, "\n");
+}
+
+static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
+                struct device_attribute *attr,
+                const char *buf,
+                size_t count)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+        int ret;
+        uint32_t mask = 0;
+
+        ret = amdgpu_read_mask(buf, count, &mask);
+        if (ret)
+                return ret;
+
+        if (adev->powerplay.pp_funcs->force_clock_level)
+                ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
+
+        if (ret)
+                return -EINVAL;
+
+        return count;
+}
+
 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
                 struct device_attribute *attr,
                 char *buf)
@@ -990,6 +1160,31 @@ static ssize_t amdgpu_get_busy_percent(struct device *dev,
         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 }
 
+/**
+ * DOC: pcie_bw
+ *
+ * The amdgpu driver provides a sysfs API for estimating how much data
+ * has been received and sent by the GPU in the last second through PCIe.
+ * The file pcie_bw is used for this.
+ * The Perf counters count the number of received and sent messages and return
+ * those values, as well as the maximum payload size of a PCIe packet (mps).
+ * Note that it is not possible to easily and quickly obtain the size of each
+ * packet transmitted, so we output the max payload size (mps) to allow for
+ * quick estimation of the PCIe bandwidth usage
+ */
+static ssize_t amdgpu_get_pcie_bw(struct device *dev,
+                struct device_attribute *attr,
+                char *buf)
+{
+        struct drm_device *ddev = dev_get_drvdata(dev);
+        struct amdgpu_device *adev = ddev->dev_private;
+        uint64_t count0, count1;
+
+        amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
+        return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
+                        count0, count1, pcie_get_mps(adev->pdev));
+}
+
 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
                    amdgpu_get_dpm_forced_performance_level,
@@ -1008,6 +1203,15 @@ static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
                 amdgpu_get_pp_dpm_mclk,
                 amdgpu_set_pp_dpm_mclk);
+static DEVICE_ATTR(pp_dpm_socclk, S_IRUGO | S_IWUSR,
+                amdgpu_get_pp_dpm_socclk,
+                amdgpu_set_pp_dpm_socclk);
+static DEVICE_ATTR(pp_dpm_fclk, S_IRUGO | S_IWUSR,
+                amdgpu_get_pp_dpm_fclk,
+                amdgpu_set_pp_dpm_fclk);
+static DEVICE_ATTR(pp_dpm_dcefclk, S_IRUGO | S_IWUSR,
+                amdgpu_get_pp_dpm_dcefclk,
+                amdgpu_set_pp_dpm_dcefclk);
 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
                 amdgpu_get_pp_dpm_pcie,
                 amdgpu_set_pp_dpm_pcie);
@@ -1025,6 +1229,10 @@ static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
                 amdgpu_set_pp_od_clk_voltage);
 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
                 amdgpu_get_busy_percent, NULL);
+static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
+static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
+                amdgpu_get_ppfeature_status,
+                amdgpu_set_ppfeature_status);
 
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
                                       struct device_attribute *attr,
@@ -1516,6 +1724,75 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
         return count;
 }
 
+static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
+                                      struct device_attribute *attr,
+                                      char *buf)
+{
+        struct amdgpu_device *adev = dev_get_drvdata(dev);
+        struct drm_device *ddev = adev->ddev;
+        uint32_t sclk;
+        int r, size = sizeof(sclk);
+
+        /* Can't get voltage when the card is off */
+        if  ((adev->flags & AMD_IS_PX) &&
+             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+                return -EINVAL;
+
+        /* sanity check PP is enabled */
+        if (!(adev->powerplay.pp_funcs &&
+              adev->powerplay.pp_funcs->read_sensor))
+              return -EINVAL;
+
+        /* get the sclk */
+        r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
+                                   (void *)&sclk, &size);
+        if (r)
+                return r;
+
+        return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000);
+}
+
+static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
+                                            struct device_attribute *attr,
+                                            char *buf)
+{
+        return snprintf(buf, PAGE_SIZE, "sclk\n");
+}
+
+static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
+                                      struct device_attribute *attr,
+                                      char *buf)
+{
+        struct amdgpu_device *adev = dev_get_drvdata(dev);
+        struct drm_device *ddev = adev->ddev;
+        uint32_t mclk;
+        int r, size = sizeof(mclk);
+
+        /* Can't get voltage when the card is off */
+        if  ((adev->flags & AMD_IS_PX) &&
+             (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+                return -EINVAL;
+
+        /* sanity check PP is enabled */
+        if (!(adev->powerplay.pp_funcs &&
+              adev->powerplay.pp_funcs->read_sensor))
+              return -EINVAL;
+
+        /* get the sclk */
+        r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
+                                   (void *)&mclk, &size);
+        if (r)
+                return r;
+
+        return snprintf(buf, PAGE_SIZE, "%d\n", mclk * 10 * 1000);
+}
+
+static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
+                                            struct device_attribute *attr,
+                                            char *buf)
+{
+        return snprintf(buf, PAGE_SIZE, "mclk\n");
+}
 
 /**
  * DOC: hwmon
@@ -1532,6 +1809,10 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
  *
  * - GPU fan
  *
+ * - GPU gfx/compute engine clock
+ *
+ * - GPU memory clock (dGPU only)
+ *
  * hwmon interfaces for GPU temperature:
  *
  * - temp1_input: the on die GPU temperature in millidegrees Celsius
@@ -1576,6 +1857,12 @@ static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
  *
  * - fan[1-*]_enable: Enable or disable the sensors.1: Enable 0: Disable
  *
+ * hwmon interfaces for GPU clocks:
+ *
+ * - freq1_input: the gfx/compute clock in hertz
+ *
+ * - freq2_input: the memory clock in hertz
+ *
  * You can use hwmon tools like sensors to view this information on your system.
  *
  */
@@ -1600,6 +1887,10 @@ static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg,
 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
+static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
+static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
+static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
+static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
 
 static struct attribute *hwmon_attributes[] = {
         &sensor_dev_attr_temp1_input.dev_attr.attr,
@@ -1622,6 +1913,10 @@ static struct attribute *hwmon_attributes[] = {
         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
         &sensor_dev_attr_power1_cap.dev_attr.attr,
+        &sensor_dev_attr_freq1_input.dev_attr.attr,
+        &sensor_dev_attr_freq1_label.dev_attr.attr,
+        &sensor_dev_attr_freq2_input.dev_attr.attr,
+        &sensor_dev_attr_freq2_label.dev_attr.attr,
         NULL
 };
 
@@ -1686,7 +1981,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
                 effective_mode &= ~S_IWUSR;
 
         if ((adev->flags & AMD_IS_APU) &&
-            (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
+            (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
+             attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
                 return 0;
@@ -1712,6 +2008,12 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
                 return 0;
 
+        /* no mclk on APUs */
+        if ((adev->flags & AMD_IS_APU) &&
+            (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
+             attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
+                return 0;
+
         return effective_mode;
 }
 
@@ -2008,6 +2310,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
 
 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 {
+        struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
         int ret;
 
         if (adev->pm.sysfs_initialized)
@@ -2069,6 +2372,25 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
                 return ret;
         }
+        if (adev->asic_type >= CHIP_VEGA10) {
+                ret = device_create_file(adev->dev, &dev_attr_pp_dpm_socclk);
+                if (ret) {
+                        DRM_ERROR("failed to create device file pp_dpm_socclk\n");
+                        return ret;
+                }
+                ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+                if (ret) {
+                        DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
+                        return ret;
+                }
+        }
+        if (adev->asic_type >= CHIP_VEGA20) {
+                ret = device_create_file(adev->dev, &dev_attr_pp_dpm_fclk);
+                if (ret) {
+                        DRM_ERROR("failed to create device file pp_dpm_fclk\n");
+                        return ret;
+                }
+        }
         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
         if (ret) {
                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
@@ -2091,12 +2413,14 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                                 "pp_power_profile_mode\n");
                 return ret;
         }
-        ret = device_create_file(adev->dev,
-                        &dev_attr_pp_od_clk_voltage);
-        if (ret) {
-                DRM_ERROR("failed to create device file "
-                                "pp_od_clk_voltage\n");
-                return ret;
+        if (hwmgr->od_enabled) {
+                ret = device_create_file(adev->dev,
+                                &dev_attr_pp_od_clk_voltage);
+                if (ret) {
+                        DRM_ERROR("failed to create device file "
+                                        "pp_od_clk_voltage\n");
+                        return ret;
+                }
         }
         ret = device_create_file(adev->dev,
                         &dev_attr_gpu_busy_percent);
@@ -2105,12 +2429,31 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                                 "gpu_busy_level\n");
                 return ret;
         }
+        /* PCIe Perf counters won't work on APU nodes */
+        if (!(adev->flags & AMD_IS_APU)) {
+                ret = device_create_file(adev->dev, &dev_attr_pcie_bw);
+                if (ret) {
+                        DRM_ERROR("failed to create device file pcie_bw\n");
+                        return ret;
+                }
+        }
         ret = amdgpu_debugfs_pm_init(adev);
         if (ret) {
                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
                 return ret;
         }
 
+        if ((adev->asic_type >= CHIP_VEGA10) &&
+            !(adev->flags & AMD_IS_APU)) {
+                ret = device_create_file(adev->dev,
+                                &dev_attr_ppfeatures);
+                if (ret) {
+                        DRM_ERROR("failed to create device file "
+                                        "ppfeatures\n");
+                        return ret;
+                }
+        }
+
         adev->pm.sysfs_initialized = true;
 
         return 0;
@@ -2118,6 +2461,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 
 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 {
+        struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
+
         if (adev->pm.dpm_enabled == 0)
                 return;
 
@@ -2133,14 +2478,26 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 
         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
+        if (adev->asic_type >= CHIP_VEGA10) {
+                device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
+                device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+        }
         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
+        if (adev->asic_type >= CHIP_VEGA20)
+                device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
         device_remove_file(adev->dev,
                         &dev_attr_pp_power_profile_mode);
-        device_remove_file(adev->dev,
-                        &dev_attr_pp_od_clk_voltage);
+        if (hwmgr->od_enabled)
+                device_remove_file(adev->dev,
+                                &dev_attr_pp_od_clk_voltage);
         device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
+        if (!(adev->flags & AMD_IS_APU))
+                device_remove_file(adev->dev, &dev_attr_pcie_bw);
+        if ((adev->asic_type >= CHIP_VEGA10) &&
+            !(adev->flags & AMD_IS_APU))
+                device_remove_file(adev->dev, &dev_attr_ppfeatures);
 }
 
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8fab0d637ee5..d87f165e3a23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -67,9 +67,6 @@ static int psp_sw_init(void *handle)
 
         psp->adev = adev;
 
-        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-                return 0;
-
         ret = psp_init_microcode(psp);
         if (ret) {
                 DRM_ERROR("Failed to load psp firmware!\n");
@@ -83,9 +80,6 @@ static int psp_sw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-                return 0;
-
         release_firmware(adev->psp.sos_fw);
         adev->psp.sos_fw = NULL;
         release_firmware(adev->psp.asd_fw);
@@ -140,13 +134,24 @@ psp_cmd_submit_buf(struct psp_context *psp,
         while (*((unsigned int *)psp->fence_buf) != index)
                 msleep(1);
 
-        /* the status field must be 0 after FW is loaded */
-        if (ucode && psp->cmd_buf_mem->resp.status) {
-                DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
-                          psp->cmd_buf_mem->resp.status, ucode->ucode_id);
-                return -EINVAL;
+        /* In some cases, psp response status is not 0 even there is no
+         * problem while the command is submitted. Some version of PSP FW
+         * doesn't write 0 to that field.
+         * So here we would like to only print a warning instead of an error
+         * during psp initialization to avoid breaking hw_init and it doesn't
+         * return -EINVAL.
+         */
+        if (psp->cmd_buf_mem->resp.status) {
+                if (ucode)
+                        DRM_WARN("failed to load ucode id (%d) ",
+                                  ucode->ucode_id);
+                DRM_WARN("psp command failed and response status is (%d)\n",
+                          psp->cmd_buf_mem->resp.status);
         }
 
+        /* get xGMI session id from response buffer */
+        cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
+
         if (ucode) {
                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
@@ -495,6 +500,98 @@ static int psp_hw_start(struct psp_context *psp)
         return 0;
 }
 
+static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
+                           enum psp_gfx_fw_type *type)
+{
+        switch (ucode->ucode_id) {
+        case AMDGPU_UCODE_ID_SDMA0:
+                *type = GFX_FW_TYPE_SDMA0;
+                break;
+        case AMDGPU_UCODE_ID_SDMA1:
+                *type = GFX_FW_TYPE_SDMA1;
+                break;
+        case AMDGPU_UCODE_ID_CP_CE:
+                *type = GFX_FW_TYPE_CP_CE;
+                break;
+        case AMDGPU_UCODE_ID_CP_PFP:
+                *type = GFX_FW_TYPE_CP_PFP;
+                break;
+        case AMDGPU_UCODE_ID_CP_ME:
+                *type = GFX_FW_TYPE_CP_ME;
+                break;
+        case AMDGPU_UCODE_ID_CP_MEC1:
+                *type = GFX_FW_TYPE_CP_MEC;
+                break;
+        case AMDGPU_UCODE_ID_CP_MEC1_JT:
+                *type = GFX_FW_TYPE_CP_MEC_ME1;
+                break;
+        case AMDGPU_UCODE_ID_CP_MEC2:
+                *type = GFX_FW_TYPE_CP_MEC;
+                break;
+        case AMDGPU_UCODE_ID_CP_MEC2_JT:
+                *type = GFX_FW_TYPE_CP_MEC_ME2;
+                break;
+        case AMDGPU_UCODE_ID_RLC_G:
+                *type = GFX_FW_TYPE_RLC_G;
+                break;
+        case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
+                *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
+                break;
+        case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
+                *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
+                break;
+        case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
+                *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
+                break;
+        case AMDGPU_UCODE_ID_SMC:
+                *type = GFX_FW_TYPE_SMU;
+                break;
+        case AMDGPU_UCODE_ID_UVD:
+                *type = GFX_FW_TYPE_UVD;
+                break;
+        case AMDGPU_UCODE_ID_UVD1:
+                *type = GFX_FW_TYPE_UVD1;
+                break;
+        case AMDGPU_UCODE_ID_VCE:
+                *type = GFX_FW_TYPE_VCE;
+                break;
+        case AMDGPU_UCODE_ID_VCN:
+                *type = GFX_FW_TYPE_VCN;
+                break;
+        case AMDGPU_UCODE_ID_DMCU_ERAM:
+                *type = GFX_FW_TYPE_DMCU_ERAM;
+                break;
+        case AMDGPU_UCODE_ID_DMCU_INTV:
+                *type = GFX_FW_TYPE_DMCU_ISR;
+                break;
+        case AMDGPU_UCODE_ID_MAXIMUM:
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
+                                       struct psp_gfx_cmd_resp *cmd)
+{
+        int ret;
+        uint64_t fw_mem_mc_addr = ucode->mc_addr;
+
+        memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+
+        cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
+        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
+        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
+        cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
+
+        ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
+        if (ret)
+                DRM_ERROR("Unknown firmware type\n");
+
+        return ret;
+}
+
 static int psp_np_fw_load(struct psp_context *psp)
 {
         int i, ret;
@@ -516,7 +613,7 @@ static int psp_np_fw_load(struct psp_context *psp)
                         /*skip ucode loading in SRIOV VF */
                         continue;
 
-                ret = psp_prep_cmd_buf(ucode, psp->cmd);
+                ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
                 if (ret)
                         return ret;
 
@@ -541,7 +638,7 @@ static int psp_load_fw(struct amdgpu_device *adev)
         struct psp_context *psp = &adev->psp;
 
         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
-                psp_ring_destroy(psp, PSP_RING_TYPE__KM);
+                psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
                 goto skip_memalloc;
         }
 
@@ -618,10 +715,6 @@ static int psp_hw_init(void *handle)
         int ret;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-
-        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-                return 0;
-
         mutex_lock(&adev->firmware.mutex);
         /*
          * This sequence is just used on hw_init only once, no need on
@@ -651,9 +744,6 @@ static int psp_hw_fini(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         struct psp_context *psp = &adev->psp;
 
-        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-                return 0;
-
         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
             psp->xgmi_context.initialized == 1)
                 psp_xgmi_terminate(psp);
@@ -682,9 +772,6 @@ static int psp_suspend(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         struct psp_context *psp = &adev->psp;
 
-        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-                return 0;
-
         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
             psp->xgmi_context.initialized == 1) {
                 ret = psp_xgmi_terminate(psp);
@@ -709,9 +796,6 @@ static int psp_resume(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         struct psp_context *psp = &adev->psp;
 
-        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
-                return 0;
-
         DRM_INFO("PSP is resuming...\n");
 
         mutex_lock(&adev->firmware.mutex);
@@ -747,11 +831,6 @@ static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 {
         struct amdgpu_firmware_info *ucode = NULL;
 
-        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
-                DRM_INFO("firmware is not loaded by PSP\n");
-                return true;
-        }
-
         if (!adev->firmware.fw_size)
                 return false;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 3ee573b4016e..2ef98cc755d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -65,8 +65,6 @@ struct psp_funcs
         int (*init_microcode)(struct psp_context *psp);
         int (*bootloader_load_sysdrv)(struct psp_context *psp);
         int (*bootloader_load_sos)(struct psp_context *psp);
-        int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
-                            struct psp_gfx_cmd_resp *cmd);
         int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
         int (*ring_create)(struct psp_context *psp,
                            enum psp_ring_type ring_type);
@@ -176,7 +174,6 @@ struct psp_xgmi_topology_info {
         struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 };
 
-#define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type))
 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index d87e828a084b..d7fae2676269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -131,7 +131,7 @@ struct amdgpu_ring_funcs {
         void (*emit_ib)(struct amdgpu_ring *ring,
                         struct amdgpu_job *job,
                         struct amdgpu_ib *ib,
-                        bool ctx_switch);
+                        uint32_t flags);
         void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
                            uint64_t seq, unsigned flags);
         void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
@@ -229,7 +229,7 @@ struct amdgpu_ring {
 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, job, ib, c) ((r)->funcs->emit_ib((r), (job), (ib), (c)))
+#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 626abca770a0..d3ca2424b5fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -76,9 +76,10 @@ TRACE_EVENT(amdgpu_mm_wreg,
 );
 
 TRACE_EVENT(amdgpu_iv,
-            TP_PROTO(struct amdgpu_iv_entry *iv),
-            TP_ARGS(iv),
+            TP_PROTO(unsigned ih, struct amdgpu_iv_entry *iv),
+            TP_ARGS(ih, iv),
             TP_STRUCT__entry(
+                             __field(unsigned, ih)
                              __field(unsigned, client_id)
                              __field(unsigned, src_id)
                              __field(unsigned, ring_id)
@@ -90,6 +91,7 @@ TRACE_EVENT(amdgpu_iv,
                              __array(unsigned, src_data, 4)
                             ),
             TP_fast_assign(
+                           __entry->ih = ih;
                            __entry->client_id = iv->client_id;
                            __entry->src_id = iv->src_id;
                            __entry->ring_id = iv->ring_id;
@@ -103,8 +105,9 @@ TRACE_EVENT(amdgpu_iv,
                            __entry->src_data[2] = iv->src_data[2];
                            __entry->src_data[3] = iv->src_data[3];
                            ),
-            TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x",
-                      __entry->client_id, __entry->src_id,
+            TP_printk("ih:%u client_id:%u src_id:%u ring:%u vmid:%u "
+                      "timestamp: %llu pasid:%u src_data: %08x %08x %08x %08x",
+                      __entry->ih, __entry->client_id, __entry->src_id,
                       __entry->ring_id, __entry->vmid,
                       __entry->timestamp, __entry->pasid,
                       __entry->src_data[0], __entry->src_data[1],
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c91ec3101d00..b852abb9db0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1546,7 +1546,8 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
         .io_mem_free = &amdgpu_ttm_io_mem_free,
         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
-        .access_memory = &amdgpu_ttm_access_memory
+        .access_memory = &amdgpu_ttm_access_memory,
+        .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 98a1b2ce2b9d..c021b114c8a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -1035,7 +1035,7 @@ out:
 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring,
                                 struct amdgpu_job *job,
                                 struct amdgpu_ib *ib,
-                                bool ctx_switch)
+                                uint32_t flags)
 {
         amdgpu_ring_write(ring, VCE_CMD_IB);
         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index 50293652af14..30ea54dd9117 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
@@ -66,7 +66,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
-                                struct amdgpu_ib *ib, bool ctx_switch);
+                                struct amdgpu_ib *ib, uint32_t flags);
 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
                                 unsigned flags);
 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e73d152659a2..0bc6f553dc08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -623,6 +623,28 @@ void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
         list_add(&entry->tv.head, validated);
 }
 
+void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
+{
+        struct amdgpu_bo *abo;
+        struct amdgpu_vm_bo_base *bo_base;
+
+        if (!amdgpu_bo_is_amdgpu_bo(bo))
+                return;
+
+        if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
+                return;
+
+        abo = ttm_to_amdgpu_bo(bo);
+        if (!abo->parent)
+                return;
+        for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
+                struct amdgpu_vm *vm = bo_base->vm;
+
+                if (abo->tbo.resv == vm->root.base.bo->tbo.resv)
+                        vm->bulk_moveable = false;
+        }
+
+}
 /**
  * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
  *
@@ -799,9 +821,16 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
                 addr += ats_entries * 8;
         }
 
-        if (entries)
+        if (entries) {
+                uint64_t value = 0;
+
+                /* Workaround for fault priority problem on GMC9 */
+                if (level == AMDGPU_VM_PTB && adev->asic_type >= CHIP_VEGA10)
+                        value = AMDGPU_PTE_EXECUTABLE;
+
                 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
-                                      entries, 0, 0);
+                                      entries, 0, value);
+        }
 
         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 
@@ -847,9 +876,6 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
         bp->size = amdgpu_vm_bo_size(adev, level);
         bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
         bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
-        if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 &&
-            adev->flags & AMD_IS_APU)
-                bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
         bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
         bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
                 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
@@ -1506,20 +1532,27 @@ error:
 }
 
 /**
- * amdgpu_vm_update_huge - figure out parameters for PTE updates
+ * amdgpu_vm_update_flags - figure out flags for PTE updates
  *
  * Make sure to set the right flags for the PTEs at the desired level.
  */
-static void amdgpu_vm_update_huge(struct amdgpu_pte_update_params *params,
-                                  struct amdgpu_bo *bo, unsigned level,
-                                  uint64_t pe, uint64_t addr,
-                                  unsigned count, uint32_t incr,
-                                  uint64_t flags)
+static void amdgpu_vm_update_flags(struct amdgpu_pte_update_params *params,
+                                   struct amdgpu_bo *bo, unsigned level,
+                                   uint64_t pe, uint64_t addr,
+                                   unsigned count, uint32_t incr,
+                                   uint64_t flags)
 
 {
         if (level != AMDGPU_VM_PTB) {
                 flags |= AMDGPU_PDE_PTE;
                 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
+
+        } else if (params->adev->asic_type >= CHIP_VEGA10 &&
+                   !(flags & AMDGPU_PTE_VALID) &&
+                   !(flags & AMDGPU_PTE_PRT)) {
+
+                /* Workaround for fault priority problem on GMC9 */
+                flags |= AMDGPU_PTE_EXECUTABLE;
         }
 
         amdgpu_vm_update_func(params, bo, pe, addr, count, incr, flags);
@@ -1676,9 +1709,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
                         uint64_t upd_end = min(entry_end, frag_end);
                         unsigned nptes = (upd_end - frag_start) >> shift;
 
-                        amdgpu_vm_update_huge(params, pt, cursor.level,
-                                              pe_start, dst, nptes, incr,
-                                              flags | AMDGPU_PTE_FRAG(frag));
+                        amdgpu_vm_update_flags(params, pt, cursor.level,
+                                               pe_start, dst, nptes, incr,
+                                               flags | AMDGPU_PTE_FRAG(frag));
 
                         pe_start += nptes * 8;
                         dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
@@ -3006,7 +3039,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
         }
         DRM_DEBUG_DRIVER("VM update mode is %s\n",
                          vm->use_cpu_for_update ? "CPU" : "SDMA");
-        WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
+        WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
                   "CPU update of VM recommended only for large BAR system\n");
         vm->last_update = NULL;
 
@@ -3136,7 +3169,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, uns
         vm->pte_support_ats = pte_support_ats;
         DRM_DEBUG_DRIVER("VM update mode is %s\n",
                          vm->use_cpu_for_update ? "CPU" : "SDMA");
-        WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
+        WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
                   "CPU update of VM recommended only for large BAR system\n");
 
         if (vm->pasid) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index e8dcfd59fc93..81ff8177f092 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -363,4 +363,6 @@ int amdgpu_vm_add_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key)
 
 void amdgpu_vm_clear_fault(struct amdgpu_retryfault_hashtable *fault_hash, u64 key);
 
+void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 8a8bc60cb6b4..dac187454b33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -40,26 +40,40 @@ void *amdgpu_xgmi_hive_try_lock(struct amdgpu_hive_info *hive)
         return &hive->device_list;
 }
 
-struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock)
 {
         int i;
         struct amdgpu_hive_info *tmp;
 
         if (!adev->gmc.xgmi.hive_id)
                 return NULL;
+
+        mutex_lock(&xgmi_mutex);
+
         for (i = 0 ; i < hive_count; ++i) {
                 tmp = &xgmi_hives[i];
-                if (tmp->hive_id == adev->gmc.xgmi.hive_id)
+                if (tmp->hive_id == adev->gmc.xgmi.hive_id) {
+                        if (lock)
+                                mutex_lock(&tmp->hive_lock);
+                        mutex_unlock(&xgmi_mutex);
                         return tmp;
+                }
         }
-        if (i >= AMDGPU_MAX_XGMI_HIVE)
+        if (i >= AMDGPU_MAX_XGMI_HIVE) {
+                mutex_unlock(&xgmi_mutex);
                 return NULL;
+        }
 
         /* initialize new hive if not exist */
         tmp = &xgmi_hives[hive_count++];
         tmp->hive_id = adev->gmc.xgmi.hive_id;
         INIT_LIST_HEAD(&tmp->device_list);
         mutex_init(&tmp->hive_lock);
+        mutex_init(&tmp->reset_lock);
+        if (lock)
+                mutex_lock(&tmp->hive_lock);
+
+        mutex_unlock(&xgmi_mutex);
 
         return tmp;
 }
@@ -111,10 +125,14 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
                 return ret;
         }
 
-        mutex_lock(&xgmi_mutex);
-        hive = amdgpu_get_xgmi_hive(adev);
-        if (!hive)
+        hive = amdgpu_get_xgmi_hive(adev, 1);
+        if (!hive) {
+                ret = -EINVAL;
+                dev_err(adev->dev,
+                        "XGMI: node 0x%llx, can not matech hive 0x%llx in the hive list.\n",
+                        adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
                 goto exit;
+        }
 
         hive_topology = &hive->topology_info;
 
@@ -142,8 +160,8 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
                         break;
         }
 
+        mutex_unlock(&hive->hive_lock);
 exit:
-        mutex_unlock(&xgmi_mutex);
         return ret;
 }
 
@@ -154,15 +172,14 @@ void amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
         if (!adev->gmc.xgmi.supported)
                 return;
 
-        mutex_lock(&xgmi_mutex);
-
-        hive = amdgpu_get_xgmi_hive(adev);
+        hive = amdgpu_get_xgmi_hive(adev, 1);
         if (!hive)
-                goto exit;
+                return;
 
-        if (!(hive->number_devices--))
+        if (!(hive->number_devices--)) {
                 mutex_destroy(&hive->hive_lock);
-
-exit:
-        mutex_unlock(&xgmi_mutex);
+                mutex_destroy(&hive->reset_lock);
+        } else {
+                mutex_unlock(&hive->hive_lock);
+        }
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
index 6151eb9c8ad3..14bc60664159 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
@@ -29,10 +29,11 @@ struct amdgpu_hive_info {
         struct list_head        device_list;
         struct psp_xgmi_topology_info   topology_info;
         int number_devices;
-        struct mutex hive_lock;
+        struct mutex hive_lock,
+                     reset_lock;
 };
 
-struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
+struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock);
 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
 int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
 void amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
deleted file mode 100644
index 86e14c754dd4..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ /dev/null
@@ -1,6844 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <linux/firmware.h>
-#include <drm/drmP.h>
-#include "amdgpu.h"
-#include "amdgpu_pm.h"
-#include "amdgpu_ucode.h"
-#include "cikd.h"
-#include "amdgpu_dpm.h"
-#include "ci_dpm.h"
-#include "gfx_v7_0.h"
-#include "atom.h"
-#include "amd_pcie.h"
-#include <linux/seq_file.h>
-
-#include "smu/smu_7_0_1_d.h"
-#include "smu/smu_7_0_1_sh_mask.h"
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-#include "bif/bif_4_1_d.h"
-#include "bif/bif_4_1_sh_mask.h"
-
-#include "gca/gfx_7_2_d.h"
-#include "gca/gfx_7_2_sh_mask.h"
-
-#include "gmc/gmc_7_1_d.h"
-#include "gmc/gmc_7_1_sh_mask.h"
-
-MODULE_FIRMWARE("amdgpu/bonaire_smc.bin");
-MODULE_FIRMWARE("amdgpu/bonaire_k_smc.bin");
-MODULE_FIRMWARE("amdgpu/hawaii_smc.bin");
-MODULE_FIRMWARE("amdgpu/hawaii_k_smc.bin");
-
-#define MC_CG_ARB_FREQ_F0           0x0a
-#define MC_CG_ARB_FREQ_F1           0x0b
-#define MC_CG_ARB_FREQ_F2           0x0c
-#define MC_CG_ARB_FREQ_F3           0x0d
-
-#define SMC_RAM_END 0x40000
-
-#define VOLTAGE_SCALE               4
-#define VOLTAGE_VID_OFFSET_SCALE1    625
-#define VOLTAGE_VID_OFFSET_SCALE2    100
-
-static const struct amd_pm_funcs ci_dpm_funcs;
-
-static const struct ci_pt_defaults defaults_hawaii_xt =
-{
-        1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
-        { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
-        { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
-};
-
-static const struct ci_pt_defaults defaults_hawaii_pro =
-{
-        1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
-        { 0x2E,  0x00,  0x00,  0x88,  0x00,  0x00,  0x72,  0x60,  0x51,  0xA7,  0x79,  0x6B,  0x90,  0xBD,  0x79  },
-        { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
-};
-
-static const struct ci_pt_defaults defaults_bonaire_xt =
-{
-        1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
-        { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
-        { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
-};
-
-#if 0
-static const struct ci_pt_defaults defaults_bonaire_pro =
-{
-        1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
-        { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
-        { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
-};
-#endif
-
-static const struct ci_pt_defaults defaults_saturn_xt =
-{
-        1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
-        { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
-        { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
-};
-
-#if 0
-static const struct ci_pt_defaults defaults_saturn_pro =
-{
-        1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
-        { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
-        { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
-};
-#endif
-
-static const struct ci_pt_config_reg didt_config_ci[] =
-{
-        { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
-        { 0xFFFFFFFF }
-};
-
-static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
-{
-        return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
-}
-
-#define MC_CG_ARB_FREQ_F0           0x0a
-#define MC_CG_ARB_FREQ_F1           0x0b
-#define MC_CG_ARB_FREQ_F2           0x0c
-#define MC_CG_ARB_FREQ_F3           0x0d
-
-static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
-                                       u32 arb_freq_src, u32 arb_freq_dest)
-{
-        u32 mc_arb_dram_timing;
-        u32 mc_arb_dram_timing2;
-        u32 burst_time;
-        u32 mc_cg_config;
-
-        switch (arb_freq_src) {
-        case MC_CG_ARB_FREQ_F0:
-                mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
-                mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
-                burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
-                         MC_ARB_BURST_TIME__STATE0__SHIFT;
-                break;
-        case MC_CG_ARB_FREQ_F1:
-                mc_arb_dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING_1);
-                mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
-                burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
-                         MC_ARB_BURST_TIME__STATE1__SHIFT;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        switch (arb_freq_dest) {
-        case MC_CG_ARB_FREQ_F0:
-                WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
-                WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
-                WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
-                        ~MC_ARB_BURST_TIME__STATE0_MASK);
-                break;
-        case MC_CG_ARB_FREQ_F1:
-                WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
-                WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
-                WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
-                        ~MC_ARB_BURST_TIME__STATE1_MASK);
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
-        WREG32(mmMC_CG_CONFIG, mc_cg_config);
-        WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
-                ~MC_ARB_CG__CG_ARB_REQ_MASK);
-
-        return 0;
-}
-
-static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
-{
-        u8 mc_para_index;
-
-        if (memory_clock < 10000)
-                mc_para_index = 0;
-        else if (memory_clock >= 80000)
-                mc_para_index = 0x0f;
-        else
-                mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
-        return mc_para_index;
-}
-
-static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
-{
-        u8 mc_para_index;
-
-        if (strobe_mode) {
-                if (memory_clock < 12500)
-                        mc_para_index = 0x00;
-                else if (memory_clock > 47500)
-                        mc_para_index = 0x0f;
-                else
-                        mc_para_index = (u8)((memory_clock - 10000) / 2500);
-        } else {
-                if (memory_clock < 65000)
-                        mc_para_index = 0x00;
-                else if (memory_clock > 135000)
-                        mc_para_index = 0x0f;
-                else
-                        mc_para_index = (u8)((memory_clock - 60000) / 5000);
-        }
-        return mc_para_index;
-}
-
-static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
-                                                     u32 max_voltage_steps,
-                                                     struct atom_voltage_table *voltage_table)
-{
-        unsigned int i, diff;
-
-        if (voltage_table->count <= max_voltage_steps)
-                return;
-
-        diff = voltage_table->count - max_voltage_steps;
-
-        for (i = 0; i < max_voltage_steps; i++)
-                voltage_table->entries[i] = voltage_table->entries[i + diff];
-
-        voltage_table->count = max_voltage_steps;
-}
-
-static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
-                                         struct atom_voltage_table_entry *voltage_table,
-                                         u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
-static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
-static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
-                                       u32 target_tdp);
-static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
-static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
-
-static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
-                                                             PPSMC_Msg msg, u32 parameter);
-static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
-static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
-
-static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = adev->pm.dpm.priv;
-
-        return pi;
-}
-
-static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
-{
-        struct ci_ps *ps = rps->ps_priv;
-
-        return ps;
-}
-
-static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        switch (adev->pdev->device) {
-        case 0x6649:
-        case 0x6650:
-        case 0x6651:
-        case 0x6658:
-        case 0x665C:
-        case 0x665D:
-        default:
-                pi->powertune_defaults = &defaults_bonaire_xt;
-                break;
-        case 0x6640:
-        case 0x6641:
-        case 0x6646:
-        case 0x6647:
-                pi->powertune_defaults = &defaults_saturn_xt;
-                break;
-        case 0x67B8:
-        case 0x67B0:
-                pi->powertune_defaults = &defaults_hawaii_xt;
-                break;
-        case 0x67BA:
-        case 0x67B1:
-                pi->powertune_defaults = &defaults_hawaii_pro;
-                break;
-        case 0x67A0:
-        case 0x67A1:
-        case 0x67A2:
-        case 0x67A8:
-        case 0x67A9:
-        case 0x67AA:
-        case 0x67B9:
-        case 0x67BE:
-                pi->powertune_defaults = &defaults_bonaire_xt;
-                break;
-        }
-
-        pi->dte_tj_offset = 0;
-
-        pi->caps_power_containment = true;
-        pi->caps_cac = false;
-        pi->caps_sq_ramping = false;
-        pi->caps_db_ramping = false;
-        pi->caps_td_ramping = false;
-        pi->caps_tcp_ramping = false;
-
-        if (pi->caps_power_containment) {
-                pi->caps_cac = true;
-                if (adev->asic_type == CHIP_HAWAII)
-                        pi->enable_bapm_feature = false;
-                else
-                        pi->enable_bapm_feature = true;
-                pi->enable_tdc_limit_feature = true;
-                pi->enable_pkg_pwr_tracking_feature = true;
-        }
-}
-
-static u8 ci_convert_to_vid(u16 vddc)
-{
-        return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
-}
-
-static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
-        u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
-        u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
-        u32 i;
-
-        if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
-                return -EINVAL;
-        if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
-                return -EINVAL;
-        if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
-            adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
-                return -EINVAL;
-
-        for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
-                if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
-                        lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
-                        hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
-                        hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
-                } else {
-                        lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
-                        hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
-                }
-        }
-        return 0;
-}
-
-static int ci_populate_vddc_vid(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u8 *vid = pi->smc_powertune_table.VddCVid;
-        u32 i;
-
-        if (pi->vddc_voltage_table.count > 8)
-                return -EINVAL;
-
-        for (i = 0; i < pi->vddc_voltage_table.count; i++)
-                vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
-
-        return 0;
-}
-
-static int ci_populate_svi_load_line(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
-
-        pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
-        pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
-        pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
-        pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
-
-        return 0;
-}
-
-static int ci_populate_tdc_limit(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
-        u16 tdc_limit;
-
-        tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
-        pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
-        pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
-                pt_defaults->tdc_vddc_throttle_release_limit_perc;
-        pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
-
-        return 0;
-}
-
-static int ci_populate_dw8(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
-        int ret;
-
-        ret = amdgpu_ci_read_smc_sram_dword(adev,
-                                     SMU7_FIRMWARE_HEADER_LOCATION +
-                                     offsetof(SMU7_Firmware_Header, PmFuseTable) +
-                                     offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
-                                     (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
-                                     pi->sram_end);
-        if (ret)
-                return -EINVAL;
-        else
-                pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
-
-        return 0;
-}
-
-static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
-            (adev->pm.dpm.fan.fan_output_sensitivity == 0))
-                adev->pm.dpm.fan.fan_output_sensitivity =
-                        adev->pm.dpm.fan.default_fan_output_sensitivity;
-
-        pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
-                cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
-
-        return 0;
-}
-
-static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
-        u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
-        int i, min, max;
-
-        min = max = hi_vid[0];
-        for (i = 0; i < 8; i++) {
-                if (0 != hi_vid[i]) {
-                        if (min > hi_vid[i])
-                                min = hi_vid[i];
-                        if (max < hi_vid[i])
-                                max = hi_vid[i];
-                }
-
-                if (0 != lo_vid[i]) {
-                        if (min > lo_vid[i])
-                                min = lo_vid[i];
-                        if (max < lo_vid[i])
-                                max = lo_vid[i];
-                }
-        }
-
-        if ((min == 0) || (max == 0))
-                return -EINVAL;
-        pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
-        pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
-
-        return 0;
-}
-
-static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
-        u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
-        struct amdgpu_cac_tdp_table *cac_tdp_table =
-                adev->pm.dpm.dyn_state.cac_tdp_table;
-
-        hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
-        lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
-
-        pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
-        pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
-
-        return 0;
-}
-
-static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
-        SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
-        struct amdgpu_cac_tdp_table *cac_tdp_table =
-                adev->pm.dpm.dyn_state.cac_tdp_table;
-        struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
-        int i, j, k;
-        const u16 *def1;
-        const u16 *def2;
-
-        dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
-        dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
-
-        dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
-        dpm_table->GpuTjMax =
-                (u8)(pi->thermal_temp_setting.temperature_high / 1000);
-        dpm_table->GpuTjHyst = 8;
-
-        dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
-
-        if (ppm) {
-                dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
-                dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
-        } else {
-                dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
-                dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
-        }
-
-        dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
-        def1 = pt_defaults->bapmti_r;
-        def2 = pt_defaults->bapmti_rc;
-
-        for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
-                for (j = 0; j < SMU7_DTE_SOURCES; j++) {
-                        for (k = 0; k < SMU7_DTE_SINKS; k++) {
-                                dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
-                                dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
-                                def1++;
-                                def2++;
-                        }
-                }
-        }
-
-        return 0;
-}
-
-static int ci_populate_pm_base(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 pm_fuse_table_offset;
-        int ret;
-
-        if (pi->caps_power_containment) {
-                ret = amdgpu_ci_read_smc_sram_dword(adev,
-                                             SMU7_FIRMWARE_HEADER_LOCATION +
-                                             offsetof(SMU7_Firmware_Header, PmFuseTable),
-                                             &pm_fuse_table_offset, pi->sram_end);
-                if (ret)
-                        return ret;
-                ret = ci_populate_bapm_vddc_vid_sidd(adev);
-                if (ret)
-                        return ret;
-                ret = ci_populate_vddc_vid(adev);
-                if (ret)
-                        return ret;
-                ret = ci_populate_svi_load_line(adev);
-                if (ret)
-                        return ret;
-                ret = ci_populate_tdc_limit(adev);
-                if (ret)
-                        return ret;
-                ret = ci_populate_dw8(adev);
-                if (ret)
-                        return ret;
-                ret = ci_populate_fuzzy_fan(adev);
-                if (ret)
-                        return ret;
-                ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
-                if (ret)
-                        return ret;
-                ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
-                if (ret)
-                        return ret;
-                ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
-                                           (u8 *)&pi->smc_powertune_table,
-                                           sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
-                if (ret)
-                        return ret;
-        }
-
-        return 0;
-}
-
-static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 data;
-
-        if (pi->caps_sq_ramping) {
-                data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
-                if (enable)
-                        data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
-                else
-                        data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
-                WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
-        }
-
-        if (pi->caps_db_ramping) {
-                data = RREG32_DIDT(ixDIDT_DB_CTRL0);
-                if (enable)
-                        data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
-                else
-                        data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
-                WREG32_DIDT(ixDIDT_DB_CTRL0, data);
-        }
-
-        if (pi->caps_td_ramping) {
-                data = RREG32_DIDT(ixDIDT_TD_CTRL0);
-                if (enable)
-                        data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
-                else
-                        data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
-                WREG32_DIDT(ixDIDT_TD_CTRL0, data);
-        }
-
-        if (pi->caps_tcp_ramping) {
-                data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
-                if (enable)
-                        data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
-                else
-                        data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
-                WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
-        }
-}
-
-static int ci_program_pt_config_registers(struct amdgpu_device *adev,
-                                          const struct ci_pt_config_reg *cac_config_regs)
-{
-        const struct ci_pt_config_reg *config_regs = cac_config_regs;
-        u32 data;
-        u32 cache = 0;
-
-        if (config_regs == NULL)
-                return -EINVAL;
-
-        while (config_regs->offset != 0xFFFFFFFF) {
-                if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
-                        cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
-                } else {
-                        switch (config_regs->type) {
-                        case CISLANDS_CONFIGREG_SMC_IND:
-                                data = RREG32_SMC(config_regs->offset);
-                                break;
-                        case CISLANDS_CONFIGREG_DIDT_IND:
-                                data = RREG32_DIDT(config_regs->offset);
-                                break;
-                        default:
-                                data = RREG32(config_regs->offset);
-                                break;
-                        }
-
-                        data &= ~config_regs->mask;
-                        data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
-                        data |= cache;
-
-                        switch (config_regs->type) {
-                        case CISLANDS_CONFIGREG_SMC_IND:
-                                WREG32_SMC(config_regs->offset, data);
-                                break;
-                        case CISLANDS_CONFIGREG_DIDT_IND:
-                                WREG32_DIDT(config_regs->offset, data);
-                                break;
-                        default:
-                                WREG32(config_regs->offset, data);
-                                break;
-                        }
-                        cache = 0;
-                }
-                config_regs++;
-        }
-        return 0;
-}
-
-static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret;
-
-        if (pi->caps_sq_ramping || pi->caps_db_ramping ||
-            pi->caps_td_ramping || pi->caps_tcp_ramping) {
-                amdgpu_gfx_rlc_enter_safe_mode(adev);
-
-                if (enable) {
-                        ret = ci_program_pt_config_registers(adev, didt_config_ci);
-                        if (ret) {
-                                amdgpu_gfx_rlc_exit_safe_mode(adev);
-                                return ret;
-                        }
-                }
-
-                ci_do_enable_didt(adev, enable);
-
-                amdgpu_gfx_rlc_exit_safe_mode(adev);
-        }
-
-        return 0;
-}
-
-static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result;
-        int ret = 0;
-
-        if (enable) {
-                pi->power_containment_features = 0;
-                if (pi->caps_power_containment) {
-                        if (pi->enable_bapm_feature) {
-                                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
-                                if (smc_result != PPSMC_Result_OK)
-                                        ret = -EINVAL;
-                                else
-                                        pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
-                        }
-
-                        if (pi->enable_tdc_limit_feature) {
-                                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
-                                if (smc_result != PPSMC_Result_OK)
-                                        ret = -EINVAL;
-                                else
-                                        pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
-                        }
-
-                        if (pi->enable_pkg_pwr_tracking_feature) {
-                                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
-                                if (smc_result != PPSMC_Result_OK) {
-                                        ret = -EINVAL;
-                                } else {
-                                        struct amdgpu_cac_tdp_table *cac_tdp_table =
-                                                adev->pm.dpm.dyn_state.cac_tdp_table;
-                                        u32 default_pwr_limit =
-                                                (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
-
-                                        pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
-
-                                        ci_set_power_limit(adev, default_pwr_limit);
-                                }
-                        }
-                }
-        } else {
-                if (pi->caps_power_containment && pi->power_containment_features) {
-                        if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
-                                amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
-
-                        if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
-                                amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
-
-                        if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
-                                amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
-                        pi->power_containment_features = 0;
-                }
-        }
-
-        return ret;
-}
-
-static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result;
-        int ret = 0;
-
-        if (pi->caps_cac) {
-                if (enable) {
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
-                        if (smc_result != PPSMC_Result_OK) {
-                                ret = -EINVAL;
-                                pi->cac_enabled = false;
-                        } else {
-                                pi->cac_enabled = true;
-                        }
-                } else if (pi->cac_enabled) {
-                        amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
-                        pi->cac_enabled = false;
-                }
-        }
-
-        return ret;
-}
-
-static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
-                                            bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result = PPSMC_Result_OK;
-
-        if (pi->thermal_sclk_dpm_enabled) {
-                if (enable)
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
-                else
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
-        }
-
-        if (smc_result == PPSMC_Result_OK)
-                return 0;
-        else
-                return -EINVAL;
-}
-
-static int ci_power_control_set_level(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_cac_tdp_table *cac_tdp_table =
-                adev->pm.dpm.dyn_state.cac_tdp_table;
-        s32 adjust_percent;
-        s32 target_tdp;
-        int ret = 0;
-        bool adjust_polarity = false; /* ??? */
-
-        if (pi->caps_power_containment) {
-                adjust_percent = adjust_polarity ?
-                        adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
-                target_tdp = ((100 + adjust_percent) *
-                              (s32)cac_tdp_table->configurable_tdp) / 100;
-
-                ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
-        }
-
-        return ret;
-}
-
-static void ci_dpm_powergate_uvd(void *handle, bool gate)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        pi->uvd_power_gated = gate;
-
-        if (gate) {
-                /* stop the UVD block */
-                amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                       AMD_PG_STATE_GATE);
-                ci_update_uvd_dpm(adev, gate);
-        } else {
-                amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
-                                                       AMD_PG_STATE_UNGATE);
-                ci_update_uvd_dpm(adev, gate);
-        }
-}
-
-static bool ci_dpm_vblank_too_short(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
-        u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
-
-        /* disable mclk switching if the refresh is >120Hz, even if the
-         * blanking period would allow it
-         */
-        if (amdgpu_dpm_get_vrefresh(adev) > 120)
-                return true;
-
-        if (vblank_time < switch_limit)
-                return true;
-        else
-                return false;
-
-}
-
-static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
-                                        struct amdgpu_ps *rps)
-{
-        struct ci_ps *ps = ci_get_ps(rps);
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_clock_and_voltage_limits *max_limits;
-        bool disable_mclk_switching;
-        u32 sclk, mclk;
-        int i;
-
-        if (rps->vce_active) {
-                rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
-                rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
-        } else {
-                rps->evclk = 0;
-                rps->ecclk = 0;
-        }
-
-        if ((adev->pm.dpm.new_active_crtc_count > 1) ||
-            ci_dpm_vblank_too_short(adev))
-                disable_mclk_switching = true;
-        else
-                disable_mclk_switching = false;
-
-        if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
-                pi->battery_state = true;
-        else
-                pi->battery_state = false;
-
-        if (adev->pm.ac_power)
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
-        else
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
-
-        if (adev->pm.ac_power == false) {
-                for (i = 0; i < ps->performance_level_count; i++) {
-                        if (ps->performance_levels[i].mclk > max_limits->mclk)
-                                ps->performance_levels[i].mclk = max_limits->mclk;
-                        if (ps->performance_levels[i].sclk > max_limits->sclk)
-                                ps->performance_levels[i].sclk = max_limits->sclk;
-                }
-        }
-
-        /* XXX validate the min clocks required for display */
-
-        if (disable_mclk_switching) {
-                mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
-                sclk = ps->performance_levels[0].sclk;
-        } else {
-                mclk = ps->performance_levels[0].mclk;
-                sclk = ps->performance_levels[0].sclk;
-        }
-
-        if (adev->pm.pm_display_cfg.min_core_set_clock > sclk)
-                sclk = adev->pm.pm_display_cfg.min_core_set_clock;
-
-        if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk)
-                mclk = adev->pm.pm_display_cfg.min_mem_set_clock;
-
-        if (rps->vce_active) {
-                if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
-                        sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
-                if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
-                        mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
-        }
-
-        ps->performance_levels[0].sclk = sclk;
-        ps->performance_levels[0].mclk = mclk;
-
-        if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
-                ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
-
-        if (disable_mclk_switching) {
-                if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
-                        ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
-        } else {
-                if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
-                        ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
-        }
-}
-
-static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
-                                            int min_temp, int max_temp)
-{
-        int low_temp = 0 * 1000;
-        int high_temp = 255 * 1000;
-        u32 tmp;
-
-        if (low_temp < min_temp)
-                low_temp = min_temp;
-        if (high_temp > max_temp)
-                high_temp = max_temp;
-        if (high_temp < low_temp) {
-                DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
-                return -EINVAL;
-        }
-
-        tmp = RREG32_SMC(ixCG_THERMAL_INT);
-        tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
-        tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
-                ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
-        WREG32_SMC(ixCG_THERMAL_INT, tmp);
-
-#if 0
-        /* XXX: need to figure out how to handle this properly */
-        tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
-        tmp &= DIG_THERM_DPM_MASK;
-        tmp |= DIG_THERM_DPM(high_temp / 1000);
-        WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
-#endif
-
-        adev->pm.dpm.thermal.min_temp = low_temp;
-        adev->pm.dpm.thermal.max_temp = high_temp;
-        return 0;
-}
-
-static int ci_thermal_enable_alert(struct amdgpu_device *adev,
-                                   bool enable)
-{
-        u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
-        PPSMC_Result result;
-
-        if (enable) {
-                thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
-                                 CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
-                WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
-                result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
-                if (result != PPSMC_Result_OK) {
-                        DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
-                        return -EINVAL;
-                }
-        } else {
-                thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
-                        CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
-                WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
-                result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
-                if (result != PPSMC_Result_OK) {
-                        DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
-                        return -EINVAL;
-                }
-        }
-
-        return 0;
-}
-
-static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp;
-
-        if (pi->fan_ctrl_is_in_default_mode) {
-                tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
-                        >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
-                pi->fan_ctrl_default_mode = tmp;
-                tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
-                        >> CG_FDO_CTRL2__TMIN__SHIFT;
-                pi->t_min = tmp;
-                pi->fan_ctrl_is_in_default_mode = false;
-        }
-
-        tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
-        tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
-        WREG32_SMC(ixCG_FDO_CTRL2, tmp);
-
-        tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
-        tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
-        WREG32_SMC(ixCG_FDO_CTRL2, tmp);
-}
-
-static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
-        u32 duty100;
-        u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
-        u16 fdo_min, slope1, slope2;
-        u32 reference_clock, tmp;
-        int ret;
-        u64 tmp64;
-
-        if (!pi->fan_table_start) {
-                adev->pm.dpm.fan.ucode_fan_control = false;
-                return 0;
-        }
-
-        duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
-                >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
-
-        if (duty100 == 0) {
-                adev->pm.dpm.fan.ucode_fan_control = false;
-                return 0;
-        }
-
-        tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
-        do_div(tmp64, 10000);
-        fdo_min = (u16)tmp64;
-
-        t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
-        t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
-
-        pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
-        pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
-
-        slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
-        slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
-
-        fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
-        fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
-        fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
-
-        fan_table.Slope1 = cpu_to_be16(slope1);
-        fan_table.Slope2 = cpu_to_be16(slope2);
-
-        fan_table.FdoMin = cpu_to_be16(fdo_min);
-
-        fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
-
-        fan_table.HystUp = cpu_to_be16(1);
-
-        fan_table.HystSlope = cpu_to_be16(1);
-
-        fan_table.TempRespLim = cpu_to_be16(5);
-
-        reference_clock = amdgpu_asic_get_xclk(adev);
-
-        fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
-                                               reference_clock) / 1600);
-
-        fan_table.FdoMax = cpu_to_be16((u16)duty100);
-
-        tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
-                >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
-        fan_table.TempSrc = (uint8_t)tmp;
-
-        ret = amdgpu_ci_copy_bytes_to_smc(adev,
-                                          pi->fan_table_start,
-                                          (u8 *)(&fan_table),
-                                          sizeof(fan_table),
-                                          pi->sram_end);
-
-        if (ret) {
-                DRM_ERROR("Failed to load fan table to the SMC.");
-                adev->pm.dpm.fan.ucode_fan_control = false;
-        }
-
-        return 0;
-}
-
-static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result ret;
-
-        if (pi->caps_od_fuzzy_fan_control_support) {
-                ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                               PPSMC_StartFanControl,
-                                                               FAN_CONTROL_FUZZY);
-                if (ret != PPSMC_Result_OK)
-                        return -EINVAL;
-                ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                               PPSMC_MSG_SetFanPwmMax,
-                                                               adev->pm.dpm.fan.default_max_fan_pwm);
-                if (ret != PPSMC_Result_OK)
-                        return -EINVAL;
-        } else {
-                ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                               PPSMC_StartFanControl,
-                                                               FAN_CONTROL_TABLE);
-                if (ret != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        pi->fan_is_controlled_by_smc = true;
-        return 0;
-}
-
-
-static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
-{
-        PPSMC_Result ret;
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
-        if (ret == PPSMC_Result_OK) {
-                pi->fan_is_controlled_by_smc = false;
-                return 0;
-        } else {
-                return -EINVAL;
-        }
-}
-
-static int ci_dpm_get_fan_speed_percent(void *handle,
-                                        u32 *speed)
-{
-        u32 duty, duty100;
-        u64 tmp64;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (adev->pm.no_fan)
-                return -ENOENT;
-
-        duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
-                >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
-        duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
-                >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
-
-        if (duty100 == 0)
-                return -EINVAL;
-
-        tmp64 = (u64)duty * 100;
-        do_div(tmp64, duty100);
-        *speed = (u32)tmp64;
-
-        if (*speed > 100)
-                *speed = 100;
-
-        return 0;
-}
-
-static int ci_dpm_set_fan_speed_percent(void *handle,
-                                        u32 speed)
-{
-        u32 tmp;
-        u32 duty, duty100;
-        u64 tmp64;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (adev->pm.no_fan)
-                return -ENOENT;
-
-        if (pi->fan_is_controlled_by_smc)
-                return -EINVAL;
-
-        if (speed > 100)
-                return -EINVAL;
-
-        duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
-                >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
-
-        if (duty100 == 0)
-                return -EINVAL;
-
-        tmp64 = (u64)speed * duty100;
-        do_div(tmp64, 100);
-        duty = (u32)tmp64;
-
-        tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
-        tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
-        WREG32_SMC(ixCG_FDO_CTRL0, tmp);
-
-        return 0;
-}
-
-static void ci_dpm_set_fan_control_mode(void *handle, u32 mode)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        switch (mode) {
-        case AMD_FAN_CTRL_NONE:
-                if (adev->pm.dpm.fan.ucode_fan_control)
-                        ci_fan_ctrl_stop_smc_fan_control(adev);
-                ci_dpm_set_fan_speed_percent(adev, 100);
-                break;
-        case AMD_FAN_CTRL_MANUAL:
-                if (adev->pm.dpm.fan.ucode_fan_control)
-                        ci_fan_ctrl_stop_smc_fan_control(adev);
-                break;
-        case AMD_FAN_CTRL_AUTO:
-                if (adev->pm.dpm.fan.ucode_fan_control)
-                        ci_thermal_start_smc_fan_control(adev);
-                break;
-        default:
-                break;
-        }
-}
-
-static u32 ci_dpm_get_fan_control_mode(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (pi->fan_is_controlled_by_smc)
-                return AMD_FAN_CTRL_AUTO;
-        else
-                return AMD_FAN_CTRL_MANUAL;
-}
-
-#if 0
-static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
-                                         u32 *speed)
-{
-        u32 tach_period;
-        u32 xclk = amdgpu_asic_get_xclk(adev);
-
-        if (adev->pm.no_fan)
-                return -ENOENT;
-
-        if (adev->pm.fan_pulses_per_revolution == 0)
-                return -ENOENT;
-
-        tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
-                >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
-        if (tach_period == 0)
-                return -ENOENT;
-
-        *speed = 60 * xclk * 10000 / tach_period;
-
-        return 0;
-}
-
-static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
-                                         u32 speed)
-{
-        u32 tach_period, tmp;
-        u32 xclk = amdgpu_asic_get_xclk(adev);
-
-        if (adev->pm.no_fan)
-                return -ENOENT;
-
-        if (adev->pm.fan_pulses_per_revolution == 0)
-                return -ENOENT;
-
-        if ((speed < adev->pm.fan_min_rpm) ||
-            (speed > adev->pm.fan_max_rpm))
-                return -EINVAL;
-
-        if (adev->pm.dpm.fan.ucode_fan_control)
-                ci_fan_ctrl_stop_smc_fan_control(adev);
-
-        tach_period = 60 * xclk * 10000 / (8 * speed);
-        tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
-        tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
-        WREG32_SMC(CG_TACH_CTRL, tmp);
-
-        ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
-
-        return 0;
-}
-#endif
-
-static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp;
-
-        if (!pi->fan_ctrl_is_in_default_mode) {
-                tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
-                tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
-                WREG32_SMC(ixCG_FDO_CTRL2, tmp);
-
-                tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
-                tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
-                WREG32_SMC(ixCG_FDO_CTRL2, tmp);
-                pi->fan_ctrl_is_in_default_mode = true;
-        }
-}
-
-static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
-{
-        if (adev->pm.dpm.fan.ucode_fan_control) {
-                ci_fan_ctrl_start_smc_fan_control(adev);
-                ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
-        }
-}
-
-static void ci_thermal_initialize(struct amdgpu_device *adev)
-{
-        u32 tmp;
-
-        if (adev->pm.fan_pulses_per_revolution) {
-                tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
-                tmp |= (adev->pm.fan_pulses_per_revolution - 1)
-                        << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
-                WREG32_SMC(ixCG_TACH_CTRL, tmp);
-        }
-
-        tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
-        tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
-        WREG32_SMC(ixCG_FDO_CTRL2, tmp);
-}
-
-static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
-{
-        int ret;
-
-        ci_thermal_initialize(adev);
-        ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
-        if (ret)
-                return ret;
-        ret = ci_thermal_enable_alert(adev, true);
-        if (ret)
-                return ret;
-        if (adev->pm.dpm.fan.ucode_fan_control) {
-                ret = ci_thermal_setup_fan_table(adev);
-                if (ret)
-                        return ret;
-                ci_thermal_start_smc_fan_control(adev);
-        }
-
-        return 0;
-}
-
-static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
-{
-        if (!adev->pm.no_fan)
-                ci_fan_ctrl_set_default_mode(adev);
-}
-
-static int ci_read_smc_soft_register(struct amdgpu_device *adev,
-                                     u16 reg_offset, u32 *value)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        return amdgpu_ci_read_smc_sram_dword(adev,
-                                      pi->soft_regs_start + reg_offset,
-                                      value, pi->sram_end);
-}
-
-static int ci_write_smc_soft_register(struct amdgpu_device *adev,
-                                      u16 reg_offset, u32 value)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        return amdgpu_ci_write_smc_sram_dword(adev,
-                                       pi->soft_regs_start + reg_offset,
-                                       value, pi->sram_end);
-}
-
-static void ci_init_fps_limits(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
-
-        if (pi->caps_fps) {
-                u16 tmp;
-
-                tmp = 45;
-                table->FpsHighT = cpu_to_be16(tmp);
-
-                tmp = 30;
-                table->FpsLowT = cpu_to_be16(tmp);
-        }
-}
-
-static int ci_update_sclk_t(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret = 0;
-        u32 low_sclk_interrupt_t = 0;
-
-        if (pi->caps_sclk_throttle_low_notification) {
-                low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
-
-                ret = amdgpu_ci_copy_bytes_to_smc(adev,
-                                           pi->dpm_table_start +
-                                           offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
-                                           (u8 *)&low_sclk_interrupt_t,
-                                           sizeof(u32), pi->sram_end);
-
-        }
-
-        return ret;
-}
-
-static void ci_get_leakage_voltages(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u16 leakage_id, virtual_voltage_id;
-        u16 vddc, vddci;
-        int i;
-
-        pi->vddc_leakage.count = 0;
-        pi->vddci_leakage.count = 0;
-
-        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
-                for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
-                        virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
-                        if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
-                                continue;
-                        if (vddc != 0 && vddc != virtual_voltage_id) {
-                                pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
-                                pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
-                                pi->vddc_leakage.count++;
-                        }
-                }
-        } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
-                for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
-                        virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
-                        if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
-                                                                                     virtual_voltage_id,
-                                                                                     leakage_id) == 0) {
-                                if (vddc != 0 && vddc != virtual_voltage_id) {
-                                        pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
-                                        pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
-                                        pi->vddc_leakage.count++;
-                                }
-                                if (vddci != 0 && vddci != virtual_voltage_id) {
-                                        pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
-                                        pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
-                                        pi->vddci_leakage.count++;
-                                }
-                        }
-                }
-        }
-}
-
-static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        bool want_thermal_protection;
-        enum amdgpu_dpm_event_src dpm_event_src;
-        u32 tmp;
-
-        switch (sources) {
-        case 0:
-        default:
-                want_thermal_protection = false;
-                break;
-        case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
-                want_thermal_protection = true;
-                dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
-                break;
-        case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
-                want_thermal_protection = true;
-                dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
-                break;
-        case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
-              (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
-                want_thermal_protection = true;
-                dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
-                break;
-        }
-
-        if (want_thermal_protection) {
-#if 0
-                /* XXX: need to figure out how to handle this properly */
-                tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
-                tmp &= DPM_EVENT_SRC_MASK;
-                tmp |= DPM_EVENT_SRC(dpm_event_src);
-                WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
-#endif
-
-                tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-                if (pi->thermal_protection)
-                        tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
-                else
-                        tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
-                WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-        } else {
-                tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-                tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
-                WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-        }
-}
-
-static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
-                                           enum amdgpu_dpm_auto_throttle_src source,
-                                           bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (enable) {
-                if (!(pi->active_auto_throttle_sources & (1 << source))) {
-                        pi->active_auto_throttle_sources |= 1 << source;
-                        ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
-                }
-        } else {
-                if (pi->active_auto_throttle_sources & (1 << source)) {
-                        pi->active_auto_throttle_sources &= ~(1 << source);
-                        ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
-                }
-        }
-}
-
-static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
-{
-        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
-                amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
-}
-
-static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result;
-
-        if (!pi->need_update_smu7_dpm_table)
-                return 0;
-
-        if ((!pi->sclk_dpm_key_disabled) &&
-            (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
-                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        if ((!pi->mclk_dpm_key_disabled) &&
-            (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
-                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        pi->need_update_smu7_dpm_table = 0;
-        return 0;
-}
-
-static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result;
-
-        if (enable) {
-                if (!pi->sclk_dpm_key_disabled) {
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
-                        if (smc_result != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-
-                if (!pi->mclk_dpm_key_disabled) {
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
-                        if (smc_result != PPSMC_Result_OK)
-                                return -EINVAL;
-
-                        WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
-                                        ~MC_SEQ_CNTL_3__CAC_EN_MASK);
-
-                        WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
-                        WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
-                        WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
-
-                        udelay(10);
-
-                        WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
-                        WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
-                        WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
-                }
-        } else {
-                if (!pi->sclk_dpm_key_disabled) {
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
-                        if (smc_result != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-
-                if (!pi->mclk_dpm_key_disabled) {
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
-                        if (smc_result != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-        }
-
-        return 0;
-}
-
-static int ci_start_dpm(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result;
-        int ret;
-        u32 tmp;
-
-        tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-        tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
-        WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-
-        tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
-        tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
-        WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
-
-        ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
-
-        WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
-
-        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
-        if (smc_result != PPSMC_Result_OK)
-                return -EINVAL;
-
-        ret = ci_enable_sclk_mclk_dpm(adev, true);
-        if (ret)
-                return ret;
-
-        if (!pi->pcie_dpm_key_disabled) {
-                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result;
-
-        if (!pi->need_update_smu7_dpm_table)
-                return 0;
-
-        if ((!pi->sclk_dpm_key_disabled) &&
-            (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
-                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        if ((!pi->mclk_dpm_key_disabled) &&
-            (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
-                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int ci_stop_dpm(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result smc_result;
-        int ret;
-        u32 tmp;
-
-        tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-        tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
-        WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-
-        tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
-        tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
-        WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
-
-        if (!pi->pcie_dpm_key_disabled) {
-                smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        ret = ci_enable_sclk_mclk_dpm(adev, false);
-        if (ret)
-                return ret;
-
-        smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
-        if (smc_result != PPSMC_Result_OK)
-                return -EINVAL;
-
-        return 0;
-}
-
-static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
-{
-        u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
-
-        if (enable)
-                tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
-        else
-                tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
-        WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
-}
-
-#if 0
-static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
-                                        bool ac_power)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_cac_tdp_table *cac_tdp_table =
-                adev->pm.dpm.dyn_state.cac_tdp_table;
-        u32 power_limit;
-
-        if (ac_power)
-                power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
-        else
-                power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
-
-        ci_set_power_limit(adev, power_limit);
-
-        if (pi->caps_automatic_dc_transition) {
-                if (ac_power)
-                        amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
-                else
-                        amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
-        }
-
-        return 0;
-}
-#endif
-
-static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
-                                                      PPSMC_Msg msg, u32 parameter)
-{
-        WREG32(mmSMC_MSG_ARG_0, parameter);
-        return amdgpu_ci_send_msg_to_smc(adev, msg);
-}
-
-static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
-                                                        PPSMC_Msg msg, u32 *parameter)
-{
-        PPSMC_Result smc_result;
-
-        smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
-
-        if ((smc_result == PPSMC_Result_OK) && parameter)
-                *parameter = RREG32(mmSMC_MSG_ARG_0);
-
-        return smc_result;
-}
-
-static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (!pi->sclk_dpm_key_disabled) {
-                PPSMC_Result smc_result =
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (!pi->mclk_dpm_key_disabled) {
-                PPSMC_Result smc_result =
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (!pi->pcie_dpm_key_disabled) {
-                PPSMC_Result smc_result =
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
-                PPSMC_Result smc_result =
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
-                if (smc_result != PPSMC_Result_OK)
-                        return -EINVAL;
-        }
-
-        return 0;
-}
-
-static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
-                                       u32 target_tdp)
-{
-        PPSMC_Result smc_result =
-                amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
-        if (smc_result != PPSMC_Result_OK)
-                return -EINVAL;
-        return 0;
-}
-
-#if 0
-static int ci_set_boot_state(struct amdgpu_device *adev)
-{
-        return ci_enable_sclk_mclk_dpm(adev, false);
-}
-#endif
-
-static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
-{
-        u32 sclk_freq;
-        PPSMC_Result smc_result =
-                amdgpu_ci_send_msg_to_smc_return_parameter(adev,
-                                                    PPSMC_MSG_API_GetSclkFrequency,
-                                                    &sclk_freq);
-        if (smc_result != PPSMC_Result_OK)
-                sclk_freq = 0;
-
-        return sclk_freq;
-}
-
-static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
-{
-        u32 mclk_freq;
-        PPSMC_Result smc_result =
-                amdgpu_ci_send_msg_to_smc_return_parameter(adev,
-                                                    PPSMC_MSG_API_GetMclkFrequency,
-                                                    &mclk_freq);
-        if (smc_result != PPSMC_Result_OK)
-                mclk_freq = 0;
-
-        return mclk_freq;
-}
-
-static void ci_dpm_start_smc(struct amdgpu_device *adev)
-{
-        int i;
-
-        amdgpu_ci_program_jump_on_start(adev);
-        amdgpu_ci_start_smc_clock(adev);
-        amdgpu_ci_start_smc(adev);
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
-                        break;
-        }
-}
-
-static void ci_dpm_stop_smc(struct amdgpu_device *adev)
-{
-        amdgpu_ci_reset_smc(adev);
-        amdgpu_ci_stop_smc_clock(adev);
-}
-
-static int ci_process_firmware_header(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp;
-        int ret;
-
-        ret = amdgpu_ci_read_smc_sram_dword(adev,
-                                     SMU7_FIRMWARE_HEADER_LOCATION +
-                                     offsetof(SMU7_Firmware_Header, DpmTable),
-                                     &tmp, pi->sram_end);
-        if (ret)
-                return ret;
-
-        pi->dpm_table_start = tmp;
-
-        ret = amdgpu_ci_read_smc_sram_dword(adev,
-                                     SMU7_FIRMWARE_HEADER_LOCATION +
-                                     offsetof(SMU7_Firmware_Header, SoftRegisters),
-                                     &tmp, pi->sram_end);
-        if (ret)
-                return ret;
-
-        pi->soft_regs_start = tmp;
-
-        ret = amdgpu_ci_read_smc_sram_dword(adev,
-                                     SMU7_FIRMWARE_HEADER_LOCATION +
-                                     offsetof(SMU7_Firmware_Header, mcRegisterTable),
-                                     &tmp, pi->sram_end);
-        if (ret)
-                return ret;
-
-        pi->mc_reg_table_start = tmp;
-
-        ret = amdgpu_ci_read_smc_sram_dword(adev,
-                                     SMU7_FIRMWARE_HEADER_LOCATION +
-                                     offsetof(SMU7_Firmware_Header, FanTable),
-                                     &tmp, pi->sram_end);
-        if (ret)
-                return ret;
-
-        pi->fan_table_start = tmp;
-
-        ret = amdgpu_ci_read_smc_sram_dword(adev,
-                                     SMU7_FIRMWARE_HEADER_LOCATION +
-                                     offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
-                                     &tmp, pi->sram_end);
-        if (ret)
-                return ret;
-
-        pi->arb_table_start = tmp;
-
-        return 0;
-}
-
-static void ci_read_clock_registers(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        pi->clock_registers.cg_spll_func_cntl =
-                RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
-        pi->clock_registers.cg_spll_func_cntl_2 =
-                RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
-        pi->clock_registers.cg_spll_func_cntl_3 =
-                RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
-        pi->clock_registers.cg_spll_func_cntl_4 =
-                RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
-        pi->clock_registers.cg_spll_spread_spectrum =
-                RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
-        pi->clock_registers.cg_spll_spread_spectrum_2 =
-                RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
-        pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
-        pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
-        pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
-        pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
-        pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
-        pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
-        pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
-        pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
-        pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
-}
-
-static void ci_init_sclk_t(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        pi->low_sclk_interrupt_t = 0;
-}
-
-static void ci_enable_thermal_protection(struct amdgpu_device *adev,
-                                         bool enable)
-{
-        u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-
-        if (enable)
-                tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
-        else
-                tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
-        WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-}
-
-static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-
-        tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
-
-        WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-}
-
-#if 0
-static int ci_enter_ulp_state(struct amdgpu_device *adev)
-{
-
-        WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
-
-        udelay(25000);
-
-        return 0;
-}
-
-static int ci_exit_ulp_state(struct amdgpu_device *adev)
-{
-        int i;
-
-        WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
-
-        udelay(7000);
-
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (RREG32(mmSMC_RESP_0) == 1)
-                        break;
-                udelay(1000);
-        }
-
-        return 0;
-}
-#endif
-
-static int ci_notify_smc_display_change(struct amdgpu_device *adev,
-                                        bool has_display)
-{
-        PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
-
-        return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
-}
-
-static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
-                                      bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (enable) {
-                if (pi->caps_sclk_ds) {
-                        if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
-                                return -EINVAL;
-                } else {
-                        if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-        } else {
-                if (pi->caps_sclk_ds) {
-                        if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-        }
-
-        return 0;
-}
-
-static void ci_program_display_gap(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
-        u32 pre_vbi_time_in_us;
-        u32 frame_time_in_us;
-        u32 ref_clock = adev->clock.spll.reference_freq;
-        u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
-        u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
-
-        tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
-        if (adev->pm.dpm.new_active_crtc_count > 0)
-                tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
-        else
-                tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
-        WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
-
-        if (refresh_rate == 0)
-                refresh_rate = 60;
-        if (vblank_time == 0xffffffff)
-                vblank_time = 500;
-        frame_time_in_us = 1000000 / refresh_rate;
-        pre_vbi_time_in_us =
-                frame_time_in_us - 200 - vblank_time;
-        tmp = pre_vbi_time_in_us * (ref_clock / 100);
-
-        WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
-        ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
-        ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
-
-
-        ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
-
-}
-
-static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp;
-
-        if (enable) {
-                if (pi->caps_sclk_ss_support) {
-                        tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-                        tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
-                        WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-                }
-        } else {
-                tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
-                tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
-                WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
-
-                tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-                tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
-                WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-        }
-}
-
-static void ci_program_sstp(struct amdgpu_device *adev)
-{
-        WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
-        ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
-         (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
-}
-
-static void ci_enable_display_gap(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
-
-        tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
-                        CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
-        tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
-                (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
-
-        WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
-}
-
-static void ci_program_vc(struct amdgpu_device *adev)
-{
-        u32 tmp;
-
-        tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
-        tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
-        WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
-
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
-}
-
-static void ci_clear_vc(struct amdgpu_device *adev)
-{
-        u32 tmp;
-
-        tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
-        tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
-        WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
-
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
-        WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
-}
-
-static int ci_upload_firmware(struct amdgpu_device *adev)
-{
-        int i, ret;
-
-        if (amdgpu_ci_is_smc_running(adev)) {
-                DRM_INFO("smc is running, no need to load smc firmware\n");
-                return 0;
-        }
-
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
-                        break;
-        }
-        WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
-
-        amdgpu_ci_stop_smc_clock(adev);
-        amdgpu_ci_reset_smc(adev);
-
-        ret = amdgpu_ci_load_smc_ucode(adev, SMC_RAM_END);
-
-        return ret;
-
-}
-
-static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
-                                     struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
-                                     struct atom_voltage_table *voltage_table)
-{
-        u32 i;
-
-        if (voltage_dependency_table == NULL)
-                return -EINVAL;
-
-        voltage_table->mask_low = 0;
-        voltage_table->phase_delay = 0;
-
-        voltage_table->count = voltage_dependency_table->count;
-        for (i = 0; i < voltage_table->count; i++) {
-                voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
-                voltage_table->entries[i].smio_low = 0;
-        }
-
-        return 0;
-}
-
-static int ci_construct_voltage_tables(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret;
-
-        if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
-                ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
-                                                        VOLTAGE_OBJ_GPIO_LUT,
-                                                        &pi->vddc_voltage_table);
-                if (ret)
-                        return ret;
-        } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
-                ret = ci_get_svi2_voltage_table(adev,
-                                                &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
-                                                &pi->vddc_voltage_table);
-                if (ret)
-                        return ret;
-        }
-
-        if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
-                ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
-                                                         &pi->vddc_voltage_table);
-
-        if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
-                ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
-                                                        VOLTAGE_OBJ_GPIO_LUT,
-                                                        &pi->vddci_voltage_table);
-                if (ret)
-                        return ret;
-        } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
-                ret = ci_get_svi2_voltage_table(adev,
-                                                &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
-                                                &pi->vddci_voltage_table);
-                if (ret)
-                        return ret;
-        }
-
-        if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
-                ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
-                                                         &pi->vddci_voltage_table);
-
-        if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
-                ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
-                                                        VOLTAGE_OBJ_GPIO_LUT,
-                                                        &pi->mvdd_voltage_table);
-                if (ret)
-                        return ret;
-        } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
-                ret = ci_get_svi2_voltage_table(adev,
-                                                &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
-                                                &pi->mvdd_voltage_table);
-                if (ret)
-                        return ret;
-        }
-
-        if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
-                ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
-                                                         &pi->mvdd_voltage_table);
-
-        return 0;
-}
-
-static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
-                                          struct atom_voltage_table_entry *voltage_table,
-                                          SMU7_Discrete_VoltageLevel *smc_voltage_table)
-{
-        int ret;
-
-        ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
-                                            &smc_voltage_table->StdVoltageHiSidd,
-                                            &smc_voltage_table->StdVoltageLoSidd);
-
-        if (ret) {
-                smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
-                smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
-        }
-
-        smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
-        smc_voltage_table->StdVoltageHiSidd =
-                cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
-        smc_voltage_table->StdVoltageLoSidd =
-                cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
-}
-
-static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
-                                      SMU7_Discrete_DpmTable *table)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        unsigned int count;
-
-        table->VddcLevelCount = pi->vddc_voltage_table.count;
-        for (count = 0; count < table->VddcLevelCount; count++) {
-                ci_populate_smc_voltage_table(adev,
-                                              &pi->vddc_voltage_table.entries[count],
-                                              &table->VddcLevel[count]);
-
-                if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
-                        table->VddcLevel[count].Smio |=
-                                pi->vddc_voltage_table.entries[count].smio_low;
-                else
-                        table->VddcLevel[count].Smio = 0;
-        }
-        table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
-
-        return 0;
-}
-
-static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
-                                       SMU7_Discrete_DpmTable *table)
-{
-        unsigned int count;
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        table->VddciLevelCount = pi->vddci_voltage_table.count;
-        for (count = 0; count < table->VddciLevelCount; count++) {
-                ci_populate_smc_voltage_table(adev,
-                                              &pi->vddci_voltage_table.entries[count],
-                                              &table->VddciLevel[count]);
-
-                if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
-                        table->VddciLevel[count].Smio |=
-                                pi->vddci_voltage_table.entries[count].smio_low;
-                else
-                        table->VddciLevel[count].Smio = 0;
-        }
-        table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
-
-        return 0;
-}
-
-static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
-                                      SMU7_Discrete_DpmTable *table)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        unsigned int count;
-
-        table->MvddLevelCount = pi->mvdd_voltage_table.count;
-        for (count = 0; count < table->MvddLevelCount; count++) {
-                ci_populate_smc_voltage_table(adev,
-                                              &pi->mvdd_voltage_table.entries[count],
-                                              &table->MvddLevel[count]);
-
-                if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
-                        table->MvddLevel[count].Smio |=
-                                pi->mvdd_voltage_table.entries[count].smio_low;
-                else
-                        table->MvddLevel[count].Smio = 0;
-        }
-        table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
-
-        return 0;
-}
-
-static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
-                                          SMU7_Discrete_DpmTable *table)
-{
-        int ret;
-
-        ret = ci_populate_smc_vddc_table(adev, table);
-        if (ret)
-                return ret;
-
-        ret = ci_populate_smc_vddci_table(adev, table);
-        if (ret)
-                return ret;
-
-        ret = ci_populate_smc_mvdd_table(adev, table);
-        if (ret)
-                return ret;
-
-        return 0;
-}
-
-static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
-                                  SMU7_Discrete_VoltageLevel *voltage)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 i = 0;
-
-        if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
-                for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
-                        if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
-                                voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
-                                break;
-                        }
-                }
-
-                if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
-                        return -EINVAL;
-        }
-
-        return -EINVAL;
-}
-
-static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
-                                         struct atom_voltage_table_entry *voltage_table,
-                                         u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
-{
-        u16 v_index, idx;
-        bool voltage_found = false;
-        *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
-        *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
-
-        if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
-                return -EINVAL;
-
-        if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
-                for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
-                        if (voltage_table->value ==
-                            adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
-                                voltage_found = true;
-                                if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
-                                        idx = v_index;
-                                else
-                                        idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
-                                *std_voltage_lo_sidd =
-                                        adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
-                                *std_voltage_hi_sidd =
-                                        adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
-                                break;
-                        }
-                }
-
-                if (!voltage_found) {
-                        for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
-                                if (voltage_table->value <=
-                                    adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
-                                        voltage_found = true;
-                                        if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
-                                                idx = v_index;
-                                        else
-                                                idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
-                                        *std_voltage_lo_sidd =
-                                                adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
-                                        *std_voltage_hi_sidd =
-                                                adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
-                                        break;
-                                }
-                        }
-                }
-        }
-
-        return 0;
-}
-
-static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
-                                                  const struct amdgpu_phase_shedding_limits_table *limits,
-                                                  u32 sclk,
-                                                  u32 *phase_shedding)
-{
-        unsigned int i;
-
-        *phase_shedding = 1;
-
-        for (i = 0; i < limits->count; i++) {
-                if (sclk < limits->entries[i].sclk) {
-                        *phase_shedding = i;
-                        break;
-                }
-        }
-}
-
-static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
-                                                  const struct amdgpu_phase_shedding_limits_table *limits,
-                                                  u32 mclk,
-                                                  u32 *phase_shedding)
-{
-        unsigned int i;
-
-        *phase_shedding = 1;
-
-        for (i = 0; i < limits->count; i++) {
-                if (mclk < limits->entries[i].mclk) {
-                        *phase_shedding = i;
-                        break;
-                }
-        }
-}
-
-static int ci_init_arb_table_index(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp;
-        int ret;
-
-        ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
-                                     &tmp, pi->sram_end);
-        if (ret)
-                return ret;
-
-        tmp &= 0x00FFFFFF;
-        tmp |= MC_CG_ARB_FREQ_F1 << 24;
-
-        return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
-                                       tmp, pi->sram_end);
-}
-
-static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
-                                         struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
-                                         u32 clock, u32 *voltage)
-{
-        u32 i = 0;
-
-        if (allowed_clock_voltage_table->count == 0)
-                return -EINVAL;
-
-        for (i = 0; i < allowed_clock_voltage_table->count; i++) {
-                if (allowed_clock_voltage_table->entries[i].clk >= clock) {
-                        *voltage = allowed_clock_voltage_table->entries[i].v;
-                        return 0;
-                }
-        }
-
-        *voltage = allowed_clock_voltage_table->entries[i-1].v;
-
-        return 0;
-}
-
-static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
-{
-        u32 i;
-        u32 tmp;
-        u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
-
-        if (sclk < min)
-                return 0;
-
-        for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
-                tmp = sclk >> i;
-                if (tmp >= min || i == 0)
-                        break;
-        }
-
-        return (u8)i;
-}
-
-static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
-{
-        return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
-}
-
-static int ci_reset_to_default(struct amdgpu_device *adev)
-{
-        return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
-                0 : -EINVAL;
-}
-
-static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
-{
-        u32 tmp;
-
-        tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
-
-        if (tmp == MC_CG_ARB_FREQ_F0)
-                return 0;
-
-        return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
-}
-
-static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
-                                        const u32 engine_clock,
-                                        const u32 memory_clock,
-                                        u32 *dram_timimg2)
-{
-        bool patch;
-        u32 tmp, tmp2;
-
-        tmp = RREG32(mmMC_SEQ_MISC0);
-        patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
-
-        if (patch &&
-            ((adev->pdev->device == 0x67B0) ||
-             (adev->pdev->device == 0x67B1))) {
-                if ((memory_clock > 100000) && (memory_clock <= 125000)) {
-                        tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
-                        *dram_timimg2 &= ~0x00ff0000;
-                        *dram_timimg2 |= tmp2 << 16;
-                } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
-                        tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
-                        *dram_timimg2 &= ~0x00ff0000;
-                        *dram_timimg2 |= tmp2 << 16;
-                }
-        }
-}
-
-static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
-                                                u32 sclk,
-                                                u32 mclk,
-                                                SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
-{
-        u32 dram_timing;
-        u32 dram_timing2;
-        u32 burst_time;
-
-        amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
-
-        dram_timing  = RREG32(mmMC_ARB_DRAM_TIMING);
-        dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
-        burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
-
-        ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
-
-        arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
-        arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
-        arb_regs->McArbBurstTime = (u8)burst_time;
-
-        return 0;
-}
-
-static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        SMU7_Discrete_MCArbDramTimingTable arb_regs;
-        u32 i, j;
-        int ret =  0;
-
-        memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
-
-        for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
-                for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
-                        ret = ci_populate_memory_timing_parameters(adev,
-                                                                   pi->dpm_table.sclk_table.dpm_levels[i].value,
-                                                                   pi->dpm_table.mclk_table.dpm_levels[j].value,
-                                                                   &arb_regs.entries[i][j]);
-                        if (ret)
-                                break;
-                }
-        }
-
-        if (ret == 0)
-                ret = amdgpu_ci_copy_bytes_to_smc(adev,
-                                           pi->arb_table_start,
-                                           (u8 *)&arb_regs,
-                                           sizeof(SMU7_Discrete_MCArbDramTimingTable),
-                                           pi->sram_end);
-
-        return ret;
-}
-
-static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (pi->need_update_smu7_dpm_table == 0)
-                return 0;
-
-        return ci_do_program_memory_timing_parameters(adev);
-}
-
-static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
-                                          struct amdgpu_ps *amdgpu_boot_state)
-{
-        struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 level = 0;
-
-        for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
-                if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
-                    boot_state->performance_levels[0].sclk) {
-                        pi->smc_state_table.GraphicsBootLevel = level;
-                        break;
-                }
-        }
-
-        for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
-                if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
-                    boot_state->performance_levels[0].mclk) {
-                        pi->smc_state_table.MemoryBootLevel = level;
-                        break;
-                }
-        }
-}
-
-static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
-{
-        u32 i;
-        u32 mask_value = 0;
-
-        for (i = dpm_table->count; i > 0; i--) {
-                mask_value = mask_value << 1;
-                if (dpm_table->dpm_levels[i-1].enabled)
-                        mask_value |= 0x1;
-                else
-                        mask_value &= 0xFFFFFFFE;
-        }
-
-        return mask_value;
-}
-
-static void ci_populate_smc_link_level(struct amdgpu_device *adev,
-                                       SMU7_Discrete_DpmTable *table)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_dpm_table *dpm_table = &pi->dpm_table;
-        u32 i;
-
-        for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
-                table->LinkLevel[i].PcieGenSpeed =
-                        (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
-                table->LinkLevel[i].PcieLaneCount =
-                        amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
-                table->LinkLevel[i].EnabledForActivity = 1;
-                table->LinkLevel[i].DownT = cpu_to_be32(5);
-                table->LinkLevel[i].UpT = cpu_to_be32(30);
-        }
-
-        pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
-        pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
-                ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
-}
-
-static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
-                                     SMU7_Discrete_DpmTable *table)
-{
-        u32 count;
-        struct atom_clock_dividers dividers;
-        int ret = -EINVAL;
-
-        table->UvdLevelCount =
-                adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
-
-        for (count = 0; count < table->UvdLevelCount; count++) {
-                table->UvdLevel[count].VclkFrequency =
-                        adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
-                table->UvdLevel[count].DclkFrequency =
-                        adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
-                table->UvdLevel[count].MinVddc =
-                        adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
-                table->UvdLevel[count].MinVddcPhases = 1;
-
-                ret = amdgpu_atombios_get_clock_dividers(adev,
-                                                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
-                                                         table->UvdLevel[count].VclkFrequency, false, &dividers);
-                if (ret)
-                        return ret;
-
-                table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
-
-                ret = amdgpu_atombios_get_clock_dividers(adev,
-                                                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
-                                                         table->UvdLevel[count].DclkFrequency, false, &dividers);
-                if (ret)
-                        return ret;
-
-                table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
-
-                table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
-                table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
-                table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
-        }
-
-        return ret;
-}
-
-static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
-                                     SMU7_Discrete_DpmTable *table)
-{
-        u32 count;
-        struct atom_clock_dividers dividers;
-        int ret = -EINVAL;
-
-        table->VceLevelCount =
-                adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
-
-        for (count = 0; count < table->VceLevelCount; count++) {
-                table->VceLevel[count].Frequency =
-                        adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
-                table->VceLevel[count].MinVoltage =
-                        (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
-                table->VceLevel[count].MinPhases = 1;
-
-                ret = amdgpu_atombios_get_clock_dividers(adev,
-                                                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
-                                                         table->VceLevel[count].Frequency, false, &dividers);
-                if (ret)
-                        return ret;
-
-                table->VceLevel[count].Divider = (u8)dividers.post_divider;
-
-                table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
-                table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
-        }
-
-        return ret;
-
-}
-
-static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
-                                     SMU7_Discrete_DpmTable *table)
-{
-        u32 count;
-        struct atom_clock_dividers dividers;
-        int ret = -EINVAL;
-
-        table->AcpLevelCount = (u8)
-                (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
-
-        for (count = 0; count < table->AcpLevelCount; count++) {
-                table->AcpLevel[count].Frequency =
-                        adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
-                table->AcpLevel[count].MinVoltage =
-                        adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
-                table->AcpLevel[count].MinPhases = 1;
-
-                ret = amdgpu_atombios_get_clock_dividers(adev,
-                                                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
-                                                         table->AcpLevel[count].Frequency, false, &dividers);
-                if (ret)
-                        return ret;
-
-                table->AcpLevel[count].Divider = (u8)dividers.post_divider;
-
-                table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
-                table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
-        }
-
-        return ret;
-}
-
-static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
-                                      SMU7_Discrete_DpmTable *table)
-{
-        u32 count;
-        struct atom_clock_dividers dividers;
-        int ret = -EINVAL;
-
-        table->SamuLevelCount =
-                adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
-
-        for (count = 0; count < table->SamuLevelCount; count++) {
-                table->SamuLevel[count].Frequency =
-                        adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
-                table->SamuLevel[count].MinVoltage =
-                        adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
-                table->SamuLevel[count].MinPhases = 1;
-
-                ret = amdgpu_atombios_get_clock_dividers(adev,
-                                                         COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
-                                                         table->SamuLevel[count].Frequency, false, &dividers);
-                if (ret)
-                        return ret;
-
-                table->SamuLevel[count].Divider = (u8)dividers.post_divider;
-
-                table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
-                table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
-        }
-
-        return ret;
-}
-
-static int ci_calculate_mclk_params(struct amdgpu_device *adev,
-                                    u32 memory_clock,
-                                    SMU7_Discrete_MemoryLevel *mclk,
-                                    bool strobe_mode,
-                                    bool dll_state_on)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32  dll_cntl = pi->clock_registers.dll_cntl;
-        u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
-        u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
-        u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
-        u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
-        u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
-        u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
-        u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
-        u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
-        struct atom_mpll_param mpll_param;
-        int ret;
-
-        ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
-        if (ret)
-                return ret;
-
-        mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
-        mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
-
-        mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
-                        MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
-        mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
-                (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
-                (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
-
-        mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
-        mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
-
-        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
-                mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
-                                MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
-                mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
-                                (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
-        }
-
-        if (pi->caps_mclk_ss_support) {
-                struct amdgpu_atom_ss ss;
-                u32 freq_nom;
-                u32 tmp;
-                u32 reference_clock = adev->clock.mpll.reference_freq;
-
-                if (mpll_param.qdr == 1)
-                        freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
-                else
-                        freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
-
-                tmp = (freq_nom / reference_clock);
-                tmp = tmp * tmp;
-                if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
-                                                     ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
-                        u32 clks = reference_clock * 5 / ss.rate;
-                        u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
-
-                        mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
-                        mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
-
-                        mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
-                        mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
-                }
-        }
-
-        mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
-        mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
-
-        if (dll_state_on)
-                mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
-                        MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
-        else
-                mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
-                        MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
-
-        mclk->MclkFrequency = memory_clock;
-        mclk->MpllFuncCntl = mpll_func_cntl;
-        mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
-        mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
-        mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
-        mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
-        mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
-        mclk->DllCntl = dll_cntl;
-        mclk->MpllSs1 = mpll_ss1;
-        mclk->MpllSs2 = mpll_ss2;
-
-        return 0;
-}
-
-static int ci_populate_single_memory_level(struct amdgpu_device *adev,
-                                           u32 memory_clock,
-                                           SMU7_Discrete_MemoryLevel *memory_level)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret;
-        bool dll_state_on;
-
-        if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
-                ret = ci_get_dependency_volt_by_clk(adev,
-                                                    &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
-                                                    memory_clock, &memory_level->MinVddc);
-                if (ret)
-                        return ret;
-        }
-
-        if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
-                ret = ci_get_dependency_volt_by_clk(adev,
-                                                    &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
-                                                    memory_clock, &memory_level->MinVddci);
-                if (ret)
-                        return ret;
-        }
-
-        if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
-                ret = ci_get_dependency_volt_by_clk(adev,
-                                                    &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
-                                                    memory_clock, &memory_level->MinMvdd);
-                if (ret)
-                        return ret;
-        }
-
-        memory_level->MinVddcPhases = 1;
-
-        if (pi->vddc_phase_shed_control)
-                ci_populate_phase_value_based_on_mclk(adev,
-                                                      &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
-                                                      memory_clock,
-                                                      &memory_level->MinVddcPhases);
-
-        memory_level->EnabledForActivity = 1;
-        memory_level->EnabledForThrottle = 1;
-        memory_level->UpH = 0;
-        memory_level->DownH = 100;
-        memory_level->VoltageDownH = 0;
-        memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
-
-        memory_level->StutterEnable = false;
-        memory_level->StrobeEnable = false;
-        memory_level->EdcReadEnable = false;
-        memory_level->EdcWriteEnable = false;
-        memory_level->RttEnable = false;
-
-        memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
-        if (pi->mclk_stutter_mode_threshold &&
-            (memory_clock <= pi->mclk_stutter_mode_threshold) &&
-            (!pi->uvd_enabled) &&
-            (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
-            (adev->pm.dpm.new_active_crtc_count <= 2))
-                memory_level->StutterEnable = true;
-
-        if (pi->mclk_strobe_mode_threshold &&
-            (memory_clock <= pi->mclk_strobe_mode_threshold))
-                memory_level->StrobeEnable = 1;
-
-        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
-                memory_level->StrobeRatio =
-                        ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
-                if (pi->mclk_edc_enable_threshold &&
-                    (memory_clock > pi->mclk_edc_enable_threshold))
-                        memory_level->EdcReadEnable = true;
-
-                if (pi->mclk_edc_wr_enable_threshold &&
-                    (memory_clock > pi->mclk_edc_wr_enable_threshold))
-                        memory_level->EdcWriteEnable = true;
-
-                if (memory_level->StrobeEnable) {
-                        if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
-                            ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
-                                dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
-                        else
-                                dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
-                } else {
-                        dll_state_on = pi->dll_default_on;
-                }
-        } else {
-                memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
-                dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
-        }
-
-        ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
-        if (ret)
-                return ret;
-
-        memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
-        memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
-        memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
-        memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
-
-        memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
-        memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
-        memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
-        memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
-        memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
-        memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
-        memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
-        memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
-        memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
-        memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
-        memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
-
-        return 0;
-}
-
-static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
-                                      SMU7_Discrete_DpmTable *table)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct atom_clock_dividers dividers;
-        SMU7_Discrete_VoltageLevel voltage_level;
-        u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
-        u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
-        u32 dll_cntl = pi->clock_registers.dll_cntl;
-        u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
-        int ret;
-
-        table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
-
-        if (pi->acpi_vddc)
-                table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
-        else
-                table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
-
-        table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
-
-        table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
-
-        ret = amdgpu_atombios_get_clock_dividers(adev,
-                                                 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
-                                                 table->ACPILevel.SclkFrequency, false, &dividers);
-        if (ret)
-                return ret;
-
-        table->ACPILevel.SclkDid = (u8)dividers.post_divider;
-        table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-        table->ACPILevel.DeepSleepDivId = 0;
-
-        spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
-        spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
-
-        spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
-        spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
-
-        table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
-        table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
-        table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
-        table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
-        table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
-        table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
-        table->ACPILevel.CcPwrDynRm = 0;
-        table->ACPILevel.CcPwrDynRm1 = 0;
-
-        table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
-        table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
-        table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
-        table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
-        table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
-        table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
-        table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
-        table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
-        table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
-        table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
-        table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
-
-        table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
-        table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
-
-        if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
-                if (pi->acpi_vddci)
-                        table->MemoryACPILevel.MinVddci =
-                                cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
-                else
-                        table->MemoryACPILevel.MinVddci =
-                                cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
-        }
-
-        if (ci_populate_mvdd_value(adev, 0, &voltage_level))
-                table->MemoryACPILevel.MinMvdd = 0;
-        else
-                table->MemoryACPILevel.MinMvdd =
-                        cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
-
-        mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
-                MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
-        mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
-                        MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
-
-        dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
-
-        table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
-        table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
-        table->MemoryACPILevel.MpllAdFuncCntl =
-                cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
-        table->MemoryACPILevel.MpllDqFuncCntl =
-                cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
-        table->MemoryACPILevel.MpllFuncCntl =
-                cpu_to_be32(pi->clock_registers.mpll_func_cntl);
-        table->MemoryACPILevel.MpllFuncCntl_1 =
-                cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
-        table->MemoryACPILevel.MpllFuncCntl_2 =
-                cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
-        table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
-        table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
-
-        table->MemoryACPILevel.EnabledForThrottle = 0;
-        table->MemoryACPILevel.EnabledForActivity = 0;
-        table->MemoryACPILevel.UpH = 0;
-        table->MemoryACPILevel.DownH = 100;
-        table->MemoryACPILevel.VoltageDownH = 0;
-        table->MemoryACPILevel.ActivityLevel =
-                cpu_to_be16((u16)pi->mclk_activity_target);
-
-        table->MemoryACPILevel.StutterEnable = false;
-        table->MemoryACPILevel.StrobeEnable = false;
-        table->MemoryACPILevel.EdcReadEnable = false;
-        table->MemoryACPILevel.EdcWriteEnable = false;
-        table->MemoryACPILevel.RttEnable = false;
-
-        return 0;
-}
-
-
-static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ulv_parm *ulv = &pi->ulv;
-
-        if (ulv->supported) {
-                if (enable)
-                        return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
-                                0 : -EINVAL;
-                else
-                        return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
-                                0 : -EINVAL;
-        }
-
-        return 0;
-}
-
-static int ci_populate_ulv_level(struct amdgpu_device *adev,
-                                 SMU7_Discrete_Ulv *state)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
-
-        state->CcPwrDynRm = 0;
-        state->CcPwrDynRm1 = 0;
-
-        if (ulv_voltage == 0) {
-                pi->ulv.supported = false;
-                return 0;
-        }
-
-        if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
-                if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
-                        state->VddcOffset = 0;
-                else
-                        state->VddcOffset =
-                                adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
-        } else {
-                if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
-                        state->VddcOffsetVid = 0;
-                else
-                        state->VddcOffsetVid = (u8)
-                                ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
-                                 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
-        }
-        state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
-
-        state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
-        state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
-        state->VddcOffset = cpu_to_be16(state->VddcOffset);
-
-        return 0;
-}
-
-static int ci_calculate_sclk_params(struct amdgpu_device *adev,
-                                    u32 engine_clock,
-                                    SMU7_Discrete_GraphicsLevel *sclk)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct atom_clock_dividers dividers;
-        u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
-        u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
-        u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
-        u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
-        u32 reference_clock = adev->clock.spll.reference_freq;
-        u32 reference_divider;
-        u32 fbdiv;
-        int ret;
-
-        ret = amdgpu_atombios_get_clock_dividers(adev,
-                                                 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
-                                                 engine_clock, false, &dividers);
-        if (ret)
-                return ret;
-
-        reference_divider = 1 + dividers.ref_div;
-        fbdiv = dividers.fb_div & 0x3FFFFFF;
-
-        spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
-        spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
-        spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
-
-        if (pi->caps_sclk_ss_support) {
-                struct amdgpu_atom_ss ss;
-                u32 vco_freq = engine_clock * dividers.post_div;
-
-                if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
-                                                     ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
-                        u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
-                        u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
-
-                        cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
-                        cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
-                        cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
-
-                        cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
-                        cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
-                }
-        }
-
-        sclk->SclkFrequency = engine_clock;
-        sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
-        sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
-        sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
-        sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
-        sclk->SclkDid = (u8)dividers.post_divider;
-
-        return 0;
-}
-
-static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
-                                            u32 engine_clock,
-                                            u16 sclk_activity_level_t,
-                                            SMU7_Discrete_GraphicsLevel *graphic_level)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret;
-
-        ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
-        if (ret)
-                return ret;
-
-        ret = ci_get_dependency_volt_by_clk(adev,
-                                            &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
-                                            engine_clock, &graphic_level->MinVddc);
-        if (ret)
-                return ret;
-
-        graphic_level->SclkFrequency = engine_clock;
-
-        graphic_level->Flags =  0;
-        graphic_level->MinVddcPhases = 1;
-
-        if (pi->vddc_phase_shed_control)
-                ci_populate_phase_value_based_on_sclk(adev,
-                                                      &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
-                                                      engine_clock,
-                                                      &graphic_level->MinVddcPhases);
-
-        graphic_level->ActivityLevel = sclk_activity_level_t;
-
-        graphic_level->CcPwrDynRm = 0;
-        graphic_level->CcPwrDynRm1 = 0;
-        graphic_level->EnabledForThrottle = 1;
-        graphic_level->UpH = 0;
-        graphic_level->DownH = 0;
-        graphic_level->VoltageDownH = 0;
-        graphic_level->PowerThrottle = 0;
-
-        if (pi->caps_sclk_ds)
-                graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
-                                                                                   CISLAND_MINIMUM_ENGINE_CLOCK);
-
-        graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
-
-        graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
-        graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
-        graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
-        graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
-        graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
-        graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
-        graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
-        graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
-        graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
-        graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
-        graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
-
-        return 0;
-}
-
-static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_dpm_table *dpm_table = &pi->dpm_table;
-        u32 level_array_address = pi->dpm_table_start +
-                offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
-        u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
-                SMU7_MAX_LEVELS_GRAPHICS;
-        SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
-        u32 i, ret;
-
-        memset(levels, 0, level_array_size);
-
-        for (i = 0; i < dpm_table->sclk_table.count; i++) {
-                ret = ci_populate_single_graphic_level(adev,
-                                                       dpm_table->sclk_table.dpm_levels[i].value,
-                                                       (u16)pi->activity_target[i],
-                                                       &pi->smc_state_table.GraphicsLevel[i]);
-                if (ret)
-                        return ret;
-                if (i > 1)
-                        pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
-                if (i == (dpm_table->sclk_table.count - 1))
-                        pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
-                                PPSMC_DISPLAY_WATERMARK_HIGH;
-        }
-        pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
-
-        pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
-        pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
-                ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
-
-        ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
-                                   (u8 *)levels, level_array_size,
-                                   pi->sram_end);
-        if (ret)
-                return ret;
-
-        return 0;
-}
-
-static int ci_populate_ulv_state(struct amdgpu_device *adev,
-                                 SMU7_Discrete_Ulv *ulv_level)
-{
-        return ci_populate_ulv_level(adev, ulv_level);
-}
-
-static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_dpm_table *dpm_table = &pi->dpm_table;
-        u32 level_array_address = pi->dpm_table_start +
-                offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
-        u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
-                SMU7_MAX_LEVELS_MEMORY;
-        SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
-        u32 i, ret;
-
-        memset(levels, 0, level_array_size);
-
-        for (i = 0; i < dpm_table->mclk_table.count; i++) {
-                if (dpm_table->mclk_table.dpm_levels[i].value == 0)
-                        return -EINVAL;
-                ret = ci_populate_single_memory_level(adev,
-                                                      dpm_table->mclk_table.dpm_levels[i].value,
-                                                      &pi->smc_state_table.MemoryLevel[i]);
-                if (ret)
-                        return ret;
-        }
-
-        if ((dpm_table->mclk_table.count >= 2) &&
-            ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
-                pi->smc_state_table.MemoryLevel[1].MinVddc =
-                        pi->smc_state_table.MemoryLevel[0].MinVddc;
-                pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
-                        pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
-        }
-
-        pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
-
-        pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
-        pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
-                ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
-
-        pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
-                PPSMC_DISPLAY_WATERMARK_HIGH;
-
-        ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
-                                   (u8 *)levels, level_array_size,
-                                   pi->sram_end);
-        if (ret)
-                return ret;
-
-        return 0;
-}
-
-static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
-                                      struct ci_single_dpm_table* dpm_table,
-                                      u32 count)
-{
-        u32 i;
-
-        dpm_table->count = count;
-        for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
-                dpm_table->dpm_levels[i].enabled = false;
-}
-
-static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
-                                      u32 index, u32 pcie_gen, u32 pcie_lanes)
-{
-        dpm_table->dpm_levels[index].value = pcie_gen;
-        dpm_table->dpm_levels[index].param1 = pcie_lanes;
-        dpm_table->dpm_levels[index].enabled = true;
-}
-
-static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
-                return -EINVAL;
-
-        if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
-                pi->pcie_gen_powersaving = pi->pcie_gen_performance;
-                pi->pcie_lane_powersaving = pi->pcie_lane_performance;
-        } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
-                pi->pcie_gen_performance = pi->pcie_gen_powersaving;
-                pi->pcie_lane_performance = pi->pcie_lane_powersaving;
-        }
-
-        ci_reset_single_dpm_table(adev,
-                                  &pi->dpm_table.pcie_speed_table,
-                                  SMU7_MAX_LEVELS_LINK);
-
-        if (adev->asic_type == CHIP_BONAIRE)
-                ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
-                                          pi->pcie_gen_powersaving.min,
-                                          pi->pcie_lane_powersaving.max);
-        else
-                ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
-                                          pi->pcie_gen_powersaving.min,
-                                          pi->pcie_lane_powersaving.min);
-        ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
-                                  pi->pcie_gen_performance.min,
-                                  pi->pcie_lane_performance.min);
-        ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
-                                  pi->pcie_gen_powersaving.min,
-                                  pi->pcie_lane_powersaving.max);
-        ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
-                                  pi->pcie_gen_performance.min,
-                                  pi->pcie_lane_performance.max);
-        ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
-                                  pi->pcie_gen_powersaving.max,
-                                  pi->pcie_lane_powersaving.max);
-        ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
-                                  pi->pcie_gen_performance.max,
-                                  pi->pcie_lane_performance.max);
-
-        pi->dpm_table.pcie_speed_table.count = 6;
-
-        return 0;
-}
-
-static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
-                &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
-        struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
-                &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
-        struct amdgpu_cac_leakage_table *std_voltage_table =
-                &adev->pm.dpm.dyn_state.cac_leakage_table;
-        u32 i;
-
-        if (allowed_sclk_vddc_table == NULL)
-                return -EINVAL;
-        if (allowed_sclk_vddc_table->count < 1)
-                return -EINVAL;
-        if (allowed_mclk_table == NULL)
-                return -EINVAL;
-        if (allowed_mclk_table->count < 1)
-                return -EINVAL;
-
-        memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
-
-        ci_reset_single_dpm_table(adev,
-                                  &pi->dpm_table.sclk_table,
-                                  SMU7_MAX_LEVELS_GRAPHICS);
-        ci_reset_single_dpm_table(adev,
-                                  &pi->dpm_table.mclk_table,
-                                  SMU7_MAX_LEVELS_MEMORY);
-        ci_reset_single_dpm_table(adev,
-                                  &pi->dpm_table.vddc_table,
-                                  SMU7_MAX_LEVELS_VDDC);
-        ci_reset_single_dpm_table(adev,
-                                  &pi->dpm_table.vddci_table,
-                                  SMU7_MAX_LEVELS_VDDCI);
-        ci_reset_single_dpm_table(adev,
-                                  &pi->dpm_table.mvdd_table,
-                                  SMU7_MAX_LEVELS_MVDD);
-
-        pi->dpm_table.sclk_table.count = 0;
-        for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
-                if ((i == 0) ||
-                    (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
-                     allowed_sclk_vddc_table->entries[i].clk)) {
-                        pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
-                                allowed_sclk_vddc_table->entries[i].clk;
-                        pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
-                                (i == 0) ? true : false;
-                        pi->dpm_table.sclk_table.count++;
-                }
-        }
-
-        pi->dpm_table.mclk_table.count = 0;
-        for (i = 0; i < allowed_mclk_table->count; i++) {
-                if ((i == 0) ||
-                    (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
-                     allowed_mclk_table->entries[i].clk)) {
-                        pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
-                                allowed_mclk_table->entries[i].clk;
-                        pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
-                                (i == 0) ? true : false;
-                        pi->dpm_table.mclk_table.count++;
-                }
-        }
-
-        for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
-                pi->dpm_table.vddc_table.dpm_levels[i].value =
-                        allowed_sclk_vddc_table->entries[i].v;
-                pi->dpm_table.vddc_table.dpm_levels[i].param1 =
-                        std_voltage_table->entries[i].leakage;
-                pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
-        }
-        pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
-
-        allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
-        if (allowed_mclk_table) {
-                for (i = 0; i < allowed_mclk_table->count; i++) {
-                        pi->dpm_table.vddci_table.dpm_levels[i].value =
-                                allowed_mclk_table->entries[i].v;
-                        pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
-                }
-                pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
-        }
-
-        allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
-        if (allowed_mclk_table) {
-                for (i = 0; i < allowed_mclk_table->count; i++) {
-                        pi->dpm_table.mvdd_table.dpm_levels[i].value =
-                                allowed_mclk_table->entries[i].v;
-                        pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
-                }
-                pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
-        }
-
-        ci_setup_default_pcie_tables(adev);
-
-        /* save a copy of the default DPM table */
-        memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),
-                        sizeof(struct ci_dpm_table));
-
-        return 0;
-}
-
-static int ci_find_boot_level(struct ci_single_dpm_table *table,
-                              u32 value, u32 *boot_level)
-{
-        u32 i;
-        int ret = -EINVAL;
-
-        for(i = 0; i < table->count; i++) {
-                if (value == table->dpm_levels[i].value) {
-                        *boot_level = i;
-                        ret = 0;
-                }
-        }
-
-        return ret;
-}
-
-static int ci_init_smc_table(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ulv_parm *ulv = &pi->ulv;
-        struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
-        SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
-        int ret;
-
-        ret = ci_setup_default_dpm_tables(adev);
-        if (ret)
-                return ret;
-
-        if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
-                ci_populate_smc_voltage_tables(adev, table);
-
-        ci_init_fps_limits(adev);
-
-        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
-                table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
-
-        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
-                table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
-
-        if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
-                table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
-
-        if (ulv->supported) {
-                ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
-                if (ret)
-                        return ret;
-                WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
-        }
-
-        ret = ci_populate_all_graphic_levels(adev);
-        if (ret)
-                return ret;
-
-        ret = ci_populate_all_memory_levels(adev);
-        if (ret)
-                return ret;
-
-        ci_populate_smc_link_level(adev, table);
-
-        ret = ci_populate_smc_acpi_level(adev, table);
-        if (ret)
-                return ret;
-
-        ret = ci_populate_smc_vce_level(adev, table);
-        if (ret)
-                return ret;
-
-        ret = ci_populate_smc_acp_level(adev, table);
-        if (ret)
-                return ret;
-
-        ret = ci_populate_smc_samu_level(adev, table);
-        if (ret)
-                return ret;
-
-        ret = ci_do_program_memory_timing_parameters(adev);
-        if (ret)
-                return ret;
-
-        ret = ci_populate_smc_uvd_level(adev, table);
-        if (ret)
-                return ret;
-
-        table->UvdBootLevel  = 0;
-        table->VceBootLevel  = 0;
-        table->AcpBootLevel  = 0;
-        table->SamuBootLevel  = 0;
-        table->GraphicsBootLevel  = 0;
-        table->MemoryBootLevel  = 0;
-
-        ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
-                                 pi->vbios_boot_state.sclk_bootup_value,
-                                 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
-
-        ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
-                                 pi->vbios_boot_state.mclk_bootup_value,
-                                 (u32 *)&pi->smc_state_table.MemoryBootLevel);
-
-        table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
-        table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
-        table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
-
-        ci_populate_smc_initial_state(adev, amdgpu_boot_state);
-
-        ret = ci_populate_bapm_parameters_in_dpm_table(adev);
-        if (ret)
-                return ret;
-
-        table->UVDInterval = 1;
-        table->VCEInterval = 1;
-        table->ACPInterval = 1;
-        table->SAMUInterval = 1;
-        table->GraphicsVoltageChangeEnable = 1;
-        table->GraphicsThermThrottleEnable = 1;
-        table->GraphicsInterval = 1;
-        table->VoltageInterval = 1;
-        table->ThermalInterval = 1;
-        table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
-                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
-        table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
-                                            CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
-        table->MemoryVoltageChangeEnable = 1;
-        table->MemoryInterval = 1;
-        table->VoltageResponseTime = 0;
-        table->VddcVddciDelta = 4000;
-        table->PhaseResponseTime = 0;
-        table->MemoryThermThrottleEnable = 1;
-        table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
-        table->PCIeGenInterval = 1;
-        if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
-                table->SVI2Enable  = 1;
-        else
-                table->SVI2Enable  = 0;
-
-        table->ThermGpio = 17;
-        table->SclkStepSize = 0x4000;
-
-        table->SystemFlags = cpu_to_be32(table->SystemFlags);
-        table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
-        table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
-        table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
-        table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
-        table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
-        table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
-        table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
-        table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
-        table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
-        table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
-        table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
-        table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
-        table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
-
-        ret = amdgpu_ci_copy_bytes_to_smc(adev,
-                                   pi->dpm_table_start +
-                                   offsetof(SMU7_Discrete_DpmTable, SystemFlags),
-                                   (u8 *)&table->SystemFlags,
-                                   sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
-                                   pi->sram_end);
-        if (ret)
-                return ret;
-
-        return 0;
-}
-
-static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
-                                      struct ci_single_dpm_table *dpm_table,
-                                      u32 low_limit, u32 high_limit)
-{
-        u32 i;
-
-        for (i = 0; i < dpm_table->count; i++) {
-                if ((dpm_table->dpm_levels[i].value < low_limit) ||
-                    (dpm_table->dpm_levels[i].value > high_limit))
-                        dpm_table->dpm_levels[i].enabled = false;
-                else
-                        dpm_table->dpm_levels[i].enabled = true;
-        }
-}
-
-static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
-                                    u32 speed_low, u32 lanes_low,
-                                    u32 speed_high, u32 lanes_high)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
-        u32 i, j;
-
-        for (i = 0; i < pcie_table->count; i++) {
-                if ((pcie_table->dpm_levels[i].value < speed_low) ||
-                    (pcie_table->dpm_levels[i].param1 < lanes_low) ||
-                    (pcie_table->dpm_levels[i].value > speed_high) ||
-                    (pcie_table->dpm_levels[i].param1 > lanes_high))
-                        pcie_table->dpm_levels[i].enabled = false;
-                else
-                        pcie_table->dpm_levels[i].enabled = true;
-        }
-
-        for (i = 0; i < pcie_table->count; i++) {
-                if (pcie_table->dpm_levels[i].enabled) {
-                        for (j = i + 1; j < pcie_table->count; j++) {
-                                if (pcie_table->dpm_levels[j].enabled) {
-                                        if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
-                                            (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
-                                                pcie_table->dpm_levels[j].enabled = false;
-                                }
-                        }
-                }
-        }
-}
-
-static int ci_trim_dpm_states(struct amdgpu_device *adev,
-                              struct amdgpu_ps *amdgpu_state)
-{
-        struct ci_ps *state = ci_get_ps(amdgpu_state);
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 high_limit_count;
-
-        if (state->performance_level_count < 1)
-                return -EINVAL;
-
-        if (state->performance_level_count == 1)
-                high_limit_count = 0;
-        else
-                high_limit_count = 1;
-
-        ci_trim_single_dpm_states(adev,
-                                  &pi->dpm_table.sclk_table,
-                                  state->performance_levels[0].sclk,
-                                  state->performance_levels[high_limit_count].sclk);
-
-        ci_trim_single_dpm_states(adev,
-                                  &pi->dpm_table.mclk_table,
-                                  state->performance_levels[0].mclk,
-                                  state->performance_levels[high_limit_count].mclk);
-
-        ci_trim_pcie_dpm_states(adev,
-                                state->performance_levels[0].pcie_gen,
-                                state->performance_levels[0].pcie_lane,
-                                state->performance_levels[high_limit_count].pcie_gen,
-                                state->performance_levels[high_limit_count].pcie_lane);
-
-        return 0;
-}
-
-static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
-{
-        struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
-                &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
-        struct amdgpu_clock_voltage_dependency_table *vddc_table =
-                &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
-        u32 requested_voltage = 0;
-        u32 i;
-
-        if (disp_voltage_table == NULL)
-                return -EINVAL;
-        if (!disp_voltage_table->count)
-                return -EINVAL;
-
-        for (i = 0; i < disp_voltage_table->count; i++) {
-                if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
-                        requested_voltage = disp_voltage_table->entries[i].v;
-        }
-
-        for (i = 0; i < vddc_table->count; i++) {
-                if (requested_voltage <= vddc_table->entries[i].v) {
-                        requested_voltage = vddc_table->entries[i].v;
-                        return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                                  PPSMC_MSG_VddC_Request,
-                                                                  requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
-                                0 : -EINVAL;
-                }
-        }
-
-        return -EINVAL;
-}
-
-static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        PPSMC_Result result;
-
-        ci_apply_disp_minimum_voltage_request(adev);
-
-        if (!pi->sclk_dpm_key_disabled) {
-                if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-                        result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                                   PPSMC_MSG_SCLKDPM_SetEnabledMask,
-                                                                   pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
-                        if (result != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-        }
-
-        if (!pi->mclk_dpm_key_disabled) {
-                if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-                        result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                                   PPSMC_MSG_MCLKDPM_SetEnabledMask,
-                                                                   pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
-                        if (result != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-        }
-
-#if 0
-        if (!pi->pcie_dpm_key_disabled) {
-                if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-                        result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                                   PPSMC_MSG_PCIeDPM_SetEnabledMask,
-                                                                   pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
-                        if (result != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-        }
-#endif
-
-        return 0;
-}
-
-static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
-                                                   struct amdgpu_ps *amdgpu_state)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ps *state = ci_get_ps(amdgpu_state);
-        struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
-        u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
-        struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
-        u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
-        u32 i;
-
-        pi->need_update_smu7_dpm_table = 0;
-
-        for (i = 0; i < sclk_table->count; i++) {
-                if (sclk == sclk_table->dpm_levels[i].value)
-                        break;
-        }
-
-        if (i >= sclk_table->count) {
-                pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
-        } else {
-                /* XXX check display min clock requirements */
-                if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
-                        pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
-        }
-
-        for (i = 0; i < mclk_table->count; i++) {
-                if (mclk == mclk_table->dpm_levels[i].value)
-                        break;
-        }
-
-        if (i >= mclk_table->count)
-                pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
-
-        if (adev->pm.dpm.current_active_crtc_count !=
-            adev->pm.dpm.new_active_crtc_count)
-                pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
-}
-
-static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
-                                                       struct amdgpu_ps *amdgpu_state)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ps *state = ci_get_ps(amdgpu_state);
-        u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
-        u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
-        struct ci_dpm_table *dpm_table = &pi->dpm_table;
-        int ret;
-
-        if (!pi->need_update_smu7_dpm_table)
-                return 0;
-
-        if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
-                dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
-
-        if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
-                dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
-
-        if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
-                ret = ci_populate_all_graphic_levels(adev);
-                if (ret)
-                        return ret;
-        }
-
-        if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
-                ret = ci_populate_all_memory_levels(adev);
-                if (ret)
-                        return ret;
-        }
-
-        return 0;
-}
-
-static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct amdgpu_clock_and_voltage_limits *max_limits;
-        int i;
-
-        if (adev->pm.ac_power)
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
-        else
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
-
-        if (enable) {
-                pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
-
-                for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
-                        if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
-                                pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
-
-                                if (!pi->caps_uvd_dpm)
-                                        break;
-                        }
-                }
-
-                amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                  PPSMC_MSG_UVDDPM_SetEnabledMask,
-                                                  pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
-
-                if (pi->last_mclk_dpm_enable_mask & 0x1) {
-                        pi->uvd_enabled = true;
-                        pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                          PPSMC_MSG_MCLKDPM_SetEnabledMask,
-                                                          pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
-                }
-        } else {
-                if (pi->uvd_enabled) {
-                        pi->uvd_enabled = false;
-                        pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                          PPSMC_MSG_MCLKDPM_SetEnabledMask,
-                                                          pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
-                }
-        }
-
-        return (amdgpu_ci_send_msg_to_smc(adev, enable ?
-                                   PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
-                0 : -EINVAL;
-}
-
-static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct amdgpu_clock_and_voltage_limits *max_limits;
-        int i;
-
-        if (adev->pm.ac_power)
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
-        else
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
-
-        if (enable) {
-                pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
-                for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
-                        if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
-                                pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
-
-                                if (!pi->caps_vce_dpm)
-                                        break;
-                        }
-                }
-
-                amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                  PPSMC_MSG_VCEDPM_SetEnabledMask,
-                                                  pi->dpm_level_enable_mask.vce_dpm_enable_mask);
-        }
-
-        return (amdgpu_ci_send_msg_to_smc(adev, enable ?
-                                   PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
-                0 : -EINVAL;
-}
-
-#if 0
-static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct amdgpu_clock_and_voltage_limits *max_limits;
-        int i;
-
-        if (adev->pm.ac_power)
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
-        else
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
-
-        if (enable) {
-                pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
-                for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
-                        if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
-                                pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
-
-                                if (!pi->caps_samu_dpm)
-                                        break;
-                        }
-                }
-
-                amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                  PPSMC_MSG_SAMUDPM_SetEnabledMask,
-                                                  pi->dpm_level_enable_mask.samu_dpm_enable_mask);
-        }
-        return (amdgpu_ci_send_msg_to_smc(adev, enable ?
-                                   PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
-                0 : -EINVAL;
-}
-
-static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        const struct amdgpu_clock_and_voltage_limits *max_limits;
-        int i;
-
-        if (adev->pm.ac_power)
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
-        else
-                max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
-
-        if (enable) {
-                pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
-                for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
-                        if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
-                                pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
-
-                                if (!pi->caps_acp_dpm)
-                                        break;
-                        }
-                }
-
-                amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                                  PPSMC_MSG_ACPDPM_SetEnabledMask,
-                                                  pi->dpm_level_enable_mask.acp_dpm_enable_mask);
-        }
-
-        return (amdgpu_ci_send_msg_to_smc(adev, enable ?
-                                   PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
-                0 : -EINVAL;
-}
-#endif
-
-static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp;
-        int ret = 0;
-
-        if (!gate) {
-                /* turn the clocks on when decoding */
-                if (pi->caps_uvd_dpm ||
-                    (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
-                        pi->smc_state_table.UvdBootLevel = 0;
-                else
-                        pi->smc_state_table.UvdBootLevel =
-                                adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
-
-                tmp = RREG32_SMC(ixDPM_TABLE_475);
-                tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
-                tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
-                WREG32_SMC(ixDPM_TABLE_475, tmp);
-                ret = ci_enable_uvd_dpm(adev, true);
-        } else {
-                ret = ci_enable_uvd_dpm(adev, false);
-                if (ret)
-                        return ret;
-        }
-
-        return ret;
-}
-
-static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
-{
-        u8 i;
-        u32 min_evclk = 30000; /* ??? */
-        struct amdgpu_vce_clock_voltage_dependency_table *table =
-                &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
-
-        for (i = 0; i < table->count; i++) {
-                if (table->entries[i].evclk >= min_evclk)
-                        return i;
-        }
-
-        return table->count - 1;
-}
-
-static int ci_update_vce_dpm(struct amdgpu_device *adev,
-                             struct amdgpu_ps *amdgpu_new_state,
-                             struct amdgpu_ps *amdgpu_current_state)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret = 0;
-        u32 tmp;
-
-        if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
-                if (amdgpu_new_state->evclk) {
-                        pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
-                        tmp = RREG32_SMC(ixDPM_TABLE_475);
-                        tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
-                        tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
-                        WREG32_SMC(ixDPM_TABLE_475, tmp);
-
-                        ret = ci_enable_vce_dpm(adev, true);
-                } else {
-                        ret = ci_enable_vce_dpm(adev, false);
-                        if (ret)
-                                return ret;
-                }
-        }
-        return ret;
-}
-
-#if 0
-static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
-{
-        return ci_enable_samu_dpm(adev, gate);
-}
-
-static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp;
-
-        if (!gate) {
-                pi->smc_state_table.AcpBootLevel = 0;
-
-                tmp = RREG32_SMC(ixDPM_TABLE_475);
-                tmp &= ~AcpBootLevel_MASK;
-                tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
-                WREG32_SMC(ixDPM_TABLE_475, tmp);
-        }
-
-        return ci_enable_acp_dpm(adev, !gate);
-}
-#endif
-
-static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
-                                             struct amdgpu_ps *amdgpu_state)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret;
-
-        ret = ci_trim_dpm_states(adev, amdgpu_state);
-        if (ret)
-                return ret;
-
-        pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
-                ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
-        pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
-                ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
-        pi->last_mclk_dpm_enable_mask =
-                pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
-        if (pi->uvd_enabled) {
-                if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
-                        pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
-        }
-        pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
-                ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
-
-        return 0;
-}
-
-static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
-                                       u32 level_mask)
-{
-        u32 level = 0;
-
-        while ((level_mask & (1 << level)) == 0)
-                level++;
-
-        return level;
-}
-
-
-static int ci_dpm_force_performance_level(void *handle,
-                                          enum amd_dpm_forced_level level)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 tmp, levels, i;
-        int ret;
-
-        if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
-                if ((!pi->pcie_dpm_key_disabled) &&
-                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-                        levels = 0;
-                        tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
-                        while (tmp >>= 1)
-                                levels++;
-                        if (levels) {
-                                ret = ci_dpm_force_state_pcie(adev, level);
-                                if (ret)
-                                        return ret;
-                                for (i = 0; i < adev->usec_timeout; i++) {
-                                        tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
-                                        TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
-                                        TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
-                                        if (tmp == levels)
-                                                break;
-                                        udelay(1);
-                                }
-                        }
-                }
-                if ((!pi->sclk_dpm_key_disabled) &&
-                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-                        levels = 0;
-                        tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
-                        while (tmp >>= 1)
-                                levels++;
-                        if (levels) {
-                                ret = ci_dpm_force_state_sclk(adev, levels);
-                                if (ret)
-                                        return ret;
-                                for (i = 0; i < adev->usec_timeout; i++) {
-                                        tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
-                                        TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
-                                        TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
-                                        if (tmp == levels)
-                                                break;
-                                        udelay(1);
-                                }
-                        }
-                }
-                if ((!pi->mclk_dpm_key_disabled) &&
-                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-                        levels = 0;
-                        tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
-                        while (tmp >>= 1)
-                                levels++;
-                        if (levels) {
-                                ret = ci_dpm_force_state_mclk(adev, levels);
-                                if (ret)
-                                        return ret;
-                                for (i = 0; i < adev->usec_timeout; i++) {
-                                        tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
-                                        TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
-                                        TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
-                                        if (tmp == levels)
-                                                break;
-                                        udelay(1);
-                                }
-                        }
-                }
-        } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
-                if ((!pi->sclk_dpm_key_disabled) &&
-                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
-                        levels = ci_get_lowest_enabled_level(adev,
-                                                             pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
-                        ret = ci_dpm_force_state_sclk(adev, levels);
-                        if (ret)
-                                return ret;
-                        for (i = 0; i < adev->usec_timeout; i++) {
-                                tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
-                                TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
-                                TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
-                                if (tmp == levels)
-                                        break;
-                                udelay(1);
-                        }
-                }
-                if ((!pi->mclk_dpm_key_disabled) &&
-                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
-                        levels = ci_get_lowest_enabled_level(adev,
-                                                             pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
-                        ret = ci_dpm_force_state_mclk(adev, levels);
-                        if (ret)
-                                return ret;
-                        for (i = 0; i < adev->usec_timeout; i++) {
-                                tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
-                                TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
-                                TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
-                                if (tmp == levels)
-                                        break;
-                                udelay(1);
-                        }
-                }
-                if ((!pi->pcie_dpm_key_disabled) &&
-                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
-                        levels = ci_get_lowest_enabled_level(adev,
-                                                             pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
-                        ret = ci_dpm_force_state_pcie(adev, levels);
-                        if (ret)
-                                return ret;
-                        for (i = 0; i < adev->usec_timeout; i++) {
-                                tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
-                                TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
-                                TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
-                                if (tmp == levels)
-                                        break;
-                                udelay(1);
-                        }
-                }
-        } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
-                if (!pi->pcie_dpm_key_disabled) {
-                        PPSMC_Result smc_result;
-
-                        smc_result = amdgpu_ci_send_msg_to_smc(adev,
-                                                               PPSMC_MSG_PCIeDPM_UnForceLevel);
-                        if (smc_result != PPSMC_Result_OK)
-                                return -EINVAL;
-                }
-                ret = ci_upload_dpm_level_enable_mask(adev);
-                if (ret)
-                        return ret;
-        }
-
-        adev->pm.dpm.forced_level = level;
-
-        return 0;
-}
-
-static int ci_set_mc_special_registers(struct amdgpu_device *adev,
-                                       struct ci_mc_reg_table *table)
-{
-        u8 i, j, k;
-        u32 temp_reg;
-
-        for (i = 0, j = table->last; i < table->last; i++) {
-                if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
-                        return -EINVAL;
-                switch(table->mc_reg_address[i].s1) {
-                case mmMC_SEQ_MISC1:
-                        temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
-                        table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
-                        table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
-                        for (k = 0; k < table->num_entries; k++) {
-                                table->mc_reg_table_entry[k].mc_data[j] =
-                                        ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
-                        }
-                        j++;
-
-                        if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
-                                return -EINVAL;
-                        temp_reg = RREG32(mmMC_PMG_CMD_MRS);
-                        table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
-                        table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
-                        for (k = 0; k < table->num_entries; k++) {
-                                table->mc_reg_table_entry[k].mc_data[j] =
-                                        (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-                                if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
-                                        table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
-                        }
-                        j++;
-
-                        if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
-                                if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
-                                        return -EINVAL;
-                                table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
-                                table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
-                                for (k = 0; k < table->num_entries; k++) {
-                                        table->mc_reg_table_entry[k].mc_data[j] =
-                                                (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
-                                }
-                                j++;
-                        }
-                        break;
-                case mmMC_SEQ_RESERVE_M:
-                        temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
-                        table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
-                        table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
-                        for (k = 0; k < table->num_entries; k++) {
-                                table->mc_reg_table_entry[k].mc_data[j] =
-                                        (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
-                        }
-                        j++;
-                        break;
-                default:
-                        break;
-                }
-
-        }
-
-        table->last = j;
-
-        return 0;
-}
-
-static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
-{
-        bool result = true;
-
-        switch(in_reg) {
-        case mmMC_SEQ_RAS_TIMING:
-                *out_reg = mmMC_SEQ_RAS_TIMING_LP;
-                break;
-        case mmMC_SEQ_DLL_STBY:
-                *out_reg = mmMC_SEQ_DLL_STBY_LP;
-                break;
-        case mmMC_SEQ_G5PDX_CMD0:
-                *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
-                break;
-        case mmMC_SEQ_G5PDX_CMD1:
-                *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
-                break;
-        case mmMC_SEQ_G5PDX_CTRL:
-                *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
-                break;
-        case mmMC_SEQ_CAS_TIMING:
-                *out_reg = mmMC_SEQ_CAS_TIMING_LP;
-            break;
-        case mmMC_SEQ_MISC_TIMING:
-                *out_reg = mmMC_SEQ_MISC_TIMING_LP;
-                break;
-        case mmMC_SEQ_MISC_TIMING2:
-                *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
-                break;
-        case mmMC_SEQ_PMG_DVS_CMD:
-                *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
-                break;
-        case mmMC_SEQ_PMG_DVS_CTL:
-                *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
-                break;
-        case mmMC_SEQ_RD_CTL_D0:
-                *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
-                break;
-        case mmMC_SEQ_RD_CTL_D1:
-                *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
-                break;
-        case mmMC_SEQ_WR_CTL_D0:
-                *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
-                break;
-        case mmMC_SEQ_WR_CTL_D1:
-                *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
-                break;
-        case mmMC_PMG_CMD_EMRS:
-                *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
-                break;
-        case mmMC_PMG_CMD_MRS:
-                *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
-                break;
-        case mmMC_PMG_CMD_MRS1:
-                *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
-                break;
-        case mmMC_SEQ_PMG_TIMING:
-                *out_reg = mmMC_SEQ_PMG_TIMING_LP;
-                break;
-        case mmMC_PMG_CMD_MRS2:
-                *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
-                break;
-        case mmMC_SEQ_WR_CTL_2:
-                *out_reg = mmMC_SEQ_WR_CTL_2_LP;
-                break;
-        default:
-                result = false;
-                break;
-        }
-
-        return result;
-}
-
-static void ci_set_valid_flag(struct ci_mc_reg_table *table)
-{
-        u8 i, j;
-
-        for (i = 0; i < table->last; i++) {
-                for (j = 1; j < table->num_entries; j++) {
-                        if (table->mc_reg_table_entry[j-1].mc_data[i] !=
-                            table->mc_reg_table_entry[j].mc_data[i]) {
-                                table->valid_flag |= 1 << i;
-                                break;
-                        }
-                }
-        }
-}
-
-static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
-{
-        u32 i;
-        u16 address;
-
-        for (i = 0; i < table->last; i++) {
-                table->mc_reg_address[i].s0 =
-                        ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
-                        address : table->mc_reg_address[i].s1;
-        }
-}
-
-static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
-                                      struct ci_mc_reg_table *ci_table)
-{
-        u8 i, j;
-
-        if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
-                return -EINVAL;
-        if (table->num_entries > MAX_AC_TIMING_ENTRIES)
-                return -EINVAL;
-
-        for (i = 0; i < table->last; i++)
-                ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
-
-        ci_table->last = table->last;
-
-        for (i = 0; i < table->num_entries; i++) {
-                ci_table->mc_reg_table_entry[i].mclk_max =
-                        table->mc_reg_table_entry[i].mclk_max;
-                for (j = 0; j < table->last; j++)
-                        ci_table->mc_reg_table_entry[i].mc_data[j] =
-                                table->mc_reg_table_entry[i].mc_data[j];
-        }
-        ci_table->num_entries = table->num_entries;
-
-        return 0;
-}
-
-static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
-                                       struct ci_mc_reg_table *table)
-{
-        u8 i, k;
-        u32 tmp;
-        bool patch;
-
-        tmp = RREG32(mmMC_SEQ_MISC0);
-        patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
-
-        if (patch &&
-            ((adev->pdev->device == 0x67B0) ||
-             (adev->pdev->device == 0x67B1))) {
-                for (i = 0; i < table->last; i++) {
-                        if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
-                                return -EINVAL;
-                        switch (table->mc_reg_address[i].s1) {
-                        case mmMC_SEQ_MISC1:
-                                for (k = 0; k < table->num_entries; k++) {
-                                        if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
-                                            (table->mc_reg_table_entry[k].mclk_max == 137500))
-                                                table->mc_reg_table_entry[k].mc_data[i] =
-                                                        (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
-                                                        0x00000007;
-                                }
-                                break;
-                        case mmMC_SEQ_WR_CTL_D0:
-                                for (k = 0; k < table->num_entries; k++) {
-                                        if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
-                                            (table->mc_reg_table_entry[k].mclk_max == 137500))
-                                                table->mc_reg_table_entry[k].mc_data[i] =
-                                                        (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
-                                                        0x0000D0DD;
-                                }
-                                break;
-                        case mmMC_SEQ_WR_CTL_D1:
-                                for (k = 0; k < table->num_entries; k++) {
-                                        if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
-                                            (table->mc_reg_table_entry[k].mclk_max == 137500))
-                                                table->mc_reg_table_entry[k].mc_data[i] =
-                                                        (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
-                                                        0x0000D0DD;
-                                }
-                                break;
-                        case mmMC_SEQ_WR_CTL_2:
-                                for (k = 0; k < table->num_entries; k++) {
-                                        if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
-                                            (table->mc_reg_table_entry[k].mclk_max == 137500))
-                                                table->mc_reg_table_entry[k].mc_data[i] = 0;
-                                }
-                                break;
-                        case mmMC_SEQ_CAS_TIMING:
-                                for (k = 0; k < table->num_entries; k++) {
-                                        if (table->mc_reg_table_entry[k].mclk_max == 125000)
-                                                table->mc_reg_table_entry[k].mc_data[i] =
-                                                        (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
-                                                        0x000C0140;
-                                        else if (table->mc_reg_table_entry[k].mclk_max == 137500)
-                                                table->mc_reg_table_entry[k].mc_data[i] =
-                                                        (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
-                                                        0x000C0150;
-                                }
-                                break;
-                        case mmMC_SEQ_MISC_TIMING:
-                                for (k = 0; k < table->num_entries; k++) {
-                                        if (table->mc_reg_table_entry[k].mclk_max == 125000)
-                                                table->mc_reg_table_entry[k].mc_data[i] =
-                                                        (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
-                                                        0x00000030;
-                                        else if (table->mc_reg_table_entry[k].mclk_max == 137500)
-                                                table->mc_reg_table_entry[k].mc_data[i] =
-                                                        (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
-                                                        0x00000035;
-                                }
-                                break;
-                        default:
-                                break;
-                        }
-                }
-
-                WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
-                tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
-                tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
-                WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
-                WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
-        }
-
-        return 0;
-}
-
-static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct atom_mc_reg_table *table;
-        struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
-        u8 module_index = ci_get_memory_module_index(adev);
-        int ret;
-
-        table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
-        if (!table)
-                return -ENOMEM;
-
-        WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
-        WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
-        WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
-        WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
-        WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
-        WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
-        WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
-        WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
-        WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
-        WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
-        WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
-        WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
-        WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
-        WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
-        WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
-        WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
-        WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
-        WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
-        WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
-        WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
-
-        ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
-        if (ret)
-                goto init_mc_done;
-
-        ret = ci_copy_vbios_mc_reg_table(table, ci_table);
-        if (ret)
-                goto init_mc_done;
-
-        ci_set_s0_mc_reg_index(ci_table);
-
-        ret = ci_register_patching_mc_seq(adev, ci_table);
-        if (ret)
-                goto init_mc_done;
-
-        ret = ci_set_mc_special_registers(adev, ci_table);
-        if (ret)
-                goto init_mc_done;
-
-        ci_set_valid_flag(ci_table);
-
-init_mc_done:
-        kfree(table);
-
-        return ret;
-}
-
-static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
-                                        SMU7_Discrete_MCRegisters *mc_reg_table)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 i, j;
-
-        for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
-                if (pi->mc_reg_table.valid_flag & (1 << j)) {
-                        if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
-                                return -EINVAL;
-                        mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
-                        mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
-                        i++;
-                }
-        }
-
-        mc_reg_table->last = (u8)i;
-
-        return 0;
-}
-
-static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
-                                    SMU7_Discrete_MCRegisterSet *data,
-                                    u32 num_entries, u32 valid_flag)
-{
-        u32 i, j;
-
-        for (i = 0, j = 0; j < num_entries; j++) {
-                if (valid_flag & (1 << j)) {
-                        data->value[i] = cpu_to_be32(entry->mc_data[j]);
-                        i++;
-                }
-        }
-}
-
-static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
-                                                 const u32 memory_clock,
-                                                 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 i = 0;
-
-        for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
-                if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
-                        break;
-        }
-
-        if ((i == pi->mc_reg_table.num_entries) && (i > 0))
-                --i;
-
-        ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
-                                mc_reg_table_data, pi->mc_reg_table.last,
-                                pi->mc_reg_table.valid_flag);
-}
-
-static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
-                                           SMU7_Discrete_MCRegisters *mc_reg_table)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        u32 i;
-
-        for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
-                ci_convert_mc_reg_table_entry_to_smc(adev,
-                                                     pi->dpm_table.mclk_table.dpm_levels[i].value,
-                                                     &mc_reg_table->data[i]);
-}
-
-static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        int ret;
-
-        memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
-
-        ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
-        if (ret)
-                return ret;
-        ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
-
-        return amdgpu_ci_copy_bytes_to_smc(adev,
-                                    pi->mc_reg_table_start,
-                                    (u8 *)&pi->smc_mc_reg_table,
-                                    sizeof(SMU7_Discrete_MCRegisters),
-                                    pi->sram_end);
-}
-
-static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
-                return 0;
-
-        memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
-
-        ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
-
-        return amdgpu_ci_copy_bytes_to_smc(adev,
-                                    pi->mc_reg_table_start +
-                                    offsetof(SMU7_Discrete_MCRegisters, data[0]),
-                                    (u8 *)&pi->smc_mc_reg_table.data[0],
-                                    sizeof(SMU7_Discrete_MCRegisterSet) *
-                                    pi->dpm_table.mclk_table.count,
-                                    pi->sram_end);
-}
-
-static void ci_enable_voltage_control(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
-
-        tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
-        WREG32_SMC(ixGENERAL_PWRMGT, tmp);
-}
-
-static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
-                                                      struct amdgpu_ps *amdgpu_state)
-{
-        struct ci_ps *state = ci_get_ps(amdgpu_state);
-        int i;
-        u16 pcie_speed, max_speed = 0;
-
-        for (i = 0; i < state->performance_level_count; i++) {
-                pcie_speed = state->performance_levels[i].pcie_gen;
-                if (max_speed < pcie_speed)
-                        max_speed = pcie_speed;
-        }
-
-        return max_speed;
-}
-
-static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
-{
-        u32 speed_cntl = 0;
-
-        speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
-                PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
-        speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
-
-        return (u16)speed_cntl;
-}
-
-static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
-{
-        u32 link_width = 0;
-
-        link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
-                PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
-        link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
-
-        switch (link_width) {
-        case 1:
-                return 1;
-        case 2:
-                return 2;
-        case 3:
-                return 4;
-        case 4:
-                return 8;
-        case 0:
-        case 6:
-        default:
-                return 16;
-        }
-}
-
-static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
-                                                             struct amdgpu_ps *amdgpu_new_state,
-                                                             struct amdgpu_ps *amdgpu_current_state)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        enum amdgpu_pcie_gen target_link_speed =
-                ci_get_maximum_link_speed(adev, amdgpu_new_state);
-        enum amdgpu_pcie_gen current_link_speed;
-
-        if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
-                current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
-        else
-                current_link_speed = pi->force_pcie_gen;
-
-        pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
-        pi->pspp_notify_required = false;
-        if (target_link_speed > current_link_speed) {
-                switch (target_link_speed) {
-#ifdef CONFIG_ACPI
-                case AMDGPU_PCIE_GEN3:
-                        if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
-                                break;
-                        pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
-                        if (current_link_speed == AMDGPU_PCIE_GEN2)
-                                break;
-                case AMDGPU_PCIE_GEN2:
-                        if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
-                                break;
-#endif
-                default:
-                        pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
-                        break;
-                }
-        } else {
-                if (target_link_speed < current_link_speed)
-                        pi->pspp_notify_required = true;
-        }
-}
-
-static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
-                                                           struct amdgpu_ps *amdgpu_new_state,
-                                                           struct amdgpu_ps *amdgpu_current_state)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        enum amdgpu_pcie_gen target_link_speed =
-                ci_get_maximum_link_speed(adev, amdgpu_new_state);
-        u8 request;
-
-        if (pi->pspp_notify_required) {
-                if (target_link_speed == AMDGPU_PCIE_GEN3)
-                        request = PCIE_PERF_REQ_PECI_GEN3;
-                else if (target_link_speed == AMDGPU_PCIE_GEN2)
-                        request = PCIE_PERF_REQ_PECI_GEN2;
-                else
-                        request = PCIE_PERF_REQ_PECI_GEN1;
-
-                if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
-                    (ci_get_current_pcie_speed(adev) > 0))
-                        return;
-
-#ifdef CONFIG_ACPI
-                amdgpu_acpi_pcie_performance_request(adev, request, false);
-#endif
-        }
-}
-
-static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
-                &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
-        struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
-                &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
-        struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
-                &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
-
-        if (allowed_sclk_vddc_table == NULL)
-                return -EINVAL;
-        if (allowed_sclk_vddc_table->count < 1)
-                return -EINVAL;
-        if (allowed_mclk_vddc_table == NULL)
-                return -EINVAL;
-        if (allowed_mclk_vddc_table->count < 1)
-                return -EINVAL;
-        if (allowed_mclk_vddci_table == NULL)
-                return -EINVAL;
-        if (allowed_mclk_vddci_table->count < 1)
-                return -EINVAL;
-
-        pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
-        pi->max_vddc_in_pp_table =
-                allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
-
-        pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
-        pi->max_vddci_in_pp_table =
-                allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
-
-        adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
-                allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
-        adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
-                allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
-        adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
-                allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
-        adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
-                allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
-
-        return 0;
-}
-
-static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
-        u32 leakage_index;
-
-        for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
-                if (leakage_table->leakage_id[leakage_index] == *vddc) {
-                        *vddc = leakage_table->actual_voltage[leakage_index];
-                        break;
-                }
-        }
-}
-
-static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
-        u32 leakage_index;
-
-        for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
-                if (leakage_table->leakage_id[leakage_index] == *vddci) {
-                        *vddci = leakage_table->actual_voltage[leakage_index];
-                        break;
-                }
-        }
-}
-
-static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
-                                                                      struct amdgpu_clock_voltage_dependency_table *table)
-{
-        u32 i;
-
-        if (table) {
-                for (i = 0; i < table->count; i++)
-                        ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
-        }
-}
-
-static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
-                                                                       struct amdgpu_clock_voltage_dependency_table *table)
-{
-        u32 i;
-
-        if (table) {
-                for (i = 0; i < table->count; i++)
-                        ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
-        }
-}
-
-static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
-                                                                          struct amdgpu_vce_clock_voltage_dependency_table *table)
-{
-        u32 i;
-
-        if (table) {
-                for (i = 0; i < table->count; i++)
-                        ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
-        }
-}
-
-static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
-                                                                          struct amdgpu_uvd_clock_voltage_dependency_table *table)
-{
-        u32 i;
-
-        if (table) {
-                for (i = 0; i < table->count; i++)
-                        ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
-        }
-}
-
-static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
-                                                                   struct amdgpu_phase_shedding_limits_table *table)
-{
-        u32 i;
-
-        if (table) {
-                for (i = 0; i < table->count; i++)
-                        ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
-        }
-}
-
-static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
-                                                            struct amdgpu_clock_and_voltage_limits *table)
-{
-        if (table) {
-                ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
-                ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
-        }
-}
-
-static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
-                                                         struct amdgpu_cac_leakage_table *table)
-{
-        u32 i;
-
-        if (table) {
-                for (i = 0; i < table->count; i++)
-                        ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
-        }
-}
-
-static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
-{
-
-        ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
-                                                                  &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
-        ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
-                                                                  &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
-        ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
-                                                                  &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
-        ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
-                                                                   &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
-        ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
-                                                                      &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
-        ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
-                                                                      &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
-        ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
-                                                                  &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
-        ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
-                                                                  &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
-        ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
-                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
-        ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
-                                                        &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
-        ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
-                                                        &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
-        ci_patch_cac_leakage_table_with_vddc_leakage(adev,
-                                                     &adev->pm.dpm.dyn_state.cac_leakage_table);
-
-}
-
-static void ci_update_current_ps(struct amdgpu_device *adev,
-                                 struct amdgpu_ps *rps)
-{
-        struct ci_ps *new_ps = ci_get_ps(rps);
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        pi->current_rps = *rps;
-        pi->current_ps = *new_ps;
-        pi->current_rps.ps_priv = &pi->current_ps;
-        adev->pm.dpm.current_ps = &pi->current_rps;
-}
-
-static void ci_update_requested_ps(struct amdgpu_device *adev,
-                                   struct amdgpu_ps *rps)
-{
-        struct ci_ps *new_ps = ci_get_ps(rps);
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        pi->requested_rps = *rps;
-        pi->requested_ps = *new_ps;
-        pi->requested_rps.ps_priv = &pi->requested_ps;
-        adev->pm.dpm.requested_ps = &pi->requested_rps;
-}
-
-static int ci_dpm_pre_set_power_state(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
-        struct amdgpu_ps *new_ps = &requested_ps;
-
-        ci_update_requested_ps(adev, new_ps);
-
-        ci_apply_state_adjust_rules(adev, &pi->requested_rps);
-
-        return 0;
-}
-
-static void ci_dpm_post_set_power_state(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_ps *new_ps = &pi->requested_rps;
-
-        ci_update_current_ps(adev, new_ps);
-}
-
-
-static void ci_dpm_setup_asic(struct amdgpu_device *adev)
-{
-        ci_read_clock_registers(adev);
-        ci_enable_acpi_power_management(adev);
-        ci_init_sclk_t(adev);
-}
-
-static int ci_dpm_enable(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
-        int ret;
-
-        if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
-                ci_enable_voltage_control(adev);
-                ret = ci_construct_voltage_tables(adev);
-                if (ret) {
-                        DRM_ERROR("ci_construct_voltage_tables failed\n");
-                        return ret;
-                }
-        }
-        if (pi->caps_dynamic_ac_timing) {
-                ret = ci_initialize_mc_reg_table(adev);
-                if (ret)
-                        pi->caps_dynamic_ac_timing = false;
-        }
-        if (pi->dynamic_ss)
-                ci_enable_spread_spectrum(adev, true);
-        if (pi->thermal_protection)
-                ci_enable_thermal_protection(adev, true);
-        ci_program_sstp(adev);
-        ci_enable_display_gap(adev);
-        ci_program_vc(adev);
-        ret = ci_upload_firmware(adev);
-        if (ret) {
-                DRM_ERROR("ci_upload_firmware failed\n");
-                return ret;
-        }
-        ret = ci_process_firmware_header(adev);
-        if (ret) {
-                DRM_ERROR("ci_process_firmware_header failed\n");
-                return ret;
-        }
-        ret = ci_initial_switch_from_arb_f0_to_f1(adev);
-        if (ret) {
-                DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
-                return ret;
-        }
-        ret = ci_init_smc_table(adev);
-        if (ret) {
-                DRM_ERROR("ci_init_smc_table failed\n");
-                return ret;
-        }
-        ret = ci_init_arb_table_index(adev);
-        if (ret) {
-                DRM_ERROR("ci_init_arb_table_index failed\n");
-                return ret;
-        }
-        if (pi->caps_dynamic_ac_timing) {
-                ret = ci_populate_initial_mc_reg_table(adev);
-                if (ret) {
-                        DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
-                        return ret;
-                }
-        }
-        ret = ci_populate_pm_base(adev);
-        if (ret) {
-                DRM_ERROR("ci_populate_pm_base failed\n");
-                return ret;
-        }
-        ci_dpm_start_smc(adev);
-        ci_enable_vr_hot_gpio_interrupt(adev);
-        ret = ci_notify_smc_display_change(adev, false);
-        if (ret) {
-                DRM_ERROR("ci_notify_smc_display_change failed\n");
-                return ret;
-        }
-        ci_enable_sclk_control(adev, true);
-        ret = ci_enable_ulv(adev, true);
-        if (ret) {
-                DRM_ERROR("ci_enable_ulv failed\n");
-                return ret;
-        }
-        ret = ci_enable_ds_master_switch(adev, true);
-        if (ret) {
-                DRM_ERROR("ci_enable_ds_master_switch failed\n");
-                return ret;
-        }
-        ret = ci_start_dpm(adev);
-        if (ret) {
-                DRM_ERROR("ci_start_dpm failed\n");
-                return ret;
-        }
-        ret = ci_enable_didt(adev, true);
-        if (ret) {
-                DRM_ERROR("ci_enable_didt failed\n");
-                return ret;
-        }
-        ret = ci_enable_smc_cac(adev, true);
-        if (ret) {
-                DRM_ERROR("ci_enable_smc_cac failed\n");
-                return ret;
-        }
-        ret = ci_enable_power_containment(adev, true);
-        if (ret) {
-                DRM_ERROR("ci_enable_power_containment failed\n");
-                return ret;
-        }
-
-        ret = ci_power_control_set_level(adev);
-        if (ret) {
-                DRM_ERROR("ci_power_control_set_level failed\n");
-                return ret;
-        }
-
-        ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
-
-        ret = ci_enable_thermal_based_sclk_dpm(adev, true);
-        if (ret) {
-                DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
-                return ret;
-        }
-
-        ci_thermal_start_thermal_controller(adev);
-
-        ci_update_current_ps(adev, boot_ps);
-
-        return 0;
-}
-
-static void ci_dpm_disable(struct amdgpu_device *adev)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
-
-        amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
-                       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
-        amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
-                       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
-
-        ci_dpm_powergate_uvd(adev, true);
-
-        if (!amdgpu_ci_is_smc_running(adev))
-                return;
-
-        ci_thermal_stop_thermal_controller(adev);
-
-        if (pi->thermal_protection)
-                ci_enable_thermal_protection(adev, false);
-        ci_enable_power_containment(adev, false);
-        ci_enable_smc_cac(adev, false);
-        ci_enable_didt(adev, false);
-        ci_enable_spread_spectrum(adev, false);
-        ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
-        ci_stop_dpm(adev);
-        ci_enable_ds_master_switch(adev, false);
-        ci_enable_ulv(adev, false);
-        ci_clear_vc(adev);
-        ci_reset_to_default(adev);
-        ci_dpm_stop_smc(adev);
-        ci_force_switch_to_arb_f0(adev);
-        ci_enable_thermal_based_sclk_dpm(adev, false);
-
-        ci_update_current_ps(adev, boot_ps);
-}
-
-static int ci_dpm_set_power_state(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_ps *new_ps = &pi->requested_rps;
-        struct amdgpu_ps *old_ps = &pi->current_rps;
-        int ret;
-
-        ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
-        if (pi->pcie_performance_request)
-                ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
-        ret = ci_freeze_sclk_mclk_dpm(adev);
-        if (ret) {
-                DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
-                return ret;
-        }
-        ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
-        if (ret) {
-                DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
-                return ret;
-        }
-        ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
-        if (ret) {
-                DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
-                return ret;
-        }
-
-        ret = ci_update_vce_dpm(adev, new_ps, old_ps);
-        if (ret) {
-                DRM_ERROR("ci_update_vce_dpm failed\n");
-                return ret;
-        }
-
-        ret = ci_update_sclk_t(adev);
-        if (ret) {
-                DRM_ERROR("ci_update_sclk_t failed\n");
-                return ret;
-        }
-        if (pi->caps_dynamic_ac_timing) {
-                ret = ci_update_and_upload_mc_reg_table(adev);
-                if (ret) {
-                        DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
-                        return ret;
-                }
-        }
-        ret = ci_program_memory_timing_parameters(adev);
-        if (ret) {
-                DRM_ERROR("ci_program_memory_timing_parameters failed\n");
-                return ret;
-        }
-        ret = ci_unfreeze_sclk_mclk_dpm(adev);
-        if (ret) {
-                DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
-                return ret;
-        }
-        ret = ci_upload_dpm_level_enable_mask(adev);
-        if (ret) {
-                DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
-                return ret;
-        }
-        if (pi->pcie_performance_request)
-                ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
-
-        return 0;
-}
-
-#if 0
-static void ci_dpm_reset_asic(struct amdgpu_device *adev)
-{
-        ci_set_boot_state(adev);
-}
-#endif
-
-static void ci_dpm_display_configuration_changed(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        ci_program_display_gap(adev);
-}
-
-union power_info {
-        struct _ATOM_POWERPLAY_INFO info;
-        struct _ATOM_POWERPLAY_INFO_V2 info_2;
-        struct _ATOM_POWERPLAY_INFO_V3 info_3;
-        struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
-        struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
-        struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
-};
-
-union pplib_clock_info {
-        struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
-        struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
-        struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
-        struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
-        struct _ATOM_PPLIB_SI_CLOCK_INFO si;
-        struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
-};
-
-union pplib_power_state {
-        struct _ATOM_PPLIB_STATE v1;
-        struct _ATOM_PPLIB_STATE_V2 v2;
-};
-
-static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
-                                          struct amdgpu_ps *rps,
-                                          struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
-                                          u8 table_rev)
-{
-        rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
-        rps->class = le16_to_cpu(non_clock_info->usClassification);
-        rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
-
-        if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
-                rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
-                rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
-        } else {
-                rps->vclk = 0;
-                rps->dclk = 0;
-        }
-
-        if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
-                adev->pm.dpm.boot_ps = rps;
-        if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
-                adev->pm.dpm.uvd_ps = rps;
-}
-
-static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
-                                      struct amdgpu_ps *rps, int index,
-                                      union pplib_clock_info *clock_info)
-{
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ps *ps = ci_get_ps(rps);
-        struct ci_pl *pl = &ps->performance_levels[index];
-
-        ps->performance_level_count = index + 1;
-
-        pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
-        pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
-        pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
-        pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
-
-        pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
-                                                   pi->sys_pcie_mask,
-                                                   pi->vbios_boot_state.pcie_gen_bootup_value,
-                                                   clock_info->ci.ucPCIEGen);
-        pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
-                                                     pi->vbios_boot_state.pcie_lane_bootup_value,
-                                                     le16_to_cpu(clock_info->ci.usPCIELane));
-
-        if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
-                pi->acpi_pcie_gen = pl->pcie_gen;
-        }
-
-        if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
-                pi->ulv.supported = true;
-                pi->ulv.pl = *pl;
-                pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
-        }
-
-        /* patch up boot state */
-        if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
-                pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
-                pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
-                pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
-                pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
-        }
-
-        switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
-        case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
-                pi->use_pcie_powersaving_levels = true;
-                if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
-                        pi->pcie_gen_powersaving.max = pl->pcie_gen;
-                if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
-                        pi->pcie_gen_powersaving.min = pl->pcie_gen;
-                if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
-                        pi->pcie_lane_powersaving.max = pl->pcie_lane;
-                if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
-                        pi->pcie_lane_powersaving.min = pl->pcie_lane;
-                break;
-        case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
-                pi->use_pcie_performance_levels = true;
-                if (pi->pcie_gen_performance.max < pl->pcie_gen)
-                        pi->pcie_gen_performance.max = pl->pcie_gen;
-                if (pi->pcie_gen_performance.min > pl->pcie_gen)
-                        pi->pcie_gen_performance.min = pl->pcie_gen;
-                if (pi->pcie_lane_performance.max < pl->pcie_lane)
-                        pi->pcie_lane_performance.max = pl->pcie_lane;
-                if (pi->pcie_lane_performance.min > pl->pcie_lane)
-                        pi->pcie_lane_performance.min = pl->pcie_lane;
-                break;
-        default:
-                break;
-        }
-}
-
-static int ci_parse_power_table(struct amdgpu_device *adev)
-{
-        struct amdgpu_mode_info *mode_info = &adev->mode_info;
-        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
-        union pplib_power_state *power_state;
-        int i, j, k, non_clock_array_index, clock_array_index;
-        union pplib_clock_info *clock_info;
-        struct _StateArray *state_array;
-        struct _ClockInfoArray *clock_info_array;
-        struct _NonClockInfoArray *non_clock_info_array;
-        union power_info *power_info;
-        int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
-        u16 data_offset;
-        u8 frev, crev;
-        u8 *power_state_offset;
-        struct ci_ps *ps;
-
-        if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
-                                   &frev, &crev, &data_offset))
-                return -EINVAL;
-        power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
-
-        amdgpu_add_thermal_controller(adev);
-
-        state_array = (struct _StateArray *)
-                (mode_info->atom_context->bios + data_offset +
-                 le16_to_cpu(power_info->pplib.usStateArrayOffset));
-        clock_info_array = (struct _ClockInfoArray *)
-                (mode_info->atom_context->bios + data_offset +
-                 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
-        non_clock_info_array = (struct _NonClockInfoArray *)
-                (mode_info->atom_context->bios + data_offset +
-                 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
-
-        adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
-                                  sizeof(struct amdgpu_ps),
-                                  GFP_KERNEL);
-        if (!adev->pm.dpm.ps)
-                return -ENOMEM;
-        power_state_offset = (u8 *)state_array->states;
-        for (i = 0; i < state_array->ucNumEntries; i++) {
-                u8 *idx;
-                power_state = (union pplib_power_state *)power_state_offset;
-                non_clock_array_index = power_state->v2.nonClockInfoIndex;
-                non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
-                        &non_clock_info_array->nonClockInfo[non_clock_array_index];
-                ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
-                if (ps == NULL) {
-                        kfree(adev->pm.dpm.ps);
-                        return -ENOMEM;
-                }
-                adev->pm.dpm.ps[i].ps_priv = ps;
-                ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
-                                              non_clock_info,
-                                              non_clock_info_array->ucEntrySize);
-                k = 0;
-                idx = (u8 *)&power_state->v2.clockInfoIndex[0];
-                for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
-                        clock_array_index = idx[j];
-                        if (clock_array_index >= clock_info_array->ucNumEntries)
-                                continue;
-                        if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
-                                break;
-                        clock_info = (union pplib_clock_info *)
-                                ((u8 *)&clock_info_array->clockInfo[0] +
-                                 (clock_array_index * clock_info_array->ucEntrySize));
-                        ci_parse_pplib_clock_info(adev,
-                                                  &adev->pm.dpm.ps[i], k,
-                                                  clock_info);
-                        k++;
-                }
-                power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
-        }
-        adev->pm.dpm.num_ps = state_array->ucNumEntries;
-
-        /* fill in the vce power states */
-        for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
-                u32 sclk, mclk;
-                clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
-                clock_info = (union pplib_clock_info *)
-                        &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
-                sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
-                sclk |= clock_info->ci.ucEngineClockHigh << 16;
-                mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
-                mclk |= clock_info->ci.ucMemoryClockHigh << 16;
-                adev->pm.dpm.vce_states[i].sclk = sclk;
-                adev->pm.dpm.vce_states[i].mclk = mclk;
-        }
-
-        return 0;
-}
-
-static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
-                                    struct ci_vbios_boot_state *boot_state)
-{
-        struct amdgpu_mode_info *mode_info = &adev->mode_info;
-        int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
-        ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
-        u8 frev, crev;
-        u16 data_offset;
-
-        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
-                                   &frev, &crev, &data_offset)) {
-                firmware_info =
-                        (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
-                                                    data_offset);
-                boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
-                boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
-                boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
-                boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
-                boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
-                boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
-                boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
-
-                return 0;
-        }
-        return -EINVAL;
-}
-
-static void ci_dpm_fini(struct amdgpu_device *adev)
-{
-        int i;
-
-        for (i = 0; i < adev->pm.dpm.num_ps; i++) {
-                kfree(adev->pm.dpm.ps[i].ps_priv);
-        }
-        kfree(adev->pm.dpm.ps);
-        kfree(adev->pm.dpm.priv);
-        kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
-        amdgpu_free_extended_power_table(adev);
-}
-
-/**
- * ci_dpm_init_microcode - load ucode images from disk
- *
- * @adev: amdgpu_device pointer
- *
- * Use the firmware interface to load the ucode images into
- * the driver (not loaded into hw).
- * Returns 0 on success, error on failure.
- */
-static int ci_dpm_init_microcode(struct amdgpu_device *adev)
-{
-        const char *chip_name;
-        char fw_name[30];
-        int err;
-
-        DRM_DEBUG("\n");
-
-        switch (adev->asic_type) {
-        case CHIP_BONAIRE:
-                if ((adev->pdev->revision == 0x80) ||
-                    (adev->pdev->revision == 0x81) ||
-                    (adev->pdev->device == 0x665f))
-                        chip_name = "bonaire_k";
-                else
-                        chip_name = "bonaire";
-                break;
-        case CHIP_HAWAII:
-                if (adev->pdev->revision == 0x80)
-                        chip_name = "hawaii_k";
-                else
-                        chip_name = "hawaii";
-                break;
-        case CHIP_KAVERI:
-        case CHIP_KABINI:
-        case CHIP_MULLINS:
-        default: BUG();
-        }
-
-        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
-        err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
-        if (err)
-                goto out;
-        err = amdgpu_ucode_validate(adev->pm.fw);
-
-out:
-        if (err) {
-                pr_err("cik_smc: Failed to load firmware \"%s\"\n", fw_name);
-                release_firmware(adev->pm.fw);
-                adev->pm.fw = NULL;
-        }
-        return err;
-}
-
-static int ci_dpm_init(struct amdgpu_device *adev)
-{
-        int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
-        SMU7_Discrete_DpmTable *dpm_table;
-        struct amdgpu_gpio_rec gpio;
-        u16 data_offset, size;
-        u8 frev, crev;
-        struct ci_power_info *pi;
-        int ret;
-
-        pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
-        if (pi == NULL)
-                return -ENOMEM;
-        adev->pm.dpm.priv = pi;
-
-        pi->sys_pcie_mask =
-                adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
-
-        pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
-
-        pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
-        pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
-        pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
-        pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
-
-        pi->pcie_lane_performance.max = 0;
-        pi->pcie_lane_performance.min = 16;
-        pi->pcie_lane_powersaving.max = 0;
-        pi->pcie_lane_powersaving.min = 16;
-
-        ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
-        if (ret) {
-                ci_dpm_fini(adev);
-                return ret;
-        }
-
-        ret = amdgpu_get_platform_caps(adev);
-        if (ret) {
-                ci_dpm_fini(adev);
-                return ret;
-        }
-
-        ret = amdgpu_parse_extended_power_table(adev);
-        if (ret) {
-                ci_dpm_fini(adev);
-                return ret;
-        }
-
-        ret = ci_parse_power_table(adev);
-        if (ret) {
-                ci_dpm_fini(adev);
-                return ret;
-        }
-
-        pi->dll_default_on = false;
-        pi->sram_end = SMC_RAM_END;
-
-        pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
-        pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
-        pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
-        pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
-        pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
-        pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
-        pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
-        pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
-
-        pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
-
-        pi->sclk_dpm_key_disabled = 0;
-        pi->mclk_dpm_key_disabled = 0;
-        pi->pcie_dpm_key_disabled = 0;
-        pi->thermal_sclk_dpm_enabled = 0;
-
-        if (adev->powerplay.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
-                pi->caps_sclk_ds = true;
-        else
-                pi->caps_sclk_ds = false;
-
-        pi->mclk_strobe_mode_threshold = 40000;
-        pi->mclk_stutter_mode_threshold = 40000;
-        pi->mclk_edc_enable_threshold = 40000;
-        pi->mclk_edc_wr_enable_threshold = 40000;
-
-        ci_initialize_powertune_defaults(adev);
-
-        pi->caps_fps = false;
-
-        pi->caps_sclk_throttle_low_notification = false;
-
-        pi->caps_uvd_dpm = true;
-        pi->caps_vce_dpm = true;
-
-        ci_get_leakage_voltages(adev);
-        ci_patch_dependency_tables_with_leakage(adev);
-        ci_set_private_data_variables_based_on_pptable(adev);
-
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
-                kcalloc(4,
-                        sizeof(struct amdgpu_clock_voltage_dependency_entry),
-                        GFP_KERNEL);
-        if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
-                ci_dpm_fini(adev);
-                return -ENOMEM;
-        }
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
-        adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
-
-        adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
-        adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
-        adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
-
-        adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
-        adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
-        adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
-        adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
-
-        if (adev->asic_type == CHIP_HAWAII) {
-                pi->thermal_temp_setting.temperature_low = 94500;
-                pi->thermal_temp_setting.temperature_high = 95000;
-                pi->thermal_temp_setting.temperature_shutdown = 104000;
-        } else {
-                pi->thermal_temp_setting.temperature_low = 99500;
-                pi->thermal_temp_setting.temperature_high = 100000;
-                pi->thermal_temp_setting.temperature_shutdown = 104000;
-        }
-
-        pi->uvd_enabled = false;
-
-        dpm_table = &pi->smc_state_table;
-
-        gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
-        if (gpio.valid) {
-                dpm_table->VRHotGpio = gpio.shift;
-                adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
-        } else {
-                dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
-                adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
-        }
-
-        gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
-        if (gpio.valid) {
-                dpm_table->AcDcGpio = gpio.shift;
-                adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
-        } else {
-                dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
-                adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
-        }
-
-        gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
-        if (gpio.valid) {
-                u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
-
-                switch (gpio.shift) {
-                case 0:
-                        tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
-                        tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
-                        break;
-                case 1:
-                        tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
-                        tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
-                        break;
-                case 2:
-                        tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
-                        break;
-                case 3:
-                        tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
-                        break;
-                case 4:
-                        tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
-                        break;
-                default:
-                        DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift);
-                        break;
-                }
-                WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
-        }
-
-        pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
-        pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
-        pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
-        if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
-                pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
-        else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
-                pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
-
-        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
-                if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
-                        pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
-                else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
-                        pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
-                else
-                        adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
-        }
-
-        if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
-                if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
-                        pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
-                else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
-                        pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
-                else
-                        adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
-        }
-
-        pi->vddc_phase_shed_control = true;
-
-#if defined(CONFIG_ACPI)
-        pi->pcie_performance_request =
-                amdgpu_acpi_is_pcie_performance_request_supported(adev);
-#else
-        pi->pcie_performance_request = false;
-#endif
-
-        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
-                                   &frev, &crev, &data_offset)) {
-                pi->caps_sclk_ss_support = true;
-                pi->caps_mclk_ss_support = true;
-                pi->dynamic_ss = true;
-        } else {
-                pi->caps_sclk_ss_support = false;
-                pi->caps_mclk_ss_support = false;
-                pi->dynamic_ss = true;
-        }
-
-        if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
-                pi->thermal_protection = true;
-        else
-                pi->thermal_protection = false;
-
-        pi->caps_dynamic_ac_timing = true;
-
-        pi->uvd_power_gated = true;
-
-        /* make sure dc limits are valid */
-        if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
-            (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
-                adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
-                        adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
-
-        pi->fan_ctrl_is_in_default_mode = true;
-
-        return 0;
-}
-
-static void
-ci_dpm_debugfs_print_current_performance_level(void *handle,
-                                               struct seq_file *m)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct amdgpu_ps *rps = &pi->current_rps;
-        u32 sclk = ci_get_average_sclk_freq(adev);
-        u32 mclk = ci_get_average_mclk_freq(adev);
-        u32 activity_percent = 50;
-        int ret;
-
-        ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
-                                        &activity_percent);
-
-        if (ret == 0) {
-                activity_percent += 0x80;
-                activity_percent >>= 8;
-                activity_percent = activity_percent > 100 ? 100 : activity_percent;
-        }
-
-        seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
-        seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
-        seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
-                   sclk, mclk);
-        seq_printf(m, "GPU load: %u %%\n", activity_percent);
-}
-
-static void ci_dpm_print_power_state(void *handle, void *current_ps)
-{
-        struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
-        struct ci_ps *ps = ci_get_ps(rps);
-        struct ci_pl *pl;
-        int i;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        amdgpu_dpm_print_class_info(rps->class, rps->class2);
-        amdgpu_dpm_print_cap_info(rps->caps);
-        printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
-        for (i = 0; i < ps->performance_level_count; i++) {
-                pl = &ps->performance_levels[i];
-                printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
-                       i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
-        }
-        amdgpu_dpm_print_ps_status(adev, rps);
-}
-
-static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1,
-                                                const struct ci_pl *ci_cpl2)
-{
-        return ((ci_cpl1->mclk == ci_cpl2->mclk) &&
-                  (ci_cpl1->sclk == ci_cpl2->sclk) &&
-                  (ci_cpl1->pcie_gen == ci_cpl2->pcie_gen) &&
-                  (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));
-}
-
-static int ci_check_state_equal(void *handle,
-                                void *current_ps,
-                                void *request_ps,
-                                bool *equal)
-{
-        struct ci_ps *ci_cps;
-        struct ci_ps *ci_rps;
-        int i;
-        struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
-        struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
-                return -EINVAL;
-
-        ci_cps = ci_get_ps((struct amdgpu_ps *)cps);
-        ci_rps = ci_get_ps((struct amdgpu_ps *)rps);
-
-        if (ci_cps == NULL) {
-                *equal = false;
-                return 0;
-        }
-
-        if (ci_cps->performance_level_count != ci_rps->performance_level_count) {
-
-                *equal = false;
-                return 0;
-        }
-
-        for (i = 0; i < ci_cps->performance_level_count; i++) {
-                if (!ci_are_power_levels_equal(&(ci_cps->performance_levels[i]),
-                                        &(ci_rps->performance_levels[i]))) {
-                        *equal = false;
-                        return 0;
-                }
-        }
-
-        /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
-        *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
-        *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
-
-        return 0;
-}
-
-static u32 ci_dpm_get_sclk(void *handle, bool low)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
-
-        if (low)
-                return requested_state->performance_levels[0].sclk;
-        else
-                return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
-}
-
-static u32 ci_dpm_get_mclk(void *handle, bool low)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
-
-        if (low)
-                return requested_state->performance_levels[0].mclk;
-        else
-                return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
-}
-
-/* get temperature in millidegrees */
-static int ci_dpm_get_temp(void *handle)
-{
-        u32 temp;
-        int actual_temp = 0;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
-                CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
-
-        if (temp & 0x200)
-                actual_temp = 255;
-        else
-                actual_temp = temp & 0x1ff;
-
-        actual_temp = actual_temp * 1000;
-
-        return actual_temp;
-}
-
-static int ci_set_temperature_range(struct amdgpu_device *adev)
-{
-        int ret;
-
-        ret = ci_thermal_enable_alert(adev, false);
-        if (ret)
-                return ret;
-        ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
-                                               CISLANDS_TEMP_RANGE_MAX);
-        if (ret)
-                return ret;
-        ret = ci_thermal_enable_alert(adev, true);
-        if (ret)
-                return ret;
-        return ret;
-}
-
-static int ci_dpm_early_init(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        adev->powerplay.pp_funcs = &ci_dpm_funcs;
-        adev->powerplay.pp_handle = adev;
-        ci_dpm_set_irq_funcs(adev);
-
-        return 0;
-}
-
-static int ci_dpm_late_init(void *handle)
-{
-        int ret;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (!adev->pm.dpm_enabled)
-                return 0;
-
-        /* init the sysfs and debugfs files late */
-        ret = amdgpu_pm_sysfs_init(adev);
-        if (ret)
-                return ret;
-
-        ret = ci_set_temperature_range(adev);
-        if (ret)
-                return ret;
-
-        return 0;
-}
-
-static int ci_dpm_sw_init(void *handle)
-{
-        int ret;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230,
-                                &adev->pm.dpm.thermal.irq);
-        if (ret)
-                return ret;
-
-        ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231,
-                                &adev->pm.dpm.thermal.irq);
-        if (ret)
-                return ret;
-
-        /* default to balanced state */
-        adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
-        adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
-        adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
-        adev->pm.default_sclk = adev->clock.default_sclk;
-        adev->pm.default_mclk = adev->clock.default_mclk;
-        adev->pm.current_sclk = adev->clock.default_sclk;
-        adev->pm.current_mclk = adev->clock.default_mclk;
-        adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
-
-        ret = ci_dpm_init_microcode(adev);
-        if (ret)
-                return ret;
-
-        if (amdgpu_dpm == 0)
-                return 0;
-
-        INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
-        mutex_lock(&adev->pm.mutex);
-        ret = ci_dpm_init(adev);
-        if (ret)
-                goto dpm_failed;
-        adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
-        if (amdgpu_dpm == 1)
-                amdgpu_pm_print_power_states(adev);
-        mutex_unlock(&adev->pm.mutex);
-        DRM_INFO("amdgpu: dpm initialized\n");
-
-        return 0;
-
-dpm_failed:
-        ci_dpm_fini(adev);
-        mutex_unlock(&adev->pm.mutex);
-        DRM_ERROR("amdgpu: dpm initialization failed\n");
-        return ret;
-}
-
-static int ci_dpm_sw_fini(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        flush_work(&adev->pm.dpm.thermal.work);
-
-        mutex_lock(&adev->pm.mutex);
-        ci_dpm_fini(adev);
-        mutex_unlock(&adev->pm.mutex);
-
-        release_firmware(adev->pm.fw);
-        adev->pm.fw = NULL;
-
-        return 0;
-}
-
-static int ci_dpm_hw_init(void *handle)
-{
-        int ret;
-
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (!amdgpu_dpm) {
-                ret = ci_upload_firmware(adev);
-                if (ret) {
-                        DRM_ERROR("ci_upload_firmware failed\n");
-                        return ret;
-                }
-                ci_dpm_start_smc(adev);
-                return 0;
-        }
-
-        mutex_lock(&adev->pm.mutex);
-        ci_dpm_setup_asic(adev);
-        ret = ci_dpm_enable(adev);
-        if (ret)
-                adev->pm.dpm_enabled = false;
-        else
-                adev->pm.dpm_enabled = true;
-        mutex_unlock(&adev->pm.mutex);
-
-        return ret;
-}
-
-static int ci_dpm_hw_fini(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (adev->pm.dpm_enabled) {
-                mutex_lock(&adev->pm.mutex);
-                ci_dpm_disable(adev);
-                mutex_unlock(&adev->pm.mutex);
-        } else {
-                ci_dpm_stop_smc(adev);
-        }
-
-        return 0;
-}
-
-static int ci_dpm_suspend(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (adev->pm.dpm_enabled) {
-                mutex_lock(&adev->pm.mutex);
-                amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
-                               AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
-                amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
-                               AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
-                adev->pm.dpm.last_user_state = adev->pm.dpm.user_state;
-                adev->pm.dpm.last_state = adev->pm.dpm.state;
-                adev->pm.dpm.user_state = POWER_STATE_TYPE_INTERNAL_BOOT;
-                adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_BOOT;
-                mutex_unlock(&adev->pm.mutex);
-                amdgpu_pm_compute_clocks(adev);
-
-        }
-
-        return 0;
-}
-
-static int ci_dpm_resume(void *handle)
-{
-        int ret;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        if (adev->pm.dpm_enabled) {
-                /* asic init will reset to the boot state */
-                mutex_lock(&adev->pm.mutex);
-                ci_dpm_setup_asic(adev);
-                ret = ci_dpm_enable(adev);
-                if (ret)
-                        adev->pm.dpm_enabled = false;
-                else
-                        adev->pm.dpm_enabled = true;
-                adev->pm.dpm.user_state = adev->pm.dpm.last_user_state;
-                adev->pm.dpm.state = adev->pm.dpm.last_state;
-                mutex_unlock(&adev->pm.mutex);
-                if (adev->pm.dpm_enabled)
-                        amdgpu_pm_compute_clocks(adev);
-        }
-        return 0;
-}
-
-static bool ci_dpm_is_idle(void *handle)
-{
-        /* XXX */
-        return true;
-}
-
-static int ci_dpm_wait_for_idle(void *handle)
-{
-        /* XXX */
-        return 0;
-}
-
-static int ci_dpm_soft_reset(void *handle)
-{
-        return 0;
-}
-
-static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
-                                      struct amdgpu_irq_src *source,
-                                      unsigned type,
-                                      enum amdgpu_interrupt_state state)
-{
-        u32 cg_thermal_int;
-
-        switch (type) {
-        case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
-                switch (state) {
-                case AMDGPU_IRQ_STATE_DISABLE:
-                        cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
-                        cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
-                        WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
-                        break;
-                case AMDGPU_IRQ_STATE_ENABLE:
-                        cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
-                        cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
-                        WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
-                        break;
-                default:
-                        break;
-                }
-                break;
-
-        case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
-                switch (state) {
-                case AMDGPU_IRQ_STATE_DISABLE:
-                        cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
-                        cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
-                        WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
-                        break;
-                case AMDGPU_IRQ_STATE_ENABLE:
-                        cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
-                        cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
-                        WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
-                        break;
-                default:
-                        break;
-                }
-                break;
-
-        default:
-                break;
-        }
-        return 0;
-}
-
-static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
-                                    struct amdgpu_irq_src *source,
-                                    struct amdgpu_iv_entry *entry)
-{
-        bool queue_thermal = false;
-
-        if (entry == NULL)
-                return -EINVAL;
-
-        switch (entry->src_id) {
-        case 230: /* thermal low to high */
-                DRM_DEBUG("IH: thermal low to high\n");
-                adev->pm.dpm.thermal.high_to_low = false;
-                queue_thermal = true;
-                break;
-        case 231: /* thermal high to low */
-                DRM_DEBUG("IH: thermal high to low\n");
-                adev->pm.dpm.thermal.high_to_low = true;
-                queue_thermal = true;
-                break;
-        default:
-                break;
-        }
-
-        if (queue_thermal)
-                schedule_work(&adev->pm.dpm.thermal.work);
-
-        return 0;
-}
-
-static int ci_dpm_set_clockgating_state(void *handle,
-                                          enum amd_clockgating_state state)
-{
-        return 0;
-}
-
-static int ci_dpm_set_powergating_state(void *handle,
-                                          enum amd_powergating_state state)
-{
-        return 0;
-}
-
-static int ci_dpm_print_clock_levels(void *handle,
-                enum pp_clock_type type, char *buf)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
-        struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
-        struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
-
-        int i, now, size = 0;
-        uint32_t clock, pcie_speed;
-
-        switch (type) {
-        case PP_SCLK:
-                amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
-                clock = RREG32(mmSMC_MSG_ARG_0);
-
-                for (i = 0; i < sclk_table->count; i++) {
-                        if (clock > sclk_table->dpm_levels[i].value)
-                                continue;
-                        break;
-                }
-                now = i;
-
-                for (i = 0; i < sclk_table->count; i++)
-                        size += sprintf(buf + size, "%d: %uMhz %s\n",
-                                        i, sclk_table->dpm_levels[i].value / 100,
-                                        (i == now) ? "*" : "");
-                break;
-        case PP_MCLK:
-                amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
-                clock = RREG32(mmSMC_MSG_ARG_0);
-
-                for (i = 0; i < mclk_table->count; i++) {
-                        if (clock > mclk_table->dpm_levels[i].value)
-                                continue;
-                        break;
-                }
-                now = i;
-
-                for (i = 0; i < mclk_table->count; i++)
-                        size += sprintf(buf + size, "%d: %uMhz %s\n",
-                                        i, mclk_table->dpm_levels[i].value / 100,
-                                        (i == now) ? "*" : "");
-                break;
-        case PP_PCIE:
-                pcie_speed = ci_get_current_pcie_speed(adev);
-                for (i = 0; i < pcie_table->count; i++) {
-                        if (pcie_speed != pcie_table->dpm_levels[i].value)
-                                continue;
-                        break;
-                }
-                now = i;
-
-                for (i = 0; i < pcie_table->count; i++)
-                        size += sprintf(buf + size, "%d: %s %s\n", i,
-                                        (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x1" :
-                                        (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" :
-                                        (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
-                                        (i == now) ? "*" : "");
-                break;
-        default:
-                break;
-        }
-
-        return size;
-}
-
-static int ci_dpm_force_clock_level(void *handle,
-                enum pp_clock_type type, uint32_t mask)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-
-        if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL)
-                return -EINVAL;
-
-        if (mask == 0)
-                return -EINVAL;
-
-        switch (type) {
-        case PP_SCLK:
-                if (!pi->sclk_dpm_key_disabled)
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                        PPSMC_MSG_SCLKDPM_SetEnabledMask,
-                                        pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
-                break;
-
-        case PP_MCLK:
-                if (!pi->mclk_dpm_key_disabled)
-                        amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                        PPSMC_MSG_MCLKDPM_SetEnabledMask,
-                                        pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
-                break;
-
-        case PP_PCIE:
-        {
-                uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
-
-                if (!pi->pcie_dpm_key_disabled) {
-                        if (fls(tmp) != ffs(tmp))
-                                amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_UnForceLevel);
-                        else
-                                amdgpu_ci_send_msg_to_smc_with_parameter(adev,
-                                        PPSMC_MSG_PCIeDPM_ForceLevel,
-                                        fls(tmp) - 1);
-                }
-                break;
-        }
-        default:
-                break;
-        }
-
-        return 0;
-}
-
-static int ci_dpm_get_sclk_od(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
-        struct ci_single_dpm_table *golden_sclk_table =
-                        &(pi->golden_dpm_table.sclk_table);
-        int value;
-
-        value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
-                        golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
-                        100 /
-                        golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
-
-        return value;
-}
-
-static int ci_dpm_set_sclk_od(void *handle, uint32_t value)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
-        struct ci_single_dpm_table *golden_sclk_table =
-                        &(pi->golden_dpm_table.sclk_table);
-
-        if (value > 20)
-                value = 20;
-
-        ps->performance_levels[ps->performance_level_count - 1].sclk =
-                        golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
-                        value / 100 +
-                        golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
-
-        return 0;
-}
-
-static int ci_dpm_get_mclk_od(void *handle)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
-        struct ci_single_dpm_table *golden_mclk_table =
-                        &(pi->golden_dpm_table.mclk_table);
-        int value;
-
-        value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
-                        golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
-                        100 /
-                        golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
-
-        return value;
-}
-
-static int ci_dpm_set_mclk_od(void *handle, uint32_t value)
-{
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct ci_power_info *pi = ci_get_pi(adev);
-        struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
-        struct ci_single_dpm_table *golden_mclk_table =
-                        &(pi->golden_dpm_table.mclk_table);
-
-        if (value > 20)
-                value = 20;
-
-        ps->performance_levels[ps->performance_level_count - 1].mclk =
-                        golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
-                        value / 100 +
-                        golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
-
-        return 0;
-}
-
-static int ci_dpm_read_sensor(void *handle, int idx,
-                              void *value, int *size)
-{
-        u32 activity_percent = 50;
-        int ret;
-        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-        /* size must be at least 4 bytes for all sensors */
-        if (*size < 4)
-                return -EINVAL;
-
-        switch (idx) {
-        case AMDGPU_PP_SENSOR_GFX_SCLK:
-                *((uint32_t *)value) = ci_get_average_sclk_freq(adev);
-                *size = 4;
-                return 0;
-        case AMDGPU_PP_SENSOR_GFX_MCLK:
-                *((uint32_t *)value) = ci_get_average_mclk_freq(adev);
-                *size = 4;
-                return 0;
-        case AMDGPU_PP_SENSOR_GPU_TEMP:
-                *((uint32_t *)value) = ci_dpm_get_temp(adev);
-                *size = 4;
-                return 0;
-        case AMDGPU_PP_SENSOR_GPU_LOAD:
-                ret = ci_read_smc_soft_register(adev,
-                                                offsetof(SMU7_SoftRegisters,
-                                                         AverageGraphicsA),
-                                                &activity_percent);
-                if (ret == 0) {
-                        activity_percent += 0x80;
-                        activity_percent >>= 8;
-                        activity_percent =
-                                activity_percent > 100 ? 100 : activity_percent;
-                }
-                *((uint32_t *)value) = activity_percent;
-                *size = 4;
-                return 0;
-        default:
-                return -EINVAL;
-        }
-}
-
-static int ci_set_powergating_by_smu(void *handle,
-                                uint32_t block_type, bool gate)
-{
-        switch (block_type) {
-        case AMD_IP_BLOCK_TYPE_UVD:
-                ci_dpm_powergate_uvd(handle, gate);
-                break;
-        default:
-                break;
-        }
-        return 0;
-}
-
-static const struct amd_ip_funcs ci_dpm_ip_funcs = {
-        .name = "ci_dpm",
-        .early_init = ci_dpm_early_init,
-        .late_init = ci_dpm_late_init,
-        .sw_init = ci_dpm_sw_init,
-        .sw_fini = ci_dpm_sw_fini,
-        .hw_init = ci_dpm_hw_init,
-        .hw_fini = ci_dpm_hw_fini,
-        .suspend = ci_dpm_suspend,
-        .resume = ci_dpm_resume,
-        .is_idle = ci_dpm_is_idle,
-        .wait_for_idle = ci_dpm_wait_for_idle,
-        .soft_reset = ci_dpm_soft_reset,
-        .set_clockgating_state = ci_dpm_set_clockgating_state,
-        .set_powergating_state = ci_dpm_set_powergating_state,
-};
-
-const struct amdgpu_ip_block_version ci_smu_ip_block =
-{
-        .type = AMD_IP_BLOCK_TYPE_SMC,
-        .major = 7,
-        .minor = 0,
-        .rev = 0,
-        .funcs = &ci_dpm_ip_funcs,
-};
-
-static const struct amd_pm_funcs ci_dpm_funcs = {
-        .pre_set_power_state = &ci_dpm_pre_set_power_state,
-        .set_power_state = &ci_dpm_set_power_state,
-        .post_set_power_state = &ci_dpm_post_set_power_state,
-        .display_configuration_changed = &ci_dpm_display_configuration_changed,
-        .get_sclk = &ci_dpm_get_sclk,
-        .get_mclk = &ci_dpm_get_mclk,
-        .print_power_state = &ci_dpm_print_power_state,
-        .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
-        .force_performance_level = &ci_dpm_force_performance_level,
-        .vblank_too_short = &ci_dpm_vblank_too_short,
-        .set_powergating_by_smu = &ci_set_powergating_by_smu,
-        .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
-        .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
-        .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
-        .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
-        .print_clock_levels = ci_dpm_print_clock_levels,
-        .force_clock_level = ci_dpm_force_clock_level,
-        .get_sclk_od = ci_dpm_get_sclk_od,
-        .set_sclk_od = ci_dpm_set_sclk_od,
-        .get_mclk_od = ci_dpm_get_mclk_od,
-        .set_mclk_od = ci_dpm_set_mclk_od,
-        .check_state_equal = ci_check_state_equal,
-        .get_vce_clock_state = amdgpu_get_vce_clock_state,
-        .read_sensor = ci_dpm_read_sensor,
-};
-
-static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
-        .set = ci_dpm_set_interrupt_state,
-        .process = ci_dpm_process_interrupt,
-};
-
-static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
-{
-        adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
-        adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.h b/drivers/gpu/drm/amd/amdgpu/ci_dpm.h
deleted file mode 100644
index 91be2996ae7c..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright 2013 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-#ifndef __CI_DPM_H__
-#define __CI_DPM_H__
-
-#include "amdgpu_atombios.h"
-#include "ppsmc.h"
-
-#define SMU__NUM_SCLK_DPM_STATE  8
-#define SMU__NUM_MCLK_DPM_LEVELS 6
-#define SMU__NUM_LCLK_DPM_LEVELS 8
-#define SMU__NUM_PCIE_DPM_LEVELS 8
-#include "smu7_discrete.h"
-
-#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
-
-#define CISLANDS_UNUSED_GPIO_PIN 0x7F
-
-struct ci_pl {
-        u32 mclk;
-        u32 sclk;
-        enum amdgpu_pcie_gen pcie_gen;
-        u16 pcie_lane;
-};
-
-struct ci_ps {
-        u16 performance_level_count;
-        bool dc_compatible;
-        u32 sclk_t;
-        struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
-};
-
-struct ci_dpm_level {
-        bool enabled;
-        u32 value;
-        u32 param1;
-};
-
-#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
-#define MAX_REGULAR_DPM_NUMBER 8
-#define CISLAND_MINIMUM_ENGINE_CLOCK 800
-
-struct ci_single_dpm_table {
-        u32 count;
-        struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
-};
-
-struct ci_dpm_table {
-        struct ci_single_dpm_table sclk_table;
-        struct ci_single_dpm_table mclk_table;
-        struct ci_single_dpm_table pcie_speed_table;
-        struct ci_single_dpm_table vddc_table;
-        struct ci_single_dpm_table vddci_table;
-        struct ci_single_dpm_table mvdd_table;
-};
-
-struct ci_mc_reg_entry {
-        u32 mclk_max;
-        u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-};
-
-struct ci_mc_reg_table {
-        u8 last;
-        u8 num_entries;
-        u16 valid_flag;
-        struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
-        SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
-};
-
-struct ci_ulv_parm
-{
-        bool supported;
-        u32 cg_ulv_parameter;
-        u32 volt_change_delay;
-        struct ci_pl pl;
-};
-
-#define CISLANDS_MAX_LEAKAGE_COUNT  8
-
-struct ci_leakage_voltage {
-        u16 count;
-        u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
-        u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
-};
-
-struct ci_dpm_level_enable_mask {
-        u32 uvd_dpm_enable_mask;
-        u32 vce_dpm_enable_mask;
-        u32 acp_dpm_enable_mask;
-        u32 samu_dpm_enable_mask;
-        u32 sclk_dpm_enable_mask;
-        u32 mclk_dpm_enable_mask;
-        u32 pcie_dpm_enable_mask;
-};
-
-struct ci_vbios_boot_state
-{
-        u16 mvdd_bootup_value;
-        u16 vddc_bootup_value;
-        u16 vddci_bootup_value;
-        u32 sclk_bootup_value;
-        u32 mclk_bootup_value;
-        u16 pcie_gen_bootup_value;
-        u16 pcie_lane_bootup_value;
-};
-
-struct ci_clock_registers {
-        u32 cg_spll_func_cntl;
-        u32 cg_spll_func_cntl_2;
-        u32 cg_spll_func_cntl_3;
-        u32 cg_spll_func_cntl_4;
-        u32 cg_spll_spread_spectrum;
-        u32 cg_spll_spread_spectrum_2;
-        u32 dll_cntl;
-        u32 mclk_pwrmgt_cntl;
-        u32 mpll_ad_func_cntl;
-        u32 mpll_dq_func_cntl;
-        u32 mpll_func_cntl;
-        u32 mpll_func_cntl_1;
-        u32 mpll_func_cntl_2;
-        u32 mpll_ss1;
-        u32 mpll_ss2;
-};
-
-struct ci_thermal_temperature_setting {
-        s32 temperature_low;
-        s32 temperature_high;
-        s32 temperature_shutdown;
-};
-
-struct ci_pcie_perf_range {
-        u16 max;
-        u16 min;
-};
-
-enum ci_pt_config_reg_type {
-        CISLANDS_CONFIGREG_MMR = 0,
-        CISLANDS_CONFIGREG_SMC_IND,
-        CISLANDS_CONFIGREG_DIDT_IND,
-        CISLANDS_CONFIGREG_CACHE,
-        CISLANDS_CONFIGREG_MAX
-};
-
-#define POWERCONTAINMENT_FEATURE_BAPM            0x00000001
-#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
-#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
-
-struct ci_pt_config_reg {
-        u32 offset;
-        u32 mask;
-        u32 shift;
-        u32 value;
-        enum ci_pt_config_reg_type type;
-};
-
-struct ci_pt_defaults {
-        u8 svi_load_line_en;
-        u8 svi_load_line_vddc;
-        u8 tdc_vddc_throttle_release_limit_perc;
-        u8 tdc_mawt;
-        u8 tdc_waterfall_ctl;
-        u8 dte_ambient_temp_base;
-        u32 display_cac;
-        u32 bapm_temp_gradient;
-        u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
-        u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
-};
-
-#define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK     0x00000002
-#define DPMTABLE_UPDATE_SCLK        0x00000004
-#define DPMTABLE_UPDATE_MCLK        0x00000008
-
-struct ci_power_info {
-        struct ci_dpm_table dpm_table;
-        struct ci_dpm_table golden_dpm_table;
-        u32 voltage_control;
-        u32 mvdd_control;
-        u32 vddci_control;
-        u32 active_auto_throttle_sources;
-        struct ci_clock_registers clock_registers;
-        u16 acpi_vddc;
-        u16 acpi_vddci;
-        enum amdgpu_pcie_gen force_pcie_gen;
-        enum amdgpu_pcie_gen acpi_pcie_gen;
-        struct ci_leakage_voltage vddc_leakage;
-        struct ci_leakage_voltage vddci_leakage;
-        u16 max_vddc_in_pp_table;
-        u16 min_vddc_in_pp_table;
-        u16 max_vddci_in_pp_table;
-        u16 min_vddci_in_pp_table;
-        u32 mclk_strobe_mode_threshold;
-        u32 mclk_stutter_mode_threshold;
-        u32 mclk_edc_enable_threshold;
-        u32 mclk_edc_wr_enable_threshold;
-        struct ci_vbios_boot_state vbios_boot_state;
-        /* smc offsets */
-        u32 sram_end;
-        u32 dpm_table_start;
-        u32 soft_regs_start;
-        u32 mc_reg_table_start;
-        u32 fan_table_start;
-        u32 arb_table_start;
-        /* smc tables */
-        SMU7_Discrete_DpmTable smc_state_table;
-        SMU7_Discrete_MCRegisters smc_mc_reg_table;
-        SMU7_Discrete_PmFuses smc_powertune_table;
-        /* other stuff */
-        struct ci_mc_reg_table mc_reg_table;
-        struct atom_voltage_table vddc_voltage_table;
-        struct atom_voltage_table vddci_voltage_table;
-        struct atom_voltage_table mvdd_voltage_table;
-        struct ci_ulv_parm ulv;
-        u32 power_containment_features;
-        const struct ci_pt_defaults *powertune_defaults;
-        u32 dte_tj_offset;
-        bool vddc_phase_shed_control;
-        struct ci_thermal_temperature_setting thermal_temp_setting;
-        struct ci_dpm_level_enable_mask dpm_level_enable_mask;
-        u32 need_update_smu7_dpm_table;
-        u32 sclk_dpm_key_disabled;
-        u32 mclk_dpm_key_disabled;
-        u32 pcie_dpm_key_disabled;
-        u32 thermal_sclk_dpm_enabled;
-        struct ci_pcie_perf_range pcie_gen_performance;
-        struct ci_pcie_perf_range pcie_lane_performance;
-        struct ci_pcie_perf_range pcie_gen_powersaving;
-        struct ci_pcie_perf_range pcie_lane_powersaving;
-        u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
-        u32 mclk_activity_target;
-        u32 low_sclk_interrupt_t;
-        u32 last_mclk_dpm_enable_mask;
-        u32 sys_pcie_mask;
-        /* caps */
-        bool caps_power_containment;
-        bool caps_cac;
-        bool caps_sq_ramping;
-        bool caps_db_ramping;
-        bool caps_td_ramping;
-        bool caps_tcp_ramping;
-        bool caps_fps;
-        bool caps_sclk_ds;
-        bool caps_sclk_ss_support;
-        bool caps_mclk_ss_support;
-        bool caps_uvd_dpm;
-        bool caps_vce_dpm;
-        bool caps_samu_dpm;
-        bool caps_acp_dpm;
-        bool caps_automatic_dc_transition;
-        bool caps_sclk_throttle_low_notification;
-        bool caps_dynamic_ac_timing;
-        bool caps_od_fuzzy_fan_control_support;
-        /* flags */
-        bool thermal_protection;
-        bool pcie_performance_request;
-        bool dynamic_ss;
-        bool dll_default_on;
-        bool cac_enabled;
-        bool uvd_enabled;
-        bool battery_state;
-        bool pspp_notify_required;
-        bool enable_bapm_feature;
-        bool enable_tdc_limit_feature;
-        bool enable_pkg_pwr_tracking_feature;
-        bool use_pcie_performance_levels;
-        bool use_pcie_powersaving_levels;
-        bool uvd_power_gated;
-        /* driver states */
-        struct amdgpu_ps current_rps;
-        struct ci_ps current_ps;
-        struct amdgpu_ps requested_rps;
-        struct ci_ps requested_ps;
-        /* fan control */
-        bool fan_ctrl_is_in_default_mode;
-        bool fan_is_controlled_by_smc;
-        u32 t_min;
-        u32 fan_ctrl_default_mode;
-};
-
-#define CISLANDS_VOLTAGE_CONTROL_NONE                   0x0
-#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO                0x1
-#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2               0x2
-
-#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT             256
-
-#define CISLANDS_VRC_DFLT0                              0x3FFFC000
-#define CISLANDS_VRC_DFLT1                              0x000400
-#define CISLANDS_VRC_DFLT2                              0xC00080
-#define CISLANDS_VRC_DFLT3                              0xC00200
-#define CISLANDS_VRC_DFLT4                              0xC01680
-#define CISLANDS_VRC_DFLT5                              0xC00033
-#define CISLANDS_VRC_DFLT6                              0xC00033
-#define CISLANDS_VRC_DFLT7                              0x3FFFC000
-
-#define CISLANDS_CGULVPARAMETER_DFLT                    0x00040035
-#define CISLAND_TARGETACTIVITY_DFLT                     30
-#define CISLAND_MCLK_TARGETACTIVITY_DFLT                10
-
-#define PCIE_PERF_REQ_REMOVE_REGISTRY   0
-#define PCIE_PERF_REQ_FORCE_LOWPOWER    1
-#define PCIE_PERF_REQ_PECI_GEN1         2
-#define PCIE_PERF_REQ_PECI_GEN2         3
-#define PCIE_PERF_REQ_PECI_GEN3         4
-
-#define CISLANDS_SSTU_DFLT                               0
-#define CISLANDS_SST_DFLT                                0x00C8
-
-/* XXX are these ok? */
-#define CISLANDS_TEMP_RANGE_MIN (90 * 1000)
-#define CISLANDS_TEMP_RANGE_MAX (120 * 1000)
-
-int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev,
-                         u32 smc_start_address,
-                         const u8 *src, u32 byte_count, u32 limit);
-void amdgpu_ci_start_smc(struct amdgpu_device *adev);
-void amdgpu_ci_reset_smc(struct amdgpu_device *adev);
-int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev);
-void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev);
-void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev);
-bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev);
-PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg);
-PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev);
-int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit);
-int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev,
-                           u32 smc_address, u32 *value, u32 limit);
-int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev,
-                            u32 smc_address, u32 value, u32 limit);
-
-#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_smc.c b/drivers/gpu/drm/amd/amdgpu/ci_smc.c
deleted file mode 100644
index b8ba51e045b5..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/ci_smc.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * Copyright 2011 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Alex Deucher
- */
-
-#include <linux/firmware.h>
-#include <drm/drmP.h>
-#include "amdgpu.h"
-#include "cikd.h"
-#include "ppsmc.h"
-#include "amdgpu_ucode.h"
-#include "ci_dpm.h"
-
-#include "smu/smu_7_0_1_d.h"
-#include "smu/smu_7_0_1_sh_mask.h"
-
-static int ci_set_smc_sram_address(struct amdgpu_device *adev,
-                                   u32 smc_address, u32 limit)
-{
-        if (smc_address & 3)
-                return -EINVAL;
-        if ((smc_address + 3) > limit)
-                return -EINVAL;
-
-        WREG32(mmSMC_IND_INDEX_0, smc_address);
-        WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
-
-        return 0;
-}
-
-int amdgpu_ci_copy_bytes_to_smc(struct amdgpu_device *adev,
-                         u32 smc_start_address,
-                         const u8 *src, u32 byte_count, u32 limit)
-{
-        unsigned long flags;
-        u32 data, original_data;
-        u32 addr;
-        u32 extra_shift;
-        int ret = 0;
-
-        if (smc_start_address & 3)
-                return -EINVAL;
-        if ((smc_start_address + byte_count) > limit)
-                return -EINVAL;
-
-        addr = smc_start_address;
-
-        spin_lock_irqsave(&adev->smc_idx_lock, flags);
-        while (byte_count >= 4) {
-                /* SMC address space is BE */
-                data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
-
-                ret = ci_set_smc_sram_address(adev, addr, limit);
-                if (ret)
-                        goto done;
-
-                WREG32(mmSMC_IND_DATA_0, data);
-
-                src += 4;
-                byte_count -= 4;
-                addr += 4;
-        }
-
-        /* RMW for the final bytes */
-        if (byte_count > 0) {
-                data = 0;
-
-                ret = ci_set_smc_sram_address(adev, addr, limit);
-                if (ret)
-                        goto done;
-
-                original_data = RREG32(mmSMC_IND_DATA_0);
-
-                extra_shift = 8 * (4 - byte_count);
-
-                while (byte_count > 0) {
-                        data = (data << 8) + *src++;
-                        byte_count--;
-                }
-
-                data <<= extra_shift;
-
-                data |= (original_data & ~((~0UL) << extra_shift));
-
-                ret = ci_set_smc_sram_address(adev, addr, limit);
-                if (ret)
-                        goto done;
-
-                WREG32(mmSMC_IND_DATA_0, data);
-        }
-
-done:
-        spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-
-        return ret;
-}
-
-void amdgpu_ci_start_smc(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
-
-        tmp &= ~SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
-        WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
-}
-
-void amdgpu_ci_reset_smc(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
-
-        tmp |= SMC_SYSCON_RESET_CNTL__rst_reg_MASK;
-        WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp);
-}
-
-int amdgpu_ci_program_jump_on_start(struct amdgpu_device *adev)
-{
-        static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };
-
-        return amdgpu_ci_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
-}
-
-void amdgpu_ci_stop_smc_clock(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
-
-        tmp |= SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
-
-        WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
-}
-
-void amdgpu_ci_start_smc_clock(struct amdgpu_device *adev)
-{
-        u32 tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
-
-        tmp &= ~SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK;
-
-        WREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0, tmp);
-}
-
-bool amdgpu_ci_is_smc_running(struct amdgpu_device *adev)
-{
-        u32 clk = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
-        u32 pc_c = RREG32_SMC(ixSMC_PC_C);
-
-        if (!(clk & SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK) && (0x20100 <= pc_c))
-                return true;
-
-        return false;
-}
-
-PPSMC_Result amdgpu_ci_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg)
-{
-        u32 tmp;
-        int i;
-
-        if (!amdgpu_ci_is_smc_running(adev))
-                return PPSMC_Result_Failed;
-
-        WREG32(mmSMC_MESSAGE_0, msg);
-
-        for (i = 0; i < adev->usec_timeout; i++) {
-                tmp = RREG32(mmSMC_RESP_0);
-                if (tmp != 0)
-                        break;
-                udelay(1);
-        }
-        tmp = RREG32(mmSMC_RESP_0);
-
-        return (PPSMC_Result)tmp;
-}
-
-PPSMC_Result amdgpu_ci_wait_for_smc_inactive(struct amdgpu_device *adev)
-{
-        u32 tmp;
-        int i;
-
-        if (!amdgpu_ci_is_smc_running(adev))
-                return PPSMC_Result_OK;
-
-        for (i = 0; i < adev->usec_timeout; i++) {
-                tmp = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
-                if ((tmp & SMC_SYSCON_CLOCK_CNTL_0__cken_MASK) == 0)
-                        break;
-                udelay(1);
-        }
-
-        return PPSMC_Result_OK;
-}
-
-int amdgpu_ci_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
-{
-        const struct smc_firmware_header_v1_0 *hdr;
-        unsigned long flags;
-        u32 ucode_start_address;
-        u32 ucode_size;
-        const u8 *src;
-        u32 data;
-
-        if (!adev->pm.fw)
-                return -EINVAL;
-
-        hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
-        amdgpu_ucode_print_smc_hdr(&hdr->header);
-
-        adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
-        ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
-        ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
-        src = (const u8 *)
-                (adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-
-        if (ucode_size & 3)
-                return -EINVAL;
-
-        spin_lock_irqsave(&adev->smc_idx_lock, flags);
-        WREG32(mmSMC_IND_INDEX_0, ucode_start_address);
-        WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK,
-                ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
-        while (ucode_size >= 4) {
-                /* SMC address space is BE */
-                data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
-
-                WREG32(mmSMC_IND_DATA_0, data);
-
-                src += 4;
-                ucode_size -= 4;
-        }
-        WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK);
-        spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-
-        return 0;
-}
-
-int amdgpu_ci_read_smc_sram_dword(struct amdgpu_device *adev,
-                           u32 smc_address, u32 *value, u32 limit)
-{
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&adev->smc_idx_lock, flags);
-        ret = ci_set_smc_sram_address(adev, smc_address, limit);
-        if (ret == 0)
-                *value = RREG32(mmSMC_IND_DATA_0);
-        spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-
-        return ret;
-}
-
-int amdgpu_ci_write_smc_sram_dword(struct amdgpu_device *adev,
-                            u32 smc_address, u32 value, u32 limit)
-{
-        unsigned long flags;
-        int ret;
-
-        spin_lock_irqsave(&adev->smc_idx_lock, flags);
-        ret = ci_set_smc_sram_address(adev, smc_address, limit);
-        if (ret == 0)
-                WREG32(mmSMC_IND_DATA_0, value);
-        spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
-
-        return ret;
-}
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 71c50d8900e3..07c1f239e9c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1741,6 +1741,69 @@ static bool cik_need_full_reset(struct amdgpu_device *adev)
         return true;
 }
 
+static void cik_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+                               uint64_t *count1)
+{
+        uint32_t perfctr = 0;
+        uint64_t cnt0_of, cnt1_of;
+        int tmp;
+
+        /* This reports 0 on APUs, so return to avoid writing/reading registers
+         * that may or may not be different from their GPU counterparts
+         */
+        if (adev->flags & AMD_IS_APU)
+                return;
+
+        /* Set the 2 events that we wish to watch, defined above */
+        /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+
+        /* Write to enable desired perf counters */
+        WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
+        /* Zero out and enable the perf counters
+         * Write 0x5:
+         * Bit 0 = Start all counters(1)
+         * Bit 2 = Global counter reset enable(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
+
+        msleep(1000);
+
+        /* Load the shadow and disable the perf counters
+         * Write 0x2:
+         * Bit 0 = Stop counters(0)
+         * Bit 1 = Load the shadow counters(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
+
+        /* Read register values to get any >32bit overflow */
+        tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
+        cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
+        cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
+
+        /* Get the values and add the overflow */
+        *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
+        *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
+}
+
+static bool cik_need_reset_on_init(struct amdgpu_device *adev)
+{
+        u32 clock_cntl, pc;
+
+        if (adev->flags & AMD_IS_APU)
+                return false;
+
+        /* check if the SMC is already running */
+        clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
+        pc = RREG32_SMC(ixSMC_PC_C);
+        if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
+            (0x20100 <= pc))
+                return true;
+
+        return false;
+}
+
 static const struct amdgpu_asic_funcs cik_asic_funcs =
 {
         .read_disabled_bios = &cik_read_disabled_bios,
@@ -1756,6 +1819,8 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
         .invalidate_hdp = &cik_invalidate_hdp,
         .need_full_reset = &cik_need_full_reset,
         .init_doorbell_index = &legacy_doorbell_index_init,
+        .get_pcie_usage = &cik_get_pcie_usage,
+        .need_reset_on_init = &cik_need_reset_on_init,
 };
 
 static int cik_common_early_init(void *handle)
@@ -2005,10 +2070,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
                 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
                 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
                 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
-                if (amdgpu_dpm == -1)
-                        amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
-                else
-                        amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
+                amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
                 if (adev->enable_virtual_display)
                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
@@ -2026,10 +2088,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
                 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
                 amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
                 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
-                if (amdgpu_dpm == -1)
-                        amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
-                else
-                        amdgpu_device_ip_block_add(adev, &ci_smu_ip_block);
+                amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
                 if (adev->enable_virtual_display)
                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
index 2a086610f74d..2fcc4b60153c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
@@ -24,7 +24,6 @@
 #ifndef __CIK_DPM_H__
 #define __CIK_DPM_H__
 
-extern const struct amdgpu_ip_block_version ci_smu_ip_block;
 extern const struct amdgpu_ip_block_version kv_smu_ip_block;
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 8a8b4967a101..721c757156e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -103,9 +103,9 @@ static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int cik_ih_irq_init(struct amdgpu_device *adev)
 {
+        struct amdgpu_ih_ring *ih = &adev->irq.ih;
         int rb_bufsz;
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
-        u64 wptr_off;
 
         /* disable irqs */
         cik_ih_disable_interrupts(adev);
@@ -131,9 +131,8 @@ static int cik_ih_irq_init(struct amdgpu_device *adev)
         ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK;
 
         /* set the writeback address whether it's enabled or not */
-        wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
-        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
 
         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
 
@@ -183,11 +182,12 @@ static void cik_ih_irq_disable(struct amdgpu_device *adev)
  * Used by cik_irq_process().
  * Returns the value of the wptr.
  */
-static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
+static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
+                           struct amdgpu_ih_ring *ih)
 {
         u32 wptr, tmp;
 
-        wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+        wptr = le32_to_cpu(*ih->wptr_cpu);
 
         if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
                 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
@@ -196,13 +196,13 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
                  * this should allow us to catchup.
                  */
                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
-                        wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
-                adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+                         wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+                ih->rptr = (wptr + 16) & ih->ptr_mask;
                 tmp = RREG32(mmIH_RB_CNTL);
                 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
                 WREG32(mmIH_RB_CNTL, tmp);
         }
-        return (wptr & adev->irq.ih.ptr_mask);
+        return (wptr & ih->ptr_mask);
 }
 
 /*        CIK IV Ring
@@ -237,16 +237,17 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev)
  * position and also advance the position.
  */
 static void cik_ih_decode_iv(struct amdgpu_device *adev,
+                             struct amdgpu_ih_ring *ih,
                              struct amdgpu_iv_entry *entry)
 {
         /* wptr/rptr are in bytes! */
-        u32 ring_index = adev->irq.ih.rptr >> 2;
+        u32 ring_index = ih->rptr >> 2;
         uint32_t dw[4];
 
-        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
-        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
-        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-        dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
+        dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
+        dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
+        dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
+        dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
 
         entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
         entry->src_id = dw[0] & 0xff;
@@ -256,7 +257,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
         entry->pasid = (dw[2] >> 16) & 0xffff;
 
         /* wptr/rptr are in bytes! */
-        adev->irq.ih.rptr += 16;
+        ih->rptr += 16;
 }
 
 /**
@@ -266,9 +267,10 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
  *
  * Set the IH ring buffer rptr.
  */
-static void cik_ih_set_rptr(struct amdgpu_device *adev)
+static void cik_ih_set_rptr(struct amdgpu_device *adev,
+                            struct amdgpu_ih_ring *ih)
 {
-        WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+        WREG32(mmIH_RB_RPTR, ih->rptr);
 }
 
 static int cik_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 45795191de1f..189599b694e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -220,7 +220,7 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job,
                                   struct amdgpu_ib *ib,
-                                  bool ctx_switch)
+                                  uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 extra_bits = vmid & 0xf;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 9d3ea298e116..61024b9c7a4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -103,9 +103,9 @@ static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int cz_ih_irq_init(struct amdgpu_device *adev)
 {
-        int rb_bufsz;
+        struct amdgpu_ih_ring *ih = &adev->irq.ih;
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
-        u64 wptr_off;
+        int rb_bufsz;
 
         /* disable irqs */
         cz_ih_disable_interrupts(adev);
@@ -133,9 +133,8 @@ static int cz_ih_irq_init(struct amdgpu_device *adev)
         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
 
         /* set the writeback address whether it's enabled or not */
-        wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
-        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
 
         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
 
@@ -185,11 +184,12 @@ static void cz_ih_irq_disable(struct amdgpu_device *adev)
  * Used by cz_irq_process(VI).
  * Returns the value of the wptr.
  */
-static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
+static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
+                          struct amdgpu_ih_ring *ih)
 {
         u32 wptr, tmp;
 
-        wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+        wptr = le32_to_cpu(*ih->wptr_cpu);
 
         if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
                 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -198,13 +198,13 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
                  * this should allow us to catchup.
                  */
                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
-                        wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
-                adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+                        wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+                ih->rptr = (wptr + 16) & ih->ptr_mask;
                 tmp = RREG32(mmIH_RB_CNTL);
                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
                 WREG32(mmIH_RB_CNTL, tmp);
         }
-        return (wptr & adev->irq.ih.ptr_mask);
+        return (wptr & ih->ptr_mask);
 }
 
 /**
@@ -216,16 +216,17 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
  * position and also advance the position.
  */
 static void cz_ih_decode_iv(struct amdgpu_device *adev,
-                                 struct amdgpu_iv_entry *entry)
+                            struct amdgpu_ih_ring *ih,
+                            struct amdgpu_iv_entry *entry)
 {
         /* wptr/rptr are in bytes! */
-        u32 ring_index = adev->irq.ih.rptr >> 2;
+        u32 ring_index = ih->rptr >> 2;
         uint32_t dw[4];
 
-        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
-        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
-        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-        dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
+        dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
+        dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
+        dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
+        dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
 
         entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
         entry->src_id = dw[0] & 0xff;
@@ -235,7 +236,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
         entry->pasid = (dw[2] >> 16) & 0xffff;
 
         /* wptr/rptr are in bytes! */
-        adev->irq.ih.rptr += 16;
+        ih->rptr += 16;
 }
 
 /**
@@ -245,9 +246,10 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
  *
  * Set the IH ring buffer rptr.
  */
-static void cz_ih_set_rptr(struct amdgpu_device *adev)
+static void cz_ih_set_rptr(struct amdgpu_device *adev,
+                           struct amdgpu_ih_ring *ih)
 {
-        WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+        WREG32(mmIH_RB_RPTR, ih->rptr);
 }
 
 static int cz_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index fdace004544d..e4cc1d48eaab 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -167,19 +167,6 @@ static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 
         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
-        if (crtc->primary->fb) {
-                int r;
-                struct amdgpu_bo *abo;
-
-                abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
-                r = amdgpu_bo_reserve(abo, true);
-                if (unlikely(r))
-                        DRM_ERROR("failed to reserve abo before unpin\n");
-                else {
-                        amdgpu_bo_unpin(abo);
-                        amdgpu_bo_unreserve(abo);
-                }
-        }
 
         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
         amdgpu_crtc->encoder = NULL;
@@ -692,7 +679,9 @@ static int dce_virtual_pageflip(struct amdgpu_device *adev,
         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
         drm_crtc_vblank_put(&amdgpu_crtc->base);
-        schedule_work(&works->unpin_work);
+        amdgpu_bo_unref(&works->old_abo);
+        kfree(works->shared);
+        kfree(works);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 1dc3013ea1d5..305276c7e4bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1842,13 +1842,13 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job,
                                   struct amdgpu_ib *ib,
-                                  bool ctx_switch)
+                                  uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 header, control = 0;
 
         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
-        if (ctx_switch) {
+        if (flags & AMDGPU_HAVE_CTX_SWITCH) {
                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
                 amdgpu_ring_write(ring, 0);
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 3a9fb6018c16..7984292f9282 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2228,13 +2228,13 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 header, control = 0;
 
         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
-        if (ctx_switch) {
+        if (flags & AMDGPU_HAVE_CTX_SWITCH) {
                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
                 amdgpu_ring_write(ring, 0);
         }
@@ -2259,7 +2259,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                           struct amdgpu_job *job,
                                           struct amdgpu_ib *ib,
-                                          bool ctx_switch)
+                                          uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 381f593b0cda..a26747681ed6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4233,7 +4233,6 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         u32 tmp;
         u32 rb_bufsz;
         u64 rb_addr, rptr_addr, wptr_gpu_addr;
-        int r;
 
         /* Set the write pointer delay */
         WREG32(mmCP_RB_WPTR_DELAY, 0);
@@ -4278,9 +4277,8 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
         amdgpu_ring_clear_ring(ring);
         gfx_v8_0_cp_gfx_start(adev);
         ring->sched.ready = true;
-        r = amdgpu_ring_test_helper(ring);
 
-        return r;
+        return 0;
 }
 
 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
@@ -4369,10 +4367,9 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
         }
 
-        r = amdgpu_ring_test_helper(kiq_ring);
-        if (r)
-                DRM_ERROR("KCQ enable failed\n");
-        return r;
+        amdgpu_ring_commit(kiq_ring);
+
+        return 0;
 }
 
 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
@@ -4709,16 +4706,32 @@ static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
         if (r)
                 goto done;
 
-        /* Test KCQs - reversing the order of rings seems to fix ring test failure
-         * after GPU reset
-         */
-        for (i = adev->gfx.num_compute_rings - 1; i >= 0; i--) {
+done:
+        return r;
+}
+
+static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
+{
+        int r, i;
+        struct amdgpu_ring *ring;
+
+        /* collect all the ring_tests here, gfx, kiq, compute */
+        ring = &adev->gfx.gfx_ring[0];
+        r = amdgpu_ring_test_helper(ring);
+        if (r)
+                return r;
+
+        ring = &adev->gfx.kiq.ring;
+        r = amdgpu_ring_test_helper(ring);
+        if (r)
+                return r;
+
+        for (i = 0; i < adev->gfx.num_compute_rings; i++) {
                 ring = &adev->gfx.compute_ring[i];
-                r = amdgpu_ring_test_helper(ring);
+                amdgpu_ring_test_helper(ring);
         }
 
-done:
-        return r;
+        return 0;
 }
 
 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
@@ -4739,6 +4752,11 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
         r = gfx_v8_0_kcq_resume(adev);
         if (r)
                 return r;
+
+        r = gfx_v8_0_cp_test_all_rings(adev);
+        if (r)
+                return r;
+
         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
 
         return 0;
@@ -5086,6 +5104,8 @@ static int gfx_v8_0_post_soft_reset(void *handle)
             REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
                 gfx_v8_0_cp_gfx_resume(adev);
 
+        gfx_v8_0_cp_test_all_rings(adev);
+
         adev->gfx.rlc.funcs->start(adev);
 
         return 0;
@@ -6027,7 +6047,7 @@ static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 header, control = 0;
@@ -6059,7 +6079,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                           struct amdgpu_job *job,
                                           struct amdgpu_ib *ib,
-                                          bool ctx_switch)
+                                          uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7556716038d3..262ee3cf6f1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -113,7 +113,10 @@ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
@@ -135,10 +138,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000000, 0x00000800),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000000, 0x00000800),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
@@ -3587,6 +3587,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
 {
         uint32_t data, def;
 
+        amdgpu_gfx_rlc_enter_safe_mode(adev);
+
         /* It is disabled by HW by default */
         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
@@ -3651,6 +3653,8 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
                 }
         }
+
+        amdgpu_gfx_rlc_exit_safe_mode(adev);
 }
 
 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
@@ -3968,7 +3972,7 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 header, control = 0;
@@ -4001,7 +4005,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                           struct amdgpu_job *job,
                                           struct amdgpu_ib *ib,
-                                          bool ctx_switch)
+                                          uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 1ad7e6b8ed1d..34440672f938 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1471,8 +1471,9 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
                 gmc_v8_0_set_fault_enable_default(adev, false);
 
         if (printk_ratelimit()) {
-                struct amdgpu_task_info task_info = { 0 };
+                struct amdgpu_task_info task_info;
 
+                memset(&task_info, 0, sizeof(struct amdgpu_task_info));
                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 
                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index bacdaef77b6c..9c082f9aea1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -305,6 +305,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
                                 struct amdgpu_iv_entry *entry)
 {
         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
+        bool retry_fault = !!(entry->src_data[1] & 0x80);
         uint32_t status = 0;
         u64 addr;
 
@@ -320,13 +321,16 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
         }
 
         if (printk_ratelimit()) {
-                struct amdgpu_task_info task_info = { 0 };
+                struct amdgpu_task_info task_info;
 
+                memset(&task_info, 0, sizeof(struct amdgpu_task_info));
                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 
                 dev_err(adev->dev,
-                        "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
+                        "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
+                        "pasid:%u, for process %s pid %d thread %s pid %d)\n",
                         entry->vmid_src ? "mmhub" : "gfxhub",
+                        retry_fault ? "retry" : "no-retry",
                         entry->src_id, entry->ring_id, entry->vmid,
                         entry->pasid, task_info.process_name, task_info.tgid,
                         task_info.task_name, task_info.pid);
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index a3984d10b604..b1626e1d2f5d 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -103,9 +103,9 @@ static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int iceland_ih_irq_init(struct amdgpu_device *adev)
 {
+        struct amdgpu_ih_ring *ih = &adev->irq.ih;
         int rb_bufsz;
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
-        u64 wptr_off;
 
         /* disable irqs */
         iceland_ih_disable_interrupts(adev);
@@ -133,9 +133,8 @@ static int iceland_ih_irq_init(struct amdgpu_device *adev)
         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
 
         /* set the writeback address whether it's enabled or not */
-        wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
-        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
 
         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
 
@@ -185,11 +184,12 @@ static void iceland_ih_irq_disable(struct amdgpu_device *adev)
  * Used by cz_irq_process(VI).
  * Returns the value of the wptr.
  */
-static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
+static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
+                               struct amdgpu_ih_ring *ih)
 {
         u32 wptr, tmp;
 
-        wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+        wptr = le32_to_cpu(*ih->wptr_cpu);
 
         if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
                 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -198,13 +198,13 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
                  * this should allow us to catchup.
                  */
                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
-                        wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
-                adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+                         wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+                ih->rptr = (wptr + 16) & ih->ptr_mask;
                 tmp = RREG32(mmIH_RB_CNTL);
                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
                 WREG32(mmIH_RB_CNTL, tmp);
         }
-        return (wptr & adev->irq.ih.ptr_mask);
+        return (wptr & ih->ptr_mask);
 }
 
 /**
@@ -216,16 +216,17 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev)
  * position and also advance the position.
  */
 static void iceland_ih_decode_iv(struct amdgpu_device *adev,
+                                 struct amdgpu_ih_ring *ih,
                                  struct amdgpu_iv_entry *entry)
 {
         /* wptr/rptr are in bytes! */
-        u32 ring_index = adev->irq.ih.rptr >> 2;
+        u32 ring_index = ih->rptr >> 2;
         uint32_t dw[4];
 
-        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
-        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
-        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-        dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
+        dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
+        dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
+        dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
+        dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
 
         entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
         entry->src_id = dw[0] & 0xff;
@@ -235,7 +236,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
         entry->pasid = (dw[2] >> 16) & 0xffff;
 
         /* wptr/rptr are in bytes! */
-        adev->irq.ih.rptr += 16;
+        ih->rptr += 16;
 }
 
 /**
@@ -245,9 +246,10 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
  *
  * Set the IH ring buffer rptr.
  */
-static void iceland_ih_set_rptr(struct amdgpu_device *adev)
+static void iceland_ih_set_rptr(struct amdgpu_device *adev,
+                                struct amdgpu_ih_ring *ih)
 {
-        WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+        WREG32(mmIH_RB_RPTR, ih->rptr);
 }
 
 static int iceland_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 8cbb4655896a..b11a1c17a7f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -174,7 +174,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
                         return r;
                 }
                 /* Retrieve checksum from mailbox2 */
-                if (req == IDH_REQ_GPU_INIT_ACCESS) {
+                if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
                         adev->virt.fw_reserve.checksum_key =
                                 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
                                         mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index accdedd63c98..cc967dbfd631 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -27,13 +27,9 @@
 #include "nbio/nbio_6_1_default.h"
 #include "nbio/nbio_6_1_offset.h"
 #include "nbio/nbio_6_1_sh_mask.h"
+#include "nbio/nbio_6_1_smn.h"
 #include "vega10_enum.h"
 
-#define smnCPM_CONTROL                                                                                  0x11180460
-#define smnPCIE_CNTL2                                                                                   0x11180070
-#define smnPCIE_CONFIG_CNTL                                                                             0x11180044
-#define smnPCIE_CI_CNTL                                                                                 0x11180080
-
 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -72,7 +68,7 @@ static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
 }
 
 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
-                                  bool use_doorbell, int doorbell_index)
+                        bool use_doorbell, int doorbell_index, int doorbell_size)
 {
         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
@@ -81,7 +77,7 @@ static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instan
 
         if (use_doorbell) {
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
         } else
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index df34dc79d444..1cdb98ad2db3 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -27,13 +27,11 @@
 #include "nbio/nbio_7_0_default.h"
 #include "nbio/nbio_7_0_offset.h"
 #include "nbio/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_smn.h"
 #include "vega10_enum.h"
 
 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c
 
-#define smnCPM_CONTROL                                                                                  0x11180460
-#define smnPCIE_CNTL2                                                                                   0x11180070
-
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -69,7 +67,7 @@ static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
 }
 
 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
-                                          bool use_doorbell, int doorbell_index)
+                        bool use_doorbell, int doorbell_index, int doorbell_size)
 {
         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
@@ -78,7 +76,7 @@ static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instan
 
         if (use_doorbell) {
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
         } else
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a276dcd..e347b407bd03 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -26,13 +26,10 @@
 
 #include "nbio/nbio_7_4_offset.h"
 #include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_7_4_0_smn.h"
 
 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a21c
 
-#define smnCPM_CONTROL                                                                                  0x11180460
-#define smnPCIE_CNTL2                                                                                   0x11180070
-#define smnPCIE_CI_CNTL                                                                                 0x11180080
-
 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
 {
     u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
@@ -68,7 +65,7 @@ static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
 }
 
 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
-                                          bool use_doorbell, int doorbell_index)
+                        bool use_doorbell, int doorbell_index, int doorbell_size)
 {
         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
@@ -77,7 +74,7 @@ static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instan
 
         if (use_doorbell) {
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
         } else
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index 0de00fbe9233..f3a7d207af07 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -191,7 +191,7 @@ enum psp_gfx_fw_type
     GFX_FW_TYPE_MMSCH       = 19,
     GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM        = 20,
     GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM        = 21,
-    GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL           = 22,
+    GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL       = 22,
     GFX_FW_TYPE_UVD1        = 23,
     GFX_FW_TYPE_MAX         = 24
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index d78b4306a36f..77c2bc344dfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -38,75 +38,6 @@ MODULE_FIRMWARE("amdgpu/raven_asd.bin");
 MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
 MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
 
-static int
-psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
-{
-        switch(ucode->ucode_id) {
-        case AMDGPU_UCODE_ID_SDMA0:
-                *type = GFX_FW_TYPE_SDMA0;
-                break;
-        case AMDGPU_UCODE_ID_SDMA1:
-                *type = GFX_FW_TYPE_SDMA1;
-                break;
-        case AMDGPU_UCODE_ID_CP_CE:
-                *type = GFX_FW_TYPE_CP_CE;
-                break;
-        case AMDGPU_UCODE_ID_CP_PFP:
-                *type = GFX_FW_TYPE_CP_PFP;
-                break;
-        case AMDGPU_UCODE_ID_CP_ME:
-                *type = GFX_FW_TYPE_CP_ME;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC1:
-                *type = GFX_FW_TYPE_CP_MEC;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC1_JT:
-                *type = GFX_FW_TYPE_CP_MEC_ME1;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC2:
-                *type = GFX_FW_TYPE_CP_MEC;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC2_JT:
-                *type = GFX_FW_TYPE_CP_MEC_ME2;
-                break;
-        case AMDGPU_UCODE_ID_RLC_G:
-                *type = GFX_FW_TYPE_RLC_G;
-                break;
-        case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
-                *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
-                break;
-        case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
-                *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
-                break;
-        case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
-                *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
-                break;
-        case AMDGPU_UCODE_ID_SMC:
-                *type = GFX_FW_TYPE_SMU;
-                break;
-        case AMDGPU_UCODE_ID_UVD:
-                *type = GFX_FW_TYPE_UVD;
-                break;
-        case AMDGPU_UCODE_ID_VCE:
-                *type = GFX_FW_TYPE_VCE;
-                break;
-        case AMDGPU_UCODE_ID_VCN:
-                *type = GFX_FW_TYPE_VCN;
-                break;
-        case AMDGPU_UCODE_ID_DMCU_ERAM:
-                *type = GFX_FW_TYPE_DMCU_ERAM;
-                break;
-        case AMDGPU_UCODE_ID_DMCU_INTV:
-                *type = GFX_FW_TYPE_DMCU_ISR;
-                break;
-        case AMDGPU_UCODE_ID_MAXIMUM:
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
 static int psp_v10_0_init_microcode(struct psp_context *psp)
 {
         struct amdgpu_device *adev = psp->adev;
@@ -158,26 +89,6 @@ out:
         return err;
 }
 
-static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
-                                  struct psp_gfx_cmd_resp *cmd)
-{
-        int ret;
-        uint64_t fw_mem_mc_addr = ucode->mc_addr;
-
-        memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
-
-        cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
-        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
-        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
-        cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
-
-        ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
-        if (ret)
-                DRM_ERROR("Unknown firmware type\n");
-
-        return ret;
-}
-
 static int psp_v10_0_ring_init(struct psp_context *psp,
                                enum psp_ring_type ring_type)
 {
@@ -454,7 +365,6 @@ static int psp_v10_0_mode1_reset(struct psp_context *psp)
 
 static const struct psp_funcs psp_v10_0_funcs = {
         .init_microcode = psp_v10_0_init_microcode,
-        .prep_cmd_buf = psp_v10_0_prep_cmd_buf,
         .ring_init = psp_v10_0_ring_init,
         .ring_create = psp_v10_0_ring_create,
         .ring_stop = psp_v10_0_ring_stop,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0c6e7f9b143f..f71384be1f97 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -40,60 +40,6 @@ MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
 /* address block */
 #define smnMP1_FIRMWARE_FLAGS           0x3010024
 
-static int
-psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
-{
-        switch (ucode->ucode_id) {
-        case AMDGPU_UCODE_ID_SDMA0:
-                *type = GFX_FW_TYPE_SDMA0;
-                break;
-        case AMDGPU_UCODE_ID_SDMA1:
-                *type = GFX_FW_TYPE_SDMA1;
-                break;
-        case AMDGPU_UCODE_ID_CP_CE:
-                *type = GFX_FW_TYPE_CP_CE;
-                break;
-        case AMDGPU_UCODE_ID_CP_PFP:
-                *type = GFX_FW_TYPE_CP_PFP;
-                break;
-        case AMDGPU_UCODE_ID_CP_ME:
-                *type = GFX_FW_TYPE_CP_ME;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC1:
-                *type = GFX_FW_TYPE_CP_MEC;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC1_JT:
-                *type = GFX_FW_TYPE_CP_MEC_ME1;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC2:
-                *type = GFX_FW_TYPE_CP_MEC;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC2_JT:
-                *type = GFX_FW_TYPE_CP_MEC_ME2;
-                break;
-        case AMDGPU_UCODE_ID_RLC_G:
-                *type = GFX_FW_TYPE_RLC_G;
-                break;
-        case AMDGPU_UCODE_ID_SMC:
-                *type = GFX_FW_TYPE_SMU;
-                break;
-        case AMDGPU_UCODE_ID_UVD:
-                *type = GFX_FW_TYPE_UVD;
-                break;
-        case AMDGPU_UCODE_ID_VCE:
-                *type = GFX_FW_TYPE_VCE;
-                break;
-        case AMDGPU_UCODE_ID_UVD1:
-                *type = GFX_FW_TYPE_UVD1;
-                break;
-        case AMDGPU_UCODE_ID_MAXIMUM:
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
 static int psp_v11_0_init_microcode(struct psp_context *psp)
 {
         struct amdgpu_device *adev = psp->adev;
@@ -267,26 +213,6 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
         return ret;
 }
 
-static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
-                                 struct psp_gfx_cmd_resp *cmd)
-{
-        int ret;
-        uint64_t fw_mem_mc_addr = ucode->mc_addr;
-
-        memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
-
-        cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
-        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
-        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
-        cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
-
-        ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
-        if (ret)
-                DRM_ERROR("Unknown firmware type\n");
-
-        return ret;
-}
-
 static int psp_v11_0_ring_init(struct psp_context *psp,
                               enum psp_ring_type ring_type)
 {
@@ -753,7 +679,6 @@ static const struct psp_funcs psp_v11_0_funcs = {
         .init_microcode = psp_v11_0_init_microcode,
         .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
         .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
-        .prep_cmd_buf = psp_v11_0_prep_cmd_buf,
         .ring_init = psp_v11_0_ring_init,
         .ring_create = psp_v11_0_ring_create,
         .ring_stop = psp_v11_0_ring_stop,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 79694ff16969..c63de945c021 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -47,57 +47,6 @@ MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
 
 static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554};
 
-static int
-psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
-{
-        switch(ucode->ucode_id) {
-        case AMDGPU_UCODE_ID_SDMA0:
-                *type = GFX_FW_TYPE_SDMA0;
-                break;
-        case AMDGPU_UCODE_ID_SDMA1:
-                *type = GFX_FW_TYPE_SDMA1;
-                break;
-        case AMDGPU_UCODE_ID_CP_CE:
-                *type = GFX_FW_TYPE_CP_CE;
-                break;
-        case AMDGPU_UCODE_ID_CP_PFP:
-                *type = GFX_FW_TYPE_CP_PFP;
-                break;
-        case AMDGPU_UCODE_ID_CP_ME:
-                *type = GFX_FW_TYPE_CP_ME;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC1:
-                *type = GFX_FW_TYPE_CP_MEC;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC1_JT:
-                *type = GFX_FW_TYPE_CP_MEC_ME1;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC2:
-                *type = GFX_FW_TYPE_CP_MEC;
-                break;
-        case AMDGPU_UCODE_ID_CP_MEC2_JT:
-                *type = GFX_FW_TYPE_CP_MEC_ME2;
-                break;
-        case AMDGPU_UCODE_ID_RLC_G:
-                *type = GFX_FW_TYPE_RLC_G;
-                break;
-        case AMDGPU_UCODE_ID_SMC:
-                *type = GFX_FW_TYPE_SMU;
-                break;
-        case AMDGPU_UCODE_ID_UVD:
-                *type = GFX_FW_TYPE_UVD;
-                break;
-        case AMDGPU_UCODE_ID_VCE:
-                *type = GFX_FW_TYPE_VCE;
-                break;
-        case AMDGPU_UCODE_ID_MAXIMUM:
-        default:
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
 static int psp_v3_1_init_microcode(struct psp_context *psp)
 {
         struct amdgpu_device *adev = psp->adev;
@@ -277,26 +226,6 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
         return ret;
 }
 
-static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
-                                 struct psp_gfx_cmd_resp *cmd)
-{
-        int ret;
-        uint64_t fw_mem_mc_addr = ucode->mc_addr;
-
-        memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
-
-        cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
-        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
-        cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
-        cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
-
-        ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
-        if (ret)
-                DRM_ERROR("Unknown firmware type\n");
-
-        return ret;
-}
-
 static int psp_v3_1_ring_init(struct psp_context *psp,
                               enum psp_ring_type ring_type)
 {
@@ -615,7 +544,6 @@ static const struct psp_funcs psp_v3_1_funcs = {
         .init_microcode = psp_v3_1_init_microcode,
         .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
         .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
-        .prep_cmd_buf = psp_v3_1_prep_cmd_buf,
         .ring_init = psp_v3_1_ring_init,
         .ring_create = psp_v3_1_ring_create,
         .ring_stop = psp_v3_1_ring_stop,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 9f3cb2aec7c2..cca3552b36ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -247,7 +247,7 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
                                    struct amdgpu_job *job,
                                    struct amdgpu_ib *ib,
-                                   bool ctx_switch)
+                                   uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 1bccc5fe2d9d..0ce8331baeb2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -421,7 +421,7 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
                                    struct amdgpu_job *job,
                                    struct amdgpu_ib *ib,
-                                   bool ctx_switch)
+                                   uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
@@ -1145,8 +1145,7 @@ static int sdma_v3_0_sw_init(void *handle)
                 ring->ring_obj = NULL;
                 if (!amdgpu_sriov_vf(adev)) {
                         ring->use_doorbell = true;
-                        ring->doorbell_index = (i == 0) ?
-                                adev->doorbell_index.sdma_engine0 : adev->doorbell_index.sdma_engine1;
+                        ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
                 } else {
                         ring->use_pollmem = true;
                 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fd0bfe140ee0..127b85983e8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -78,7 +78,6 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = {
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
-        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
@@ -96,6 +95,7 @@ static const struct soc15_reg_golden golden_settings_sdma_4[] = {
 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
 };
@@ -103,6 +103,7 @@ static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
 };
@@ -499,7 +500,7 @@ static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
                                    struct amdgpu_job *job,
                                    struct amdgpu_ib *ib,
-                                   bool ctx_switch)
+                                   uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
@@ -833,8 +834,6 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
                                         OFFSET, ring->doorbell_index);
         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
         WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
-        adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
-                                              ring->doorbell_index);
 
         sdma_v4_0_ring_set_wptr(ring);
 
@@ -1521,9 +1520,7 @@ static int sdma_v4_0_sw_init(void *handle)
                                 ring->use_doorbell?"true":"false");
 
                 /* doorbell size is 2 dwords, get DWORD offset */
-                ring->doorbell_index = (i == 0) ?
-                        (adev->doorbell_index.sdma_engine0 << 1)
-                        : (adev->doorbell_index.sdma_engine1 << 1);
+                ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
 
                 sprintf(ring->name, "sdma%d", i);
                 r = amdgpu_ring_init(adev, ring, 1024,
@@ -1542,9 +1539,7 @@ static int sdma_v4_0_sw_init(void *handle)
                         /* paging queue use same doorbell index/routing as gfx queue
                          * with 0x400 (4096 dwords) offset on second doorbell page
                          */
-                        ring->doorbell_index = (i == 0) ?
-                                (adev->doorbell_index.sdma_engine0 << 1)
-                                : (adev->doorbell_index.sdma_engine1 << 1);
+                        ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
                         ring->doorbell_index += 0x400;
 
                         sprintf(ring->name, "page%d", i);
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index f8408f88cd37..79c1a9bbcc21 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -47,6 +47,7 @@
 #include "dce/dce_6_0_d.h"
 #include "uvd/uvd_4_0_d.h"
 #include "bif/bif_3_0_d.h"
+#include "bif/bif_3_0_sh_mask.h"
 
 static const u32 tahiti_golden_registers[] =
 {
@@ -1258,6 +1259,11 @@ static bool si_need_full_reset(struct amdgpu_device *adev)
         return true;
 }
 
+static bool si_need_reset_on_init(struct amdgpu_device *adev)
+{
+        return false;
+}
+
 static int si_get_pcie_lanes(struct amdgpu_device *adev)
 {
         u32 link_width_cntl;
@@ -1323,6 +1329,52 @@ static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)
         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 }
 
+static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+                              uint64_t *count1)
+{
+        uint32_t perfctr = 0;
+        uint64_t cnt0_of, cnt1_of;
+        int tmp;
+
+        /* This reports 0 on APUs, so return to avoid writing/reading registers
+         * that may or may not be different from their GPU counterparts
+         */
+        if (adev->flags & AMD_IS_APU)
+                return;
+
+        /* Set the 2 events that we wish to watch, defined above */
+        /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+
+        /* Write to enable desired perf counters */
+        WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
+        /* Zero out and enable the perf counters
+         * Write 0x5:
+         * Bit 0 = Start all counters(1)
+         * Bit 2 = Global counter reset enable(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
+
+        msleep(1000);
+
+        /* Load the shadow and disable the perf counters
+         * Write 0x2:
+         * Bit 0 = Stop counters(0)
+         * Bit 1 = Load the shadow counters(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
+
+        /* Read register values to get any >32bit overflow */
+        tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
+        cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
+        cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
+
+        /* Get the values and add the overflow */
+        *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
+        *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
+}
+
 static const struct amdgpu_asic_funcs si_asic_funcs =
 {
         .read_disabled_bios = &si_read_disabled_bios,
@@ -1339,6 +1391,8 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
         .flush_hdp = &si_flush_hdp,
         .invalidate_hdp = &si_invalidate_hdp,
         .need_full_reset = &si_need_full_reset,
+        .get_pcie_usage = &si_get_pcie_usage,
+        .need_reset_on_init = &si_need_reset_on_init,
 };
 
 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index b6e473134e19..f15f196684ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -63,7 +63,7 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)
 static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
                                 struct amdgpu_job *job,
                                 struct amdgpu_ib *ib,
-                                bool ctx_switch)
+                                uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 2938fb9f17cc..8c50c9cab455 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -57,9 +57,9 @@ static void si_ih_disable_interrupts(struct amdgpu_device *adev)
 
 static int si_ih_irq_init(struct amdgpu_device *adev)
 {
+        struct amdgpu_ih_ring *ih = &adev->irq.ih;
         int rb_bufsz;
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
-        u64 wptr_off;
 
         si_ih_disable_interrupts(adev);
         WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
@@ -76,9 +76,8 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
                      (rb_bufsz << 1) |
                      IH_WPTR_WRITEBACK_ENABLE;
 
-        wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
-        WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-        WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+        WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+        WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
         WREG32(IH_RB_CNTL, ih_rb_cntl);
         WREG32(IH_RB_RPTR, 0);
         WREG32(IH_RB_WPTR, 0);
@@ -100,34 +99,36 @@ static void si_ih_irq_disable(struct amdgpu_device *adev)
         mdelay(1);
 }
 
-static u32 si_ih_get_wptr(struct amdgpu_device *adev)
+static u32 si_ih_get_wptr(struct amdgpu_device *adev,
+                          struct amdgpu_ih_ring *ih)
 {
         u32 wptr, tmp;
 
-        wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+        wptr = le32_to_cpu(*ih->wptr_cpu);
 
         if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
                 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
-                        wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
-                adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+                        wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+                ih->rptr = (wptr + 16) & ih->ptr_mask;
                 tmp = RREG32(IH_RB_CNTL);
                 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
                 WREG32(IH_RB_CNTL, tmp);
         }
-        return (wptr & adev->irq.ih.ptr_mask);
+        return (wptr & ih->ptr_mask);
 }
 
 static void si_ih_decode_iv(struct amdgpu_device *adev,
-                             struct amdgpu_iv_entry *entry)
+                            struct amdgpu_ih_ring *ih,
+                            struct amdgpu_iv_entry *entry)
 {
-        u32 ring_index = adev->irq.ih.rptr >> 2;
+        u32 ring_index = ih->rptr >> 2;
         uint32_t dw[4];
 
-        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
-        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
-        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-        dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
+        dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
+        dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
+        dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
+        dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
 
         entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
         entry->src_id = dw[0] & 0xff;
@@ -135,12 +136,13 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
         entry->ring_id = dw[2] & 0xff;
         entry->vmid = (dw[2] >> 8) & 0xff;
 
-        adev->irq.ih.rptr += 16;
+        ih->rptr += 16;
 }
 
-static void si_ih_set_rptr(struct amdgpu_device *adev)
+static void si_ih_set_rptr(struct amdgpu_device *adev,
+                           struct amdgpu_ih_ring *ih)
 {
-        WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
+        WREG32(IH_RB_RPTR, ih->rptr);
 }
 
 static int si_ih_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 8849b74078d6..62d272b4be19 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -43,6 +43,10 @@
 #include "hdp/hdp_4_0_sh_mask.h"
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
+#include "nbio/nbio_7_0_default.h"
+#include "nbio/nbio_7_0_sh_mask.h"
+#include "nbio/nbio_7_0_smn.h"
+#include "mp/mp_9_0_offset.h"
 
 #include "soc15.h"
 #include "soc15_common.h"
@@ -385,14 +389,13 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
 
 }
 
-
-static int soc15_asic_reset(struct amdgpu_device *adev)
+static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
 {
         u32 i;
 
         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 
-        dev_info(adev->dev, "GPU reset\n");
+        dev_info(adev->dev, "GPU mode1 reset\n");
 
         /* disable BM */
         pci_clear_master(adev->pdev);
@@ -417,6 +420,63 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
         return 0;
 }
 
+static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
+{
+        void *pp_handle = adev->powerplay.pp_handle;
+        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+        if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
+                *cap = false;
+                return -ENOENT;
+        }
+
+        return pp_funcs->get_asic_baco_capability(pp_handle, cap);
+}
+
+static int soc15_asic_baco_reset(struct amdgpu_device *adev)
+{
+        void *pp_handle = adev->powerplay.pp_handle;
+        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+        if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state)
+                return -ENOENT;
+
+        /* enter BACO state */
+        if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+                return -EIO;
+
+        /* exit BACO state */
+        if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+                return -EIO;
+
+        dev_info(adev->dev, "GPU BACO reset\n");
+
+        return 0;
+}
+
+static int soc15_asic_reset(struct amdgpu_device *adev)
+{
+        int ret;
+        bool baco_reset;
+
+        switch (adev->asic_type) {
+        case CHIP_VEGA10:
+        case CHIP_VEGA20:
+                soc15_asic_get_baco_capability(adev, &baco_reset);
+                break;
+        default:
+                baco_reset = false;
+                break;
+        }
+
+        if (baco_reset)
+                ret = soc15_asic_baco_reset(adev);
+        else
+                ret = soc15_asic_mode1_reset(adev);
+
+        return ret;
+}
+
 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
                         u32 cntl_reg, u32 status_reg)
 {
@@ -535,10 +595,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
-                if (adev->asic_type == CHIP_VEGA20)
-                        amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
-                else
-                        amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+                if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+                        if (adev->asic_type == CHIP_VEGA20)
+                                amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+                        else
+                                amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+                }
                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
                 if (!amdgpu_sriov_vf(adev))
@@ -560,7 +622,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
-                amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
+                if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+                        amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
@@ -601,6 +664,68 @@ static bool soc15_need_full_reset(struct amdgpu_device *adev)
         /* change this when we implement soft reset */
         return true;
 }
+static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+                                 uint64_t *count1)
+{
+        uint32_t perfctr = 0;
+        uint64_t cnt0_of, cnt1_of;
+        int tmp;
+
+        /* This reports 0 on APUs, so return to avoid writing/reading registers
+         * that may or may not be different from their GPU counterparts
+         */
+         if (adev->flags & AMD_IS_APU)
+                 return;
+
+        /* Set the 2 events that we wish to watch, defined above */
+        /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+
+        /* Write to enable desired perf counters */
+        WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
+        /* Zero out and enable the perf counters
+         * Write 0x5:
+         * Bit 0 = Start all counters(1)
+         * Bit 2 = Global counter reset enable(1)
+         */
+        WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
+
+        msleep(1000);
+
+        /* Load the shadow and disable the perf counters
+         * Write 0x2:
+         * Bit 0 = Stop counters(0)
+         * Bit 1 = Load the shadow counters(1)
+         */
+        WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
+
+        /* Read register values to get any >32bit overflow */
+        tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
+        cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
+        cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
+
+        /* Get the values and add the overflow */
+        *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
+        *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
+}
+
+static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
+{
+        u32 sol_reg;
+
+        if (adev->flags & AMD_IS_APU)
+                return false;
+
+        /* Check sOS sign of life register to confirm sys driver and sOS
+         * are already been loaded.
+         */
+        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+        if (sol_reg)
+                return true;
+
+        return false;
+}
 
 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 {
@@ -617,6 +742,8 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
         .invalidate_hdp = &soc15_invalidate_hdp,
         .need_full_reset = &soc15_need_full_reset,
         .init_doorbell_index = &vega10_doorbell_index_init,
+        .get_pcie_usage = &soc15_get_pcie_usage,
+        .need_reset_on_init = &soc15_need_reset_on_init,
 };
 
 static const struct amdgpu_asic_funcs vega20_asic_funcs =
@@ -634,6 +761,8 @@ static const struct amdgpu_asic_funcs vega20_asic_funcs =
         .invalidate_hdp = &soc15_invalidate_hdp,
         .need_full_reset = &soc15_need_full_reset,
         .init_doorbell_index = &vega20_doorbell_index_init,
+        .get_pcie_usage = &soc15_get_pcie_usage,
+        .need_reset_on_init = &soc15_need_reset_on_init,
 };
 
 static int soc15_common_early_init(void *handle)
@@ -840,6 +969,22 @@ static int soc15_common_sw_fini(void *handle)
         return 0;
 }
 
+static void soc15_doorbell_range_init(struct amdgpu_device *adev)
+{
+        int i;
+        struct amdgpu_ring *ring;
+
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
+                adev->nbio_funcs->sdma_doorbell_range(adev, i,
+                        ring->use_doorbell, ring->doorbell_index,
+                        adev->doorbell_index.sdma_doorbell_range);
+        }
+
+        adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
+                                                adev->irq.ih.doorbell_index);
+}
+
 static int soc15_common_hw_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -852,6 +997,12 @@ static int soc15_common_hw_init(void *handle)
         adev->nbio_funcs->init_registers(adev);
         /* enable the doorbell aperture */
         soc15_enable_doorbell_aperture(adev, true);
+        /* HW doorbell routing policy: doorbell writing not
+         * in SDMA/IH/MM/ACV range will be routed to CP. So
+         * we need to init SDMA/IH/MM/ACV doorbell range prior
+         * to CP ip block init and ring test.
+         */
+        soc15_doorbell_range_init(adev);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index 15da06ddeb75..a20b711a6756 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -99,9 +99,9 @@ static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int tonga_ih_irq_init(struct amdgpu_device *adev)
 {
-        int rb_bufsz;
         u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
-        u64 wptr_off;
+        struct amdgpu_ih_ring *ih = &adev->irq.ih;
+        int rb_bufsz;
 
         /* disable irqs */
         tonga_ih_disable_interrupts(adev);
@@ -118,10 +118,7 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)
         WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
 
         /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
-        if (adev->irq.ih.use_bus_addr)
-                WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
-        else
-                WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
+        WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8);
 
         rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
         ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
@@ -136,12 +133,8 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)
         WREG32(mmIH_RB_CNTL, ih_rb_cntl);
 
         /* set the writeback address whether it's enabled or not */
-        if (adev->irq.ih.use_bus_addr)
-                wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
-        else
-                wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
-        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
+        WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
+        WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);
 
         /* set rptr, wptr to 0 */
         WREG32(mmIH_RB_RPTR, 0);
@@ -193,14 +186,12 @@ static void tonga_ih_irq_disable(struct amdgpu_device *adev)
  * Used by cz_irq_process(VI).
  * Returns the value of the wptr.
  */
-static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
+static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
+                             struct amdgpu_ih_ring *ih)
 {
         u32 wptr, tmp;
 
-        if (adev->irq.ih.use_bus_addr)
-                wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
-        else
-                wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
+        wptr = le32_to_cpu(*ih->wptr_cpu);
 
         if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
                 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
@@ -209,13 +200,13 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
                  * this should allow us to catchup.
                  */
                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
-                        wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
-                adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
+                         wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);
+                ih->rptr = (wptr + 16) & ih->ptr_mask;
                 tmp = RREG32(mmIH_RB_CNTL);
                 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
                 WREG32(mmIH_RB_CNTL, tmp);
         }
-        return (wptr & adev->irq.ih.ptr_mask);
+        return (wptr & ih->ptr_mask);
 }
 
 /**
@@ -227,16 +218,17 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)
  * position and also advance the position.
  */
 static void tonga_ih_decode_iv(struct amdgpu_device *adev,
-                                 struct amdgpu_iv_entry *entry)
+                               struct amdgpu_ih_ring *ih,
+                               struct amdgpu_iv_entry *entry)
 {
         /* wptr/rptr are in bytes! */
-        u32 ring_index = adev->irq.ih.rptr >> 2;
+        u32 ring_index = ih->rptr >> 2;
         uint32_t dw[4];
 
-        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
-        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
-        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-        dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
+        dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
+        dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
+        dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
+        dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
 
         entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
         entry->src_id = dw[0] & 0xff;
@@ -246,7 +238,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
         entry->pasid = (dw[2] >> 16) & 0xffff;
 
         /* wptr/rptr are in bytes! */
-        adev->irq.ih.rptr += 16;
+        ih->rptr += 16;
 }
 
 /**
@@ -256,17 +248,15 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
  *
  * Set the IH ring buffer rptr.
  */
-static void tonga_ih_set_rptr(struct amdgpu_device *adev)
+static void tonga_ih_set_rptr(struct amdgpu_device *adev,
+                              struct amdgpu_ih_ring *ih)
 {
-        if (adev->irq.ih.use_doorbell) {
+        if (ih->use_doorbell) {
                 /* XXX check if swapping is necessary on BE */
-                if (adev->irq.ih.use_bus_addr)
-                        adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
-                else
-                        adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
-                WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
+                *ih->rptr_cpu = ih->rptr;
+                WDOORBELL32(ih->doorbell_index, ih->rptr);
         } else {
-                WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
+                WREG32(mmIH_RB_RPTR, ih->rptr);
         }
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index d69c8f6daaf8..c4fb58667fd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -511,7 +511,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job,
                                   struct amdgpu_ib *ib,
-                                  bool ctx_switch)
+                                  uint32_t flags)
 {
         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
         amdgpu_ring_write(ring, ib->gpu_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index ee8cd06ddc38..52bd8a654734 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -526,7 +526,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job,
                                   struct amdgpu_ib *ib,
-                                  bool ctx_switch)
+                                  uint32_t flags)
 {
         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index d4f4a66f8324..c9edddf9f88a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -977,7 +977,7 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job,
                                   struct amdgpu_ib *ib,
-                                  bool ctx_switch)
+                                  uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
@@ -1003,7 +1003,7 @@ static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index aef924026a28..dc461df48da0 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1272,7 +1272,7 @@ static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job,
                                   struct amdgpu_ib *ib,
-                                  bool ctx_switch)
+                                  uint32_t flags)
 {
         struct amdgpu_device *adev = ring->adev;
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
@@ -1303,7 +1303,7 @@ static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 2668effadd27..6ec65cf11112 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -834,7 +834,7 @@ out:
 static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_job *job,
                                   struct amdgpu_ib *ib,
-                                  bool ctx_switch)
+                                  uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 9fb34b7d8e03..aadc3e66ebd7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -947,7 +947,7 @@ static int vce_v4_0_set_powergating_state(void *handle,
 #endif
 
 static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
-                                        struct amdgpu_ib *ib, bool ctx_switch)
+                                        struct amdgpu_ib *ib, uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 89bb2fef90eb..3dbc51f9d3b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1371,7 +1371,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64
 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         struct amdgpu_device *adev = ring->adev;
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
@@ -1531,7 +1531,7 @@ static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 
@@ -1736,7 +1736,7 @@ static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u6
 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
                                         struct amdgpu_job *job,
                                         struct amdgpu_ib *ib,
-                                        bool ctx_switch)
+                                        uint32_t flags)
 {
         struct amdgpu_device *adev = ring->adev;
         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 2c250b01a903..6d1f804277f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -50,6 +50,22 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
         WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
         adev->irq.ih.enabled = true;
+
+        if (adev->irq.ih1.ring_size) {
+                ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+                                           RB_ENABLE, 1);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+                adev->irq.ih1.enabled = true;
+        }
+
+        if (adev->irq.ih2.ring_size) {
+                ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+                                           RB_ENABLE, 1);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+                adev->irq.ih2.enabled = true;
+        }
 }
 
 /**
@@ -71,6 +87,53 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
         WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
         adev->irq.ih.enabled = false;
         adev->irq.ih.rptr = 0;
+
+        if (adev->irq.ih1.ring_size) {
+                ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
+                                           RB_ENABLE, 0);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+                /* set rptr, wptr to 0 */
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+                adev->irq.ih1.enabled = false;
+                adev->irq.ih1.rptr = 0;
+        }
+
+        if (adev->irq.ih2.ring_size) {
+                ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
+                                           RB_ENABLE, 0);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+                /* set rptr, wptr to 0 */
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+                adev->irq.ih2.enabled = false;
+                adev->irq.ih2.rptr = 0;
+        }
+}
+
+static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
+{
+        int rb_bufsz = order_base_2(ih->ring_size / 4);
+
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+                                   MC_SPACE, ih->use_bus_addr ? 1 : 4);
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+                                   WPTR_OVERFLOW_CLEAR, 1);
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+                                   WPTR_OVERFLOW_ENABLE, 1);
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
+        /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
+         * value is written to memory
+         */
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
+                                   WPTR_WRITEBACK_ENABLE, 1);
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
+
+        return ih_rb_cntl;
 }
 
 /**
@@ -86,50 +149,32 @@ static void vega10_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int vega10_ih_irq_init(struct amdgpu_device *adev)
 {
+        struct amdgpu_ih_ring *ih;
         int ret = 0;
-        int rb_bufsz;
         u32 ih_rb_cntl, ih_doorbell_rtpr;
         u32 tmp;
-        u64 wptr_off;
 
         /* disable irqs */
         vega10_ih_disable_interrupts(adev);
 
         adev->nbio_funcs->ih_control(adev);
 
-        ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
+        ih = &adev->irq.ih;
         /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
-        if (adev->irq.ih.use_bus_addr) {
-                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);
-                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, ((u64)adev->irq.ih.rb_dma_addr >> 40) & 0xff);
-                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1);
-        } else {
-                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
-                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (adev->irq.ih.gpu_addr >> 40) & 0xff);
-                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4);
-        }
-        rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
-        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
-        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
-        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
-        /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
-        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
-        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
-        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
-        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
-
-        if (adev->irq.msi_enabled)
-                ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1);
+        WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);
+        WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
 
+        ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
+        ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+        ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
+                                   !!adev->irq.msi_enabled);
         WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
 
         /* set the writeback address whether it's enabled or not */
-        if (adev->irq.ih.use_bus_addr)
-                wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);
-        else
-                wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
-        WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
-        WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);
+        WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
+                     lower_32_bits(ih->wptr_addr));
+        WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,
+                     upper_32_bits(ih->wptr_addr) & 0xFFFF);
 
         /* set rptr, wptr to 0 */
         WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);
@@ -137,17 +182,48 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev)
 
         ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR);
         if (adev->irq.ih.use_doorbell) {
-                ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
-                                                 OFFSET, adev->irq.ih.doorbell_index);
-                ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
+                ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+                                                 IH_DOORBELL_RPTR, OFFSET,
+                                                 adev->irq.ih.doorbell_index);
+                ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+                                                 IH_DOORBELL_RPTR,
                                                  ENABLE, 1);
         } else {
-                ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR,
+                ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
+                                                 IH_DOORBELL_RPTR,
                                                  ENABLE, 0);
         }
         WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);
-        adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
-                                            adev->irq.ih.doorbell_index);
+
+        ih = &adev->irq.ih1;
+        if (ih->ring_size) {
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,
+                             (ih->gpu_addr >> 40) & 0xff);
+
+                ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+                ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+
+                /* set rptr, wptr to 0 */
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
+        }
+
+        ih = &adev->irq.ih2;
+        if (ih->ring_size) {
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,
+                             (ih->gpu_addr >> 40) & 0xff);
+
+                ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+                ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+
+                /* set rptr, wptr to 0 */
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
+        }
 
         tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
         tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
@@ -191,32 +267,58 @@ static void vega10_ih_irq_disable(struct amdgpu_device *adev)
  * ring buffer overflow and deal with it.
  * Returns the value of the wptr.
  */
-static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
+static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
+                              struct amdgpu_ih_ring *ih)
 {
-        u32 wptr, tmp;
+        u32 wptr, reg, tmp;
 
-        if (adev->irq.ih.use_bus_addr)
-                wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);
+        wptr = le32_to_cpu(*ih->wptr_cpu);
+
+        if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
+                goto out;
+
+        /* Double check that the overflow wasn't already cleared. */
+
+        if (ih == &adev->irq.ih)
+                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
+        else if (ih == &adev->irq.ih1)
+                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
+        else if (ih == &adev->irq.ih2)
+                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
         else
-                wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
-
-        if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
-                wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
-
-                /* When a ring buffer overflow happen start parsing interrupt
-                 * from the last not overwritten vector (wptr + 32). Hopefully
-                 * this should allow us to catchup.
-                 */
-                tmp = (wptr + 32) & adev->irq.ih.ptr_mask;
-                dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
-                        wptr, adev->irq.ih.rptr, tmp);
-                adev->irq.ih.rptr = tmp;
-
-                tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL));
-                tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
-                WREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL), tmp);
-        }
-        return (wptr & adev->irq.ih.ptr_mask);
+                BUG();
+
+        wptr = RREG32_NO_KIQ(reg);
+        if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
+                goto out;
+
+        wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
+
+        /* When a ring buffer overflow happen start parsing interrupt
+         * from the last not overwritten vector (wptr + 32). Hopefully
+         * this should allow us to catchup.
+         */
+        tmp = (wptr + 32) & ih->ptr_mask;
+        dev_warn(adev->dev, "IH ring buffer overflow "
+                 "(0x%08X, 0x%08X, 0x%08X)\n",
+                 wptr, ih->rptr, tmp);
+        ih->rptr = tmp;
+
+        if (ih == &adev->irq.ih)
+                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
+        else if (ih == &adev->irq.ih1)
+                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
+        else if (ih == &adev->irq.ih2)
+                reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
+        else
+                BUG();
+
+        tmp = RREG32_NO_KIQ(reg);
+        tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
+        WREG32_NO_KIQ(reg, tmp);
+
+out:
+        return (wptr & ih->ptr_mask);
 }
 
 /**
@@ -228,20 +330,21 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev)
  * position and also advance the position.
  */
 static void vega10_ih_decode_iv(struct amdgpu_device *adev,
-                                 struct amdgpu_iv_entry *entry)
+                                struct amdgpu_ih_ring *ih,
+                                struct amdgpu_iv_entry *entry)
 {
         /* wptr/rptr are in bytes! */
-        u32 ring_index = adev->irq.ih.rptr >> 2;
+        u32 ring_index = ih->rptr >> 2;
         uint32_t dw[8];
 
-        dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
-        dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
-        dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
-        dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
-        dw[4] = le32_to_cpu(adev->irq.ih.ring[ring_index + 4]);
-        dw[5] = le32_to_cpu(adev->irq.ih.ring[ring_index + 5]);
-        dw[6] = le32_to_cpu(adev->irq.ih.ring[ring_index + 6]);
-        dw[7] = le32_to_cpu(adev->irq.ih.ring[ring_index + 7]);
+        dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);
+        dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);
+        dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);
+        dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);
+        dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);
+        dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);
+        dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);
+        dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);
 
         entry->client_id = dw[0] & 0xff;
         entry->src_id = (dw[0] >> 8) & 0xff;
@@ -257,9 +360,8 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
         entry->src_data[2] = dw[6];
         entry->src_data[3] = dw[7];
 
-
         /* wptr/rptr are in bytes! */
-        adev->irq.ih.rptr += 32;
+        ih->rptr += 32;
 }
 
 /**
@@ -269,37 +371,95 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
  *
  * Set the IH ring buffer rptr.
  */
-static void vega10_ih_set_rptr(struct amdgpu_device *adev)
+static void vega10_ih_set_rptr(struct amdgpu_device *adev,
+                               struct amdgpu_ih_ring *ih)
 {
-        if (adev->irq.ih.use_doorbell) {
+        if (ih->use_doorbell) {
                 /* XXX check if swapping is necessary on BE */
-                if (adev->irq.ih.use_bus_addr)
-                        adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
-                else
-                        adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;
-                WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);
-        } else {
-                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, adev->irq.ih.rptr);
+                *ih->rptr_cpu = ih->rptr;
+                WDOORBELL32(ih->doorbell_index, ih->rptr);
+        } else if (ih == &adev->irq.ih) {
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
+        } else if (ih == &adev->irq.ih1) {
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr);
+        } else if (ih == &adev->irq.ih2) {
+                WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr);
         }
 }
 
+/**
+ * vega10_ih_self_irq - dispatch work for ring 1 and 2
+ *
+ * @adev: amdgpu_device pointer
+ * @source: irq source
+ * @entry: IV with WPTR update
+ *
+ * Update the WPTR from the IV and schedule work to handle the entries.
+ */
+static int vega10_ih_self_irq(struct amdgpu_device *adev,
+                              struct amdgpu_irq_src *source,
+                              struct amdgpu_iv_entry *entry)
+{
+        uint32_t wptr = cpu_to_le32(entry->src_data[0]);
+
+        switch (entry->ring_id) {
+        case 1:
+                *adev->irq.ih1.wptr_cpu = wptr;
+                schedule_work(&adev->irq.ih1_work);
+                break;
+        case 2:
+                *adev->irq.ih2.wptr_cpu = wptr;
+                schedule_work(&adev->irq.ih2_work);
+                break;
+        default: break;
+        }
+        return 0;
+}
+
+static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = {
+        .process = vega10_ih_self_irq,
+};
+
+static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
+{
+        adev->irq.self_irq.num_types = 0;
+        adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs;
+}
+
 static int vega10_ih_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
         vega10_ih_set_interrupt_funcs(adev);
+        vega10_ih_set_self_irq_funcs(adev);
         return 0;
 }
 
 static int vega10_ih_sw_init(void *handle)
 {
-        int r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int r;
+
+        r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
+                              &adev->irq.self_irq);
+        if (r)
+                return r;
 
         r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
         if (r)
                 return r;
 
+        if (adev->asic_type == CHIP_VEGA10) {
+                r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
+                if (r)
+                        return r;
+
+                r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
+                if (r)
+                        return r;
+        }
+
+        /* TODO add doorbell for IH1 & IH2 as well */
         adev->irq.ih.use_doorbell = true;
         adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
@@ -313,6 +473,8 @@ static int vega10_ih_sw_fini(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
         amdgpu_irq_fini(adev);
+        amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
+        amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
         amdgpu_ih_ring_fini(adev, &adev->irq.ih);
 
         return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 422674bb3cdf..4b5d60ea3e78 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -70,8 +70,8 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
         adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL64_USERQUEUE_START;
         adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
         adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
-        adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL64_sDMA_ENGINE0;
-        adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL64_sDMA_ENGINE1;
+        adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL64_sDMA_ENGINE0;
+        adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL64_sDMA_ENGINE1;
         adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
         adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_DOORBELL64_UVD_RING0_1;
         adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_DOORBELL64_UVD_RING2_3;
@@ -83,5 +83,6 @@ void vega10_doorbell_index_init(struct amdgpu_device *adev)
         adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
         /* In unit of dword doorbell */
         adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
+        adev->doorbell_index.sdma_doorbell_range = 4;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
index edce413fda9a..53716c593b2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -68,14 +68,14 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
         adev->doorbell_index.userqueue_start = AMDGPU_VEGA20_DOORBELL_USERQUEUE_START;
         adev->doorbell_index.userqueue_end = AMDGPU_VEGA20_DOORBELL_USERQUEUE_END;
         adev->doorbell_index.gfx_ring0 = AMDGPU_VEGA20_DOORBELL_GFX_RING0;
-        adev->doorbell_index.sdma_engine0 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0;
-        adev->doorbell_index.sdma_engine1 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1;
-        adev->doorbell_index.sdma_engine2 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2;
-        adev->doorbell_index.sdma_engine3 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3;
-        adev->doorbell_index.sdma_engine4 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4;
-        adev->doorbell_index.sdma_engine5 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5;
-        adev->doorbell_index.sdma_engine6 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6;
-        adev->doorbell_index.sdma_engine7 = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7;
+        adev->doorbell_index.sdma_engine[0] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0;
+        adev->doorbell_index.sdma_engine[1] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1;
+        adev->doorbell_index.sdma_engine[2] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2;
+        adev->doorbell_index.sdma_engine[3] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3;
+        adev->doorbell_index.sdma_engine[4] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4;
+        adev->doorbell_index.sdma_engine[5] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5;
+        adev->doorbell_index.sdma_engine[6] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6;
+        adev->doorbell_index.sdma_engine[7] = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7;
         adev->doorbell_index.ih = AMDGPU_VEGA20_DOORBELL_IH;
         adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1;
         adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3;
@@ -86,5 +86,6 @@ void vega20_doorbell_index_init(struct amdgpu_device *adev)
         adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
         adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
         adev->doorbell_index.max_assignment = AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT << 1;
+        adev->doorbell_index.sdma_doorbell_range = 20;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 77e367459101..5e5b42a0744a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -941,6 +941,69 @@ static bool vi_need_full_reset(struct amdgpu_device *adev)
         }
 }
 
+static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
+                              uint64_t *count1)
+{
+        uint32_t perfctr = 0;
+        uint64_t cnt0_of, cnt1_of;
+        int tmp;
+
+        /* This reports 0 on APUs, so return to avoid writing/reading registers
+         * that may or may not be different from their GPU counterparts
+         */
+        if (adev->flags & AMD_IS_APU)
+                return;
+
+        /* Set the 2 events that we wish to watch, defined above */
+        /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
+        perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
+
+        /* Write to enable desired perf counters */
+        WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr);
+        /* Zero out and enable the perf counters
+         * Write 0x5:
+         * Bit 0 = Start all counters(1)
+         * Bit 2 = Global counter reset enable(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005);
+
+        msleep(1000);
+
+        /* Load the shadow and disable the perf counters
+         * Write 0x2:
+         * Bit 0 = Stop counters(0)
+         * Bit 1 = Load the shadow counters(1)
+         */
+        WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002);
+
+        /* Read register values to get any >32bit overflow */
+        tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK);
+        cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
+        cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
+
+        /* Get the values and add the overflow */
+        *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
+        *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
+}
+
+static bool vi_need_reset_on_init(struct amdgpu_device *adev)
+{
+        u32 clock_cntl, pc;
+
+        if (adev->flags & AMD_IS_APU)
+                return false;
+
+        /* check if the SMC is already running */
+        clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0);
+        pc = RREG32_SMC(ixSMC_PC_C);
+        if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) &&
+            (0x20100 <= pc))
+                return true;
+
+        return false;
+}
+
 static const struct amdgpu_asic_funcs vi_asic_funcs =
 {
         .read_disabled_bios = &vi_read_disabled_bios,
@@ -956,6 +1019,8 @@ static const struct amdgpu_asic_funcs vi_asic_funcs =
         .invalidate_hdp = &vi_invalidate_hdp,
         .need_full_reset = &vi_need_full_reset,
         .init_doorbell_index = &legacy_doorbell_index_init,
+        .get_pcie_usage = &vi_get_pcie_usage,
+        .need_reset_on_init = &vi_need_reset_on_init,
 };
 
 #define CZ_REV_BRISTOL(rev)      \
@@ -1726,8 +1791,8 @@ void legacy_doorbell_index_init(struct amdgpu_device *adev)
         adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
         adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
         adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
-        adev->doorbell_index.sdma_engine0 = AMDGPU_DOORBELL_sDMA_ENGINE0;
-        adev->doorbell_index.sdma_engine1 = AMDGPU_DOORBELL_sDMA_ENGINE1;
+        adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
+        adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
         adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
         adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;
 }
diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig b/drivers/gpu/drm/amd/amdkfd/Kconfig
index fbf0ee5201c3..c3613604a4f8 100644
--- a/drivers/gpu/drm/amd/amdkfd/Kconfig
+++ b/drivers/gpu/drm/amd/amdkfd/Kconfig
@@ -4,8 +4,8 @@
 
 config HSA_AMD
         bool "HSA kernel driver for AMD GPU devices"
-        depends on DRM_AMDGPU && X86_64
-        imply AMD_IOMMU_V2
+        depends on DRM_AMDGPU && (X86_64 || ARM64)
+        imply AMD_IOMMU_V2 if X86_64
         select MMU_NOTIFIER
         help
           Enable this if you want to use HSA features on AMD GPU devices.
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index b7bc7d7d048f..5d85ff341385 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -863,6 +863,7 @@ static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
         return 0;
 }
 
+#if CONFIG_X86_64
 static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
                                 uint32_t *num_entries,
                                 struct crat_subtype_iolink *sub_type_hdr)
@@ -905,6 +906,7 @@ static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
 
         return 0;
 }
+#endif
 
 /* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU
  *
@@ -920,7 +922,9 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
         struct crat_subtype_generic *sub_type_hdr;
         int avail_size = *size;
         int numa_node_id;
+#ifdef CONFIG_X86_64
         uint32_t entries = 0;
+#endif
         int ret = 0;
 
         if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_CPU)
@@ -982,6 +986,7 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
                         sub_type_hdr->length);
 
                 /* Fill in Subtype: IO Link */
+#ifdef CONFIG_X86_64
                 ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
                                 &entries,
                                 (struct crat_subtype_iolink *)sub_type_hdr);
@@ -992,6 +997,9 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
 
                 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
                                 sub_type_hdr->length * entries);
+#else
+                pr_info("IO link not available for non x86 platforms\n");
+#endif
 
                 crat_table->num_domains++;
         }
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
index 8018163414ff..932007eb9168 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c
@@ -23,22 +23,7 @@
 #include <linux/sched.h>
 #include <linux/device.h>
 #include "kfd_priv.h"
-
-static const struct kgd2kfd_calls kgd2kfd = {
-        .exit           = kgd2kfd_exit,
-        .probe          = kgd2kfd_probe,
-        .device_init    = kgd2kfd_device_init,
-        .device_exit    = kgd2kfd_device_exit,
-        .interrupt      = kgd2kfd_interrupt,
-        .suspend        = kgd2kfd_suspend,
-        .resume         = kgd2kfd_resume,
-        .quiesce_mm     = kgd2kfd_quiesce_mm,
-        .resume_mm      = kgd2kfd_resume_mm,
-        .schedule_evict_and_restore_process =
-                          kgd2kfd_schedule_evict_and_restore_process,
-        .pre_reset      = kgd2kfd_pre_reset,
-        .post_reset     = kgd2kfd_post_reset,
-};
+#include "amdgpu_amdkfd.h"
 
 static int kfd_init(void)
 {
@@ -91,20 +76,10 @@ static void kfd_exit(void)
         kfd_chardev_exit();
 }
 
-int kgd2kfd_init(unsigned int interface_version,
-                const struct kgd2kfd_calls **g2f)
+int kgd2kfd_init()
 {
-        int err;
-
-        err = kfd_init();
-        if (err)
-                return err;
-
-        *g2f = &kgd2kfd;
-
-        return 0;
+        return kfd_init();
 }
-EXPORT_SYMBOL(kgd2kfd_init);
 
 void kgd2kfd_exit(void)
 {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 0689d4ccbbc0..12b66330fc6d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -266,14 +266,6 @@ struct kfd_dev {
         bool pci_atomic_requested;
 };
 
-/* KGD2KFD callbacks */
-void kgd2kfd_exit(void);
-struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
-                        struct pci_dev *pdev, const struct kfd2kgd_calls *f2g);
-bool kgd2kfd_device_init(struct kfd_dev *kfd,
-                        const struct kgd2kfd_shared_resources *gpu_resources);
-void kgd2kfd_device_exit(struct kfd_dev *kfd);
-
 enum kfd_mempool {
         KFD_MEMPOOL_SYSTEM_CACHEABLE = 1,
         KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2,
@@ -541,11 +533,6 @@ struct qcm_process_device {
 /* Approx. time before evicting the process again */
 #define PROCESS_ACTIVE_TIME_MS 10
 
-int kgd2kfd_quiesce_mm(struct mm_struct *mm);
-int kgd2kfd_resume_mm(struct mm_struct *mm);
-int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
-                                               struct dma_fence *fence);
-
 /* 8 byte handle containing GPU ID in the most significant 4 bytes and
  * idr_handle in the least significant 4 bytes
  */
@@ -800,20 +787,11 @@ int kfd_numa_node_to_apic_id(int numa_node_id);
 /* Interrupts */
 int kfd_interrupt_init(struct kfd_dev *dev);
 void kfd_interrupt_exit(struct kfd_dev *dev);
-void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
 bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry);
 bool interrupt_is_wanted(struct kfd_dev *dev,
                                 const uint32_t *ih_ring_entry,
                                 uint32_t *patched_ihre, bool *flag);
 
-/* Power Management */
-void kgd2kfd_suspend(struct kfd_dev *kfd);
-int kgd2kfd_resume(struct kfd_dev *kfd);
-
-/* GPU reset */
-int kgd2kfd_pre_reset(struct kfd_dev *kfd);
-int kgd2kfd_post_reset(struct kfd_dev *kfd);
-
 /* amdkfd Apertures */
 int kfd_init_apertures(struct kfd_process *process);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 5f5b2acedbac..09da91644f9f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1093,8 +1093,6 @@ static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu)
  *              the GPU device is not already present in the topology device
  *              list then return NULL. This means a new topology device has to
  *              be created for this GPU.
- * TODO: Rather than assiging @gpu to first topology device withtout
- *              gpu attached, it will better to have more stringent check.
  */
 static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
 {
@@ -1102,12 +1100,20 @@ static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
         struct kfd_topology_device *out_dev = NULL;
 
         down_write(&topology_lock);
-        list_for_each_entry(dev, &topology_device_list, list)
+        list_for_each_entry(dev, &topology_device_list, list) {
+                /* Discrete GPUs need their own topology device list
+                 * entries. Don't assign them to CPU/APU nodes.
+                 */
+                if (!gpu->device_info->needs_iommu_device &&
+                    dev->node_props.cpu_cores_count)
+                        continue;
+
                 if (!dev->gpu && (dev->node_props.simd_count > 0)) {
                         dev->gpu = gpu;
                         out_dev = dev;
                         break;
                 }
+        }
         up_write(&topology_lock);
         return out_dev;
 }
@@ -1392,7 +1398,6 @@ int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_dev **kdev)
 
 static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask)
 {
-        const struct cpuinfo_x86 *cpuinfo;
         int first_cpu_of_numa_node;
 
         if (!cpumask || cpumask == cpu_none_mask)
@@ -1400,9 +1405,11 @@ static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask)
         first_cpu_of_numa_node = cpumask_first(cpumask);
         if (first_cpu_of_numa_node >= nr_cpu_ids)
                 return -1;
-        cpuinfo = &cpu_data(first_cpu_of_numa_node);
-
-        return cpuinfo->apicid;
+#ifdef CONFIG_X86_64
+        return cpu_data(first_cpu_of_numa_node).apicid;
+#else
+        return first_cpu_of_numa_node;
+#endif
 }
 
 /* kfd_numa_node_to_apic_id - Returns the APIC ID of the first logical processor
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8a626d16e8e3..407f733a47ea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1760,7 +1760,7 @@ static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
                 + caps.min_input_signal * 0x101;
 
         if (dc_link_set_backlight_level(dm->backlight_link,
-                        brightness, 0, 0))
+                        brightness, 0))
                 return 0;
         else
                 return 1;
@@ -2284,6 +2284,68 @@ static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
         return r;
 }
 
+static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
+{
+        uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
+
+        return offset ? (address + offset * 256) : 0;
+}
+
+static bool fill_plane_dcc_attributes(struct amdgpu_device *adev,
+                                      const struct amdgpu_framebuffer *afb,
+                                      struct dc_plane_state *plane_state,
+                                      uint64_t info)
+{
+        struct dc *dc = adev->dm.dc;
+        struct dc_dcc_surface_param input = {0};
+        struct dc_surface_dcc_cap output = {0};
+        uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
+        uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
+        uint64_t dcc_address;
+
+        if (!offset)
+                return false;
+
+        if (!dc->cap_funcs.get_dcc_compression_cap)
+                return false;
+
+        input.format = plane_state->format;
+        input.surface_size.width =
+                plane_state->plane_size.grph.surface_size.width;
+        input.surface_size.height =
+                plane_state->plane_size.grph.surface_size.height;
+        input.swizzle_mode = plane_state->tiling_info.gfx9.swizzle;
+
+        if (plane_state->rotation == ROTATION_ANGLE_0 ||
+            plane_state->rotation == ROTATION_ANGLE_180)
+                input.scan = SCAN_DIRECTION_HORIZONTAL;
+        else if (plane_state->rotation == ROTATION_ANGLE_90 ||
+                 plane_state->rotation == ROTATION_ANGLE_270)
+                input.scan = SCAN_DIRECTION_VERTICAL;
+
+        if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
+                return false;
+
+        if (!output.capable)
+                return false;
+
+        if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
+                return false;
+
+        plane_state->dcc.enable = 1;
+        plane_state->dcc.grph.meta_pitch =
+                AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
+        plane_state->dcc.grph.independent_64b_blks = i64b;
+
+        dcc_address = get_dcc_address(afb->address, info);
+        plane_state->address.grph.meta_addr.low_part =
+                lower_32_bits(dcc_address);
+        plane_state->address.grph.meta_addr.high_part =
+                upper_32_bits(dcc_address);
+
+        return true;
+}
+
 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
                                          struct dc_plane_state *plane_state,
                                          const struct amdgpu_framebuffer *amdgpu_fb)
@@ -2336,6 +2398,10 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
                 return -EINVAL;
         }
 
+        memset(&plane_state->address, 0, sizeof(plane_state->address));
+        memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
+        memset(&plane_state->dcc, 0, sizeof(plane_state->dcc));
+
         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
                 plane_state->plane_size.grph.surface_size.x = 0;
@@ -2367,8 +2433,6 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
                 plane_state->color_space = COLOR_SPACE_YCBCR709;
         }
 
-        memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
-
         /* Fill GFX8 params */
         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
@@ -2417,6 +2481,9 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
                 plane_state->tiling_info.gfx9.swizzle =
                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
                 plane_state->tiling_info.gfx9.shaderEnable = 1;
+
+                fill_plane_dcc_attributes(adev, amdgpu_fb, plane_state,
+                                          tiling_flags);
         }
 
         plane_state->visible = true;
@@ -2580,7 +2647,7 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
                  * according to HDMI spec, we use YCbCr709 and YCbCr601
                  * respectively
                  */
-                if (dc_crtc_timing->pix_clk_khz > 27030) {
+                if (dc_crtc_timing->pix_clk_100hz > 270300) {
                         if (dc_crtc_timing->flags.Y_ONLY)
                                 color_space =
                                         COLOR_SPACE_YCBCR709_LIMITED;
@@ -2623,7 +2690,7 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
                 return;
         do {
-                normalized_clk = timing_out->pix_clk_khz;
+                normalized_clk = timing_out->pix_clk_100hz / 10;
                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
                         normalized_clk /= 2;
@@ -2666,10 +2733,10 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
         timing_out->v_border_bottom = 0;
         /* TODO: un-hardcode */
         if (drm_mode_is_420_only(info, mode_in)
-                        && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
+                        && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
-                        && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
+                        && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
         else
                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
@@ -2704,14 +2771,14 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
         timing_out->v_sync_width =
                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
-        timing_out->pix_clk_khz = mode_in->crtc_clock;
+        timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
 
         stream->output_color_space = get_output_color_space(timing_out);
 
         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
-        if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
+        if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
                 adjust_colour_depth_from_display_info(timing_out, info);
 }
 
@@ -2832,7 +2899,7 @@ static void set_master_stream(struct dc_stream_state *stream_set[],
                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
                         int refresh_rate = 0;
 
-                        refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
+                        refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
                         if (refresh_rate > highest_rfr) {
                                 highest_rfr = refresh_rate;
@@ -2905,6 +2972,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
                 goto finish;
         }
 
+        stream->dm_stream_context = aconnector;
+
         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
                 /* Search for preferred mode */
                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
@@ -2956,7 +3025,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
                 drm_connector,
                 sink);
 
-        update_stream_signal(stream);
+        update_stream_signal(stream, sink);
 
         if (dm_state && dm_state->freesync_capable)
                 stream->ignore_msa_timing_param = true;
@@ -3532,6 +3601,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
         struct amdgpu_bo *rbo;
         uint64_t chroma_addr = 0;
         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
+        uint64_t tiling_flags, dcc_address;
         unsigned int awidth;
         uint32_t domain;
         int r;
@@ -3572,6 +3642,9 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
                 DRM_ERROR("%p bind failed\n", rbo);
                 return r;
         }
+
+        amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
+
         amdgpu_bo_unreserve(rbo);
 
         afb->address = amdgpu_bo_gpu_offset(rbo);
@@ -3585,6 +3658,13 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
+
+                        dcc_address =
+                                get_dcc_address(afb->address, tiling_flags);
+                        plane_state->address.grph.meta_addr.low_part =
+                                lower_32_bits(dcc_address);
+                        plane_state->address.grph.meta_addr.high_part =
+                                upper_32_bits(dcc_address);
                 } else {
                         awidth = ALIGN(new_state->fb->width, 64);
                         plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
@@ -4456,20 +4536,6 @@ static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
                                                  acrtc->crtc_id);
 }
 
-struct dc_stream_status *dc_state_get_stream_status(
-        struct dc_state *state,
-        struct dc_stream_state *stream)
-{
-        uint8_t i;
-
-        for (i = 0; i < state->stream_count; i++) {
-                if (stream == state->streams[i])
-                        return &state->stream_status[i];
-        }
-
-        return NULL;
-}
-
 static void update_freesync_state_on_stream(
         struct amdgpu_display_manager *dm,
         struct dm_crtc_state *new_crtc_state,
@@ -4523,12 +4589,12 @@ static void update_freesync_state_on_stream(
                 TRANSFER_FUNC_UNKNOWN,
                 &vrr_infopacket);
 
-        new_crtc_state->freesync_timing_changed =
+        new_crtc_state->freesync_timing_changed |=
                 (memcmp(&new_crtc_state->vrr_params.adjust,
                         &vrr_params.adjust,
                         sizeof(vrr_params.adjust)) != 0);
 
-        new_crtc_state->freesync_vrr_info_changed =
+        new_crtc_state->freesync_vrr_info_changed |=
                 (memcmp(&new_crtc_state->vrr_infopacket,
                         &vrr_infopacket,
                         sizeof(vrr_infopacket)) != 0);
@@ -4552,248 +4618,6 @@ static void update_freesync_state_on_stream(
                                   vrr_params.adjust.v_total_max);
 }
 
-/*
- * Executes flip
- *
- * Waits on all BO's fences and for proper vblank count
- */
-static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
-                              struct drm_framebuffer *fb,
-                              uint32_t target,
-                              struct dc_state *state)
-{
-        unsigned long flags;
-        uint64_t timestamp_ns;
-        uint32_t target_vblank;
-        int r, vpos, hpos;
-        struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-        struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
-        struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
-        struct amdgpu_device *adev = crtc->dev->dev_private;
-        bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
-        struct dc_flip_addrs addr = { {0} };
-        /* TODO eliminate or rename surface_update */
-        struct dc_surface_update surface_updates[1] = { {0} };
-        struct dc_stream_update stream_update = {0};
-        struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
-        struct dc_stream_status *stream_status;
-        struct dc_plane_state *surface;
-
-
-        /* Prepare wait for target vblank early - before the fence-waits */
-        target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
-                        amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
-
-        /*
-         * TODO This might fail and hence better not used, wait
-         * explicitly on fences instead
-         * and in general should be called for
-         * blocking commit to as per framework helpers
-         */
-        r = amdgpu_bo_reserve(abo, true);
-        if (unlikely(r != 0)) {
-                DRM_ERROR("failed to reserve buffer before flip\n");
-                WARN_ON(1);
-        }
-
-        /* Wait for all fences on this FB */
-        WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
-                                                                    MAX_SCHEDULE_TIMEOUT) < 0);
-
-        amdgpu_bo_unreserve(abo);
-
-        /*
-         * Wait until we're out of the vertical blank period before the one
-         * targeted by the flip
-         */
-        while ((acrtc->enabled &&
-                (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
-                                                    0, &vpos, &hpos, NULL,
-                                                    NULL, &crtc->hwmode)
-                 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
-                (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
-                (int)(target_vblank -
-                  amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
-                usleep_range(1000, 1100);
-        }
-
-        /* Flip */
-        spin_lock_irqsave(&crtc->dev->event_lock, flags);
-
-        WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
-        WARN_ON(!acrtc_state->stream);
-
-        addr.address.grph.addr.low_part = lower_32_bits(afb->address);
-        addr.address.grph.addr.high_part = upper_32_bits(afb->address);
-        addr.flip_immediate = async_flip;
-
-        timestamp_ns = ktime_get_ns();
-        addr.flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
-
-
-        if (acrtc->base.state->event)
-                prepare_flip_isr(acrtc);
-
-        spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
-
-        stream_status = dc_stream_get_status(acrtc_state->stream);
-        if (!stream_status) {
-                DRM_ERROR("No stream status for CRTC: id=%d\n",
-                        acrtc->crtc_id);
-                return;
-        }
-
-        surface = stream_status->plane_states[0];
-        surface_updates->surface = surface;
-
-        if (!surface) {
-                DRM_ERROR("No surface for CRTC: id=%d\n",
-                        acrtc->crtc_id);
-                return;
-        }
-        surface_updates->flip_addr = &addr;
-
-        if (acrtc_state->stream) {
-                update_freesync_state_on_stream(
-                        &adev->dm,
-                        acrtc_state,
-                        acrtc_state->stream,
-                        surface,
-                        addr.flip_timestamp_in_us);
-
-                if (acrtc_state->freesync_timing_changed)
-                        stream_update.adjust =
-                                &acrtc_state->stream->adjust;
-
-                if (acrtc_state->freesync_vrr_info_changed)
-                        stream_update.vrr_infopacket =
-                                &acrtc_state->stream->vrr_infopacket;
-        }
-
-        /* Update surface timing information. */
-        surface->time.time_elapsed_in_us[surface->time.index] =
-                addr.flip_timestamp_in_us - surface->time.prev_update_time_in_us;
-        surface->time.prev_update_time_in_us = addr.flip_timestamp_in_us;
-        surface->time.index++;
-        if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
-                surface->time.index = 0;
-
-        mutex_lock(&adev->dm.dc_lock);
-
-        dc_commit_updates_for_stream(adev->dm.dc,
-                                             surface_updates,
-                                             1,
-                                             acrtc_state->stream,
-                                             &stream_update,
-                                             &surface_updates->surface,
-                                             state);
-        mutex_unlock(&adev->dm.dc_lock);
-
-        DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
-                         __func__,
-                         addr.address.grph.addr.high_part,
-                         addr.address.grph.addr.low_part);
-}
-
-/*
- * TODO this whole function needs to go
- *
- * dc_surface_update is needlessly complex. See if we can just replace this
- * with a dc_plane_state and follow the atomic model a bit more closely here.
- */
-static bool commit_planes_to_stream(
-                struct amdgpu_display_manager *dm,
-                struct dc *dc,
-                struct dc_plane_state **plane_states,
-                uint8_t new_plane_count,
-                struct dm_crtc_state *dm_new_crtc_state,
-                struct dm_crtc_state *dm_old_crtc_state,
-                struct dc_state *state)
-{
-        /* no need to dynamically allocate this. it's pretty small */
-        struct dc_surface_update updates[MAX_SURFACES];
-        struct dc_flip_addrs *flip_addr;
-        struct dc_plane_info *plane_info;
-        struct dc_scaling_info *scaling_info;
-        int i;
-        struct dc_stream_state *dc_stream = dm_new_crtc_state->stream;
-        struct dc_stream_update *stream_update =
-                        kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
-        unsigned int abm_level;
-
-        if (!stream_update) {
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
-                            GFP_KERNEL);
-        plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
-                             GFP_KERNEL);
-        scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
-                               GFP_KERNEL);
-
-        if (!flip_addr || !plane_info || !scaling_info) {
-                kfree(flip_addr);
-                kfree(plane_info);
-                kfree(scaling_info);
-                kfree(stream_update);
-                return false;
-        }
-
-        memset(updates, 0, sizeof(updates));
-
-        stream_update->src = dc_stream->src;
-        stream_update->dst = dc_stream->dst;
-        stream_update->out_transfer_func = dc_stream->out_transfer_func;
-
-        if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
-                abm_level = dm_new_crtc_state->abm_level;
-                stream_update->abm_level = &abm_level;
-        }
-
-        for (i = 0; i < new_plane_count; i++) {
-                updates[i].surface = plane_states[i];
-                updates[i].gamma =
-                        (struct dc_gamma *)plane_states[i]->gamma_correction;
-                updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
-                flip_addr[i].address = plane_states[i]->address;
-                flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
-                plane_info[i].color_space = plane_states[i]->color_space;
-                plane_info[i].format = plane_states[i]->format;
-                plane_info[i].plane_size = plane_states[i]->plane_size;
-                plane_info[i].rotation = plane_states[i]->rotation;
-                plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
-                plane_info[i].stereo_format = plane_states[i]->stereo_format;
-                plane_info[i].tiling_info = plane_states[i]->tiling_info;
-                plane_info[i].visible = plane_states[i]->visible;
-                plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
-                plane_info[i].dcc = plane_states[i]->dcc;
-                scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
-                scaling_info[i].src_rect = plane_states[i]->src_rect;
-                scaling_info[i].dst_rect = plane_states[i]->dst_rect;
-                scaling_info[i].clip_rect = plane_states[i]->clip_rect;
-
-                updates[i].flip_addr = &flip_addr[i];
-                updates[i].plane_info = &plane_info[i];
-                updates[i].scaling_info = &scaling_info[i];
-        }
-
-        mutex_lock(&dm->dc_lock);
-        dc_commit_updates_for_stream(
-                        dc,
-                        updates,
-                        new_plane_count,
-                        dc_stream, stream_update, plane_states, state);
-        mutex_unlock(&dm->dc_lock);
-
-        kfree(flip_addr);
-        kfree(plane_info);
-        kfree(scaling_info);
-        kfree(stream_update);
-        return true;
-}
-
 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                                     struct dc_state *dc_state,
                                     struct drm_device *dev,
@@ -4801,26 +4625,50 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                                     struct drm_crtc *pcrtc,
                                     bool *wait_for_vblank)
 {
-        uint32_t i;
+        uint32_t i, r;
+        uint64_t timestamp_ns;
         struct drm_plane *plane;
         struct drm_plane_state *old_plane_state, *new_plane_state;
-        struct dc_stream_state *dc_stream_attach;
-        struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
         struct drm_crtc_state *new_pcrtc_state =
                         drm_atomic_get_new_crtc_state(state, pcrtc);
         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
         struct dm_crtc_state *dm_old_crtc_state =
                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
-        int planes_count = 0;
+        int flip_count = 0, planes_count = 0, vpos, hpos;
         unsigned long flags;
+        struct amdgpu_bo *abo;
+        uint64_t tiling_flags, dcc_address;
+        struct dc_stream_status *stream_status;
+        uint32_t target, target_vblank;
+
+        struct {
+                struct dc_surface_update surface_updates[MAX_SURFACES];
+                struct dc_flip_addrs flip_addrs[MAX_SURFACES];
+                struct dc_stream_update stream_update;
+        } *flip;
+
+        struct {
+                struct dc_surface_update surface_updates[MAX_SURFACES];
+                struct dc_plane_info plane_infos[MAX_SURFACES];
+                struct dc_scaling_info scaling_infos[MAX_SURFACES];
+                struct dc_stream_update stream_update;
+        } *full;
+
+        flip = kzalloc(sizeof(*flip), GFP_KERNEL);
+        full = kzalloc(sizeof(*full), GFP_KERNEL);
+
+        if (!flip || !full)
+                dm_error("Failed to allocate update bundles\n");
 
         /* update planes when needed */
         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
                 struct drm_crtc *crtc = new_plane_state->crtc;
                 struct drm_crtc_state *new_crtc_state;
                 struct drm_framebuffer *fb = new_plane_state->fb;
+                struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
                 bool pflip_needed;
+                struct dc_plane_state *surface, *dc_plane;
                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
 
                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
@@ -4835,72 +4683,205 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
                 if (!new_crtc_state->active)
                         continue;
 
-                pflip_needed = !state->allow_modeset;
+                pflip_needed = old_plane_state->fb &&
+                        old_plane_state->fb != new_plane_state->fb;
 
-                spin_lock_irqsave(&crtc->dev->event_lock, flags);
-                if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
-                        DRM_ERROR("%s: acrtc %d, already busy\n",
-                                  __func__,
-                                  acrtc_attach->crtc_id);
-                        /* In commit tail framework this cannot happen */
-                        WARN_ON(1);
-                }
-                spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
-
-                if (!pflip_needed || plane->type == DRM_PLANE_TYPE_OVERLAY) {
-                        WARN_ON(!dm_new_plane_state->dc_state);
-
-                        plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
+                dc_plane = dm_new_plane_state->dc_state;
 
-                        dc_stream_attach = acrtc_state->stream;
-                        planes_count++;
-
-                } else if (new_crtc_state->planes_changed) {
-                        /* Assume even ONE crtc with immediate flip means
+                if (pflip_needed) {
+                        /*
+                         * Assume even ONE crtc with immediate flip means
                          * entire can't wait for VBLANK
                          * TODO Check if it's correct
                          */
-                        *wait_for_vblank =
-                                        new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
-                                false : true;
-
-                        /* TODO: Needs rework for multiplane flip */
-                        if (plane->type == DRM_PLANE_TYPE_PRIMARY)
-                                drm_crtc_vblank_get(crtc);
-
-                        amdgpu_dm_do_flip(
-                                crtc,
-                                fb,
-                                (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
-                                dc_state);
+                        if (new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
+                                *wait_for_vblank = false;
+
+                        /*
+                         * TODO This might fail and hence better not used, wait
+                         * explicitly on fences instead
+                         * and in general should be called for
+                         * blocking commit to as per framework helpers
+                         */
+                        abo = gem_to_amdgpu_bo(fb->obj[0]);
+                        r = amdgpu_bo_reserve(abo, true);
+                        if (unlikely(r != 0)) {
+                                DRM_ERROR("failed to reserve buffer before flip\n");
+                                WARN_ON(1);
+                        }
+
+                        /* Wait for all fences on this FB */
+                        WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
+                                                                                    MAX_SCHEDULE_TIMEOUT) < 0);
+
+                        amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
+
+                        amdgpu_bo_unreserve(abo);
+
+                        flip->flip_addrs[flip_count].address.grph.addr.low_part = lower_32_bits(afb->address);
+                        flip->flip_addrs[flip_count].address.grph.addr.high_part = upper_32_bits(afb->address);
+
+                        dcc_address = get_dcc_address(afb->address, tiling_flags);
+                        flip->flip_addrs[flip_count].address.grph.meta_addr.low_part = lower_32_bits(dcc_address);
+                        flip->flip_addrs[flip_count].address.grph.meta_addr.high_part = upper_32_bits(dcc_address);
+
+                        flip->flip_addrs[flip_count].flip_immediate =
+                                        (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
+
+                        timestamp_ns = ktime_get_ns();
+                        flip->flip_addrs[flip_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
+                        flip->surface_updates[flip_count].flip_addr = &flip->flip_addrs[flip_count];
+
+                        stream_status = dc_stream_get_status(acrtc_state->stream);
+                        if (!stream_status) {
+                                DRM_ERROR("No stream status for CRTC: id=%d\n",
+                                                acrtc_attach->crtc_id);
+                                continue;
+                        }
+
+                        surface = stream_status->plane_states[0];
+                        flip->surface_updates[flip_count].surface = surface;
+                        if (!flip->surface_updates[flip_count].surface) {
+                                DRM_ERROR("No surface for CRTC: id=%d\n",
+                                                acrtc_attach->crtc_id);
+                                continue;
+                        }
+
+                        if (acrtc_state->stream)
+                                update_freesync_state_on_stream(
+                                        dm,
+                                        acrtc_state,
+                                        acrtc_state->stream,
+                                        surface,
+                                        flip->flip_addrs[flip_count].flip_timestamp_in_us);
+
+                        /* Update surface timing information. */
+                        surface->time.time_elapsed_in_us[surface->time.index] =
+                                flip->flip_addrs[flip_count].flip_timestamp_in_us -
+                                surface->time.prev_update_time_in_us;
+                        surface->time.prev_update_time_in_us = flip->flip_addrs[flip_count].flip_timestamp_in_us;
+                        surface->time.index++;
+                        if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
+                                surface->time.index = 0;
+
+                        DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
+                                         __func__,
+                                         flip->flip_addrs[flip_count].address.grph.addr.high_part,
+                                         flip->flip_addrs[flip_count].address.grph.addr.low_part);
+
+                        flip_count += 1;
                 }
 
+                full->surface_updates[planes_count].surface = dc_plane;
+                if (new_pcrtc_state->color_mgmt_changed) {
+                        full->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
+                        full->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
+                }
+
+
+                full->scaling_infos[planes_count].scaling_quality = dc_plane->scaling_quality;
+                full->scaling_infos[planes_count].src_rect = dc_plane->src_rect;
+                full->scaling_infos[planes_count].dst_rect = dc_plane->dst_rect;
+                full->scaling_infos[planes_count].clip_rect = dc_plane->clip_rect;
+                full->surface_updates[planes_count].scaling_info = &full->scaling_infos[planes_count];
+
+
+                full->plane_infos[planes_count].color_space = dc_plane->color_space;
+                full->plane_infos[planes_count].format = dc_plane->format;
+                full->plane_infos[planes_count].plane_size = dc_plane->plane_size;
+                full->plane_infos[planes_count].rotation = dc_plane->rotation;
+                full->plane_infos[planes_count].horizontal_mirror = dc_plane->horizontal_mirror;
+                full->plane_infos[planes_count].stereo_format = dc_plane->stereo_format;
+                full->plane_infos[planes_count].tiling_info = dc_plane->tiling_info;
+                full->plane_infos[planes_count].visible = dc_plane->visible;
+                full->plane_infos[planes_count].per_pixel_alpha = dc_plane->per_pixel_alpha;
+                full->plane_infos[planes_count].dcc = dc_plane->dcc;
+                full->surface_updates[planes_count].plane_info = &full->plane_infos[planes_count];
+
+                planes_count += 1;
+
         }
 
-        if (planes_count) {
-                unsigned long flags;
+        /*
+         * TODO: For proper atomic behaviour, we should be calling into DC once with
+         * all the changes.  However, DC refuses to do pageflips and non-pageflip
+         * changes in the same call.  Change DC to respect atomic behaviour,
+         * hopefully eliminating dc_*_update structs in their entirety.
+         */
+        if (flip_count) {
+                target = (uint32_t)drm_crtc_vblank_count(pcrtc) + *wait_for_vblank;
+                /* Prepare wait for target vblank early - before the fence-waits */
+                target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) +
+                                amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id);
 
-                if (new_pcrtc_state->event) {
+                /*
+                 * Wait until we're out of the vertical blank period before the one
+                 * targeted by the flip
+                 */
+                while ((acrtc_attach->enabled &&
+                        (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
+                                                            0, &vpos, &hpos, NULL,
+                                                            NULL, &pcrtc->hwmode)
+                         & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
+                        (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
+                        (int)(target_vblank -
+                          amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
+                        usleep_range(1000, 1100);
+                }
 
+                if (acrtc_attach->base.state->event) {
                         drm_crtc_vblank_get(pcrtc);
 
                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
+
+                        WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
                         prepare_flip_isr(acrtc_attach);
+
                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
                 }
 
-                dc_stream_attach->abm_level = acrtc_state->abm_level;
+                if (acrtc_state->stream) {
 
-                if (false == commit_planes_to_stream(dm,
-                                                        dm->dc,
-                                                        plane_states_constructed,
-                                                        planes_count,
-                                                        acrtc_state,
-                                                        dm_old_crtc_state,
-                                                        dc_state))
-                        dm_error("%s: Failed to attach plane!\n", __func__);
-        } else {
-                /*TODO BUG Here should go disable planes on CRTC. */
+                        if (acrtc_state->freesync_timing_changed)
+                                flip->stream_update.adjust =
+                                        &acrtc_state->stream->adjust;
+
+                        if (acrtc_state->freesync_vrr_info_changed)
+                                flip->stream_update.vrr_infopacket =
+                                        &acrtc_state->stream->vrr_infopacket;
+                }
+
+                mutex_lock(&dm->dc_lock);
+                dc_commit_updates_for_stream(dm->dc,
+                                                     flip->surface_updates,
+                                                     flip_count,
+                                                     acrtc_state->stream,
+                                                     &flip->stream_update,
+                                                     dc_state);
+                mutex_unlock(&dm->dc_lock);
+        }
+
+        if (planes_count) {
+                if (new_pcrtc_state->mode_changed) {
+                        full->stream_update.src = acrtc_state->stream->src;
+                        full->stream_update.dst = acrtc_state->stream->dst;
+                }
+
+                if (new_pcrtc_state->color_mgmt_changed)
+                        full->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
+
+                acrtc_state->stream->abm_level = acrtc_state->abm_level;
+                if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
+                        full->stream_update.abm_level = &acrtc_state->abm_level;
+
+                mutex_lock(&dm->dc_lock);
+                dc_commit_updates_for_stream(dm->dc,
+                                                     full->surface_updates,
+                                                     planes_count,
+                                                     acrtc_state->stream,
+                                                     &full->stream_update,
+                                                     dc_state);
+                mutex_unlock(&dm->dc_lock);
         }
 }
 
@@ -5077,8 +5058,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                                         dc_stream_get_status(dm_new_crtc_state->stream);
 
                         if (!status)
-                                status = dc_state_get_stream_status(dc_state,
-                                                                    dm_new_crtc_state->stream);
+                                status = dc_stream_get_status_from_state(dc_state,
+                                                                         dm_new_crtc_state->stream);
 
                         if (!status)
                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
@@ -5087,11 +5068,13 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 }
         }
 
-        /* Handle scaling, underscan, and abm changes*/
+        /* Handle connector state changes */
         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
+                struct dc_surface_update dummy_updates[MAX_SURFACES] = { 0 };
+                struct dc_stream_update stream_update = { 0 };
                 struct dc_stream_status *status = NULL;
 
                 if (acrtc) {
@@ -5103,37 +5086,48 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
                         continue;
 
-
                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
 
-                /* Skip anything that is not scaling or underscan changes */
                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
                                 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
                         continue;
 
-                update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
-                                dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
+                if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
+                        update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
+                                        dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
 
-                if (!dm_new_crtc_state->stream)
-                        continue;
+                        stream_update.src = dm_new_crtc_state->stream->src;
+                        stream_update.dst = dm_new_crtc_state->stream->dst;
+                }
+
+                if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
+                        dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
+
+                        stream_update.abm_level = &dm_new_crtc_state->abm_level;
+                }
 
                 status = dc_stream_get_status(dm_new_crtc_state->stream);
                 WARN_ON(!status);
                 WARN_ON(!status->plane_count);
 
-                dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
+                /*
+                 * TODO: DC refuses to perform stream updates without a dc_surface_update.
+                 * Here we create an empty update on each plane.
+                 * To fix this, DC should permit updating only stream properties.
+                 */
+                for (j = 0; j < status->plane_count; j++)
+                        dummy_updates[j].surface = status->plane_states[0];
+
 
-                /*TODO How it works with MPO ?*/
-                if (!commit_planes_to_stream(
-                                dm,
-                                dm->dc,
-                                status->plane_states,
-                                status->plane_count,
-                                dm_new_crtc_state,
-                                to_dm_crtc_state(old_crtc_state),
-                                dc_state))
-                        dm_error("%s: Failed to update stream scaling!\n", __func__);
+                mutex_lock(&dm->dc_lock);
+                dc_commit_updates_for_stream(dm->dc,
+                                                     dummy_updates,
+                                                     status->plane_count,
+                                                     dm_new_crtc_state->stream,
+                                                     &stream_update,
+                                                     dc_state);
+                mutex_unlock(&dm->dc_lock);
         }
 
         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
@@ -5184,18 +5178,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
         }
         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 
+        /* Signal HW programming completion */
+        drm_atomic_helper_commit_hw_done(state);
 
         if (wait_for_vblank)
                 drm_atomic_helper_wait_for_flip_done(dev, state);
 
-        /*
-         * FIXME:
-         * Delay hw_done() until flip_done() is signaled. This is to block
-         * another commit from freeing the CRTC state while we're still
-         * waiting on flip_done.
-         */
-        drm_atomic_helper_commit_hw_done(state);
-
         drm_atomic_helper_cleanup_planes(dev, state);
 
         /*
@@ -5388,15 +5376,15 @@ static void reset_freesync_config_for_crtc(
                sizeof(new_crtc_state->vrr_infopacket));
 }
 
-static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
-                                 struct drm_atomic_state *state,
-                                 bool enable,
-                                 bool *lock_and_validation_needed)
+static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
+                                struct drm_atomic_state *state,
+                                struct drm_crtc *crtc,
+                                struct drm_crtc_state *old_crtc_state,
+                                struct drm_crtc_state *new_crtc_state,
+                                bool enable,
+                                bool *lock_and_validation_needed)
 {
         struct dm_atomic_state *dm_state = NULL;
-        struct drm_crtc *crtc;
-        struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-        int i;
         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
         struct dc_stream_state *new_stream;
         int ret = 0;
@@ -5405,200 +5393,203 @@ static int dm_update_crtcs_state(struct amdgpu_display_manager *dm,
          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
          * update changed items
          */
-        for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
-                struct amdgpu_crtc *acrtc = NULL;
-                struct amdgpu_dm_connector *aconnector = NULL;
-                struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
-                struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
-                struct drm_plane_state *new_plane_state = NULL;
-
-                new_stream = NULL;
+        struct amdgpu_crtc *acrtc = NULL;
+        struct amdgpu_dm_connector *aconnector = NULL;
+        struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
+        struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
+        struct drm_plane_state *new_plane_state = NULL;
 
-                dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
-                dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
-                acrtc = to_amdgpu_crtc(crtc);
+        new_stream = NULL;
 
-                new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
+        dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+        dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+        acrtc = to_amdgpu_crtc(crtc);
 
-                if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
-                        ret = -EINVAL;
-                        goto fail;
-                }
+        new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
 
-                aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
+        if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
+                ret = -EINVAL;
+                goto fail;
+        }
 
-                /* TODO This hack should go away */
-                if (aconnector && enable) {
-                        /* Make sure fake sink is created in plug-in scenario */
-                        drm_new_conn_state = drm_atomic_get_new_connector_state(state,
-                                                                    &aconnector->base);
-                        drm_old_conn_state = drm_atomic_get_old_connector_state(state,
-                                                                    &aconnector->base);
+        aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
 
-                        if (IS_ERR(drm_new_conn_state)) {
-                                ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
-                                break;
-                        }
+        /* TODO This hack should go away */
+        if (aconnector && enable) {
+                /* Make sure fake sink is created in plug-in scenario */
+                drm_new_conn_state = drm_atomic_get_new_connector_state(state,
+                                                            &aconnector->base);
+                drm_old_conn_state = drm_atomic_get_old_connector_state(state,
+                                                            &aconnector->base);
 
-                        dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
-                        dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
+                if (IS_ERR(drm_new_conn_state)) {
+                        ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
+                        goto fail;
+                }
 
-                        new_stream = create_stream_for_sink(aconnector,
-                                                             &new_crtc_state->mode,
-                                                            dm_new_conn_state,
-                                                            dm_old_crtc_state->stream);
+                dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
+                dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
 
-                        /*
-                         * we can have no stream on ACTION_SET if a display
-                         * was disconnected during S3, in this case it is not an
-                         * error, the OS will be updated after detection, and
-                         * will do the right thing on next atomic commit
-                         */
+                if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+                        goto skip_modeset;
 
-                        if (!new_stream) {
-                                DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
-                                                __func__, acrtc->base.base.id);
-                                break;
-                        }
+                new_stream = create_stream_for_sink(aconnector,
+                                                     &new_crtc_state->mode,
+                                                    dm_new_conn_state,
+                                                    dm_old_crtc_state->stream);
 
-                        dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
+                /*
+                 * we can have no stream on ACTION_SET if a display
+                 * was disconnected during S3, in this case it is not an
+                 * error, the OS will be updated after detection, and
+                 * will do the right thing on next atomic commit
+                 */
 
-                        if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
-                            dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
-                                new_crtc_state->mode_changed = false;
-                                DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
-                                                 new_crtc_state->mode_changed);
-                        }
+                if (!new_stream) {
+                        DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
+                                        __func__, acrtc->base.base.id);
+                        ret = -ENOMEM;
+                        goto fail;
                 }
 
-                if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
-                        goto next_crtc;
+                dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
 
-                DRM_DEBUG_DRIVER(
-                        "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
-                        "planes_changed:%d, mode_changed:%d,active_changed:%d,"
-                        "connectors_changed:%d\n",
-                        acrtc->crtc_id,
-                        new_crtc_state->enable,
-                        new_crtc_state->active,
-                        new_crtc_state->planes_changed,
-                        new_crtc_state->mode_changed,
-                        new_crtc_state->active_changed,
-                        new_crtc_state->connectors_changed);
+                if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
+                    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
+                        new_crtc_state->mode_changed = false;
+                        DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
+                                         new_crtc_state->mode_changed);
+                }
+        }
 
-                /* Remove stream for any changed/disabled CRTC */
-                if (!enable) {
+        /* mode_changed flag may get updated above, need to check again */
+        if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+                goto skip_modeset;
 
-                        if (!dm_old_crtc_state->stream)
-                                goto next_crtc;
+        DRM_DEBUG_DRIVER(
+                "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
+                "planes_changed:%d, mode_changed:%d,active_changed:%d,"
+                "connectors_changed:%d\n",
+                acrtc->crtc_id,
+                new_crtc_state->enable,
+                new_crtc_state->active,
+                new_crtc_state->planes_changed,
+                new_crtc_state->mode_changed,
+                new_crtc_state->active_changed,
+                new_crtc_state->connectors_changed);
 
-                        ret = dm_atomic_get_state(state, &dm_state);
-                        if (ret)
-                                goto fail;
+        /* Remove stream for any changed/disabled CRTC */
+        if (!enable) {
 
-                        DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
-                                        crtc->base.id);
+                if (!dm_old_crtc_state->stream)
+                        goto skip_modeset;
 
-                        /* i.e. reset mode */
-                        if (dc_remove_stream_from_ctx(
-                                        dm->dc,
-                                        dm_state->context,
-                                        dm_old_crtc_state->stream) != DC_OK) {
-                                ret = -EINVAL;
-                                goto fail;
-                        }
+                ret = dm_atomic_get_state(state, &dm_state);
+                if (ret)
+                        goto fail;
 
-                        dc_stream_release(dm_old_crtc_state->stream);
-                        dm_new_crtc_state->stream = NULL;
+                DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
+                                crtc->base.id);
 
-                        reset_freesync_config_for_crtc(dm_new_crtc_state);
+                /* i.e. reset mode */
+                if (dc_remove_stream_from_ctx(
+                                dm->dc,
+                                dm_state->context,
+                                dm_old_crtc_state->stream) != DC_OK) {
+                        ret = -EINVAL;
+                        goto fail;
+                }
 
-                        *lock_and_validation_needed = true;
+                dc_stream_release(dm_old_crtc_state->stream);
+                dm_new_crtc_state->stream = NULL;
 
-                } else {/* Add stream for any updated/enabled CRTC */
-                        /*
-                         * Quick fix to prevent NULL pointer on new_stream when
-                         * added MST connectors not found in existing crtc_state in the chained mode
-                         * TODO: need to dig out the root cause of that
-                         */
-                        if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
-                                goto next_crtc;
+                reset_freesync_config_for_crtc(dm_new_crtc_state);
 
-                        if (modereset_required(new_crtc_state))
-                                goto next_crtc;
+                *lock_and_validation_needed = true;
 
-                        if (modeset_required(new_crtc_state, new_stream,
-                                             dm_old_crtc_state->stream)) {
+        } else {/* Add stream for any updated/enabled CRTC */
+                /*
+                 * Quick fix to prevent NULL pointer on new_stream when
+                 * added MST connectors not found in existing crtc_state in the chained mode
+                 * TODO: need to dig out the root cause of that
+                 */
+                if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
+                        goto skip_modeset;
 
-                                WARN_ON(dm_new_crtc_state->stream);
+                if (modereset_required(new_crtc_state))
+                        goto skip_modeset;
 
-                                ret = dm_atomic_get_state(state, &dm_state);
-                                if (ret)
-                                        goto fail;
+                if (modeset_required(new_crtc_state, new_stream,
+                                     dm_old_crtc_state->stream)) {
 
-                                dm_new_crtc_state->stream = new_stream;
+                        WARN_ON(dm_new_crtc_state->stream);
 
-                                dc_stream_retain(new_stream);
+                        ret = dm_atomic_get_state(state, &dm_state);
+                        if (ret)
+                                goto fail;
 
-                                DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
-                                                        crtc->base.id);
+                        dm_new_crtc_state->stream = new_stream;
 
-                                if (dc_add_stream_to_ctx(
-                                                dm->dc,
-                                                dm_state->context,
-                                                dm_new_crtc_state->stream) != DC_OK) {
-                                        ret = -EINVAL;
-                                        goto fail;
-                                }
+                        dc_stream_retain(new_stream);
 
-                                *lock_and_validation_needed = true;
+                        DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
+                                                crtc->base.id);
+
+                        if (dc_add_stream_to_ctx(
+                                        dm->dc,
+                                        dm_state->context,
+                                        dm_new_crtc_state->stream) != DC_OK) {
+                                ret = -EINVAL;
+                                goto fail;
                         }
+
+                        *lock_and_validation_needed = true;
                 }
+        }
 
-next_crtc:
-                /* Release extra reference */
-                if (new_stream)
-                         dc_stream_release(new_stream);
+skip_modeset:
+        /* Release extra reference */
+        if (new_stream)
+                 dc_stream_release(new_stream);
 
-                /*
-                 * We want to do dc stream updates that do not require a
-                 * full modeset below.
-                 */
-                if (!(enable && aconnector && new_crtc_state->enable &&
-                      new_crtc_state->active))
-                        continue;
-                /*
-                 * Given above conditions, the dc state cannot be NULL because:
-                 * 1. We're in the process of enabling CRTCs (just been added
-                 *    to the dc context, or already is on the context)
-                 * 2. Has a valid connector attached, and
-                 * 3. Is currently active and enabled.
-                 * => The dc stream state currently exists.
-                 */
-                BUG_ON(dm_new_crtc_state->stream == NULL);
+        /*
+         * We want to do dc stream updates that do not require a
+         * full modeset below.
+         */
+        if (!(enable && aconnector && new_crtc_state->enable &&
+              new_crtc_state->active))
+                return 0;
+        /*
+         * Given above conditions, the dc state cannot be NULL because:
+         * 1. We're in the process of enabling CRTCs (just been added
+         *    to the dc context, or already is on the context)
+         * 2. Has a valid connector attached, and
+         * 3. Is currently active and enabled.
+         * => The dc stream state currently exists.
+         */
+        BUG_ON(dm_new_crtc_state->stream == NULL);
 
-                /* Scaling or underscan settings */
-                if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
-                        update_stream_scaling_settings(
-                                &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
+        /* Scaling or underscan settings */
+        if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
+                update_stream_scaling_settings(
+                        &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
 
-                /*
-                 * Color management settings. We also update color properties
-                 * when a modeset is needed, to ensure it gets reprogrammed.
-                 */
-                if (dm_new_crtc_state->base.color_mgmt_changed ||
-                    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
-                        ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
-                        if (ret)
-                                goto fail;
-                        amdgpu_dm_set_ctm(dm_new_crtc_state);
-                }
-
-                /* Update Freesync settings. */
-                get_freesync_config_for_crtc(dm_new_crtc_state,
-                                             dm_new_conn_state);
+        /*
+         * Color management settings. We also update color properties
+         * when a modeset is needed, to ensure it gets reprogrammed.
+         */
+        if (dm_new_crtc_state->base.color_mgmt_changed ||
+            drm_atomic_crtc_needs_modeset(new_crtc_state)) {
+                ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
+                if (ret)
+                        goto fail;
+                amdgpu_dm_set_ctm(dm_new_crtc_state);
         }
 
+        /* Update Freesync settings. */
+        get_freesync_config_for_crtc(dm_new_crtc_state,
+                                     dm_new_conn_state);
+
         return ret;
 
 fail:
@@ -5607,145 +5598,141 @@ fail:
         return ret;
 }
 
-static int dm_update_planes_state(struct dc *dc,
-                                  struct drm_atomic_state *state,
-                                  bool enable,
-                                  bool *lock_and_validation_needed)
+static int dm_update_plane_state(struct dc *dc,
+                                 struct drm_atomic_state *state,
+                                 struct drm_plane *plane,
+                                 struct drm_plane_state *old_plane_state,
+                                 struct drm_plane_state *new_plane_state,
+                                 bool enable,
+                                 bool *lock_and_validation_needed)
 {
 
         struct dm_atomic_state *dm_state = NULL;
         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
-        struct drm_plane *plane;
-        struct drm_plane_state *old_plane_state, *new_plane_state;
         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
-        int i ;
         /* TODO return page_flip_needed() function */
         bool pflip_needed  = !state->allow_modeset;
         int ret = 0;
 
 
-        /* Add new planes, in reverse order as DC expectation */
-        for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
-                new_plane_crtc = new_plane_state->crtc;
-                old_plane_crtc = old_plane_state->crtc;
-                dm_new_plane_state = to_dm_plane_state(new_plane_state);
-                dm_old_plane_state = to_dm_plane_state(old_plane_state);
+        new_plane_crtc = new_plane_state->crtc;
+        old_plane_crtc = old_plane_state->crtc;
+        dm_new_plane_state = to_dm_plane_state(new_plane_state);
+        dm_old_plane_state = to_dm_plane_state(old_plane_state);
 
-                /*TODO Implement atomic check for cursor plane */
-                if (plane->type == DRM_PLANE_TYPE_CURSOR)
-                        continue;
+        /*TODO Implement atomic check for cursor plane */
+        if (plane->type == DRM_PLANE_TYPE_CURSOR)
+                return 0;
 
-                /* Remove any changed/removed planes */
-                if (!enable) {
-                        if (pflip_needed &&
-                            plane->type != DRM_PLANE_TYPE_OVERLAY)
-                                continue;
+        /* Remove any changed/removed planes */
+        if (!enable) {
+                if (pflip_needed &&
+                    plane->type != DRM_PLANE_TYPE_OVERLAY)
+                        return 0;
 
-                        if (!old_plane_crtc)
-                                continue;
+                if (!old_plane_crtc)
+                        return 0;
 
-                        old_crtc_state = drm_atomic_get_old_crtc_state(
-                                        state, old_plane_crtc);
-                        dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+                old_crtc_state = drm_atomic_get_old_crtc_state(
+                                state, old_plane_crtc);
+                dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
 
-                        if (!dm_old_crtc_state->stream)
-                                continue;
+                if (!dm_old_crtc_state->stream)
+                        return 0;
 
-                        DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
-                                        plane->base.id, old_plane_crtc->base.id);
+                DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
+                                plane->base.id, old_plane_crtc->base.id);
 
-                        ret = dm_atomic_get_state(state, &dm_state);
-                        if (ret)
-                                return ret;
+                ret = dm_atomic_get_state(state, &dm_state);
+                if (ret)
+                        return ret;
 
-                        if (!dc_remove_plane_from_context(
-                                        dc,
-                                        dm_old_crtc_state->stream,
-                                        dm_old_plane_state->dc_state,
-                                        dm_state->context)) {
+                if (!dc_remove_plane_from_context(
+                                dc,
+                                dm_old_crtc_state->stream,
+                                dm_old_plane_state->dc_state,
+                                dm_state->context)) {
 
-                                ret = EINVAL;
-                                return ret;
-                        }
+                        ret = EINVAL;
+                        return ret;
+                }
 
 
-                        dc_plane_state_release(dm_old_plane_state->dc_state);
-                        dm_new_plane_state->dc_state = NULL;
+                dc_plane_state_release(dm_old_plane_state->dc_state);
+                dm_new_plane_state->dc_state = NULL;
 
-                        *lock_and_validation_needed = true;
+                *lock_and_validation_needed = true;
 
-                } else { /* Add new planes */
-                        struct dc_plane_state *dc_new_plane_state;
+        } else { /* Add new planes */
+                struct dc_plane_state *dc_new_plane_state;
 
-                        if (drm_atomic_plane_disabling(plane->state, new_plane_state))
-                                continue;
+                if (drm_atomic_plane_disabling(plane->state, new_plane_state))
+                        return 0;
 
-                        if (!new_plane_crtc)
-                                continue;
+                if (!new_plane_crtc)
+                        return 0;
 
-                        new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
-                        dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+                new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
+                dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 
-                        if (!dm_new_crtc_state->stream)
-                                continue;
+                if (!dm_new_crtc_state->stream)
+                        return 0;
 
-                        if (pflip_needed &&
-                            plane->type != DRM_PLANE_TYPE_OVERLAY)
-                                continue;
+                if (pflip_needed && plane->type != DRM_PLANE_TYPE_OVERLAY)
+                        return 0;
 
-                        WARN_ON(dm_new_plane_state->dc_state);
+                WARN_ON(dm_new_plane_state->dc_state);
 
-                        dc_new_plane_state = dc_create_plane_state(dc);
-                        if (!dc_new_plane_state)
-                                return -ENOMEM;
+                dc_new_plane_state = dc_create_plane_state(dc);
+                if (!dc_new_plane_state)
+                        return -ENOMEM;
 
-                        DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
-                                        plane->base.id, new_plane_crtc->base.id);
+                DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
+                                plane->base.id, new_plane_crtc->base.id);
 
-                        ret = fill_plane_attributes(
-                                new_plane_crtc->dev->dev_private,
-                                dc_new_plane_state,
-                                new_plane_state,
-                                new_crtc_state);
-                        if (ret) {
-                                dc_plane_state_release(dc_new_plane_state);
-                                return ret;
-                        }
+                ret = fill_plane_attributes(
+                        new_plane_crtc->dev->dev_private,
+                        dc_new_plane_state,
+                        new_plane_state,
+                        new_crtc_state);
+                if (ret) {
+                        dc_plane_state_release(dc_new_plane_state);
+                        return ret;
+                }
 
-                        ret = dm_atomic_get_state(state, &dm_state);
-                        if (ret) {
-                                dc_plane_state_release(dc_new_plane_state);
-                                return ret;
-                        }
+                ret = dm_atomic_get_state(state, &dm_state);
+                if (ret) {
+                        dc_plane_state_release(dc_new_plane_state);
+                        return ret;
+                }
 
-                        /*
-                         * Any atomic check errors that occur after this will
-                         * not need a release. The plane state will be attached
-                         * to the stream, and therefore part of the atomic
-                         * state. It'll be released when the atomic state is
-                         * cleaned.
-                         */
-                        if (!dc_add_plane_to_context(
-                                        dc,
-                                        dm_new_crtc_state->stream,
-                                        dc_new_plane_state,
-                                        dm_state->context)) {
-
-                                dc_plane_state_release(dc_new_plane_state);
-                                return -EINVAL;
-                        }
+                /*
+                 * Any atomic check errors that occur after this will
+                 * not need a release. The plane state will be attached
+                 * to the stream, and therefore part of the atomic
+                 * state. It'll be released when the atomic state is
+                 * cleaned.
+                 */
+                if (!dc_add_plane_to_context(
+                                dc,
+                                dm_new_crtc_state->stream,
+                                dc_new_plane_state,
+                                dm_state->context)) {
 
-                        dm_new_plane_state->dc_state = dc_new_plane_state;
+                        dc_plane_state_release(dc_new_plane_state);
+                        return -EINVAL;
+                }
 
-                        /* Tell DC to do a full surface update every time there
-                         * is a plane change. Inefficient, but works for now.
-                         */
-                        dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
+                dm_new_plane_state->dc_state = dc_new_plane_state;
 
-                        *lock_and_validation_needed = true;
-                }
+                /* Tell DC to do a full surface update every time there
+                 * is a plane change. Inefficient, but works for now.
+                 */
+                dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
+
+                *lock_and_validation_needed = true;
         }
 
 
@@ -5769,11 +5756,14 @@ dm_determine_update_type_for_commit(struct dc *dc,
         struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
         struct dc_stream_status *status = NULL;
 
-        struct dc_surface_update *updates = kzalloc(MAX_SURFACES * sizeof(struct dc_surface_update), GFP_KERNEL);
-        struct dc_plane_state *surface = kzalloc(MAX_SURFACES * sizeof(struct dc_plane_state), GFP_KERNEL);
+        struct dc_surface_update *updates;
+        struct dc_plane_state *surface;
         struct dc_stream_update stream_update;
         enum surface_update_type update_type = UPDATE_TYPE_FAST;
 
+        updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
+        surface = kcalloc(MAX_SURFACES, sizeof(*surface), GFP_KERNEL);
+
         if (!updates || !surface) {
                 DRM_ERROR("Plane or surface update failed to allocate");
                 /* Set type to FULL to avoid crashing in DC*/
@@ -5842,8 +5832,8 @@ dm_determine_update_type_for_commit(struct dc *dc,
                                         goto cleanup;
                                 }
 
-                                status = dc_state_get_stream_status(old_dm_state->context,
-                                                                    new_dm_crtc_state->stream);
+                                status = dc_stream_get_status_from_state(old_dm_state->context,
+                                                                         new_dm_crtc_state->stream);
 
                                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
                                                                                   &stream_update, status);
@@ -5903,6 +5893,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
         struct drm_connector_state *old_con_state, *new_con_state;
         struct drm_crtc *crtc;
         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+        struct drm_plane *plane;
+        struct drm_plane_state *old_plane_state, *new_plane_state;
         enum surface_update_type update_type = UPDATE_TYPE_FAST;
         enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
 
@@ -5921,7 +5913,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
                     !new_crtc_state->color_mgmt_changed &&
-                    !new_crtc_state->vrr_enabled)
+                    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
                         continue;
 
                 if (!new_crtc_state->enable)
@@ -5937,27 +5929,47 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
         }
 
         /* Remove exiting planes if they are modified */
-        ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
-        if (ret) {
-                goto fail;
+        for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
+                ret = dm_update_plane_state(dc, state, plane,
+                                            old_plane_state,
+                                            new_plane_state,
+                                            false,
+                                            &lock_and_validation_needed);
+                if (ret)
+                        goto fail;
         }
 
         /* Disable all crtcs which require disable */
-        ret = dm_update_crtcs_state(&adev->dm, state, false, &lock_and_validation_needed);
-        if (ret) {
-                goto fail;
+        for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+                ret = dm_update_crtc_state(&adev->dm, state, crtc,
+                                           old_crtc_state,
+                                           new_crtc_state,
+                                           false,
+                                           &lock_and_validation_needed);
+                if (ret)
+                        goto fail;
         }
 
         /* Enable all crtcs which require enable */
-        ret = dm_update_crtcs_state(&adev->dm, state, true, &lock_and_validation_needed);
-        if (ret) {
-                goto fail;
+        for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+                ret = dm_update_crtc_state(&adev->dm, state, crtc,
+                                           old_crtc_state,
+                                           new_crtc_state,
+                                           true,
+                                           &lock_and_validation_needed);
+                if (ret)
+                        goto fail;
         }
 
         /* Add new/modified planes */
-        ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
-        if (ret) {
-                goto fail;
+        for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
+                ret = dm_update_plane_state(dc, state, plane,
+                                            old_plane_state,
+                                            new_plane_state,
+                                            true,
+                                            &lock_and_validation_needed);
+                if (ret)
+                        goto fail;
         }
 
         /* Run this here since we want to validate the streams we created */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 9a7ac58eb18e..cca3e16cda4f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -783,6 +783,45 @@ static ssize_t dtn_log_write(
         return size;
 }
 
+/*
+ * Backlight at this moment.  Read only.
+ * As written to display, taking ABM and backlight lut into account.
+ * Ranges from 0x0 to 0x10000 (= 100% PWM)
+ */
+static int current_backlight_read(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *)m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct amdgpu_device *adev = dev->dev_private;
+        struct dc *dc = adev->dm.dc;
+        unsigned int backlight = dc_get_current_backlight_pwm(dc);
+
+        seq_printf(m, "0x%x\n", backlight);
+        return 0;
+}
+
+/*
+ * Backlight value that is being approached.  Read only.
+ * As written to display, taking ABM and backlight lut into account.
+ * Ranges from 0x0 to 0x10000 (= 100% PWM)
+ */
+static int target_backlight_read(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *)m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct amdgpu_device *adev = dev->dev_private;
+        struct dc *dc = adev->dm.dc;
+        unsigned int backlight = dc_get_target_backlight_pwm(dc);
+
+        seq_printf(m, "0x%x\n", backlight);
+        return 0;
+}
+
+static const struct drm_info_list amdgpu_dm_debugfs_list[] = {
+        {"amdgpu_current_backlight_pwm", &current_backlight_read},
+        {"amdgpu_target_backlight_pwm", &target_backlight_read},
+};
+
 int dtn_debugfs_init(struct amdgpu_device *adev)
 {
         static const struct file_operations dtn_log_fops = {
@@ -793,9 +832,15 @@ int dtn_debugfs_init(struct amdgpu_device *adev)
         };
 
         struct drm_minor *minor = adev->ddev->primary;
-        struct dentry *root = minor->debugfs_root;
+        struct dentry *ent, *root = minor->debugfs_root;
+        int ret;
+
+        ret = amdgpu_debugfs_add_files(adev, amdgpu_dm_debugfs_list,
+                                ARRAY_SIZE(amdgpu_dm_debugfs_list));
+        if (ret)
+                return ret;
 
-        struct dentry *ent = debugfs_create_file(
+        ent = debugfs_create_file(
                 "amdgpu_dm_dtn_log",
                 0644,
                 root,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 39997d977efb..e6ab0186955c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -192,7 +192,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
         int bpp = 0;
         int pbn = 0;
 
-        aconnector = stream->sink->priv;
+        aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 
         if (!aconnector || !aconnector->mst_port)
                 return false;
@@ -205,7 +205,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
         mst_port = aconnector->port;
 
         if (enable) {
-                clock = stream->timing.pix_clk_khz;
+                clock = stream->timing.pix_clk_100hz / 10;
 
                 switch (stream->timing.display_color_depth) {
 
@@ -284,7 +284,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger(
         struct drm_dp_mst_topology_mgr *mst_mgr;
         int ret;
 
-        aconnector = stream->sink->priv;
+        aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 
         if (!aconnector || !aconnector->mst_port)
                 return false;
@@ -312,7 +312,7 @@ bool dm_helpers_dp_mst_send_payload_allocation(
         struct drm_dp_mst_port *mst_port;
         int ret;
 
-        aconnector = stream->sink->priv;
+        aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 
         if (!aconnector || !aconnector->mst_port)
                 return false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 24632727e127..748d6ff3e4f3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -35,6 +35,8 @@
 
 #include "dc_link_ddc.h"
 
+#include "i2caux_interface.h"
+
 /* #define TRACE_DPCD */
 
 #ifdef TRACE_DPCD
@@ -81,80 +83,24 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
                                   struct drm_dp_aux_msg *msg)
 {
         ssize_t result = 0;
-        enum i2caux_transaction_action action;
-        enum aux_transaction_type type;
+        struct aux_payload payload;
 
         if (WARN_ON(msg->size > 16))
                 return -E2BIG;
 
-        switch (msg->request & ~DP_AUX_I2C_MOT) {
-        case DP_AUX_NATIVE_READ:
-                type = AUX_TRANSACTION_TYPE_DP;
-                action = I2CAUX_TRANSACTION_ACTION_DP_READ;
-
-                result = dc_link_aux_transfer(TO_DM_AUX(aux)->ddc_service,
-                                              msg->address,
-                                              &msg->reply,
-                                              msg->buffer,
-                                              msg->size,
-                                              type,
-                                              action);
-                break;
-        case DP_AUX_NATIVE_WRITE:
-                type = AUX_TRANSACTION_TYPE_DP;
-                action = I2CAUX_TRANSACTION_ACTION_DP_WRITE;
-
-                dc_link_aux_transfer(TO_DM_AUX(aux)->ddc_service,
-                                     msg->address,
-                                     &msg->reply,
-                                     msg->buffer,
-                                     msg->size,
-                                     type,
-                                     action);
-                result = msg->size;
-                break;
-        case DP_AUX_I2C_READ:
-                type = AUX_TRANSACTION_TYPE_I2C;
-                if (msg->request & DP_AUX_I2C_MOT)
-                        action = I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT;
-                else
-                        action = I2CAUX_TRANSACTION_ACTION_I2C_READ;
-
-                result = dc_link_aux_transfer(TO_DM_AUX(aux)->ddc_service,
-                                              msg->address,
-                                              &msg->reply,
-                                              msg->buffer,
-                                              msg->size,
-                                              type,
-                                              action);
-                break;
-        case DP_AUX_I2C_WRITE:
-                type = AUX_TRANSACTION_TYPE_I2C;
-                if (msg->request & DP_AUX_I2C_MOT)
-                        action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT;
-                else
-                        action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-
-                dc_link_aux_transfer(TO_DM_AUX(aux)->ddc_service,
-                                     msg->address,
-                                     &msg->reply,
-                                     msg->buffer,
-                                     msg->size,
-                                     type,
-                                     action);
-                result = msg->size;
-                break;
-        default:
-                return -EINVAL;
-        }
+        payload.address = msg->address;
+        payload.data = msg->buffer;
+        payload.length = msg->size;
+        payload.reply = &msg->reply;
+        payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
+        payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
+        payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
+        payload.defer_delay = 0;
 
-#ifdef TRACE_DPCD
-        log_dpcd(msg->request,
-                 msg->address,
-                 msg->buffer,
-                 msg->size,
-                 r == DDC_RESULT_SUCESSFULL);
-#endif
+        result = dc_link_aux_transfer(TO_DM_AUX(aux)->ddc_service, &payload);
+
+        if (payload.write)
+                result = msg->size;
 
         if (result < 0) /* DC doesn't know about kernel error codes */
                 result = -EIO;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 9d2d6986b983..e8e9eebbae3f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -559,6 +559,58 @@ void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
         pp_funcs->notify_smu_enable_pwe(pp_handle);
 }
 
+void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
+{
+        const struct dc_context *ctx = pp->dm;
+        struct amdgpu_device *adev = ctx->driver_context;
+        void *pp_handle = adev->powerplay.pp_handle;
+        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+        if (!pp_funcs || !pp_funcs->set_active_display_count)
+                return;
+
+        pp_funcs->set_active_display_count(pp_handle, count);
+}
+
+void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
+{
+        const struct dc_context *ctx = pp->dm;
+        struct amdgpu_device *adev = ctx->driver_context;
+        void *pp_handle = adev->powerplay.pp_handle;
+        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+        if (!pp_funcs || !pp_funcs->set_min_deep_sleep_dcefclk)
+                return;
+
+        pp_funcs->set_min_deep_sleep_dcefclk(pp_handle, clock);
+}
+
+void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
+{
+        const struct dc_context *ctx = pp->dm;
+        struct amdgpu_device *adev = ctx->driver_context;
+        void *pp_handle = adev->powerplay.pp_handle;
+        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+        if (!pp_funcs || !pp_funcs->set_hard_min_dcefclk_by_freq)
+                return;
+
+        pp_funcs->set_hard_min_dcefclk_by_freq(pp_handle, clock);
+}
+
+void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
+{
+        const struct dc_context *ctx = pp->dm;
+        struct amdgpu_device *adev = ctx->driver_context;
+        void *pp_handle = adev->powerplay.pp_handle;
+        const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+        if (!pp_funcs || !pp_funcs->set_hard_min_fclk_by_freq)
+                return;
+
+        pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz);
+}
+
 void dm_pp_get_funcs_rv(
                 struct dc_context *ctx,
                 struct pp_smu_funcs_rv *funcs)
@@ -567,4 +619,9 @@ void dm_pp_get_funcs_rv(
         funcs->set_display_requirement = pp_rv_set_display_requirement;
         funcs->set_wm_ranges = pp_rv_set_wm_ranges;
         funcs->set_pme_wa_enable = pp_rv_set_pme_wa_enable;
+        funcs->set_display_count = pp_rv_set_active_display_count;
+        funcs->set_min_deep_sleep_dcfclk = pp_rv_set_min_deep_sleep_dcfclk;
+        funcs->set_hard_min_dcfclk_by_freq = pp_rv_set_hard_min_dcefclk_by_freq;
+        funcs->set_hard_min_fclk_by_freq = pp_rv_set_hard_min_fclk_by_freq;
 }
+
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index aed538a4d1ba..b8ddb4acccdb 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -23,7 +23,7 @@
 # Makefile for Display Core (dc) component.
 #
 
-DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
+DC_LIBS = basics bios calcs dce gpio irq virtual
 
 ifdef CONFIG_DRM_AMD_DC_DCN1_0
 DC_LIBS += dcn10 dml
@@ -41,7 +41,8 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI
 include $(AMD_DC)
 
 DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
-dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
+dc_vm_helper.o
 
 AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index c2ab026aee91..a4c97d32e751 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -835,18 +835,6 @@ static enum bp_result bios_parser_enable_crtc(
         return bp->cmd_tbl.enable_crtc(bp, id, enable);
 }
 
-static enum bp_result bios_parser_crtc_source_select(
-        struct dc_bios *dcb,
-        struct bp_crtc_source_select *bp_params)
-{
-        struct bios_parser *bp = BP_FROM_DCB(dcb);
-
-        if (!bp->cmd_tbl.select_crtc_source)
-                return BP_RESULT_FAILURE;
-
-        return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-}
-
 static enum bp_result bios_parser_enable_disp_power_gating(
         struct dc_bios *dcb,
         enum controller_id controller_id,
@@ -2842,8 +2830,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
 
         .program_crtc_timing = bios_parser_program_crtc_timing, /* still use.  should probably retire and program directly */
 
-        .crtc_source_select = bios_parser_crtc_source_select,  /* still use.  should probably retire and program directly */
-
         .program_display_engine_pll = bios_parser_program_display_engine_pll,
 
         .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index c513ab6f3843..a1c56f29cfeb 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1083,18 +1083,6 @@ static enum bp_result bios_parser_enable_crtc(
         return bp->cmd_tbl.enable_crtc(bp, id, enable);
 }
 
-static enum bp_result bios_parser_crtc_source_select(
-        struct dc_bios *dcb,
-        struct bp_crtc_source_select *bp_params)
-{
-        struct bios_parser *bp = BP_FROM_DCB(dcb);
-
-        if (!bp->cmd_tbl.select_crtc_source)
-                return BP_RESULT_FAILURE;
-
-        return bp->cmd_tbl.select_crtc_source(bp, bp_params);
-}
-
 static enum bp_result bios_parser_enable_disp_power_gating(
         struct dc_bios *dcb,
         enum controller_id controller_id,
@@ -1899,8 +1887,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
 
         .is_accelerated_mode = bios_parser_is_accelerated_mode,
 
-        .is_active_display = bios_is_active_display,
-
         .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
 
 
@@ -1917,8 +1903,6 @@ static const struct dc_vbios_funcs vbios_funcs = {
 
         .program_crtc_timing = bios_parser_program_crtc_timing,
 
-        .crtc_source_select = bios_parser_crtc_source_select,
-
         .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
 
         .bios_parser_destroy = firmware_parser_destroy,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index fdda8aa8e303..fce46ab54c54 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -83,101 +83,7 @@ uint32_t bios_get_vga_enabled_displays(
 {
         uint32_t active_disp = 1;
 
-        if (bios->regs->BIOS_SCRATCH_3) /*follow up with other asic, todo*/
-                active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF;
+        active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF;
         return active_disp;
 }
 
-bool bios_is_active_display(
-                struct dc_bios *bios,
-                enum signal_type signal,
-                const struct connector_device_tag_info *device_tag)
-{
-        uint32_t active = 0;
-        uint32_t connected = 0;
-        uint32_t bios_scratch_0 = 0;
-        uint32_t bios_scratch_3 = 0;
-
-        switch (signal) {
-        case SIGNAL_TYPE_DVI_SINGLE_LINK:
-        case SIGNAL_TYPE_DVI_DUAL_LINK:
-        case SIGNAL_TYPE_HDMI_TYPE_A:
-        case SIGNAL_TYPE_DISPLAY_PORT:
-        case SIGNAL_TYPE_DISPLAY_PORT_MST:
-                {
-                        if (device_tag->dev_id.device_type == DEVICE_TYPE_DFP) {
-                                switch (device_tag->dev_id.enum_id)     {
-                                case 1:
-                                        {
-                                                active    = ATOM_S3_DFP1_ACTIVE;
-                                                connected = 0x0008;     //ATOM_DISPLAY_DFP1_CONNECT
-                                        }
-                                        break;
-
-                                case 2:
-                                        {
-                                                active    = ATOM_S3_DFP2_ACTIVE;
-                                                connected = 0x0080; //ATOM_DISPLAY_DFP2_CONNECT
-                                        }
-                                        break;
-
-                                case 3:
-                                        {
-                                                active    = ATOM_S3_DFP3_ACTIVE;
-                                                connected = 0x0200; //ATOM_DISPLAY_DFP3_CONNECT
-                                        }
-                                        break;
-
-                                case 4:
-                                        {
-                                                active    = ATOM_S3_DFP4_ACTIVE;
-                                                connected = 0x0400;     //ATOM_DISPLAY_DFP4_CONNECT
-                                        }
-                                        break;
-
-                                case 5:
-                                        {
-                                                active    = ATOM_S3_DFP5_ACTIVE;
-                                                connected = 0x0800; //ATOM_DISPLAY_DFP5_CONNECT
-                                        }
-                                        break;
-
-                                case 6:
-                                        {
-                                                active    = ATOM_S3_DFP6_ACTIVE;
-                                                connected = 0x0040; //ATOM_DISPLAY_DFP6_CONNECT
-                                        }
-                                        break;
-
-                                default:
-                                        break;
-                                }
-                                }
-                        }
-                        break;
-
-        case SIGNAL_TYPE_LVDS:
-        case SIGNAL_TYPE_EDP:
-                {
-                        active    = ATOM_S3_LCD1_ACTIVE;
-                        connected = 0x0002;     //ATOM_DISPLAY_LCD1_CONNECT
-                }
-                break;
-
-        default:
-                break;
-        }
-
-
-        if (bios->regs->BIOS_SCRATCH_0) /*follow up with other asic, todo*/
-                bios_scratch_0 = REG_READ(BIOS_SCRATCH_0);
-        if (bios->regs->BIOS_SCRATCH_3) /*follow up with other asic, todo*/
-                bios_scratch_3 = REG_READ(BIOS_SCRATCH_3);
-
-        bios_scratch_3 &= ATOM_S3_DEVICE_ACTIVE_MASK;
-        if ((active & bios_scratch_3) && (connected & bios_scratch_0))
-                return true;
-
-        return false;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
index f33cac2147e3..75a29e68fb27 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h
@@ -35,10 +35,6 @@ bool bios_is_accelerated_mode(struct dc_bios *bios);
 void bios_set_scratch_acc_mode_change(struct dc_bios *bios);
 void bios_set_scratch_critical_state(struct dc_bios *bios, bool state);
 uint32_t bios_get_vga_enabled_displays(struct dc_bios *bios);
-bool bios_is_active_display(
-        struct dc_bios *bios,
-        enum signal_type signal,
-        const struct connector_device_tag_info *device_tag);
 
 #define GET_IMAGE(type, offset) ((type *) bios_get_image(&bp->base, offset, sizeof(type)))
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 2bd7cd97e00d..5815983caaf8 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -55,7 +55,6 @@ static void init_adjust_display_pll(struct bios_parser *bp);
 static void init_dac_encoder_control(struct bios_parser *bp);
 static void init_dac_output_control(struct bios_parser *bp);
 static void init_set_crtc_timing(struct bios_parser *bp);
-static void init_select_crtc_source(struct bios_parser *bp);
 static void init_enable_crtc(struct bios_parser *bp);
 static void init_enable_crtc_mem_req(struct bios_parser *bp);
 static void init_external_encoder_control(struct bios_parser *bp);
@@ -73,7 +72,6 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
         init_dac_encoder_control(bp);
         init_dac_output_control(bp);
         init_set_crtc_timing(bp);
-        init_select_crtc_source(bp);
         init_enable_crtc(bp);
         init_enable_crtc_mem_req(bp);
         init_program_clock(bp);
@@ -964,9 +962,9 @@ static enum bp_result set_pixel_clock_v3(
         allocation.sPCLKInput.ucPostDiv =
                         (uint8_t)bp_params->pixel_clock_post_divider;
 
-        /* We need to convert from KHz units into 10KHz units */
+        /* We need to convert from 100Hz units into 10KHz units */
         allocation.sPCLKInput.usPixelClock =
-                        cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
+                        cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
 
         params = (PIXEL_CLOCK_PARAMETERS_V3 *)&allocation.sPCLKInput;
         params->ucTransmitterId =
@@ -1042,9 +1040,9 @@ static enum bp_result set_pixel_clock_v5(
                                 (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
                                                 bp_params->signal_type, false);
 
-                /* We need to convert from KHz units into 10KHz units */
+                /* We need to convert from 100Hz units into 10KHz units */
                 clk.sPCLKInput.usPixelClock =
-                                cpu_to_le16((uint16_t)(bp_params->target_pixel_clock / 10));
+                                cpu_to_le16((uint16_t)(bp_params->target_pixel_clock_100hz / 100));
 
                 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
                         clk.sPCLKInput.ucMiscInfo |=
@@ -1118,9 +1116,9 @@ static enum bp_result set_pixel_clock_v6(
                                 (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(
                                                 bp_params->signal_type, false);
 
-                /* We need to convert from KHz units into 10KHz units */
+                /* We need to convert from 100 Hz units into 10KHz units */
                 clk.sPCLKInput.ulCrtcPclkFreq.ulPixelClock =
-                                cpu_to_le32(bp_params->target_pixel_clock / 10);
+                                cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
 
                 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) {
                         clk.sPCLKInput.ucMiscInfo |=
@@ -1182,8 +1180,7 @@ static enum bp_result set_pixel_clock_v7(
                 clk.ucTransmitterID = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
                 clk.ucEncoderMode = (uint8_t) bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
 
-                /* We need to convert from KHz units into 10KHz units */
-                clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock * 10);
+                clk.ulPixelClock = cpu_to_le32(bp_params->target_pixel_clock_100hz);
 
                 clk.ucDeepColorRatio = (uint8_t) bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
 
@@ -1899,120 +1896,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
 /*******************************************************************************
  ********************************************************************************
  **
- **                  SELECT CRTC SOURCE
- **
- ********************************************************************************
- *******************************************************************************/
-
-static enum bp_result select_crtc_source_v2(
-        struct bios_parser *bp,
-        struct bp_crtc_source_select *bp_params);
-static enum bp_result select_crtc_source_v3(
-        struct bios_parser *bp,
-        struct bp_crtc_source_select *bp_params);
-
-static void init_select_crtc_source(struct bios_parser *bp)
-{
-        switch (BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source)) {
-        case 2:
-                bp->cmd_tbl.select_crtc_source = select_crtc_source_v2;
-                break;
-        case 3:
-                bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
-                break;
-        default:
-                dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
-                         BIOS_CMD_TABLE_PARA_REVISION(SelectCRTC_Source));
-                bp->cmd_tbl.select_crtc_source = NULL;
-                break;
-        }
-}
-
-static enum bp_result select_crtc_source_v2(
-        struct bios_parser *bp,
-        struct bp_crtc_source_select *bp_params)
-{
-        enum bp_result result = BP_RESULT_FAILURE;
-        SELECT_CRTC_SOURCE_PARAMETERS_V2 params;
-        uint8_t atom_controller_id;
-        uint32_t atom_engine_id;
-        enum signal_type s = bp_params->signal;
-
-        memset(&params, 0, sizeof(params));
-
-        /* set controller id */
-        if (bp->cmd_helper->controller_id_to_atom(
-                        bp_params->controller_id, &atom_controller_id))
-                params.ucCRTC = atom_controller_id;
-        else
-                return BP_RESULT_FAILURE;
-
-        /* set encoder id */
-        if (bp->cmd_helper->engine_bp_to_atom(
-                        bp_params->engine_id, &atom_engine_id))
-                params.ucEncoderID = (uint8_t)atom_engine_id;
-        else
-                return BP_RESULT_FAILURE;
-
-        if (SIGNAL_TYPE_EDP == s ||
-                        (SIGNAL_TYPE_DISPLAY_PORT == s &&
-                                        SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-                s = SIGNAL_TYPE_LVDS;
-
-        params.ucEncodeMode =
-                        (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(
-                                        s, bp_params->enable_dp_audio);
-
-        if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-                result = BP_RESULT_OK;
-
-        return result;
-}
-
-static enum bp_result select_crtc_source_v3(
-        struct bios_parser *bp,
-        struct bp_crtc_source_select *bp_params)
-{
-        bool result = BP_RESULT_FAILURE;
-        SELECT_CRTC_SOURCE_PARAMETERS_V3 params;
-        uint8_t atom_controller_id;
-        uint32_t atom_engine_id;
-        enum signal_type s = bp_params->signal;
-
-        memset(&params, 0, sizeof(params));
-
-        if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-                        &atom_controller_id))
-                params.ucCRTC = atom_controller_id;
-        else
-                return result;
-
-        if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
-                        &atom_engine_id))
-                params.ucEncoderID = (uint8_t)atom_engine_id;
-        else
-                return result;
-
-        if (SIGNAL_TYPE_EDP == s ||
-                        (SIGNAL_TYPE_DISPLAY_PORT == s &&
-                                        SIGNAL_TYPE_LVDS == bp_params->sink_signal))
-                s = SIGNAL_TYPE_LVDS;
-
-        params.ucEncodeMode =
-                        bp->cmd_helper->encoder_mode_bp_to_atom(
-                                        s, bp_params->enable_dp_audio);
-        /* Needed for VBIOS Random Spatial Dithering feature */
-        params.ucDstBpc = (uint8_t)(bp_params->display_output_bit_depth);
-
-        if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
-                result = BP_RESULT_OK;
-
-        return result;
-}
-
-/*******************************************************************************
- ********************************************************************************
- **
  **                  ENABLE CRTC
  **
  ********************************************************************************
@@ -2164,7 +2047,7 @@ static enum bp_result program_clock_v5(
         /* We need to convert from KHz units into 10KHz units */
         params.sPCLKInput.ucPpll = (uint8_t) atom_pll_id;
         params.sPCLKInput.usPixelClock =
-                        cpu_to_le16((uint16_t) (bp_params->target_pixel_clock / 10));
+                        cpu_to_le16((uint16_t) (bp_params->target_pixel_clock_100hz / 100));
         params.sPCLKInput.ucCRTC = (uint8_t) ATOM_CRTC_INVALID;
 
         if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
@@ -2196,7 +2079,7 @@ static enum bp_result program_clock_v6(
         /* We need to convert from KHz units into 10KHz units */
         params.sPCLKInput.ucPpll = (uint8_t)atom_pll_id;
         params.sPCLKInput.ulDispEngClkFreq =
-                        cpu_to_le32(bp_params->target_pixel_clock / 10);
+                        cpu_to_le32(bp_params->target_pixel_clock_100hz / 100);
 
         if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
                 params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.h b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
index 94f3d43a7471..ad533775e724 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.h
@@ -71,9 +71,6 @@ struct cmd_tbl {
         enum bp_result (*set_crtc_timing)(
                 struct bios_parser *bp,
                 struct bp_hw_crtc_timing_parameters *bp_params);
-        enum bp_result (*select_crtc_source)(
-                struct bios_parser *bp,
-                struct bp_crtc_source_select *bp_params);
         enum bp_result (*enable_crtc)(
                 struct bios_parser *bp,
                 enum controller_id controller_id,
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index 2b5dc499a35e..bb2e8105e6ab 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -301,17 +301,17 @@ static enum bp_result set_pixel_clock_v7(
                         cmd_helper->encoder_mode_bp_to_atom(
                                 bp_params->signal_type, false);
 
-                /* We need to convert from KHz units into 10KHz units */
-                clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock *
-                                10);
+                clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock_100hz);
 
                 clk.deep_color_ratio =
                         (uint8_t) bp->cmd_helper->
                                 transmitter_color_depth_to_atom(
                                         bp_params->color_depth);
-                DC_LOG_BIOS("%s:program display clock = %d"\
-                                "colorDepth = %d\n", __func__,\
-                                bp_params->target_pixel_clock, bp_params->color_depth);
+
+                DC_LOG_BIOS("%s:program display clock = %d, tg = %d, pll = %d, "\
+                                "colorDepth = %d\n", __func__,
+                                bp_params->target_pixel_clock_100hz, (int)controller_id,
+                                pll_id, bp_params->color_depth);
 
                 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL)
                         clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
@@ -463,75 +463,6 @@ static enum bp_result set_crtc_using_dtd_timing_v3(
 /******************************************************************************
  ******************************************************************************
  **
- **                  SELECT CRTC SOURCE
- **
- ******************************************************************************
- *****************************************************************************/
-
-
-static enum bp_result select_crtc_source_v3(
-        struct bios_parser *bp,
-        struct bp_crtc_source_select *bp_params);
-
-static void init_select_crtc_source(struct bios_parser *bp)
-{
-        switch (BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)) {
-        case 3:
-                bp->cmd_tbl.select_crtc_source = select_crtc_source_v3;
-                break;
-        default:
-                dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n",
-                         BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source));
-                bp->cmd_tbl.select_crtc_source = NULL;
-                break;
-        }
-}
-
-
-static enum bp_result select_crtc_source_v3(
-        struct bios_parser *bp,
-        struct bp_crtc_source_select *bp_params)
-{
-        bool result = BP_RESULT_FAILURE;
-        struct select_crtc_source_parameters_v2_3 params;
-        uint8_t atom_controller_id;
-        uint32_t atom_engine_id;
-        enum signal_type s = bp_params->signal;
-
-        memset(&params, 0, sizeof(params));
-
-        if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
-                        &atom_controller_id))
-                params.crtc_id = atom_controller_id;
-        else
-                return result;
-
-        if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id,
-                        &atom_engine_id))
-                params.encoder_id = (uint8_t)atom_engine_id;
-        else
-                return result;
-
-        if (s == SIGNAL_TYPE_EDP ||
-                (s == SIGNAL_TYPE_DISPLAY_PORT && bp_params->sink_signal ==
-                                                        SIGNAL_TYPE_LVDS))
-                s = SIGNAL_TYPE_LVDS;
-
-        params.encode_mode =
-                        bp->cmd_helper->encoder_mode_bp_to_atom(
-                                        s, bp_params->enable_dp_audio);
-        /* Needed for VBIOS Random Spatial Dithering feature */
-        params.dst_bpc = (uint8_t)(bp_params->display_output_bit_depth);
-
-        if (EXEC_BIOS_CMD_TABLE(selectcrtc_source, params))
-                result = BP_RESULT_OK;
-
-        return result;
-}
-
-/******************************************************************************
- ******************************************************************************
- **
  **                  ENABLE CRTC
  **
  ******************************************************************************
@@ -808,7 +739,6 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
 
         init_set_crtc_timing(bp);
 
-        init_select_crtc_source(bp);
         init_enable_crtc(bp);
 
         init_external_encoder_control(bp);
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
index ec1c0c9f3f1d..7a2af24dfe60 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.h
@@ -71,9 +71,6 @@ struct cmd_tbl {
         enum bp_result (*set_crtc_timing)(
                 struct bios_parser *bp,
                 struct bp_hw_crtc_timing_parameters *bp_params);
-        enum bp_result (*select_crtc_source)(
-                struct bios_parser *bp,
-                struct bp_crtc_source_select *bp_params);
         enum bp_result (*enable_crtc)(
                 struct bios_parser *bp,
                 enum controller_id controller_id,
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
index 95f332ee3e7e..dc85a3c088af 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
@@ -30,7 +30,7 @@ else ifneq ($(call cc-option, -mstack-alignment=16),)
         cc_stack_align := -mstack-alignment=16
 endif
 
-calcs_ccflags := -mhard-float -msse $(cc_stack_align)
+calcs_ccflags := -mhard-float -msse -msse2 $(cc_stack_align)
 
 CFLAGS_dcn_calcs.o := $(calcs_ccflags)
 CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 9ebe30ba4dab..f3aa7b53d2aa 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -2792,7 +2792,7 @@ static void populate_initial_data(
                 data->lpt_en[num_displays + 4] = false;
                 data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
                 data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
-                data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
+                data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_100hz, 10000);
                 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
                 data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
                 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
@@ -2881,7 +2881,7 @@ static void populate_initial_data(
 
         /* Pipes without underlay after */
         for (i = 0; i < pipe_count; i++) {
-                unsigned int pixel_clock_khz;
+                unsigned int pixel_clock_100hz;
                 if (!pipe[i].stream || pipe[i].bottom_pipe)
                         continue;
 
@@ -2890,10 +2890,10 @@ static void populate_initial_data(
                 data->lpt_en[num_displays + 4] = false;
                 data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
                 data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
-                pixel_clock_khz = pipe[i].stream->timing.pix_clk_khz;
+                pixel_clock_100hz = pipe[i].stream->timing.pix_clk_100hz;
                 if (pipe[i].stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
-                        pixel_clock_khz *= 2;
-                data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pixel_clock_khz, 1000);
+                        pixel_clock_100hz *= 2;
+                data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pixel_clock_100hz, 10000);
                 if (pipe[i].plane_state) {
                         data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
                         data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
index d0fc54f8fb1c..7d102ac0d61b 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -797,9 +797,40 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
                                 else {
                                         v->maximum_vstartup = v->v_sync_plus_back_porch[k] - 1.0;
                                 }
-                                v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]);
-                                v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4;
-                                v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
+
+                                do {
+                                        v->line_times_for_prefetch[k] = v->maximum_vstartup - v->urgent_latency / (v->htotal[k] / v->pixel_clock[k]) - (v->time_calc + v->time_setup) / (v->htotal[k] / v->pixel_clock[k]) - (v->dst_y_after_scaler + v->dst_x_after_scaler / v->htotal[k]);
+                                        v->line_times_for_prefetch[k] =dcn_bw_floor2(4.0 * (v->line_times_for_prefetch[k] + 0.125), 1.0) / 4;
+                                        v->prefetch_bw[k] = (v->meta_pte_bytes_per_frame[k] + 2.0 * v->meta_row_bytes[k] + 2.0 * v->dpte_bytes_per_row[k] + v->prefetch_lines_y[k] * v->swath_width_yper_state[i][j][k] *dcn_bw_ceil2(v->byte_per_pixel_in_dety[k], 1.0) + v->prefetch_lines_c[k] * v->swath_width_yper_state[i][j][k] / 2.0 *dcn_bw_ceil2(v->byte_per_pixel_in_detc[k], 2.0)) / (v->line_times_for_prefetch[k] * v->htotal[k] / v->pixel_clock[k]);
+
+                                        if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
+                                                v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
+                                                                v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k],
+                                                                v->extra_latency,
+                                                                v->htotal[k] / v->pixel_clock[k] / 4.0);
+                                        } else {
+                                                v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
+                                        }
+
+                                        if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
+                                                v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max3((
+                                                                v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bandwidth[k],
+                                                                v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
+                                                                v->extra_latency);
+                                        } else {
+                                                v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max2(
+                                                                v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,
+                                                                v->extra_latency - v->time_for_meta_pte_with_immediate_flip);
+                                        }
+
+                                        v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
+                                        v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
+                                        v->maximum_vstartup = v->maximum_vstartup - 1;
+
+                                        if (v->lines_for_meta_pte_without_immediate_flip[k] < 8.0 && v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
+                                                break;
+
+                                } while(1);
                         }
                         v->bw_available_for_immediate_flip = v->return_bw_per_state[i];
                         for (k = 0; k <= v->number_of_active_planes - 1; k++) {
@@ -814,24 +845,18 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v)
                         for (k = 0; k <= v->number_of_active_planes - 1; k++) {
                                 if (v->pte_enable == dcn_bw_yes && v->dcc_enable[k] == dcn_bw_yes) {
                                         v->time_for_meta_pte_with_immediate_flip =dcn_bw_max5(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->meta_pte_bytes_per_frame[k] * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->extra_latency, v->urgent_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
-                                        v->time_for_meta_pte_without_immediate_flip =dcn_bw_max3(v->meta_pte_bytes_per_frame[k] / v->prefetch_bw[k], v->extra_latency, v->htotal[k] / v->pixel_clock[k] / 4.0);
                                 }
                                 else {
                                         v->time_for_meta_pte_with_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
-                                        v->time_for_meta_pte_without_immediate_flip = v->htotal[k] / v->pixel_clock[k] / 4.0;
                                 }
                                 if (v->pte_enable == dcn_bw_yes || v->dcc_enable[k] == dcn_bw_yes) {
                                         v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max5((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], (v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) * v->total_immediate_flip_bytes[k] / (v->bw_available_for_immediate_flip * (v->meta_pte_bytes_per_frame[k] + v->meta_row_bytes[k] + v->dpte_bytes_per_row[k])), v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency, 2.0 * v->urgent_latency);
-                                        v->time_for_meta_and_dpte_row_without_immediate_flip =dcn_bw_max3((v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k], v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, v->extra_latency);
                                 }
                                 else {
                                         v->time_for_meta_and_dpte_row_with_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_with_immediate_flip, v->extra_latency - v->time_for_meta_pte_with_immediate_flip);
-                                        v->time_for_meta_and_dpte_row_without_immediate_flip =dcn_bw_max2(v->htotal[k] / v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip, v->extra_latency - v->time_for_meta_pte_without_immediate_flip);
                                 }
                                 v->lines_for_meta_pte_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-                                v->lines_for_meta_pte_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_pte_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
                                 v->lines_for_meta_and_dpte_row_with_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_with_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
-                                v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * (v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / v->pixel_clock[k]) + 0.125), 1.0) / 4;
                                 v->line_times_to_request_prefetch_pixel_data_with_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_with_immediate_flip[k] - v->lines_for_meta_and_dpte_row_with_immediate_flip[k];
                                 v->line_times_to_request_prefetch_pixel_data_without_immediate_flip = v->line_times_for_prefetch[k] - v->lines_for_meta_pte_without_immediate_flip[k] - v->lines_for_meta_and_dpte_row_without_immediate_flip[k];
                                 if (v->line_times_to_request_prefetch_pixel_data_with_immediate_flip > 0.0) {
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 43e4a2be0fa6..12d1842079ae 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -290,41 +290,34 @@ static void pipe_ctx_to_e2e_pipe_params (
         switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
         /* for 4/8/16 high tiles */
         case DC_SW_LINEAR:
-                input->src.is_display_sw = 1;
                 input->src.macro_tile_size = dm_4k_tile;
                 break;
         case DC_SW_4KB_S:
         case DC_SW_4KB_S_X:
-                input->src.is_display_sw = 0;
                 input->src.macro_tile_size = dm_4k_tile;
                 break;
         case DC_SW_64KB_S:
         case DC_SW_64KB_S_X:
         case DC_SW_64KB_S_T:
-                input->src.is_display_sw = 0;
                 input->src.macro_tile_size = dm_64k_tile;
                 break;
         case DC_SW_VAR_S:
         case DC_SW_VAR_S_X:
-                input->src.is_display_sw = 0;
                 input->src.macro_tile_size = dm_256k_tile;
                 break;
 
         /* For 64bpp 2 high tiles */
         case DC_SW_4KB_D:
         case DC_SW_4KB_D_X:
-                input->src.is_display_sw = 1;
                 input->src.macro_tile_size = dm_4k_tile;
                 break;
         case DC_SW_64KB_D:
         case DC_SW_64KB_D_X:
         case DC_SW_64KB_D_T:
-                input->src.is_display_sw = 1;
                 input->src.macro_tile_size = dm_64k_tile;
                 break;
         case DC_SW_VAR_D:
         case DC_SW_VAR_D_X:
-                input->src.is_display_sw = 1;
                 input->src.macro_tile_size = dm_256k_tile;
                 break;
 
@@ -423,7 +416,7 @@ static void pipe_ctx_to_e2e_pipe_params (
                         - pipe->stream->timing.v_addressable
                         - pipe->stream->timing.v_border_bottom
                         - pipe->stream->timing.v_border_top;
-        input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
+        input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
         input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
         input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
@@ -670,9 +663,9 @@ static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
 }
 
 static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
-                unsigned int pixel_rate_khz)
+                unsigned int pixel_rate_100hz)
 {
-        float pixel_rate_mhz = pixel_rate_khz / 1000;
+        float pixel_rate_mhz = pixel_rate_100hz / 10000;
 
         /*
          * force enabling pipe split by lower dpp clock for DPM0 to just
@@ -695,7 +688,7 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
 
         if (context->stream_count == 1 &&
                         dbg->force_single_disp_pipe_split)
-                hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_khz);
+                hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
 }
 
 bool dcn_validate_bandwidth(
@@ -852,7 +845,7 @@ bool dcn_validate_bandwidth(
                 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
                                 - v->vactive[input_idx]
                                 - pipe->stream->timing.v_front_porch;
-                v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz/1000.0;
+                v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
                 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
                         v->pixel_clock[input_idx] *= 2;
                 if (!pipe->plane_state) {
@@ -961,7 +954,7 @@ bool dcn_validate_bandwidth(
                 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
                 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
                                 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
-                v->output[input_idx] = pipe->stream->sink->sink_signal ==
+                v->output[input_idx] = pipe->stream->signal ==
                                 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
                 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
                 if (v->output[input_idx] == dcn_bw_hdmi) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5fd52094d459..1dabafc12cfe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -384,7 +384,7 @@ void dc_stream_set_dither_option(struct dc_stream_state *stream,
                 enum dc_dither_option option)
 {
         struct bit_depth_reduction_params params;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         struct pipe_ctx *pipes = NULL;
         int i;
 
@@ -451,7 +451,7 @@ bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
                                         pipes,
                                         stream->output_color_space,
                                         stream->csc_color_matrix.matrix,
-                                        pipes->plane_res.hubp->opp_id);
+                                        pipes->plane_res.hubp ? pipes->plane_res.hubp->opp_id : 0);
                         ret = true;
                 }
         }
@@ -526,9 +526,8 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
 
         for (i = 0; i < MAX_PIPES; i++) {
                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-                if (pipe->stream && pipe->stream->sink
-                        && pipe->stream->sink->link) {
-                        if (pipe->stream->sink->link == link)
+                if (pipe->stream && pipe->stream->link) {
+                        if (pipe->stream->link == link)
                                 break;
                 }
         }
@@ -586,9 +585,6 @@ static void destruct(struct dc *dc)
         if (dc->ctx->gpio_service)
                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 
-        if (dc->ctx->i2caux)
-                dal_i2caux_destroy(&dc->ctx->i2caux);
-
         if (dc->ctx->created_bios)
                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 
@@ -670,6 +666,7 @@ static bool construct(struct dc *dc,
         dc_ctx->dc = dc;
         dc_ctx->asic_id = init_params->asic_id;
         dc_ctx->dc_sink_id_count = 0;
+        dc_ctx->dc_stream_id_count = 0;
         dc->ctx = dc_ctx;
 
         dc->current_state = dc_create_state();
@@ -709,14 +706,6 @@ static bool construct(struct dc *dc,
                 dc_ctx->created_bios = true;
                 }
 
-        /* Create I2C AUX */
-        dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
-
-        if (!dc_ctx->i2caux) {
-                ASSERT_CRITICAL(false);
-                goto fail;
-        }
-
         dc_ctx->perf_trace = dc_perf_trace_create();
         if (!dc_ctx->perf_trace) {
                 ASSERT_CRITICAL(false);
@@ -840,6 +829,11 @@ alloc_fail:
         return NULL;
 }
 
+void dc_init_callbacks(struct dc *dc,
+                const struct dc_callback_init *init_params)
+{
+}
+
 void dc_destroy(struct dc **dc)
 {
         destruct(*dc);
@@ -1040,7 +1034,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 
         /* Program all planes within new context*/
         for (i = 0; i < context->stream_count; i++) {
-                const struct dc_sink *sink = context->streams[i]->sink;
+                const struct dc_link *link = context->streams[i]->link;
+                struct dc_stream_status *status;
 
                 if (!context->streams[i]->mode_changed)
                         continue;
@@ -1065,12 +1060,15 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
                         }
                 }
 
-                CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
+                status = dc_stream_get_status_from_state(context, context->streams[i]);
+                context->streams[i]->out.otg_offset = status->primary_otg_inst;
+
+                CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
                                 context->streams[i]->timing.h_addressable,
                                 context->streams[i]->timing.v_addressable,
                                 context->streams[i]->timing.h_total,
                                 context->streams[i]->timing.v_total,
-                                context->streams[i]->timing.pix_clk_khz);
+                                context->streams[i]->timing.pix_clk_100hz / 10);
         }
 
         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
@@ -1215,6 +1213,12 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
                  */
                 update_flags->bits.bpp_change = 1;
 
+        if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch
+                        || u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch
+                        || u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch)
+                update_flags->bits.plane_size_change = 1;
+
+
         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
                         sizeof(union dc_tiling_info)) != 0) {
                 update_flags->bits.swizzle_change = 1;
@@ -1236,7 +1240,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
                         || update_flags->bits.output_tf_change)
                 return UPDATE_TYPE_FULL;
 
-        return UPDATE_TYPE_MED;
+        return update_flags->raw ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST;
 }
 
 static enum surface_update_type get_scaling_info_update_type(
@@ -1605,7 +1609,6 @@ void dc_commit_updates_for_stream(struct dc *dc,
                 int surface_count,
                 struct dc_stream_state *stream,
                 struct dc_stream_update *stream_update,
-                struct dc_plane_state **plane_states,
                 struct dc_state *state)
 {
         const struct dc_stream_status *stream_status;
@@ -1764,6 +1767,26 @@ void dc_resume(struct dc *dc)
                 core_link_resume(dc->links[i]);
 }
 
+unsigned int dc_get_current_backlight_pwm(struct dc *dc)
+{
+        struct abm *abm = dc->res_pool->abm;
+
+        if (abm)
+                return abm->funcs->get_current_backlight(abm);
+
+        return 0;
+}
+
+unsigned int dc_get_target_backlight_pwm(struct dc *dc)
+{
+        struct abm *abm = dc->res_pool->abm;
+
+        if (abm)
+                return abm->funcs->get_target_backlight(abm);
+
+        return 0;
+}
+
 bool dc_is_dmcu_initialized(struct dc *dc)
 {
         struct dmcu *dmcu = dc->res_pool->dmcu;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 52deacf39841..3dd5f2717b53 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -43,10 +43,6 @@
 #include "dpcd_defs.h"
 #include "dmcu.h"
 
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_enum.h"
-#include "dce/dce_11_0_sh_mask.h"
-
 #define DC_LOGGER_INIT(logger)
 
 
@@ -789,7 +785,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                         return false;
                 }
 
-                sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
+                sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
                 sink->converter_disable_audio = converter_disable_audio;
 
                 link->local_sink = sink;
@@ -1372,7 +1368,7 @@ static void dpcd_configure_panel_mode(
 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
 {
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         union down_spread_ctrl old_downspread;
         union down_spread_ctrl new_downspread;
 
@@ -1397,7 +1393,7 @@ static enum dc_status enable_link_dp(
         struct dc_stream_state *stream = pipe_ctx->stream;
         enum dc_status status;
         bool skip_video_pattern;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         struct dc_link_settings link_settings = {0};
         enum dp_panel_mode panel_mode;
 
@@ -1414,8 +1410,8 @@ static enum dc_status enable_link_dp(
                 pipe_ctx->clock_source->id,
                 &link_settings);
 
-        if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
-                int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
+        if (stream->sink_patches.dppowerup_delay > 0) {
+                int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
 
                 msleep(delay_dp_power_up_in_ms);
         }
@@ -1448,7 +1444,7 @@ static enum dc_status enable_link_edp(
 {
         enum dc_status status;
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         /*in case it is not on*/
         link->dc->hwss.edp_power_control(link, true);
         link->dc->hwss.edp_wait_for_hpd_ready(link, true);
@@ -1463,7 +1459,7 @@ static enum dc_status enable_link_dp_mst(
                 struct dc_state *state,
                 struct pipe_ctx *pipe_ctx)
 {
-        struct dc_link *link = pipe_ctx->stream->sink->link;
+        struct dc_link *link = pipe_ctx->stream->link;
 
         /* sink signal type after MST branch is MST. Multiple MST sinks
          * share one link. Link DP PHY is enable or training only once.
@@ -1597,7 +1593,7 @@ static bool i2c_write(struct pipe_ctx *pipe_ctx,
         cmd.payloads = &payload;
 
         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
-                        pipe_ctx->stream->sink->link, &cmd))
+                        pipe_ctx->stream->link, &cmd))
                 return true;
 
         return false;
@@ -1651,7 +1647,7 @@ static void write_i2c_retimer_setting(
                                 else {
                                         i2c_success =
                                                 dal_ddc_service_query_ddc_data(
-                                                pipe_ctx->stream->sink->link->ddc,
+                                                pipe_ctx->stream->link->ddc,
                                                 slave_address, &offset, 1, &value, 1);
                                         if (!i2c_success)
                                                 /* Write failure */
@@ -1704,7 +1700,7 @@ static void write_i2c_retimer_setting(
                                         else {
                                                 i2c_success =
                                                                 dal_ddc_service_query_ddc_data(
-                                                                pipe_ctx->stream->sink->link->ddc,
+                                                                pipe_ctx->stream->link->ddc,
                                                                 slave_address, &offset, 1, &value, 1);
                                                 if (!i2c_success)
                                                         /* Write failure */
@@ -1929,7 +1925,7 @@ static void write_i2c_redriver_setting(
 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
 {
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         enum dc_color_depth display_color_depth;
         enum engine_id eng_id;
         struct ext_hdmi_settings settings = {0};
@@ -1938,12 +1934,12 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
                         && (stream->timing.v_addressable == 480);
 
         if (stream->phy_pix_clk == 0)
-                stream->phy_pix_clk = stream->timing.pix_clk_khz;
+                stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
         if (stream->phy_pix_clk > 340000)
                 is_over_340mhz = true;
 
         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
-                unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
+                unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
                         /* DP159, Retimer settings */
@@ -1964,11 +1960,11 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
 
         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
                 dal_ddc_service_write_scdc_data(
-                        stream->sink->link->ddc,
+                        stream->link->ddc,
                         stream->phy_pix_clk,
                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
 
-        memset(&stream->sink->link->cur_link_settings, 0,
+        memset(&stream->link->cur_link_settings, 0,
                         sizeof(struct dc_link_settings));
 
         display_color_depth = stream->timing.display_color_depth;
@@ -1989,12 +1985,12 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
 {
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
 
         if (stream->phy_pix_clk == 0)
-                stream->phy_pix_clk = stream->timing.pix_clk_khz;
+                stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
 
-        memset(&stream->sink->link->cur_link_settings, 0,
+        memset(&stream->link->cur_link_settings, 0,
                         sizeof(struct dc_link_settings));
 
         link->link_enc->funcs->enable_lvds_output(
@@ -2067,7 +2063,7 @@ static bool dp_active_dongle_validate_timing(
                 const struct dc_crtc_timing *timing,
                 const struct dpcd_caps *dpcd_caps)
 {
-        unsigned int required_pix_clk = timing->pix_clk_khz;
+        unsigned int required_pix_clk_100hz = timing->pix_clk_100hz;
         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
 
         switch (dpcd_caps->dongle_type) {
@@ -2107,9 +2103,9 @@ static bool dp_active_dongle_validate_timing(
 
         /* Check Color Depth and Pixel Clock */
         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
-                required_pix_clk /= 2;
+                required_pix_clk_100hz /= 2;
         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
-                required_pix_clk = required_pix_clk * 2 / 3;
+                required_pix_clk_100hz = required_pix_clk_100hz * 2 / 3;
 
         switch (timing->display_color_depth) {
         case COLOR_DEPTH_666:
@@ -2119,12 +2115,12 @@ static bool dp_active_dongle_validate_timing(
         case COLOR_DEPTH_101010:
                 if (dongle_caps->dp_hdmi_max_bpc < 10)
                         return false;
-                required_pix_clk = required_pix_clk * 10 / 8;
+                required_pix_clk_100hz = required_pix_clk_100hz * 10 / 8;
                 break;
         case COLOR_DEPTH_121212:
                 if (dongle_caps->dp_hdmi_max_bpc < 12)
                         return false;
-                required_pix_clk = required_pix_clk * 12 / 8;
+                required_pix_clk_100hz = required_pix_clk_100hz * 12 / 8;
                 break;
 
         case COLOR_DEPTH_141414:
@@ -2134,7 +2130,7 @@ static bool dp_active_dongle_validate_timing(
                 return false;
         }
 
-        if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
+        if (required_pix_clk_100hz > (dongle_caps->dp_hdmi_max_pixel_clk * 10))
                 return false;
 
         return true;
@@ -2145,7 +2141,7 @@ enum dc_status dc_link_validate_mode_timing(
                 struct dc_link *link,
                 const struct dc_crtc_timing *timing)
 {
-        uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
+        uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 
         /* A hack to avoid failing any modes for EDID override feature on
@@ -2155,7 +2151,7 @@ enum dc_status dc_link_validate_mode_timing(
                 return DC_OK;
 
         /* Passive Dongle */
-        if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
+        if (0 != max_pix_clk && timing->pix_clk_100hz > max_pix_clk)
                 return DC_EXCEED_DONGLE_CAP;
 
         /* Active Dongle*/
@@ -2190,8 +2186,7 @@ int dc_link_get_backlight_level(const struct dc_link *link)
 
 bool dc_link_set_backlight_level(const struct dc_link *link,
                 uint32_t backlight_pwm_u16_16,
-                uint32_t frame_ramp,
-                const struct dc_stream_state *stream)
+                uint32_t frame_ramp)
 {
         struct dc  *core_dc = link->ctx->dc;
         struct abm *abm = core_dc->res_pool->abm;
@@ -2206,10 +2201,6 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
                 (abm->funcs->set_backlight_level_pwm == NULL))
                 return false;
 
-        if (stream)
-                ((struct dc_stream_state *)stream)->bl_pwm_level =
-                                backlight_pwm_u16_16;
-
         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
 
         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
@@ -2219,7 +2210,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link,
                 for (i = 0; i < MAX_PIPES; i++) {
                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
                                 if (core_dc->current_state->res_ctx.
-                                                pipe_ctx[i].stream->sink->link
+                                                pipe_ctx[i].stream->link
                                                 == link)
                                         /* DMCU -1 for all controller id values,
                                          * therefore +1 here
@@ -2279,7 +2270,7 @@ void core_link_resume(struct dc_link *link)
 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
 {
         struct dc_link_settings *link_settings =
-                        &stream->sink->link->cur_link_settings;
+                        &stream->link->cur_link_settings;
         uint32_t link_rate_in_mbps =
                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
         struct fixed31_32 mbps = dc_fixpt_from_int(
@@ -2310,7 +2301,7 @@ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
         uint32_t denominator;
 
         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
-        kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
+        kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 * bpc * 3;
 
         /*
          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
@@ -2386,7 +2377,7 @@ static void update_mst_stream_alloc_table(
 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 {
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         struct link_encoder *link_encoder = link->link_enc;
         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
         struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -2466,7 +2457,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
 {
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         struct link_encoder *link_encoder = link->link_enc;
         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
         struct dp_mst_stream_allocation_table proposed_table = {0};
@@ -2551,8 +2542,8 @@ void core_link_enable_stream(
         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
 
         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
-                stream->sink->link->link_enc->funcs->setup(
-                        stream->sink->link->link_enc,
+                stream->link->link_enc->funcs->setup(
+                        stream->link->link_enc,
                         pipe_ctx->stream->signal);
                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
                         pipe_ctx->stream_res.stream_enc,
@@ -2604,7 +2595,7 @@ void core_link_enable_stream(
 
                 if (status != DC_OK) {
                         DC_LOG_WARNING("enabling link %u failed: %d\n",
-                        pipe_ctx->stream->sink->link->link_index,
+                        pipe_ctx->stream->link->link_index,
                         status);
 
                         /* Abort stream enable *unless* the failure was due to
@@ -2633,15 +2624,10 @@ void core_link_enable_stream(
                         allocate_mst_payload(pipe_ctx);
 
                 core_dc->hwss.unblank_stream(pipe_ctx,
-                        &pipe_ctx->stream->sink->link->cur_link_settings);
+                        &pipe_ctx->stream->link->cur_link_settings);
 
                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
                         enable_stream_features(pipe_ctx);
-
-                dc_link_set_backlight_level(pipe_ctx->stream->sink->link,
-                                pipe_ctx->stream->bl_pwm_level,
-                                0,
-                                pipe_ctx->stream);
         }
 
 }
@@ -2657,7 +2643,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
 
         core_dc->hwss.disable_stream(pipe_ctx, option);
 
-        disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
+        disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
 }
 
 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 506a97e16956..b7ee63cd8dc7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -33,7 +33,7 @@
 #include "include/vector.h"
 #include "core_types.h"
 #include "dc_link_ddc.h"
-#include "aux_engine.h"
+#include "dce/dce_aux.h"
 
 #define AUX_POWER_UP_WA_DELAY 500
 #define I2C_OVER_AUX_DEFER_WA_DELAY 70
@@ -42,7 +42,6 @@
 #define CV_SMART_DONGLE_ADDRESS 0x20
 /* DVI-HDMI dongle slave address for retrieving dongle signature*/
 #define DVI_HDMI_DONGLE_ADDRESS 0x68
-static const int8_t dvi_hdmi_dongle_signature_str[] = "6140063500G";
 struct dvi_hdmi_dongle_signature_data {
         int8_t vendor[3];/* "AMD" */
         uint8_t version[2];
@@ -165,43 +164,6 @@ static void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p)
 
 }
 
-static struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count)
-{
-        struct aux_payloads *payloads;
-
-        payloads = kzalloc(sizeof(struct aux_payloads), GFP_KERNEL);
-
-        if (!payloads)
-                return NULL;
-
-        if (dal_vector_construct(
-                &payloads->payloads, ctx, count, sizeof(struct aux_payload)))
-                return payloads;
-
-        kfree(payloads);
-        return NULL;
-}
-
-static struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p)
-{
-        return (struct aux_payload *)p->payloads.container;
-}
-
-static uint32_t  dal_ddc_aux_payloads_get_count(struct aux_payloads *p)
-{
-        return p->payloads.count;
-}
-
-static void dal_ddc_aux_payloads_destroy(struct aux_payloads **p)
-{
-        if (!p || !*p)
-                return;
-
-        dal_vector_destruct(&(*p)->payloads);
-        kfree(*p);
-        *p = NULL;
-}
-
 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
 
 void dal_ddc_i2c_payloads_add(
@@ -225,27 +187,6 @@ void dal_ddc_i2c_payloads_add(
 
 }
 
-void dal_ddc_aux_payloads_add(
-        struct aux_payloads *payloads,
-        uint32_t address,
-        uint32_t len,
-        uint8_t *data,
-        bool write)
-{
-        uint32_t payload_size = DEFAULT_AUX_MAX_DATA_SIZE;
-        uint32_t pos;
-
-        for (pos = 0; pos < len; pos += payload_size) {
-                struct aux_payload payload = {
-                        .i2c_over_aux = true,
-                        .write = write,
-                        .address = address,
-                        .length = DDC_MIN(payload_size, len - pos),
-                        .data = data + pos };
-                dal_vector_append(&payloads->payloads, &payload);
-        }
-}
-
 static void construct(
         struct ddc_service *ddc_service,
         struct ddc_service_init_data *init_data)
@@ -574,32 +515,34 @@ bool dal_ddc_service_query_ddc_data(
         /*TODO: len of payload data for i2c and aux is uint8!!!!,
          *  but we want to read 256 over i2c!!!!*/
         if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
-
-                struct aux_payloads *payloads =
-                        dal_ddc_aux_payloads_create(ddc->ctx, payloads_num);
-
-                struct aux_command command = {
-                        .payloads = dal_ddc_aux_payloads_get(payloads),
-                        .number_of_payloads = 0,
+                struct aux_payload write_payload = {
+                        .i2c_over_aux = true,
+                        .write = true,
+                        .mot = true,
+                        .address = address,
+                        .length = write_size,
+                        .data = write_buf,
+                        .reply = NULL,
                         .defer_delay = get_defer_delay(ddc),
-                        .max_defer_write_retry = 0 };
+                };
 
-                dal_ddc_aux_payloads_add(
-                        payloads, address, write_size, write_buf, true);
-
-                dal_ddc_aux_payloads_add(
-                        payloads, address, read_size, read_buf, false);
-
-                command.number_of_payloads =
-                        dal_ddc_aux_payloads_get_count(payloads);
+                struct aux_payload read_payload = {
+                        .i2c_over_aux = true,
+                        .write = false,
+                        .mot = false,
+                        .address = address,
+                        .length = read_size,
+                        .data = read_buf,
+                        .reply = NULL,
+                        .defer_delay = get_defer_delay(ddc),
+                };
 
-                ret = dal_i2caux_submit_aux_command(
-                                ddc->ctx->i2caux,
-                                ddc->ddc_pin,
-                                &command);
+                ret = dc_link_aux_transfer_with_retries(ddc, &write_payload);
 
-                dal_ddc_aux_payloads_destroy(&payloads);
+                if (!ret)
+                        return false;
 
+                ret = dc_link_aux_transfer_with_retries(ddc, &read_payload);
         } else {
                 struct i2c_payloads *payloads =
                         dal_ddc_i2c_payloads_create(ddc->ctx, payloads_num);
@@ -631,56 +574,15 @@ bool dal_ddc_service_query_ddc_data(
 }
 
 int dc_link_aux_transfer(struct ddc_service *ddc,
-                             unsigned int address,
-                             uint8_t *reply,
-                             void *buffer,
-                             unsigned int size,
-                             enum aux_transaction_type type,
-                             enum i2caux_transaction_action action)
+                struct aux_payload *payload)
 {
-        struct ddc *ddc_pin = ddc->ddc_pin;
-        struct aux_engine *aux_engine;
-        enum aux_channel_operation_result operation_result;
-        struct aux_request_transaction_data aux_req;
-        struct aux_reply_transaction_data aux_rep;
-        uint8_t returned_bytes = 0;
-        int res = -1;
-        uint32_t status;
-
-        memset(&aux_req, 0, sizeof(aux_req));
-        memset(&aux_rep, 0, sizeof(aux_rep));
-
-        aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
-        aux_engine->funcs->acquire(aux_engine, ddc_pin);
-
-        aux_req.type = type;
-        aux_req.action = action;
-
-        aux_req.address = address;
-        aux_req.delay = 0;
-        aux_req.length = size;
-        aux_req.data = buffer;
-
-        aux_engine->funcs->submit_channel_request(aux_engine, &aux_req);
-        operation_result = aux_engine->funcs->get_channel_status(aux_engine, &returned_bytes);
-
-        switch (operation_result) {
-        case AUX_CHANNEL_OPERATION_SUCCEEDED:
-                res = aux_engine->funcs->read_channel_reply(aux_engine, size,
-                                                        buffer, reply,
-                                                        &status);
-                break;
-        case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
-                res = 0;
-                break;
-        case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
-        case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-        case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-                res = -1;
-                break;
-        }
-        aux_engine->funcs->release_engine(aux_engine);
-        return res;
+        return dce_aux_transfer(ddc, payload);
+}
+
+bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+                struct aux_payload *payload)
+{
+        return dce_aux_transfer_with_retries(ddc, payload);
 }
 
 /*test only function*/
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 0caacb60b02f..92f565ca1260 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -47,7 +47,7 @@ static void wait_for_training_aux_rd_interval(
         struct dc_link *link,
         uint32_t default_wait_in_micro_secs)
 {
-        union training_aux_rd_interval training_rd_interval;
+        union training_aux_rd_interval training_rd_interval = {0};
 
         /* overwrite the delay if rev > 1.1*/
         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
@@ -117,6 +117,13 @@ static void dpcd_set_link_settings(
         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
         &downspread.raw, sizeof(downspread));
 
+        if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
+                (link->dpcd_caps.link_rate_set >= 1 &&
+                link->dpcd_caps.link_rate_set <= 8)) {
+                core_link_write_dpcd(link, DP_LINK_RATE_SET,
+                &link->dpcd_caps.link_rate_set, 1);
+        }
+
         DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
                 __func__,
                 DP_LINK_BW_SET,
@@ -1542,7 +1549,7 @@ static uint32_t bandwidth_in_kbps_from_timing(
 
         ASSERT(bits_per_channel != 0);
 
-        kbps = timing->pix_clk_khz;
+        kbps = timing->pix_clk_100hz / 10;
         kbps *= bits_per_channel;
 
         if (timing->flags.Y_ONLY != 1) {
@@ -1584,7 +1591,7 @@ bool dp_validate_mode_timing(
         const struct dc_link_settings *link_setting;
 
         /*always DP fail safe mode*/
-        if (timing->pix_clk_khz == (uint32_t) 25175 &&
+        if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
                 timing->h_addressable == (uint32_t) 640 &&
                 timing->v_addressable == (uint32_t) 480)
                 return true;
@@ -1634,7 +1641,7 @@ void decide_link_settings(struct dc_stream_state *stream,
 
         req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
 
-        link = stream->sink->link;
+        link = stream->link;
 
         /* if preferred is specified through AMDDP, use it, if it's enough
          * to drive the mode
@@ -1656,7 +1663,7 @@ void decide_link_settings(struct dc_stream_state *stream,
         }
 
         /* EDP use the link cap setting */
-        if (stream->sink->sink_signal == SIGNAL_TYPE_EDP) {
+        if (link->connector_signal == SIGNAL_TYPE_EDP) {
                 *link_setting = link->verified_link_cap;
                 return;
         }
@@ -2002,11 +2009,7 @@ static void handle_automated_test(struct dc_link *link)
                 dp_test_send_phy_test_pattern(link);
                 test_response.bits.ACK = 1;
         }
-        if (!test_request.raw)
-                /* no requests, revert all test signals
-                 * TODO: revert all test signals
-                 */
-                test_response.bits.ACK = 1;
+
         /* send request acknowledgment */
         if (test_response.bits.ACK)
                 core_link_write_dpcd(
@@ -2493,13 +2496,105 @@ bool detect_dp_sink_caps(struct dc_link *link)
         /* TODO save sink caps in link->sink */
 }
 
+enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
+{
+        enum dc_link_rate link_rate;
+        // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
+        switch (link_rate_in_khz) {
+        case 1620000:
+                link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
+                break;
+        case 2160000:
+                link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
+                break;
+        case 2430000:
+                link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
+                break;
+        case 2700000:
+                link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
+                break;
+        case 3240000:
+                link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
+                break;
+        case 4320000:
+                link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
+                break;
+        case 5400000:
+                link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
+                break;
+        case 8100000:
+                link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
+                break;
+        default:
+                link_rate = LINK_RATE_UNKNOWN;
+                break;
+        }
+        return link_rate;
+}
+
 void detect_edp_sink_caps(struct dc_link *link)
 {
-        retrieve_link_cap(link);
+        uint8_t supported_link_rates[16] = {0};
+        uint32_t entry;
+        uint32_t link_rate_in_khz;
+        enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
+        uint8_t link_rate_set = 0;
 
-        if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
-                link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
+        retrieve_link_cap(link);
 
+        if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
+                // Read DPCD 00010h - 0001Fh 16 bytes at one shot
+                core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
+                                                        supported_link_rates, sizeof(supported_link_rates));
+
+                link->dpcd_caps.link_rate_set = 0;
+                for (entry = 0; entry < 16; entry += 2) {
+                        // DPCD register reports per-lane link rate = 16-bit link rate capability
+                        // value X 200 kHz. Need multipler to find link rate in kHz.
+                        link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
+                                                                                supported_link_rates[entry]) * 200;
+
+                        if (link_rate_in_khz != 0) {
+                                link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
+                                if (link->reported_link_cap.link_rate < link_rate) {
+                                        link->reported_link_cap.link_rate = link_rate;
+
+                                        switch (link_rate) {
+                                        case LINK_RATE_LOW:
+                                                link_rate_set = 1;
+                                                break;
+                                        case LINK_RATE_RATE_2:
+                                                link_rate_set = 2;
+                                                break;
+                                        case LINK_RATE_RATE_3:
+                                                link_rate_set = 3;
+                                                break;
+                                        case LINK_RATE_HIGH:
+                                                link_rate_set = 4;
+                                                break;
+                                        case LINK_RATE_RBR2:
+                                                link_rate_set = 5;
+                                                break;
+                                        case LINK_RATE_RATE_6:
+                                                link_rate_set = 6;
+                                                break;
+                                        case LINK_RATE_HIGH2:
+                                                link_rate_set = 7;
+                                                break;
+                                        case LINK_RATE_HIGH3:
+                                                link_rate_set = 8;
+                                                break;
+                                        default:
+                                                link_rate_set = 0;
+                                                break;
+                                        }
+
+                                        if (link->dpcd_caps.link_rate_set < link_rate_set)
+                                                link->dpcd_caps.link_rate_set = link_rate_set;
+                                }
+                        }
+                }
+        }
         link->verified_link_cap = link->reported_link_cap;
 }
 
@@ -2621,7 +2716,7 @@ bool dc_link_dp_set_test_pattern(
         memset(&training_pattern, 0, sizeof(training_pattern));
 
         for (i = 0; i < MAX_PIPES; i++) {
-                if (pipes[i].stream->sink->link == link) {
+                if (pipes[i].stream->link == link) {
                         pipe_ctx = &pipes[i];
                         break;
                 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 0065ec7d5330..16d441d3af8a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -70,13 +70,12 @@ void dp_enable_link_phy(
          */
         for (i = 0; i < MAX_PIPES; i++) {
                 if (pipes[i].stream != NULL &&
-                        pipes[i].stream->sink != NULL &&
-                        pipes[i].stream->sink->link == link) {
+                        pipes[i].stream->link == link) {
                         if (pipes[i].clock_source != NULL &&
                                         pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
                                 pipes[i].clock_source = dp_cs;
-                                pipes[i].stream_res.pix_clk_params.requested_pix_clk =
-                                                pipes[i].stream->timing.pix_clk_khz;
+                                pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
+                                                pipes[i].stream->timing.pix_clk_100hz;
                                 pipes[i].clock_source->funcs->program_pix_clk(
                                                         pipes[i].clock_source,
                                                         &pipes[i].stream_res.pix_clk_params,
@@ -279,10 +278,8 @@ void dp_retrain_link_dp_test(struct dc_link *link,
         for (i = 0; i < MAX_PIPES; i++) {
                 if (pipes[i].stream != NULL &&
                         !pipes[i].top_pipe &&
-                        pipes[i].stream->sink != NULL &&
-                        pipes[i].stream->sink->link != NULL &&
-                        pipes[i].stream_res.stream_enc != NULL &&
-                        pipes[i].stream->sink->link == link) {
+                        pipes[i].stream->link != NULL &&
+                        pipes[i].stream_res.stream_enc != NULL) {
                         udelay(100);
 
                         pipes[i].stream_res.stream_enc->funcs->dp_blank(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 76137df74a53..9888bc7659f3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -355,8 +355,8 @@ bool resource_are_streams_timing_synchronizable(
                                 != stream2->timing.v_addressable)
                 return false;
 
-        if (stream1->timing.pix_clk_khz
-                                != stream2->timing.pix_clk_khz)
+        if (stream1->timing.pix_clk_100hz
+                                != stream2->timing.pix_clk_100hz)
                 return false;
 
         if (stream1->clamping.c_depth != stream2->clamping.c_depth)
@@ -1559,7 +1559,7 @@ static struct stream_encoder *find_first_free_match_stream_enc_for_link(
 {
         int i;
         int j = -1;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
 
         for (i = 0; i < pool->stream_enc_count; i++) {
                 if (!res_ctx->is_stream_enc_acquired[i] &&
@@ -1748,7 +1748,7 @@ static struct dc_stream_state *find_pll_sharable_stream(
                 if (resource_are_streams_timing_synchronizable(
                         stream_needs_pll, stream_has_pll)
                         && !dc_is_dp_signal(stream_has_pll->signal)
-                        && stream_has_pll->sink->link->connector_signal
+                        && stream_has_pll->link->connector_signal
                         != SIGNAL_TYPE_VIRTUAL)
                         return stream_has_pll;
 
@@ -1759,7 +1759,7 @@ static struct dc_stream_state *find_pll_sharable_stream(
 
 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
 {
-        uint32_t pix_clk = timing->pix_clk_khz;
+        uint32_t pix_clk = timing->pix_clk_100hz;
         uint32_t normalized_pix_clk = pix_clk;
 
         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
@@ -1791,10 +1791,10 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream)
         /* update actual pixel clock on all streams */
         if (dc_is_hdmi_signal(stream->signal))
                 stream->phy_pix_clk = get_norm_pix_clk(
-                        &stream->timing);
+                        &stream->timing) / 10;
         else
                 stream->phy_pix_clk =
-                        stream->timing.pix_clk_khz;
+                        stream->timing.pix_clk_100hz / 10;
 
         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
                 stream->phy_pix_clk *= 2;
@@ -1842,7 +1842,7 @@ enum dc_status resource_map_pool_resources(
                         &context->res_ctx, pool, stream);
 
         if (!pipe_ctx->stream_res.stream_enc)
-                return DC_NO_STREAM_ENG_RESOURCE;
+                return DC_NO_STREAM_ENC_RESOURCE;
 
         update_stream_engine_usage(
                 &context->res_ctx, pool,
@@ -1850,7 +1850,7 @@ enum dc_status resource_map_pool_resources(
                 true);
 
         /* TODO: Add check if ASIC support and EDID audio */
-        if (!stream->sink->converter_disable_audio &&
+        if (!stream->converter_disable_audio &&
             dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
             stream->audio_info.mode_count) {
                 pipe_ctx->stream_res.audio = find_first_free_audio(
@@ -2112,7 +2112,7 @@ static void set_avi_info_frame(
         itc = true;
         itc_value = 1;
 
-        support = stream->sink->edid_caps.content_support;
+        support = stream->content_support;
 
         if (itc) {
                 if (!support.bits.valid_content_type) {
@@ -2151,8 +2151,8 @@ static void set_avi_info_frame(
 
         /* TODO : We should handle YCC quantization */
         /* but we do not have matrix calculation */
-        if (stream->sink->edid_caps.qs_bit == 1 &&
-                        stream->sink->edid_caps.qy_bit == 1) {
+        if (stream->qs_bit == 1 &&
+                        stream->qy_bit == 1) {
                 if (color_space == COLOR_SPACE_SRGB ||
                         color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
                         hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
@@ -2596,7 +2596,7 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
 {
         struct dc  *core_dc = dc;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
         enum dc_status res = DC_OK;
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 66e5c4623a49..996298c35f42 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -35,20 +35,17 @@
 /*******************************************************************************
  * Private functions
  ******************************************************************************/
-void update_stream_signal(struct dc_stream_state *stream)
+void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
 {
-
-        struct dc_sink *dc_sink = stream->sink;
-
-        if (dc_sink->sink_signal == SIGNAL_TYPE_NONE)
-                stream->signal = stream->sink->link->connector_signal;
+        if (sink->sink_signal == SIGNAL_TYPE_NONE)
+                stream->signal = stream->link->connector_signal;
         else
-                stream->signal = dc_sink->sink_signal;
+                stream->signal = sink->sink_signal;
 
         if (dc_is_dvi_signal(stream->signal)) {
                 if (stream->ctx->dc->caps.dual_link_dvi &&
-                    stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK &&
-                    stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
+                    (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
+                    sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
                         stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
                 else
                         stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
@@ -61,10 +58,15 @@ static void construct(struct dc_stream_state *stream,
         uint32_t i = 0;
 
         stream->sink = dc_sink_data;
-        stream->ctx = stream->sink->ctx;
-
         dc_sink_retain(dc_sink_data);
 
+        stream->ctx = dc_sink_data->ctx;
+        stream->link = dc_sink_data->link;
+        stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
+        stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
+        stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
+        stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
+
         /* Copy audio modes */
         /* TODO - Remove this translation */
         for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
@@ -100,11 +102,14 @@ static void construct(struct dc_stream_state *stream,
         /* EDID CAP translation for HDMI 2.0 */
         stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
 
-        update_stream_signal(stream);
+        update_stream_signal(stream, dc_sink_data);
 
         stream->out_transfer_func = dc_create_transfer_func();
         stream->out_transfer_func->type = TF_TYPE_BYPASS;
         stream->out_transfer_func->ctx = stream->ctx;
+
+        stream->stream_id = stream->ctx->dc_stream_id_count;
+        stream->ctx->dc_stream_id_count++;
 }
 
 static void destruct(struct dc_stream_state *stream)
@@ -155,21 +160,43 @@ struct dc_stream_state *dc_create_stream_for_sink(
         return stream;
 }
 
-struct dc_stream_status *dc_stream_get_status(
+/**
+ * dc_stream_get_status_from_state - Get stream status from given dc state
+ * @state: DC state to find the stream status in
+ * @stream: The stream to get the stream status for
+ *
+ * The given stream is expected to exist in the given dc state. Otherwise, NULL
+ * will be returned.
+ */
+struct dc_stream_status *dc_stream_get_status_from_state(
+        struct dc_state *state,
         struct dc_stream_state *stream)
 {
         uint8_t i;
-        struct dc  *dc = stream->ctx->dc;
 
-        for (i = 0; i < dc->current_state->stream_count; i++) {
-                if (stream == dc->current_state->streams[i])
-                        return &dc->current_state->stream_status[i];
+        for (i = 0; i < state->stream_count; i++) {
+                if (stream == state->streams[i])
+                        return &state->stream_status[i];
         }
 
         return NULL;
 }
 
 /**
+ * dc_stream_get_status() - Get current stream status of the given stream state
+ * @stream: The stream to get the stream status for.
+ *
+ * The given stream is expected to exist in dc->current_state. Otherwise, NULL
+ * will be returned.
+ */
+struct dc_stream_status *dc_stream_get_status(
+        struct dc_stream_state *stream)
+{
+        struct dc *dc = stream->ctx->dc;
+        return dc_stream_get_status_from_state(dc->current_state, stream);
+}
+
+/**
  * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
  */
 bool dc_stream_set_cursor_attributes(
@@ -334,16 +361,12 @@ void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
                         stream->output_color_space);
         DC_LOG_DC(
                         "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
-                        stream->timing.pix_clk_khz,
+                        stream->timing.pix_clk_100hz / 10,
                         stream->timing.h_total,
                         stream->timing.v_total,
                         stream->timing.pixel_encoding,
                         stream->timing.display_color_depth);
         DC_LOG_DC(
-                        "\tsink name: %s, serial: %d\n",
-                        stream->sink->edid_caps.display_name,
-                        stream->sink->edid_caps.serial_number);
-        DC_LOG_DC(
                         "\tlink: %d\n",
-                        stream->sink->link->link_index);
+                        stream->link->link_index);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index c60c9b4c3075..ee6bd50f60b8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -40,11 +40,14 @@ static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state
         plane_state->ctx = ctx;
 
         plane_state->gamma_correction = dc_create_gamma();
-        plane_state->gamma_correction->is_identity = true;
+        if (plane_state->gamma_correction != NULL)
+                plane_state->gamma_correction->is_identity = true;
 
         plane_state->in_transfer_func = dc_create_transfer_func();
-        plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
-        plane_state->in_transfer_func->ctx = ctx;
+        if (plane_state->in_transfer_func != NULL) {
+                plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
+                plane_state->in_transfer_func->ctx = ctx;
+        }
 }
 
 static void destruct(struct dc_plane_state *plane_state)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
new file mode 100644
index 000000000000..e54b8ac339b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "vm_helper.h"
+
+static void mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uint8_t hubp_idx)
+{
+        struct vmid_usage vmids = vm_helper->hubp_vmid_usage[hubp_idx];
+
+        vmids.vmid_usage[0] = vmids.vmid_usage[1];
+        vmids.vmid_usage[1] = 1 << pos;
+}
+
+static void add_ptb_to_table(struct vm_helper *vm_helper, unsigned int vmid, uint64_t ptb)
+{
+        vm_helper->ptb_assigned_to_vmid[vmid] = ptb;
+        vm_helper->num_vmids_available--;
+}
+
+static void clear_entry_from_vmid_table(struct vm_helper *vm_helper, unsigned int vmid)
+{
+        vm_helper->ptb_assigned_to_vmid[vmid] = 0;
+        vm_helper->num_vmids_available++;
+}
+
+static void evict_vmids(struct vm_helper *vm_helper)
+{
+        int i;
+        uint16_t ord = 0;
+
+        for (i = 0; i < vm_helper->num_vmid; i++)
+                ord |= vm_helper->hubp_vmid_usage[i].vmid_usage[0] | vm_helper->hubp_vmid_usage[i].vmid_usage[1];
+
+        // At this point any positions with value 0 are unused vmids, evict them
+        for (i = 1; i < vm_helper->num_vmid; i++) {
+                if (ord & (1u << i))
+                        clear_entry_from_vmid_table(vm_helper, i);
+        }
+}
+
+// Return value of -1 indicates vmid table unitialized or ptb dne in the table
+static int get_existing_vmid_for_ptb(struct vm_helper *vm_helper, uint64_t ptb)
+{
+        int i;
+
+        for (i = 0; i < vm_helper->num_vmid; i++) {
+                if (vm_helper->ptb_assigned_to_vmid[i] == ptb)
+                        return i;
+        }
+
+        return -1;
+}
+
+// Expected to be called only when there's an available vmid
+static int get_next_available_vmid(struct vm_helper *vm_helper)
+{
+        int i;
+
+        for (i = 1; i < vm_helper->num_vmid; i++) {
+                if (vm_helper->ptb_assigned_to_vmid[i] == 0)
+                        return i;
+        }
+
+        return -1;
+}
+
+uint8_t get_vmid_for_ptb(struct vm_helper *vm_helper, int64_t ptb, uint8_t hubp_idx)
+{
+        unsigned int vmid = 0;
+        int vmid_exists = -1;
+
+        // Physical address gets vmid 0
+        if (ptb == 0)
+                return 0;
+
+        vmid_exists = get_existing_vmid_for_ptb(vm_helper, ptb);
+
+        if (vmid_exists != -1) {
+                mark_vmid_used(vm_helper, vmid_exists, hubp_idx);
+                vmid = vmid_exists;
+        } else {
+                if (vm_helper->num_vmids_available == 0)
+                        evict_vmids(vm_helper);
+
+                vmid = get_next_available_vmid(vm_helper);
+                mark_vmid_used(vm_helper, vmid, hubp_idx);
+                add_ptb_to_table(vm_helper, vmid, ptb);
+        }
+
+        return vmid;
+}
+
+struct vm_helper init_vm_helper(unsigned int num_vmid, unsigned int num_hubp)
+{
+        static uint64_t ptb_assigned_to_vmid[MAX_VMID];
+        static struct vmid_usage hubp_vmid_usage[MAX_HUBP];
+
+        return (struct vm_helper){
+                .num_vmid = num_vmid,
+                .num_hubp = num_hubp,
+                .num_vmids_available = num_vmid - 1,
+                .ptb_assigned_to_vmid = ptb_assigned_to_vmid,
+                .hubp_vmid_usage = hubp_vmid_usage
+        };
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 4b5bbb13ce7f..8391bc39b7a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.08"
+#define DC_VER "3.2.15"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
@@ -255,6 +255,7 @@ struct dc_debug_options {
         bool scl_reset_length10;
         bool hdmi20_disable;
         bool skip_detection_link_training;
+        unsigned int force_fclk_khz;
 };
 
 struct dc_debug_data {
@@ -339,8 +340,13 @@ struct dc_init_data {
         uint32_t log_mask;
 };
 
-struct dc *dc_create(const struct dc_init_data *init_params);
+struct dc_callback_init {
+        uint8_t reserved;
+};
 
+struct dc *dc_create(const struct dc_init_data *init_params);
+void dc_init_callbacks(struct dc *dc,
+                const struct dc_callback_init *init_params);
 void dc_destroy(struct dc **dc);
 
 /*******************************************************************************
@@ -440,6 +446,7 @@ union surface_update_flags {
                 uint32_t coeff_reduction_change:1;
                 uint32_t output_tf_change:1;
                 uint32_t pixel_format_change:1;
+                uint32_t plane_size_change:1;
 
                 /* Full updates */
                 uint32_t new_plane:1;
@@ -652,6 +659,7 @@ struct dpcd_caps {
         int8_t branch_dev_name[6];
         int8_t branch_hw_revision;
         int8_t branch_fw_revision[2];
+        uint8_t link_rate_set;
 
         bool allow_invalid_MSA_timing_param;
         bool panel_mode_edp;
@@ -742,6 +750,9 @@ void dc_set_power_state(
                 struct dc *dc,
                 enum dc_acpi_cm_power_state power_state);
 void dc_resume(struct dc *dc);
+unsigned int dc_get_current_backlight_pwm(struct dc *dc);
+unsigned int dc_get_target_backlight_pwm(struct dc *dc);
+
 bool dc_is_dmcu_initialized(struct dc *dc);
 
 #endif /* DC_INTERFACE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index a8b3cedf9431..78c3b300ec45 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -86,10 +86,6 @@ struct dc_vbios_funcs {
 
         bool (*is_accelerated_mode)(
                 struct dc_bios *bios);
-        bool (*is_active_display)(
-                struct dc_bios *bios,
-                enum signal_type signal,
-                const struct connector_device_tag_info *device_tag);
         void (*set_scratch_critical_state)(
                 struct dc_bios *bios,
                 bool state);
@@ -125,10 +121,6 @@ struct dc_vbios_funcs {
         enum bp_result (*program_crtc_timing)(
                 struct dc_bios *bios,
                 struct bp_hw_crtc_timing_parameters *bp_params);
-
-        enum bp_result (*crtc_source_select)(
-                struct dc_bios *bios,
-                struct bp_crtc_source_select *bp_params);
         enum bp_result (*program_display_engine_pll)(
                 struct dc_bios *bios,
                 struct bp_pixel_clock_parameters *bp_params);
@@ -145,7 +137,6 @@ struct dc_vbios_funcs {
 };
 
 struct bios_registers {
-        uint32_t BIOS_SCRATCH_0;
         uint32_t BIOS_SCRATCH_3;
         uint32_t BIOS_SCRATCH_6;
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index da93ab43f2d8..d4eab33c453b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -46,11 +46,14 @@ enum dc_lane_count {
  */
 enum dc_link_rate {
         LINK_RATE_UNKNOWN = 0,
-        LINK_RATE_LOW = 0x06,
-        LINK_RATE_HIGH = 0x0A,
-        LINK_RATE_RBR2 = 0x0C,
-        LINK_RATE_HIGH2 = 0x14,
-        LINK_RATE_HIGH3 = 0x1E
+        LINK_RATE_LOW = 0x06,           // Rate_1 (RBR) - 1.62 Gbps/Lane
+        LINK_RATE_RATE_2 = 0x08,        // Rate_2               - 2.16 Gbps/Lane
+        LINK_RATE_RATE_3 = 0x09,        // Rate_3               - 2.43 Gbps/Lane
+        LINK_RATE_HIGH = 0x0A,          // Rate_4 (HBR) - 2.70 Gbps/Lane
+        LINK_RATE_RBR2 = 0x0C,          // Rate_5 (RBR2)- 3.24 Gbps/Lane
+        LINK_RATE_RATE_6 = 0x10,        // Rate_6               - 4.32 Gbps/Lane
+        LINK_RATE_HIGH2 = 0x14,         // Rate_7 (HBR2)- 5.40 Gbps/Lane
+        LINK_RATE_HIGH3 = 0x1E          // Rate_8 (HBR3)- 8.10 Gbps/Lane
 };
 
 enum dc_link_spread {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 4842d2378bbf..597d38393379 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -29,31 +29,59 @@
 #include "dm_services.h"
 #include <stdarg.h>
 
+struct dc_reg_value_masks {
+        uint32_t value;
+        uint32_t mask;
+};
+
+struct dc_reg_sequence {
+        uint32_t addr;
+        struct dc_reg_value_masks value_masks;
+};
+
+static inline void set_reg_field_value_masks(
+        struct dc_reg_value_masks *field_value_mask,
+        uint32_t value,
+        uint32_t mask,
+        uint8_t shift)
+{
+        ASSERT(mask != 0);
+
+        field_value_mask->value = (field_value_mask->value & ~mask) | (mask & (value << shift));
+        field_value_mask->mask = field_value_mask->mask | mask;
+}
+
 uint32_t generic_reg_update_ex(const struct dc_context *ctx,
                 uint32_t addr, uint32_t reg_val, int n,
                 uint8_t shift1, uint32_t mask1, uint32_t field_value1,
                 ...)
 {
+        struct dc_reg_value_masks field_value_mask = {0};
         uint32_t shift, mask, field_value;
         int i = 1;
 
         va_list ap;
         va_start(ap, field_value1);
 
-        reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
+        /* gather all bits value/mask getting updated in this register */
+        set_reg_field_value_masks(&field_value_mask,
+                        field_value1, mask1, shift1);
 
         while (i < n) {
                 shift = va_arg(ap, uint32_t);
                 mask = va_arg(ap, uint32_t);
                 field_value = va_arg(ap, uint32_t);
 
-                reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
+                set_reg_field_value_masks(&field_value_mask,
+                                field_value, mask, shift);
                 i++;
         }
-
-        dm_write_reg(ctx, addr, reg_val);
         va_end(ap);
 
+
+        /* mmio write directly */
+        reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
+        dm_write_reg(ctx, addr, reg_val);
         return reg_val;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index e72fce4eca65..da55d623647a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -97,6 +97,8 @@ struct dc_plane_address {
                         union large_integer chroma_dcc_const_color;
                 } video_progressive;
         };
+
+        union large_integer page_table_base;
 };
 
 struct dc_size {
@@ -730,7 +732,7 @@ struct dc_crtc_timing {
         uint32_t v_front_porch;
         uint32_t v_sync_width;
 
-        uint32_t pix_clk_khz;
+        uint32_t pix_clk_100hz;
 
         uint32_t vic;
         uint32_t hdmi_vic;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 29f19d57ff7a..f249ff9be2a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -110,6 +110,7 @@ struct dc_link {
         union ddi_channel_mapping ddi_channel_mapping;
         struct connector_device_tag_info device_tag;
         struct dpcd_caps dpcd_caps;
+        uint32_t dongle_max_pix_clk;
         unsigned short chip_caps;
         unsigned int dpcd_sink_count;
         enum edp_revision edp_revision;
@@ -146,8 +147,7 @@ static inline struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_
  */
 bool dc_link_set_backlight_level(const struct dc_link *dc_link,
                 uint32_t backlight_pwm_u16_16,
-                uint32_t frame_ramp,
-                const struct dc_stream_state *stream);
+                uint32_t frame_ramp);
 
 int dc_link_get_backlight_level(const struct dc_link *dc_link);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index be34d638e15d..7bb1da18c1ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -38,11 +38,6 @@ struct dc_stream_status {
         int stream_enc_inst;
         int plane_count;
         struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
-
-        /*
-         * link this stream passes through
-         */
-        struct dc_link *link;
 };
 
 // TODO: References to this needs to be removed..
@@ -51,7 +46,13 @@ struct freesync_context {
 };
 
 struct dc_stream_state {
+        // sink is deprecated, new code should not reference
+        // this pointer
         struct dc_sink *sink;
+
+        struct dc_link *link;
+        struct dc_panel_patch sink_patches;
+        union display_content_support content_support;
         struct dc_crtc_timing timing;
         struct dc_crtc_timing_adjust adjust;
         struct dc_info_packet vrr_infopacket;
@@ -80,6 +81,9 @@ struct dc_stream_state {
         enum view_3d_format view_format;
 
         bool ignore_msa_timing_param;
+        bool converter_disable_audio;
+        uint8_t qs_bit;
+        uint8_t qy_bit;
 
         unsigned long long periodic_fn_vsync_delta;
 
@@ -91,7 +95,6 @@ struct dc_stream_state {
 
         /* DMCU info */
         unsigned int abm_level;
-        unsigned int bl_pwm_level;
 
         /* from core_stream struct */
         struct dc_context *ctx;
@@ -105,6 +108,8 @@ struct dc_stream_state {
         bool dpms_off;
         bool apply_edp_fast_boot_optimization;
 
+        void *dm_stream_context;
+
         struct dc_cursor_attributes cursor_attributes;
         struct dc_cursor_position cursor_position;
         uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
@@ -117,6 +122,18 @@ struct dc_stream_state {
         /* Computed state bits */
         bool mode_changed : 1;
 
+        /* Output from DC when stream state is committed or altered
+         * DC may only access these values during:
+         * dc_commit_state, dc_commit_state_no_check, dc_commit_streams
+         * values may not change outside of those calls
+         */
+        struct {
+                // For interrupt management, some hardware instance
+                // offsets need to be exposed to DM
+                uint8_t otg_offset;
+        } out;
+
+        uint32_t stream_id;
 };
 
 struct dc_stream_update {
@@ -163,7 +180,6 @@ void dc_commit_updates_for_stream(struct dc *dc,
                 int surface_count,
                 struct dc_stream_state *stream,
                 struct dc_stream_update *stream_update,
-                struct dc_plane_state **plane_states,
                 struct dc_state *state);
 /*
  * Log the current stream state.
@@ -256,11 +272,14 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
  */
 struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
 
-void update_stream_signal(struct dc_stream_state *stream);
+void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
 
 void dc_stream_retain(struct dc_stream_state *dc_stream);
 void dc_stream_release(struct dc_stream_state *dc_stream);
 
+struct dc_stream_status *dc_stream_get_status_from_state(
+        struct dc_state *state,
+        struct dc_stream_state *stream);
 struct dc_stream_status *dc_stream_get_status(
         struct dc_stream_state *dc_stream);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 0b20ae23f169..56e7f3dab15a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -97,8 +97,8 @@ struct dc_context {
         struct dc_bios *dc_bios;
         bool created_bios;
         struct gpio_service *gpio_service;
-        struct i2caux *i2caux;
         uint32_t dc_sink_id_count;
+        uint32_t dc_stream_id_count;
         uint64_t fbc_gpu_addr;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index aaeb7faac0c4..adbb22224e1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -24,6 +24,7 @@
  */
 
 #include "dm_services.h"
+#include "core_types.h"
 #include "dce_aux.h"
 #include "dce/dce_11_0_sh_mask.h"
 
@@ -41,17 +42,17 @@
         container_of((ptr), struct aux_engine_dce110, base)
 
 #define FROM_ENGINE(ptr) \
-        FROM_AUX_ENGINE(container_of((ptr), struct aux_engine, base))
+        FROM_AUX_ENGINE(container_of((ptr), struct dce_aux, base))
 
 #define FROM_AUX_ENGINE_ENGINE(ptr) \
-        container_of((ptr), struct aux_engine, base)
+        container_of((ptr), struct dce_aux, base)
 enum {
         AUX_INVALID_REPLY_RETRY_COUNTER = 1,
         AUX_TIMED_OUT_RETRY_COUNTER = 2,
         AUX_DEFER_RETRY_COUNTER = 6
 };
 static void release_engine(
-        struct aux_engine *engine)
+        struct dce_aux *engine)
 {
         struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
 
@@ -66,7 +67,7 @@ static void release_engine(
 #define DMCU_CAN_ACCESS_AUX 2
 
 static bool is_engine_available(
-        struct aux_engine *engine)
+        struct dce_aux *engine)
 {
         struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
 
@@ -79,7 +80,7 @@ static bool is_engine_available(
         return (field != DMCU_CAN_ACCESS_AUX);
 }
 static bool acquire_engine(
-        struct aux_engine *engine)
+        struct dce_aux *engine)
 {
         struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
 
@@ -155,7 +156,7 @@ static bool acquire_engine(
         (0xFF & (address))
 
 static void submit_channel_request(
-        struct aux_engine *engine,
+        struct dce_aux *engine,
         struct aux_request_transaction_data *request)
 {
         struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
@@ -247,7 +248,7 @@ static void submit_channel_request(
         REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
 }
 
-static int read_channel_reply(struct aux_engine *engine, uint32_t size,
+static int read_channel_reply(struct dce_aux *engine, uint32_t size,
                               uint8_t *buffer, uint8_t *reply_result,
                               uint32_t *sw_status)
 {
@@ -273,7 +274,8 @@ static int read_channel_reply(struct aux_engine *engine, uint32_t size,
 
         REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
         reply_result_32 = reply_result_32 >> 4;
-        *reply_result = (uint8_t)reply_result_32;
+        if (reply_result != NULL)
+                *reply_result = (uint8_t)reply_result_32;
 
         if (reply_result_32 == 0) { /* ACK */
                 uint32_t i = 0;
@@ -299,61 +301,8 @@ static int read_channel_reply(struct aux_engine *engine, uint32_t size,
         return 0;
 }
 
-static void process_channel_reply(
-        struct aux_engine *engine,
-        struct aux_reply_transaction_data *reply)
-{
-        int bytes_replied;
-        uint8_t reply_result;
-        uint32_t sw_status;
-
-        bytes_replied = read_channel_reply(engine, reply->length, reply->data,
-                                           &reply_result, &sw_status);
-
-        /* in case HPD is LOW, exit AUX transaction */
-        if ((sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
-                reply->status = AUX_TRANSACTION_REPLY_HPD_DISCON;
-                return;
-        }
-
-        if (bytes_replied < 0) {
-                /* Need to handle an error case...
-                 * Hopefully, upper layer function won't call this function if
-                 * the number of bytes in the reply was 0, because there was
-                 * surely an error that was asserted that should have been
-                 * handled for hot plug case, this could happens
-                 */
-                if (!(sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
-                        reply->status = AUX_TRANSACTION_REPLY_INVALID;
-                        ASSERT_CRITICAL(false);
-                        return;
-                }
-        } else {
-
-                switch (reply_result) {
-                case 0: /* ACK */
-                        reply->status = AUX_TRANSACTION_REPLY_AUX_ACK;
-                break;
-                case 1: /* NACK */
-                        reply->status = AUX_TRANSACTION_REPLY_AUX_NACK;
-                break;
-                case 2: /* DEFER */
-                        reply->status = AUX_TRANSACTION_REPLY_AUX_DEFER;
-                break;
-                case 4: /* AUX ACK / I2C NACK */
-                        reply->status = AUX_TRANSACTION_REPLY_I2C_NACK;
-                break;
-                case 8: /* AUX ACK / I2C DEFER */
-                        reply->status = AUX_TRANSACTION_REPLY_I2C_DEFER;
-                break;
-                default:
-                        reply->status = AUX_TRANSACTION_REPLY_INVALID;
-                }
-        }
-}
-
 static enum aux_channel_operation_result get_channel_status(
-        struct aux_engine *engine,
+        struct dce_aux *engine,
         uint8_t *returned_bytes)
 {
         struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
@@ -414,469 +363,22 @@ static enum aux_channel_operation_result get_channel_status(
                 return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
         }
 }
-static void process_read_reply(
-        struct aux_engine *engine,
-        struct read_command_context *ctx)
-{
-        engine->funcs->process_channel_reply(engine, &ctx->reply);
-
-        switch (ctx->reply.status) {
-        case AUX_TRANSACTION_REPLY_AUX_ACK:
-                ctx->defer_retry_aux = 0;
-                if (ctx->returned_byte > ctx->current_read_length) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else if (ctx->returned_byte < ctx->current_read_length) {
-                        ctx->current_read_length -= ctx->returned_byte;
-
-                        ctx->offset += ctx->returned_byte;
-
-                        ++ctx->invalid_reply_retry_aux_on_ack;
-
-                        if (ctx->invalid_reply_retry_aux_on_ack >
-                                AUX_INVALID_REPLY_RETRY_COUNTER) {
-                                ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                                ctx->operation_succeeded = false;
-                        }
-                } else {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-                        ctx->transaction_complete = true;
-                        ctx->operation_succeeded = true;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_NACK:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-                ctx->operation_succeeded = false;
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_DEFER:
-                ++ctx->defer_retry_aux;
-
-                if (ctx->defer_retry_aux > AUX_DEFER_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_I2C_DEFER:
-                ctx->defer_retry_aux = 0;
-
-                ++ctx->defer_retry_i2c;
-
-                if (ctx->defer_retry_i2c > AUX_DEFER_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-static void process_read_request(
-        struct aux_engine *engine,
-        struct read_command_context *ctx)
-{
-        enum aux_channel_operation_result operation_result;
 
-        engine->funcs->submit_channel_request(engine, &ctx->request);
-
-        operation_result = engine->funcs->get_channel_status(
-                engine, &ctx->returned_byte);
-
-        switch (operation_result) {
-        case AUX_CHANNEL_OPERATION_SUCCEEDED:
-                if (ctx->returned_byte > ctx->current_read_length) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else {
-                        ctx->timed_out_retry_aux = 0;
-                        ctx->invalid_reply_retry_aux = 0;
-
-                        ctx->reply.length = ctx->returned_byte;
-                        ctx->reply.data = ctx->buffer;
-
-                        process_read_reply(engine, ctx);
-                }
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-                ++ctx->invalid_reply_retry_aux;
-
-                if (ctx->invalid_reply_retry_aux >
-                        AUX_INVALID_REPLY_RETRY_COUNTER) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else
-                        udelay(400);
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-                ++ctx->timed_out_retry_aux;
-
-                if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                } else {
-                        /* DP 1.2a, table 2-58:
-                         * "S3: AUX Request CMD PENDING:
-                         * retry 3 times, with 400usec wait on each"
-                         * The HW timeout is set to 550usec,
-                         * so we should not wait here
-                         */
-                }
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-static bool read_command(
-        struct aux_engine *engine,
-        struct i2caux_transaction_request *request,
-        bool middle_of_transaction)
-{
-        struct read_command_context ctx;
-
-        ctx.buffer = request->payload.data;
-        ctx.current_read_length = request->payload.length;
-        ctx.offset = 0;
-        ctx.timed_out_retry_aux = 0;
-        ctx.invalid_reply_retry_aux = 0;
-        ctx.defer_retry_aux = 0;
-        ctx.defer_retry_i2c = 0;
-        ctx.invalid_reply_retry_aux_on_ack = 0;
-        ctx.transaction_complete = false;
-        ctx.operation_succeeded = true;
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-                ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_READ;
-                ctx.request.address = request->payload.address;
-        } else if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-                ctx.request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ;
-                ctx.request.address = request->payload.address >> 1;
-        } else {
-                /* in DAL2, there was no return in such case */
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        ctx.request.delay = 0;
-
-        do {
-                memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
-
-                ctx.request.data = ctx.buffer + ctx.offset;
-                ctx.request.length = ctx.current_read_length;
-
-                process_read_request(engine, &ctx);
-
-                request->status = ctx.status;
-
-                if (ctx.operation_succeeded && !ctx.transaction_complete)
-                        if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-                                msleep(engine->delay);
-        } while (ctx.operation_succeeded && !ctx.transaction_complete);
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                DC_LOG_I2C_AUX("READ: addr:0x%x  value:0x%x Result:%d",
-                                request->payload.address,
-                                request->payload.data[0],
-                                ctx.operation_succeeded);
-        }
-
-        return ctx.operation_succeeded;
-}
-
-static void process_write_reply(
-        struct aux_engine *engine,
-        struct write_command_context *ctx)
-{
-        engine->funcs->process_channel_reply(engine, &ctx->reply);
-
-        switch (ctx->reply.status) {
-        case AUX_TRANSACTION_REPLY_AUX_ACK:
-                ctx->operation_succeeded = true;
-
-                if (ctx->returned_byte) {
-                        ctx->request.action = ctx->mot ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-
-                        ctx->current_write_length = 0;
-
-                        ++ctx->ack_m_retry;
-
-                        if (ctx->ack_m_retry > AUX_DEFER_RETRY_COUNTER) {
-                                ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                                ctx->operation_succeeded = false;
-                        } else
-                                udelay(300);
-                } else {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-                        ctx->defer_retry_aux = 0;
-                        ctx->ack_m_retry = 0;
-                        ctx->transaction_complete = true;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_NACK:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-                ctx->operation_succeeded = false;
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_DEFER:
-                ++ctx->defer_retry_aux;
-
-                if (ctx->defer_retry_aux > ctx->max_defer_retry) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_I2C_DEFER:
-                ctx->defer_retry_aux = 0;
-                ctx->current_write_length = 0;
-
-                ctx->request.action = ctx->mot ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-
-                ++ctx->defer_retry_i2c;
-
-                if (ctx->defer_retry_i2c > ctx->max_defer_retry) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-static void process_write_request(
-        struct aux_engine *engine,
-        struct write_command_context *ctx)
-{
-        enum aux_channel_operation_result operation_result;
-
-        engine->funcs->submit_channel_request(engine, &ctx->request);
-
-        operation_result = engine->funcs->get_channel_status(
-                engine, &ctx->returned_byte);
-
-        switch (operation_result) {
-        case AUX_CHANNEL_OPERATION_SUCCEEDED:
-                ctx->timed_out_retry_aux = 0;
-                ctx->invalid_reply_retry_aux = 0;
-
-                ctx->reply.length = ctx->returned_byte;
-                ctx->reply.data = ctx->reply_data;
-
-                process_write_reply(engine, ctx);
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-                ++ctx->invalid_reply_retry_aux;
-
-                if (ctx->invalid_reply_retry_aux >
-                        AUX_INVALID_REPLY_RETRY_COUNTER) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else
-                        udelay(400);
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-                ++ctx->timed_out_retry_aux;
-
-                if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                } else {
-                        /* DP 1.2a, table 2-58:
-                         * "S3: AUX Request CMD PENDING:
-                         * retry 3 times, with 400usec wait on each"
-                         * The HW timeout is set to 550usec,
-                         * so we should not wait here
-                         */
-                }
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-static bool write_command(
-        struct aux_engine *engine,
-        struct i2caux_transaction_request *request,
-        bool middle_of_transaction)
-{
-        struct write_command_context ctx;
-
-        ctx.mot = middle_of_transaction;
-        ctx.buffer = request->payload.data;
-        ctx.current_write_length = request->payload.length;
-        ctx.timed_out_retry_aux = 0;
-        ctx.invalid_reply_retry_aux = 0;
-        ctx.defer_retry_aux = 0;
-        ctx.defer_retry_i2c = 0;
-        ctx.ack_m_retry = 0;
-        ctx.transaction_complete = false;
-        ctx.operation_succeeded = true;
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-                ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_WRITE;
-                ctx.request.address = request->payload.address;
-        } else if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-                ctx.request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-                ctx.request.address = request->payload.address >> 1;
-        } else {
-                /* in DAL2, there was no return in such case */
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        ctx.request.delay = 0;
-
-        ctx.max_defer_retry =
-                (engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
-                        engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
-
-        do {
-                ctx.request.data = ctx.buffer;
-                ctx.request.length = ctx.current_write_length;
-
-                process_write_request(engine, &ctx);
-
-                request->status = ctx.status;
-
-                if (ctx.operation_succeeded && !ctx.transaction_complete)
-                        if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-                                msleep(engine->delay);
-        } while (ctx.operation_succeeded && !ctx.transaction_complete);
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                DC_LOG_I2C_AUX("WRITE: addr:0x%x  value:0x%x Result:%d",
-                                request->payload.address,
-                                request->payload.data[0],
-                                ctx.operation_succeeded);
-        }
-
-        return ctx.operation_succeeded;
-}
-static bool end_of_transaction_command(
-        struct aux_engine *engine,
-        struct i2caux_transaction_request *request)
-{
-        struct i2caux_transaction_request dummy_request;
-        uint8_t dummy_data;
-
-        /* [tcheng] We only need to send the stop (read with MOT = 0)
-         * for I2C-over-Aux, not native AUX
-         */
-
-        if (request->payload.address_space !=
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C)
-                return false;
-
-        dummy_request.operation = request->operation;
-        dummy_request.payload.address_space = request->payload.address_space;
-        dummy_request.payload.address = request->payload.address;
-
-        /*
-         * Add a dummy byte due to some receiver quirk
-         * where one byte is sent along with MOT = 0.
-         * Ideally this should be 0.
-         */
-
-        dummy_request.payload.length = 0;
-        dummy_request.payload.data = &dummy_data;
-
-        if (request->operation == I2CAUX_TRANSACTION_READ)
-                return read_command(engine, &dummy_request, false);
-        else
-                return write_command(engine, &dummy_request, false);
-
-        /* according Syed, it does not need now DoDummyMOT */
-}
-static bool submit_request(
-        struct aux_engine *engine,
-        struct i2caux_transaction_request *request,
-        bool middle_of_transaction)
-{
-
-        bool result;
-        bool mot_used = true;
-
-        switch (request->operation) {
-        case I2CAUX_TRANSACTION_READ:
-                result = read_command(engine, request, mot_used);
-        break;
-        case I2CAUX_TRANSACTION_WRITE:
-                result = write_command(engine, request, mot_used);
-        break;
-        default:
-                result = false;
-        }
-
-        /* [tcheng]
-         * need to send stop for the last transaction to free up the AUX
-         * if the above command fails, this would be the last transaction
-         */
-
-        if (!middle_of_transaction || !result)
-                end_of_transaction_command(engine, request);
-
-        /* mask AUX interrupt */
-
-        return result;
-}
 enum i2caux_engine_type get_engine_type(
-                const struct aux_engine *engine)
+                const struct dce_aux *engine)
 {
         return I2CAUX_ENGINE_TYPE_AUX;
 }
 
 static bool acquire(
-        struct aux_engine *engine,
+        struct dce_aux *engine,
         struct ddc *ddc)
 {
 
         enum gpio_result result;
 
-        if (engine->funcs->is_engine_available) {
-                /*check whether SW could use the engine*/
-                if (!engine->funcs->is_engine_available(engine))
-                        return false;
-        }
+        if (!is_engine_available(engine))
+                return false;
 
         result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
                 GPIO_DDC_CONFIG_TYPE_MODE_AUX);
@@ -884,7 +386,7 @@ static bool acquire(
         if (result != GPIO_RESULT_OK)
                 return false;
 
-        if (!engine->funcs->acquire_engine(engine)) {
+        if (!acquire_engine(engine)) {
                 dal_ddc_close(ddc);
                 return false;
         }
@@ -894,21 +396,7 @@ static bool acquire(
         return true;
 }
 
-static const struct aux_engine_funcs aux_engine_funcs = {
-        .acquire_engine = acquire_engine,
-        .submit_channel_request = submit_channel_request,
-        .process_channel_reply = process_channel_reply,
-        .read_channel_reply = read_channel_reply,
-        .get_channel_status = get_channel_status,
-        .is_engine_available = is_engine_available,
-        .release_engine = release_engine,
-        .destroy_engine = dce110_engine_destroy,
-        .submit_request = submit_request,
-        .get_engine_type = get_engine_type,
-        .acquire = acquire,
-};
-
-void dce110_engine_destroy(struct aux_engine **engine)
+void dce110_engine_destroy(struct dce_aux **engine)
 {
 
         struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine);
@@ -917,7 +405,7 @@ void dce110_engine_destroy(struct aux_engine **engine)
         *engine = NULL;
 
 }
-struct aux_engine *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
+struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,
                 struct dc_context *ctx,
                 uint32_t inst,
                 uint32_t timeout_period,
@@ -927,7 +415,6 @@ struct aux_engine *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_eng
         aux_engine110->base.ctx = ctx;
         aux_engine110->base.delay = 0;
         aux_engine110->base.max_defer_write_retry = 0;
-        aux_engine110->base.funcs = &aux_engine_funcs;
         aux_engine110->base.inst = inst;
         aux_engine110->timeout_period = timeout_period;
         aux_engine110->regs = regs;
@@ -935,3 +422,101 @@ struct aux_engine *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_eng
         return &aux_engine110->base;
 }
 
+static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payload *payload)
+{
+        if (payload->i2c_over_aux) {
+                if (payload->write) {
+                        if (payload->mot)
+                                return I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT;
+                        return I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
+                }
+                if (payload->mot)
+                        return I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT;
+                return I2CAUX_TRANSACTION_ACTION_I2C_READ;
+        }
+        if (payload->write)
+                return I2CAUX_TRANSACTION_ACTION_DP_WRITE;
+        return I2CAUX_TRANSACTION_ACTION_DP_READ;
+}
+
+int dce_aux_transfer(struct ddc_service *ddc,
+                struct aux_payload *payload)
+{
+        struct ddc *ddc_pin = ddc->ddc_pin;
+        struct dce_aux *aux_engine;
+        enum aux_channel_operation_result operation_result;
+        struct aux_request_transaction_data aux_req;
+        struct aux_reply_transaction_data aux_rep;
+        uint8_t returned_bytes = 0;
+        int res = -1;
+        uint32_t status;
+
+        memset(&aux_req, 0, sizeof(aux_req));
+        memset(&aux_rep, 0, sizeof(aux_rep));
+
+        aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+        acquire(aux_engine, ddc_pin);
+
+        if (payload->i2c_over_aux)
+                aux_req.type = AUX_TRANSACTION_TYPE_I2C;
+        else
+                aux_req.type = AUX_TRANSACTION_TYPE_DP;
+
+        aux_req.action = i2caux_action_from_payload(payload);
+
+        aux_req.address = payload->address;
+        aux_req.delay = payload->defer_delay * 10;
+        aux_req.length = payload->length;
+        aux_req.data = payload->data;
+
+        submit_channel_request(aux_engine, &aux_req);
+        operation_result = get_channel_status(aux_engine, &returned_bytes);
+
+        switch (operation_result) {
+        case AUX_CHANNEL_OPERATION_SUCCEEDED:
+                res = read_channel_reply(aux_engine, payload->length,
+                                                        payload->data, payload->reply,
+                                                        &status);
+                break;
+        case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
+                res = 0;
+                break;
+        case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
+        case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
+        case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
+                res = -1;
+                break;
+        }
+        release_engine(aux_engine);
+        return res;
+}
+
+#define AUX_RETRY_MAX 7
+
+bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+                struct aux_payload *payload)
+{
+        int i, ret = 0;
+        uint8_t reply;
+        bool payload_reply = true;
+
+        if (!payload->reply) {
+                payload_reply = false;
+                payload->reply = &reply;
+        }
+
+        for (i = 0; i < AUX_RETRY_MAX; i++) {
+                ret = dce_aux_transfer(ddc, payload);
+
+                if (ret >= 0) {
+                        if (*payload->reply == 0) {
+                                if (!payload_reply)
+                                        payload->reply = NULL;
+                                return true;
+                        }
+                }
+
+                msleep(1);
+        }
+        return false;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index f7caab85dc80..d27f22c05e4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -25,7 +25,9 @@
 
 #ifndef __DAL_AUX_ENGINE_DCE110_H__
 #define __DAL_AUX_ENGINE_DCE110_H__
-#include "aux_engine.h"
+
+#include "i2caux_interface.h"
+#include "inc/hw/aux_engine.h"
 
 #define AUX_COMMON_REG_LIST(id)\
         SRI(AUX_CONTROL, DP_AUX, id), \
@@ -75,8 +77,20 @@ enum {	/* This is the timeout as defined in DP 1.2a,
          */
         SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
 };
+
+struct dce_aux {
+        uint32_t inst;
+        struct ddc *ddc;
+        struct dc_context *ctx;
+        /* following values are expressed in milliseconds */
+        uint32_t delay;
+        uint32_t max_defer_write_retry;
+
+        bool acquire_reset;
+};
+
 struct aux_engine_dce110 {
-        struct aux_engine base;
+        struct dce_aux base;
         const struct dce110_aux_registers *regs;
         struct {
                 uint32_t aux_control;
@@ -96,16 +110,22 @@ struct aux_engine_dce110_init_data {
         const struct dce110_aux_registers *regs;
 };
 
-struct aux_engine *dce110_aux_engine_construct(
+struct dce_aux *dce110_aux_engine_construct(
                 struct aux_engine_dce110 *aux_engine110,
                 struct dc_context *ctx,
                 uint32_t inst,
                 uint32_t timeout_period,
                 const struct dce110_aux_registers *regs);
 
-void dce110_engine_destroy(struct aux_engine **engine);
+void dce110_engine_destroy(struct dce_aux **engine);
 
 bool dce110_aux_engine_acquire(
-        struct aux_engine *aux_engine,
+        struct dce_aux *aux_engine,
         struct ddc *ddc);
+
+int dce_aux_transfer(struct ddc_service *ddc,
+                struct aux_payload *cmd);
+
+bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
+                struct aux_payload *cmd);
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
index afd287f08bc9..3c52a4fc921d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
@@ -194,8 +194,8 @@ static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context)
                 if (pipe_ctx->top_pipe)
                         continue;
 
-                if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
-                        max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
+                if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
+                        max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
 
                 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS
                  * logic for HBR3 still needs Nominal (0.8V) on VDDC rail
@@ -257,7 +257,7 @@ static int dce_set_clock(
                                 clk_mgr_dce->dentist_vco_freq_khz / 64);
 
         /* Prepare to program display clock*/
-        pxl_clk_params.target_pixel_clock = requested_clk_khz;
+        pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
         pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 
         if (clk_mgr_dce->dfs_bypass_active)
@@ -450,6 +450,42 @@ void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce)
         }
 }
 
+/**
+ * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
+ * @clk_mgr: clock manager base structure
+ *
+ * Reads from VBIOS the XGMI spread spectrum info and saves it within
+ * the dce clock manager. This operation will overwrite the existing dprefclk
+ * SS values if the vBIOS query succeeds. Otherwise, it does nothing. It also
+ * sets the ->xgmi_enabled flag.
+ */
+void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr)
+{
+        struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
+        enum bp_result result;
+        struct spread_spectrum_info info = { { 0 } };
+        struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
+
+        clk_mgr_dce->xgmi_enabled = false;
+
+        result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI,
+                                                     0, &info);
+        if (result == BP_RESULT_OK && info.spread_spectrum_percentage != 0) {
+                clk_mgr_dce->xgmi_enabled = true;
+                clk_mgr_dce->ss_on_dprefclk = true;
+                clk_mgr_dce->dprefclk_ss_divider =
+                                info.spread_percentage_divider;
+
+                if (info.type.CENTER_MODE == 0) {
+                        /* Currently for DP Reference clock we
+                         * need only SS percentage for
+                         * downspread */
+                        clk_mgr_dce->dprefclk_ss_percentage =
+                                        info.spread_spectrum_percentage;
+                }
+        }
+}
+
 void dce110_fill_display_configs(
         const struct dc_state *context,
         struct dm_pp_display_configuration *pp_display_cfg)
@@ -483,18 +519,18 @@ void dce110_fill_display_configs(
                 cfg->src_height = stream->src.height;
                 cfg->src_width = stream->src.width;
                 cfg->ddi_channel_mapping =
-                        stream->sink->link->ddi_channel_mapping.raw;
+                        stream->link->ddi_channel_mapping.raw;
                 cfg->transmitter =
-                        stream->sink->link->link_enc->transmitter;
+                        stream->link->link_enc->transmitter;
                 cfg->link_settings.lane_count =
-                        stream->sink->link->cur_link_settings.lane_count;
+                        stream->link->cur_link_settings.lane_count;
                 cfg->link_settings.link_rate =
-                        stream->sink->link->cur_link_settings.link_rate;
+                        stream->link->cur_link_settings.link_rate;
                 cfg->link_settings.link_spread =
-                        stream->sink->link->cur_link_settings.link_spread;
+                        stream->link->cur_link_settings.link_spread;
                 cfg->sym_clock = stream->phy_pix_clk;
                 /* Round v_refresh*/
-                cfg->v_refresh = stream->timing.pix_clk_khz * 1000;
+                cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
                 cfg->v_refresh /= stream->timing.h_total;
                 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
                                                         / stream->timing.v_total;
@@ -518,7 +554,7 @@ static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context)
                          - stream->timing.v_addressable);
 
                 vertical_blank_time = vertical_blank_in_pixels
-                        * 1000 / stream->timing.pix_clk_khz;
+                        * 10000 / stream->timing.pix_clk_100hz;
 
                 if (min_vertical_blank_time > vertical_blank_time)
                         min_vertical_blank_time = vertical_blank_time;
@@ -612,7 +648,7 @@ static void dce11_pplib_apply_display_requirements(
 
                 pp_display_cfg->crtc_index =
                         pp_display_cfg->disp_configs[0].pipe_idx;
-                pp_display_cfg->line_time_in_us = timing->h_total * 1000 / timing->pix_clk_khz;
+                pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
         }
 
         if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
@@ -625,11 +661,11 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr,
 {
         struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
         struct dm_pp_power_level_change_request level_change_req;
-        int unpatched_disp_clk = context->bw.dce.dispclk_khz;
+        int patched_disp_clk = context->bw.dce.dispclk_khz;
 
         /*TODO: W/A for dal3 linux, investigate why this works */
         if (!clk_mgr_dce->dfs_bypass_active)
-                context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
+                patched_disp_clk = patched_disp_clk * 115 / 100;
 
         level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
         /* get max clock state from PPLIB */
@@ -639,13 +675,11 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr,
                         clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
         }
 
-        if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
-                context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
-                clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz; 
+        if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
+                patched_disp_clk = dce_set_clock(clk_mgr, patched_disp_clk);
+                clk_mgr->clks.dispclk_khz = patched_disp_clk;
         }
         dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
-
-        context->bw.dce.dispclk_khz = unpatched_disp_clk;
 }
 
 static void dce11_update_clocks(struct clk_mgr *clk_mgr,
@@ -676,11 +710,11 @@ static void dce112_update_clocks(struct clk_mgr *clk_mgr,
 {
         struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
         struct dm_pp_power_level_change_request level_change_req;
-        int unpatched_disp_clk = context->bw.dce.dispclk_khz;
+        int patched_disp_clk = context->bw.dce.dispclk_khz;
 
         /*TODO: W/A for dal3 linux, investigate why this works */
         if (!clk_mgr_dce->dfs_bypass_active)
-                context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
+                patched_disp_clk = patched_disp_clk * 115 / 100;
 
         level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
         /* get max clock state from PPLIB */
@@ -690,13 +724,11 @@ static void dce112_update_clocks(struct clk_mgr *clk_mgr,
                         clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
         }
 
-        if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
-                context->bw.dce.dispclk_khz = dce112_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
-                clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
+        if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
+                patched_disp_clk = dce112_set_clock(clk_mgr, patched_disp_clk);
+                clk_mgr->clks.dispclk_khz = patched_disp_clk;
         }
         dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
-
-        context->bw.dce.dispclk_khz = unpatched_disp_clk;
 }
 
 static void dce12_update_clocks(struct clk_mgr *clk_mgr,
@@ -706,17 +738,23 @@ static void dce12_update_clocks(struct clk_mgr *clk_mgr,
         struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
         struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
         int max_pix_clk = get_max_pixel_clock_for_all_paths(context);
-        int unpatched_disp_clk = context->bw.dce.dispclk_khz;
+        int patched_disp_clk = context->bw.dce.dispclk_khz;
 
         /*TODO: W/A for dal3 linux, investigate why this works */
         if (!clk_mgr_dce->dfs_bypass_active)
-                context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
+                patched_disp_clk = patched_disp_clk * 115 / 100;
 
-        if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
+        if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
                 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
-                clock_voltage_req.clocks_in_khz = context->bw.dce.dispclk_khz;
-                context->bw.dce.dispclk_khz = dce112_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
-                clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
+                /*
+                 * When xGMI is enabled, the display clk needs to be adjusted
+                 * with the WAFL link's SS percentage.
+                 */
+                if (clk_mgr_dce->xgmi_enabled)
+                        patched_disp_clk = clk_mgr_adjust_dp_ref_freq_for_ss(
+                                        clk_mgr_dce, patched_disp_clk);
+                clock_voltage_req.clocks_in_khz = patched_disp_clk;
+                clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk);
 
                 dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
         }
@@ -729,8 +767,6 @@ static void dce12_update_clocks(struct clk_mgr *clk_mgr,
                 dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req);
         }
         dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
-
-        context->bw.dce.dispclk_khz = unpatched_disp_clk;
 }
 
 static const struct clk_mgr_funcs dce120_funcs = {
@@ -882,6 +918,27 @@ struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx)
         return &clk_mgr_dce->base;
 }
 
+struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx)
+{
+        struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce),
+                                                  GFP_KERNEL);
+
+        if (clk_mgr_dce == NULL) {
+                BREAK_TO_DEBUGGER();
+                return NULL;
+        }
+
+        memcpy(clk_mgr_dce->max_clks_by_state, dce120_max_clks_by_state,
+               sizeof(dce120_max_clks_by_state));
+
+        dce_clk_mgr_construct(clk_mgr_dce, ctx, NULL, NULL, NULL);
+
+        clk_mgr_dce->dprefclk_khz = 625000;
+        clk_mgr_dce->base.funcs = &dce120_funcs;
+
+        return &clk_mgr_dce->base;
+}
+
 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr)
 {
         struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
index 3bceb31d910d..c8f8c442142a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.h
@@ -94,11 +94,37 @@ struct dce_clk_mgr {
          * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
         int dfs_bypass_disp_clk;
 
-        /* Flag for Enabled SS on DPREFCLK */
+        /**
+         * @ss_on_dprefclk:
+         *
+         * True if spread spectrum is enabled on the DP ref clock.
+         */
         bool ss_on_dprefclk;
-        /* DPREFCLK SS percentage (if down-spread enabled) */
+
+        /**
+         * @xgmi_enabled:
+         *
+         * True if xGMI is enabled. On VG20, both audio and display clocks need
+         * to be adjusted with the WAFL link's SS info if xGMI is enabled.
+         */
+        bool xgmi_enabled;
+
+        /**
+         * @dprefclk_ss_percentage:
+         *
+         * DPREFCLK SS percentage (if down-spread enabled).
+         *
+         * Note that if XGMI is enabled, the SS info (percentage and divider)
+         * from the WAFL link is used instead. This is decided during
+         * dce_clk_mgr initialization.
+         */
         int dprefclk_ss_percentage;
-        /* DPREFCLK SS percentage Divider (100 or 1000) */
+
+        /**
+         * @dprefclk_ss_divider:
+         *
+         * DPREFCLK SS percentage Divider (100 or 1000).
+         */
         int dprefclk_ss_divider;
         int dprefclk_khz;
 
@@ -163,6 +189,9 @@ struct clk_mgr *dce112_clk_mgr_create(
 
 struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx);
 
+struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx);
+void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr);
+
 void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr);
 
 int dentist_get_divider_from_did(int did);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 723ce80ed89c..c67e90e5c339 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -108,28 +108,28 @@ static const struct spread_spectrum_data *get_ss_data_entry(
 }
 
 /**
-* Function: calculate_fb_and_fractional_fb_divider
-*
-* * DESCRIPTION: Calculates feedback and fractional feedback dividers values
-*
-*PARAMETERS:
-* targetPixelClock             Desired frequency in 10 KHz
-* ref_divider                  Reference divider (already known)
-* postDivider                  Post Divider (already known)
-* feedback_divider_param       Pointer where to store
-*                                       calculated feedback divider value
-* fract_feedback_divider_param Pointer where to store
-*                                       calculated fract feedback divider value
-*
-*RETURNS:
-* It fills the locations pointed by feedback_divider_param
-*                                       and fract_feedback_divider_param
-* It returns    - true if feedback divider not 0
-*               - false should never happen)
-*/
+ * Function: calculate_fb_and_fractional_fb_divider
+ *
+ * * DESCRIPTION: Calculates feedback and fractional feedback dividers values
+ *
+ *PARAMETERS:
+ * targetPixelClock             Desired frequency in 100 Hz
+ * ref_divider                  Reference divider (already known)
+ * postDivider                  Post Divider (already known)
+ * feedback_divider_param       Pointer where to store
+ *                                      calculated feedback divider value
+ * fract_feedback_divider_param Pointer where to store
+ *                                      calculated fract feedback divider value
+ *
+ *RETURNS:
+ * It fills the locations pointed by feedback_divider_param
+ *                                      and fract_feedback_divider_param
+ * It returns   - true if feedback divider not 0
+ *              - false should never happen)
+ */
 static bool calculate_fb_and_fractional_fb_divider(
                 struct calc_pll_clock_source *calc_pll_cs,
-                uint32_t target_pix_clk_khz,
+                uint32_t target_pix_clk_100hz,
                 uint32_t ref_divider,
                 uint32_t post_divider,
                 uint32_t *feedback_divider_param,
@@ -138,11 +138,11 @@ static bool calculate_fb_and_fractional_fb_divider(
         uint64_t feedback_divider;
 
         feedback_divider =
-                (uint64_t)target_pix_clk_khz * ref_divider * post_divider;
+                (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
         feedback_divider *= 10;
         /* additional factor, since we divide by 10 afterwards */
         feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
-        feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz);
+        feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
 
 /*Round to the number of precision
  * The following code replace the old code (ullfeedbackDivider + 5)/10
@@ -195,36 +195,36 @@ static bool calc_fb_divider_checking_tolerance(
 {
         uint32_t feedback_divider;
         uint32_t fract_feedback_divider;
-        uint32_t actual_calculated_clock_khz;
+        uint32_t actual_calculated_clock_100hz;
         uint32_t abs_err;
-        uint64_t actual_calc_clk_khz;
+        uint64_t actual_calc_clk_100hz;
 
         calculate_fb_and_fractional_fb_divider(
                         calc_pll_cs,
-                        pll_settings->adjusted_pix_clk,
+                        pll_settings->adjusted_pix_clk_100hz,
                         ref_divider,
                         post_divider,
                         &feedback_divider,
                         &fract_feedback_divider);
 
         /*Actual calculated value*/
-        actual_calc_clk_khz = (uint64_t)feedback_divider *
+        actual_calc_clk_100hz = (uint64_t)feedback_divider *
                                         calc_pll_cs->fract_fb_divider_factor +
                                                         fract_feedback_divider;
-        actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
-        actual_calc_clk_khz =
-                div_u64(actual_calc_clk_khz,
+        actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10;
+        actual_calc_clk_100hz =
+                div_u64(actual_calc_clk_100hz,
                         ref_divider * post_divider *
                                 calc_pll_cs->fract_fb_divider_factor);
 
-        actual_calculated_clock_khz = (uint32_t)(actual_calc_clk_khz);
+        actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
 
-        abs_err = (actual_calculated_clock_khz >
-                                        pll_settings->adjusted_pix_clk)
-                        ? actual_calculated_clock_khz -
-                                        pll_settings->adjusted_pix_clk
-                        : pll_settings->adjusted_pix_clk -
-                                                actual_calculated_clock_khz;
+        abs_err = (actual_calculated_clock_100hz >
+                                        pll_settings->adjusted_pix_clk_100hz)
+                        ? actual_calculated_clock_100hz -
+                                        pll_settings->adjusted_pix_clk_100hz
+                        : pll_settings->adjusted_pix_clk_100hz -
+                                                actual_calculated_clock_100hz;
 
         if (abs_err <= tolerance) {
                 /*found good values*/
@@ -233,10 +233,10 @@ static bool calc_fb_divider_checking_tolerance(
                 pll_settings->feedback_divider = feedback_divider;
                 pll_settings->fract_feedback_divider = fract_feedback_divider;
                 pll_settings->pix_clk_post_divider = post_divider;
-                pll_settings->calculated_pix_clk =
-                        actual_calculated_clock_khz;
+                pll_settings->calculated_pix_clk_100hz =
+                        actual_calculated_clock_100hz;
                 pll_settings->vco_freq =
-                        actual_calculated_clock_khz * post_divider;
+                        actual_calculated_clock_100hz * post_divider / 10;
                 return true;
         }
         return false;
@@ -257,8 +257,8 @@ static bool calc_pll_dividers_in_range(
 
 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
  * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
-        tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /
-                                                                        10000;
+        tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
+                                                                        100000;
         if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
                 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
 
@@ -294,7 +294,7 @@ static uint32_t calculate_pixel_clock_pll_dividers(
         uint32_t min_ref_divider;
         uint32_t max_ref_divider;
 
-        if (pll_settings->adjusted_pix_clk == 0) {
+        if (pll_settings->adjusted_pix_clk_100hz == 0) {
                 DC_LOG_ERROR(
                         "%s Bad requested pixel clock", __func__);
                 return MAX_PLL_CALC_ERROR;
@@ -306,21 +306,21 @@ static uint32_t calculate_pixel_clock_pll_dividers(
                 max_post_divider = pll_settings->pix_clk_post_divider;
         } else {
                 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
-                if (min_post_divider * pll_settings->adjusted_pix_clk <
-                                                calc_pll_cs->min_vco_khz) {
-                        min_post_divider = calc_pll_cs->min_vco_khz /
-                                        pll_settings->adjusted_pix_clk;
+                if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
+                                                calc_pll_cs->min_vco_khz * 10) {
+                        min_post_divider = calc_pll_cs->min_vco_khz * 10 /
+                                        pll_settings->adjusted_pix_clk_100hz;
                         if ((min_post_divider *
-                                        pll_settings->adjusted_pix_clk) <
-                                                calc_pll_cs->min_vco_khz)
+                                        pll_settings->adjusted_pix_clk_100hz) <
+                                                calc_pll_cs->min_vco_khz * 10)
                                 min_post_divider++;
                 }
 
                 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
-                if (max_post_divider * pll_settings->adjusted_pix_clk
-                                > calc_pll_cs->max_vco_khz)
-                        max_post_divider = calc_pll_cs->max_vco_khz /
-                                        pll_settings->adjusted_pix_clk;
+                if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
+                                > calc_pll_cs->max_vco_khz * 10)
+                        max_post_divider = calc_pll_cs->max_vco_khz * 10 /
+                                        pll_settings->adjusted_pix_clk_100hz;
         }
 
 /* 2) Find Reference divider ranges
@@ -392,47 +392,47 @@ static bool pll_adjust_pix_clk(
                 struct pixel_clk_params *pix_clk_params,
                 struct pll_settings *pll_settings)
 {
-        uint32_t actual_pix_clk_khz = 0;
-        uint32_t requested_clk_khz = 0;
+        uint32_t actual_pix_clk_100hz = 0;
+        uint32_t requested_clk_100hz = 0;
         struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
                                                         0 };
         enum bp_result bp_result;
         switch (pix_clk_params->signal_type) {
         case SIGNAL_TYPE_HDMI_TYPE_A: {
-                requested_clk_khz = pix_clk_params->requested_pix_clk;
+                requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
                 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
                         switch (pix_clk_params->color_depth) {
                         case COLOR_DEPTH_101010:
-                                requested_clk_khz = (requested_clk_khz * 5) >> 2;
+                                requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
                                 break; /* x1.25*/
                         case COLOR_DEPTH_121212:
-                                requested_clk_khz = (requested_clk_khz * 6) >> 2;
+                                requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
                                 break; /* x1.5*/
                         case COLOR_DEPTH_161616:
-                                requested_clk_khz = requested_clk_khz * 2;
+                                requested_clk_100hz = requested_clk_100hz * 2;
                                 break; /* x2.0*/
                         default:
                                 break;
                         }
                 }
-                actual_pix_clk_khz = requested_clk_khz;
+                actual_pix_clk_100hz = requested_clk_100hz;
         }
                 break;
 
         case SIGNAL_TYPE_DISPLAY_PORT:
         case SIGNAL_TYPE_DISPLAY_PORT_MST:
         case SIGNAL_TYPE_EDP:
-                requested_clk_khz = pix_clk_params->requested_sym_clk;
-                actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
+                requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
+                actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
                 break;
 
         default:
-                requested_clk_khz = pix_clk_params->requested_pix_clk;
-                actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
+                requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
+                actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
                 break;
         }
 
-        bp_adjust_pixel_clock_params.pixel_clock = requested_clk_khz;
+        bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
         bp_adjust_pixel_clock_params.
                 encoder_object_id = pix_clk_params->encoder_object_id;
         bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
@@ -441,9 +441,9 @@ static bool pll_adjust_pix_clk(
         bp_result = clk_src->bios->funcs->adjust_pixel_clock(
                         clk_src->bios, &bp_adjust_pixel_clock_params);
         if (bp_result == BP_RESULT_OK) {
-                pll_settings->actual_pix_clk = actual_pix_clk_khz;
-                pll_settings->adjusted_pix_clk =
-                        bp_adjust_pixel_clock_params.adjusted_pixel_clock;
+                pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
+                pll_settings->adjusted_pix_clk_100hz =
+                        bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
                 pll_settings->reference_divider =
                         bp_adjust_pixel_clock_params.reference_divider;
                 pll_settings->pix_clk_post_divider =
@@ -490,7 +490,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
                 const struct spread_spectrum_data *ss_data = get_ss_data_entry(
                                         clk_src,
                                         pix_clk_params->signal_type,
-                                        pll_settings->adjusted_pix_clk);
+                                        pll_settings->adjusted_pix_clk_100hz / 10);
 
                 if (NULL != ss_data)
                         pll_settings->ss_percentage = ss_data->percentage;
@@ -502,13 +502,13 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
                  * to continue. */
                 DC_LOG_ERROR(
                         "%s: Failed to adjust pixel clock!!", __func__);
-                pll_settings->actual_pix_clk =
-                                pix_clk_params->requested_pix_clk;
-                pll_settings->adjusted_pix_clk =
-                                pix_clk_params->requested_pix_clk;
+                pll_settings->actual_pix_clk_100hz =
+                                pix_clk_params->requested_pix_clk_100hz;
+                pll_settings->adjusted_pix_clk_100hz =
+                                pix_clk_params->requested_pix_clk_100hz;
 
                 if (dc_is_dp_signal(pix_clk_params->signal_type))
-                        pll_settings->adjusted_pix_clk = 100000;
+                        pll_settings->adjusted_pix_clk_100hz = 1000000;
         }
 
         /* Calculate Dividers */
@@ -533,28 +533,28 @@ static void dce112_get_pix_clk_dividers_helper (
                 struct pll_settings *pll_settings,
                 struct pixel_clk_params *pix_clk_params)
 {
-        uint32_t actualPixelClockInKHz;
+        uint32_t actual_pixel_clock_100hz;
 
-        actualPixelClockInKHz = pix_clk_params->requested_pix_clk;
+        actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
         /* Calculate Dividers */
         if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
                 switch (pix_clk_params->color_depth) {
                 case COLOR_DEPTH_101010:
-                        actualPixelClockInKHz = (actualPixelClockInKHz * 5) >> 2;
+                        actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
                         break;
                 case COLOR_DEPTH_121212:
-                        actualPixelClockInKHz = (actualPixelClockInKHz * 6) >> 2;
+                        actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
                         break;
                 case COLOR_DEPTH_161616:
-                        actualPixelClockInKHz = actualPixelClockInKHz * 2;
+                        actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
                         break;
                 default:
                         break;
                 }
         }
-        pll_settings->actual_pix_clk = actualPixelClockInKHz;
-        pll_settings->adjusted_pix_clk = actualPixelClockInKHz;
-        pll_settings->calculated_pix_clk = pix_clk_params->requested_pix_clk;
+        pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
+        pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
+        pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
 }
 
 static uint32_t dce110_get_pix_clk_dividers(
@@ -567,7 +567,7 @@ static uint32_t dce110_get_pix_clk_dividers(
         DC_LOGGER_INIT();
 
         if (pix_clk_params == NULL || pll_settings == NULL
-                        || pix_clk_params->requested_pix_clk == 0) {
+                        || pix_clk_params->requested_pix_clk_100hz == 0) {
                 DC_LOG_ERROR(
                         "%s: Invalid parameters!!\n", __func__);
                 return pll_calc_error;
@@ -577,10 +577,10 @@ static uint32_t dce110_get_pix_clk_dividers(
 
         if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
                         cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
-                pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
-                pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
-                pll_settings->actual_pix_clk =
-                                        pix_clk_params->requested_pix_clk;
+                pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
+                pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
+                pll_settings->actual_pix_clk_100hz =
+                                        pix_clk_params->requested_pix_clk_100hz;
                 return 0;
         }
 
@@ -599,7 +599,7 @@ static uint32_t dce112_get_pix_clk_dividers(
         DC_LOGGER_INIT();
 
         if (pix_clk_params == NULL || pll_settings == NULL
-                        || pix_clk_params->requested_pix_clk == 0) {
+                        || pix_clk_params->requested_pix_clk_100hz == 0) {
                 DC_LOG_ERROR(
                         "%s: Invalid parameters!!\n", __func__);
                 return -1;
@@ -609,10 +609,10 @@ static uint32_t dce112_get_pix_clk_dividers(
 
         if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
                         cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
-                pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
-                pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
-                pll_settings->actual_pix_clk =
-                                        pix_clk_params->requested_pix_clk;
+                pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
+                pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
+                pll_settings->actual_pix_clk_100hz =
+                                        pix_clk_params->requested_pix_clk_100hz;
                 return -1;
         }
 
@@ -714,7 +714,7 @@ static bool enable_spread_spectrum(
         ss_data = get_ss_data_entry(
                         clk_src,
                         signal,
-                        pll_settings->calculated_pix_clk);
+                        pll_settings->calculated_pix_clk_100hz / 10);
 
 /* Pixel clock PLL has been programmed to generate desired pixel clock,
  * now enable SS on pixel clock */
@@ -853,7 +853,7 @@ static bool dce110_program_pix_clk(
         /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
         bp_pc_params.controller_id = pix_clk_params->controller_id;
         bp_pc_params.pll_id = clock_source->id;
-        bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
+        bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
         bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
         bp_pc_params.signal_type = pix_clk_params->signal_type;
 
@@ -903,12 +903,12 @@ static bool dce112_program_pix_clk(
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
         if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
                 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
-                unsigned dp_dto_ref_kHz = 700000;
-                unsigned clock_kHz = pll_settings->actual_pix_clk;
+                unsigned dp_dto_ref_100hz = 7000000;
+                unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
 
                 /* Set DTO values: phase = target clock, modulo = reference clock */
-                REG_WRITE(PHASE[inst], clock_kHz);
-                REG_WRITE(MODULO[inst], dp_dto_ref_kHz);
+                REG_WRITE(PHASE[inst], clock_100hz);
+                REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
 
                 /* Enable DTO */
                 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
@@ -927,7 +927,7 @@ static bool dce112_program_pix_clk(
         /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
         bp_pc_params.controller_id = pix_clk_params->controller_id;
         bp_pc_params.pll_id = clock_source->id;
-        bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
+        bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
         bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
         bp_pc_params.signal_type = pix_clk_params->signal_type;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index dea40b322191..c2926cf19dee 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -51,7 +51,6 @@
 #define PSR_SET_WAITLOOP 0x31
 #define MCP_INIT_DMCU 0x88
 #define MCP_INIT_IRAM 0x89
-#define MCP_DMCU_VERSION 0x90
 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x00000001L
 
 static bool dce_dmcu_init(struct dmcu *dmcu)
@@ -317,38 +316,11 @@ static void dce_get_psr_wait_loop(
 }
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-static void dcn10_get_dmcu_state(struct dmcu *dmcu)
-{
-        struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
-        uint32_t dmcu_state_offset = 0xf6;
-
-        /* Enable write access to IRAM */
-        REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-                        IRAM_HOST_ACCESS_EN, 1,
-                        IRAM_RD_ADDR_AUTO_INC, 1);
-
-        REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10);
-
-        /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */
-        REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_state_offset);
-
-        /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/
-        dmcu->dmcu_state = REG_READ(DMCU_IRAM_RD_DATA);
-
-        /* Disable write access to IRAM to allow dynamic sleep state */
-        REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
-                        IRAM_HOST_ACCESS_EN, 0,
-                        IRAM_RD_ADDR_AUTO_INC, 0);
-}
-
 static void dcn10_get_dmcu_version(struct dmcu *dmcu)
 {
         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
         uint32_t dmcu_version_offset = 0xf1;
 
-        /* Clear scratch */
-        REG_WRITE(DC_DMCU_SCRATCH, 0);
-
         /* Enable write access to IRAM */
         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
                         IRAM_HOST_ACCESS_EN, 1,
@@ -359,85 +331,74 @@ static void dcn10_get_dmcu_version(struct dmcu *dmcu)
         /* Write address to IRAM_RD_ADDR and read from DATA register */
         REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
         dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);
-        dmcu->dmcu_version.year = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
+        dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);
+        dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);
+        dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |
                                                 REG_READ(DMCU_IRAM_RD_DATA));
-        dmcu->dmcu_version.month = REG_READ(DMCU_IRAM_RD_DATA);
-        dmcu->dmcu_version.date = REG_READ(DMCU_IRAM_RD_DATA);
 
         /* Disable write access to IRAM to allow dynamic sleep state */
         REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL,
                         IRAM_HOST_ACCESS_EN, 0,
                         IRAM_RD_ADDR_AUTO_INC, 0);
-
-        /* Send MCP command message to DMCU to get version reply from FW.
-         * We expect this version should match the one in IRAM, otherwise
-         * something is wrong with DMCU and we should fail and disable UC.
-         */
-        REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-
-        /* Set command to get DMCU version from microcontroller */
-        REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
-                        MCP_DMCU_VERSION);
-
-        /* Notify microcontroller of new command */
-        REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
-
-        /* Ensure command has been executed before continuing */
-        REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
-
-        /* Somehow version does not match, so fail and return version 0 */
-        if (dmcu->dmcu_version.interface_version != REG_READ(DC_DMCU_SCRATCH))
-                dmcu->dmcu_version.interface_version = 0;
 }
 
 static bool dcn10_dmcu_init(struct dmcu *dmcu)
 {
         struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
+        bool status = false;
 
-        /* DMCU FW should populate the scratch register if running */
-        if (REG_READ(DC_DMCU_SCRATCH) == 0)
-                return false;
-
-        /* Check state is uninitialized */
-        dcn10_get_dmcu_state(dmcu);
-
-        /* If microcontroller is already initialized, do nothing */
-        if (dmcu->dmcu_state == DMCU_RUNNING)
-                return true;
-
-        /* Retrieve and cache the DMCU firmware version. */
-        dcn10_get_dmcu_version(dmcu);
-
-        /* Check interface version to confirm firmware is loaded and running */
-        if (dmcu->dmcu_version.interface_version == 0)
-                return false;
+        /*  Definition of DC_DMCU_SCRATCH
+         *  0 : firmare not loaded
+         *  1 : PSP load DMCU FW but not initialized
+         *  2 : Firmware already initialized
+         */
+        dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
 
-        /* Wait until microcontroller is ready to process interrupt */
-        REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+        switch (dmcu->dmcu_state) {
+        case DMCU_UNLOADED:
+                status = false;
+                break;
+        case DMCU_LOADED_UNINITIALIZED:
+                /* Wait until microcontroller is ready to process interrupt */
+                REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 
-        /* Set initialized ramping boundary value */
-        REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
+                /* Set initialized ramping boundary value */
+                REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
 
-        /* Set command to initialize microcontroller */
-        REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
+                /* Set command to initialize microcontroller */
+                REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
                         MCP_INIT_DMCU);
 
-        /* Notify microcontroller of new command */
-        REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
+                /* Notify microcontroller of new command */
+                REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
 
-        /* Ensure command has been executed before continuing */
-        REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
+                /* Ensure command has been executed before continuing */
+                REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800);
 
-        // Check state is initialized
-        dcn10_get_dmcu_state(dmcu);
+                // Check state is initialized
+                dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);
 
-        // If microcontroller is not in running state, fail
-        if (dmcu->dmcu_state != DMCU_RUNNING)
-                return false;
+                // If microcontroller is not in running state, fail
+                if (dmcu->dmcu_state == DMCU_RUNNING) {
+                        /* Retrieve and cache the DMCU firmware version. */
+                        dcn10_get_dmcu_version(dmcu);
+                        status = true;
+                } else
+                        status = false;
 
-        return true;
+                break;
+        case DMCU_RUNNING:
+                status = true;
+                break;
+        default:
+                status = false;
+                break;
+        }
+
+        return status;
 }
 
+
 static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,
                 unsigned int start_offset,
                 const char *src,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index c83a7f05f14c..956bdf14503f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -133,6 +133,10 @@
         SR(DCHUB_AGP_TOP), \
         BL_REG_LIST()
 
+#define HWSEQ_VG20_REG_LIST() \
+        HWSEQ_DCE120_REG_LIST(),\
+        MMHUB_SR(MC_VM_XGMI_LFB_CNTL)
+
 #define HWSEQ_DCE112_REG_LIST() \
         HWSEQ_DCE10_REG_LIST(), \
         HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
@@ -298,6 +302,7 @@ struct dce_hwseq_registers {
         uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
         uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
         uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
+        uint32_t MC_VM_XGMI_LFB_CNTL;
         uint32_t AZALIA_AUDIO_DTO;
         uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
 };
@@ -382,6 +387,11 @@ struct dce_hwseq_registers {
         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
         HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 
+#define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
+        HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
+        HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\
+        HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh)
+
 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
         HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
         HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
@@ -470,6 +480,8 @@ struct dce_hwseq_registers {
         type PHYSICAL_PAGE_NUMBER_MSB;\
         type PHYSICAL_PAGE_NUMBER_LSB;\
         type LOGICAL_ADDR; \
+        type PF_LFB_REGION;\
+        type PF_MAX_REGION;\
         type ENABLE_L1_TLB;\
         type SYSTEM_ACCESS_MODE;\
         type LVTMA_BLON;\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 3e18ea84b1f9..314c04a915d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -599,12 +599,12 @@ bool dce110_link_encoder_validate_dvi_output(
         if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
                 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
                 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
-                crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
+                crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
                 return false;
-        if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
+        if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
                 return false;
 
-        if (crtc_timing->pix_clk_khz > max_pixel_clock)
+        if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
                 return false;
 
         /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
@@ -788,7 +788,7 @@ bool dce110_link_encoder_validate_output_with_stream(
         case SIGNAL_TYPE_DVI_DUAL_LINK:
                 is_valid = dce110_link_encoder_validate_dvi_output(
                         enc110,
-                        stream->sink->link->connector_signal,
+                        stream->link->connector_signal,
                         stream->signal,
                         &stream->timing);
         break;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index cce0d18f91da..1fa2d4fd7a35 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -288,9 +288,18 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
 #endif
 
         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-
+        struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
+        if (hw_crtc_timing.flags.INTERLACE) {
+                /*the input timing is in VESA spec format with Interlace flag =1*/
+                hw_crtc_timing.v_total /= 2;
+                hw_crtc_timing.v_border_top /= 2;
+                hw_crtc_timing.v_addressable /= 2;
+                hw_crtc_timing.v_border_bottom /= 2;
+                hw_crtc_timing.v_front_porch /= 2;
+                hw_crtc_timing.v_sync_width /= 2;
+        }
         /* set pixel encoding */
-        switch (crtc_timing->pixel_encoding) {
+        switch (hw_crtc_timing.pixel_encoding) {
         case PIXEL_ENCODING_YCBCR422:
                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
                                 DP_PIXEL_ENCODING_TYPE_YCBCR422);
@@ -299,8 +308,8 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
                 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
                                 DP_PIXEL_ENCODING_TYPE_YCBCR444);
 
-                if (crtc_timing->flags.Y_ONLY)
-                        if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
+                if (hw_crtc_timing.flags.Y_ONLY)
+                        if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
                                 /* HW testing only, no use case yet.
                                  * Color depth of Y-only could be
                                  * 8, 10, 12, 16 bits */
@@ -335,7 +344,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
 
         /* set color depth */
 
-        switch (crtc_timing->display_color_depth) {
+        switch (hw_crtc_timing.display_color_depth) {
         case COLOR_DEPTH_666:
                 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
                                 0);
@@ -363,7 +372,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
 
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-        switch (crtc_timing->display_color_depth) {
+        switch (hw_crtc_timing.display_color_depth) {
         case COLOR_DEPTH_666:
                 colorimetry_bpc = 0;
                 break;
@@ -401,9 +410,9 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
                         misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
                         dynamic_range_ycbcr = 0; /*bt601*/
-                        if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+                        if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
-                        else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+                        else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
                         break;
                 case COLOR_SPACE_YCBCR709:
@@ -411,9 +420,9 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
                         misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
                         misc1 = misc1 & ~0x80; /* bit7 = 0*/
                         dynamic_range_ycbcr = 1; /*bt709*/
-                        if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+                        if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
                                 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
-                        else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+                        else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
                                 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
                         break;
                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
@@ -453,27 +462,27 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
          */
                 if (REG(DP_MSA_TIMING_PARAM1))
                         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
-                                        DP_MSA_HTOTAL, crtc_timing->h_total,
-                                        DP_MSA_VTOTAL, crtc_timing->v_total);
+                                        DP_MSA_HTOTAL, hw_crtc_timing.h_total,
+                                        DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 #endif
 
                 /* calcuate from vesa timing parameters
                  * h_active_start related to leading edge of sync
                  */
 
-                h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
-                                crtc_timing->h_addressable - crtc_timing->h_border_right;
+                h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
+                                hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 
-                h_back_porch = h_blank - crtc_timing->h_front_porch -
-                                crtc_timing->h_sync_width;
+                h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
+                                hw_crtc_timing.h_sync_width;
 
                 /* start at begining of left border */
-                h_active_start = crtc_timing->h_sync_width + h_back_porch;
+                h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 
 
-                v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
-                                crtc_timing->v_addressable - crtc_timing->v_border_bottom -
-                                crtc_timing->v_front_porch;
+                v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
+                                hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
+                                hw_crtc_timing.v_front_porch;
 
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
@@ -486,21 +495,21 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
                 if (REG(DP_MSA_TIMING_PARAM3))
                         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
                                         DP_MSA_HSYNCWIDTH,
-                                        crtc_timing->h_sync_width,
+                                        hw_crtc_timing.h_sync_width,
                                         DP_MSA_HSYNCPOLARITY,
-                                        !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
+                                        !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
                                         DP_MSA_VSYNCWIDTH,
-                                        crtc_timing->v_sync_width,
+                                        hw_crtc_timing.v_sync_width,
                                         DP_MSA_VSYNCPOLARITY,
-                                        !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
+                                        !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 
                 /* HWDITH include border or overscan */
                 if (REG(DP_MSA_TIMING_PARAM4))
                         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
-                                DP_MSA_HWIDTH, crtc_timing->h_border_left +
-                                crtc_timing->h_addressable + crtc_timing->h_border_right,
-                                DP_MSA_VHEIGHT, crtc_timing->v_border_top +
-                                crtc_timing->v_addressable + crtc_timing->v_border_bottom);
+                                DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
+                                hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
+                                DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
+                                hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 #endif
         }
 #endif
@@ -662,7 +671,7 @@ static void dce110_stream_encoder_dvi_set_stream_attribute(
         cntl.signal = is_dual_link ?
                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
         cntl.enable_dp_audio = false;
-        cntl.pixel_clock = crtc_timing->pix_clk_khz;
+        cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 
         if (enc110->base.bp->funcs->encoder_control(
@@ -686,7 +695,7 @@ static void dce110_stream_encoder_lvds_set_stream_attribute(
         cntl.engine_id = enc110->base.id;
         cntl.signal = SIGNAL_TYPE_LVDS;
         cntl.enable_dp_audio = false;
-        cntl.pixel_clock = crtc_timing->pix_clk_khz;
+        cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
         cntl.lanes_number = LANE_COUNT_FOUR;
 
         if (enc110->base.bp->funcs->encoder_control(
@@ -1575,6 +1584,14 @@ static void setup_stereo_sync(
         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
 }
 
+static void dig_connect_to_otg(
+        struct stream_encoder *enc,
+        int tg_inst)
+{
+        struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
+
+        REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
+}
 
 static const struct stream_encoder_funcs dce110_str_enc_funcs = {
         .dp_set_stream_attribute =
@@ -1609,7 +1626,7 @@ static const struct stream_encoder_funcs dce110_str_enc_funcs = {
         .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
         .setup_stereo_sync  = setup_stereo_sync,
         .set_avmute = dce110_stream_encoder_set_avmute,
-
+        .dig_connect_to_otg  = dig_connect_to_otg,
 };
 
 void dce110_stream_encoder_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
index 6c28229c76eb..f9cdf2b5242c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
@@ -199,7 +199,8 @@
         SE_SF(DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
         SE_SF(DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
         SE_SF(DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
-        SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh)
+        SE_SF(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
+        SE_SF(DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
 
 #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\
         SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
@@ -284,7 +285,8 @@
         SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
         SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
         SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
-        SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh)
+        SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+        SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
 
 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
         SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
@@ -494,6 +496,7 @@ struct dce_stream_encoder_shift {
         uint8_t HDMI_DB_DISABLE;
         uint8_t DP_VID_N_MUL;
         uint8_t DP_VID_M_DOUBLE_VALUE_EN;
+        uint8_t DIG_SOURCE_SELECT;
 };
 
 struct dce_stream_encoder_mask {
@@ -624,6 +627,7 @@ struct dce_stream_encoder_mask {
         uint32_t HDMI_DB_DISABLE;
         uint32_t DP_VID_N_MUL;
         uint32_t DP_VID_M_DOUBLE_VALUE_EN;
+        uint32_t DIG_SOURCE_SELECT;
 };
 
 struct dce110_stream_enc_registers {
diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index 6ae51a5dfc04..23044e6723e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -76,6 +76,7 @@
 
 #ifndef mmBIOS_SCRATCH_2
         #define mmBIOS_SCRATCH_2 0x05CB
+        #define mmBIOS_SCRATCH_3 0x05CC
         #define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
@@ -365,6 +366,7 @@ static const struct dce_abm_mask abm_mask = {
 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
 
 static const struct bios_registers bios_regs = {
+        .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 };
 
@@ -587,7 +589,7 @@ struct output_pixel_processor *dce100_opp_create(
         return &opp->base;
 }
 
-struct aux_engine *dce100_aux_engine_create(
+struct dce_aux *dce100_aux_engine_create(
         struct dc_context *ctx,
         uint32_t inst)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 52d50e24a995..7b23239d33fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -62,8 +62,6 @@ static const struct dce110_compressor_reg_offsets reg_offsets[] = {
 }
 };
 
-static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
-
 static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
 {
         return 256 * ((pixels + 255) / 256);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 4bf24758217f..db0ef41eb91c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -614,55 +614,6 @@ dce110_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
         return true;
 }
 
-static enum dc_status bios_parser_crtc_source_select(
-                struct pipe_ctx *pipe_ctx)
-{
-        struct dc_bios *dcb;
-        /* call VBIOS table to set CRTC source for the HW
-         * encoder block
-         * note: video bios clears all FMT setting here. */
-        struct bp_crtc_source_select crtc_source_select = {0};
-        const struct dc_sink *sink = pipe_ctx->stream->sink;
-
-        crtc_source_select.engine_id = pipe_ctx->stream_res.stream_enc->id;
-        crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;
-        /*TODO: Need to un-hardcode color depth, dp_audio and account for
-         * the case where signal and sink signal is different (translator
-         * encoder)*/
-        crtc_source_select.signal = pipe_ctx->stream->signal;
-        crtc_source_select.enable_dp_audio = false;
-        crtc_source_select.sink_signal = pipe_ctx->stream->signal;
-
-        switch (pipe_ctx->stream->timing.display_color_depth) {
-        case COLOR_DEPTH_666:
-                crtc_source_select.display_output_bit_depth = PANEL_6BIT_COLOR;
-                break;
-        case COLOR_DEPTH_888:
-                crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
-                break;
-        case COLOR_DEPTH_101010:
-                crtc_source_select.display_output_bit_depth = PANEL_10BIT_COLOR;
-                break;
-        case COLOR_DEPTH_121212:
-                crtc_source_select.display_output_bit_depth = PANEL_12BIT_COLOR;
-                break;
-        default:
-                BREAK_TO_DEBUGGER();
-                crtc_source_select.display_output_bit_depth = PANEL_8BIT_COLOR;
-                break;
-        }
-
-        dcb = sink->ctx->dc_bios;
-
-        if (BP_RESULT_OK != dcb->funcs->crtc_source_select(
-                dcb,
-                &crtc_source_select)) {
-                return DC_ERROR_UNEXPECTED;
-        }
-
-        return DC_OK;
-}
-
 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 {
         bool is_hdmi;
@@ -692,10 +643,10 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 {
         enum dc_lane_count lane_count =
-                pipe_ctx->stream->sink->link->cur_link_settings.lane_count;
+                pipe_ctx->stream->link->cur_link_settings.lane_count;
 
         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
-        struct dc_link *link = pipe_ctx->stream->sink->link;
+        struct dc_link *link = pipe_ctx->stream->link;
 
 
         uint32_t active_total_with_borders;
@@ -1000,7 +951,7 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
 
                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
 
-                if (num_audio == 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
+                if (num_audio >= 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
                         pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
                 /* un-mute audio */
@@ -1017,6 +968,8 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
                         pipe_ctx->stream_res.stream_enc, true);
         if (pipe_ctx->stream_res.audio) {
+                struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
+
                 if (option != KEEP_ACQUIRED_RESOURCE ||
                                 !dc->debug.az_endpoint_mute_only) {
                         /*only disalbe az_endpoint if power down or free*/
@@ -1036,6 +989,9 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
                         update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
                         pipe_ctx->stream_res.audio = NULL;
                 }
+                if (pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)
+                        /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
+                        pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
 
                 /* TODO: notify audio driver for if audio modes list changed
                  * add audio mode list change flag */
@@ -1048,7 +1004,7 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
 void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
 {
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
         struct dc *dc = pipe_ctx->stream->ctx->dc;
 
         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
@@ -1073,11 +1029,11 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
 {
         struct encoder_unblank_param params = { { 0 } };
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
 
         /* only 3 items below are used by unblank */
         params.pixel_clk_khz =
-                pipe_ctx->stream->timing.pix_clk_khz;
+                pipe_ctx->stream->timing.pix_clk_100hz / 10;
         params.link_settings.link_rate = link_settings->link_rate;
 
         if (dc_is_dp_signal(pipe_ctx->stream->signal))
@@ -1090,7 +1046,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
 {
         struct dc_stream_state *stream = pipe_ctx->stream;
-        struct dc_link *link = stream->sink->link;
+        struct dc_link *link = stream->link;
 
         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
                 link->dc->hwss.edp_backlight_control(link, false);
@@ -1163,27 +1119,27 @@ static void build_audio_output(
                         stream->timing.flags.INTERLACE;
 
         audio_output->crtc_info.refresh_rate =
-                (stream->timing.pix_clk_khz*1000)/
+                (stream->timing.pix_clk_100hz*10000)/
                 (stream->timing.h_total*stream->timing.v_total);
 
         audio_output->crtc_info.color_depth =
                 stream->timing.display_color_depth;
 
         audio_output->crtc_info.requested_pixel_clock =
-                        pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
+                        pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
 
         audio_output->crtc_info.calculated_pixel_clock =
-                        pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
+                        pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
 
 /*for HDMI, audio ACR is with deep color ratio factor*/
         if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
                 audio_output->crtc_info.requested_pixel_clock ==
-                                stream->timing.pix_clk_khz) {
+                                (stream->timing.pix_clk_100hz / 10)) {
                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
                         audio_output->crtc_info.requested_pixel_clock =
                                         audio_output->crtc_info.requested_pixel_clock/2;
                         audio_output->crtc_info.calculated_pixel_clock =
-                                        pipe_ctx->stream_res.pix_clk_params.requested_pix_clk/2;
+                                        pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20;
 
                 }
         }
@@ -1385,12 +1341,10 @@ static enum dc_status apply_single_controller_ctx_to_hw(
         /*  */
         dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
 
-        /* TODO: move to stream encoder */
         if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
-                if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
-                        BREAK_TO_DEBUGGER();
-                        return DC_ERROR_UNEXPECTED;
-                }
+                pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
+                        pipe_ctx->stream_res.stream_enc,
+                        pipe_ctx->stream_res.tg->inst);
 
         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
                         pipe_ctx->stream_res.opp,
@@ -1408,7 +1362,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 
         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
 
-        pipe_ctx->stream->sink->link->psr_enabled = false;
+        pipe_ctx->stream->link->psr_enabled = false;
 
         return DC_OK;
 }
@@ -1518,7 +1472,7 @@ static struct dc_link *get_link_for_edp(struct dc *dc)
         return NULL;
 }
 
-static struct dc_link *get_link_for_edp_not_in_use(
+static struct dc_link *get_link_for_edp_to_turn_off(
                 struct dc *dc,
                 struct dc_state *context)
 {
@@ -1527,8 +1481,12 @@ static struct dc_link *get_link_for_edp_not_in_use(
 
         /* check if eDP panel is suppose to be set mode, if yes, no need to disable */
         for (i = 0; i < context->stream_count; i++) {
-                if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
-                        return NULL;
+                if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
+                        if (context->streams[i]->dpms_off == true)
+                                return context->streams[i]->sink->link;
+                        else
+                                return NULL;
+                }
         }
 
         /* check if there is an eDP panel not in use */
@@ -1555,7 +1513,6 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
         int i;
         struct dc_link *edp_link_to_turnoff = NULL;
         struct dc_link *edp_link = get_link_for_edp(dc);
-        struct dc_bios *bios = dc->ctx->dc_bios;
         bool can_edp_fast_boot_optimize = false;
         bool apply_edp_fast_boot_optimization = false;
 
@@ -1571,7 +1528,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
         }
 
         if (can_edp_fast_boot_optimize)
-                edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
+                edp_link_to_turnoff = get_link_for_edp_to_turn_off(dc, context);
 
         /* if OS doesn't light up eDP and eDP link is available, we want to disable
          * If resume from S4/S5, should optimization.
@@ -1582,20 +1539,6 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
                         if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
                                 context->streams[i]->apply_edp_fast_boot_optimization = true;
                                 apply_edp_fast_boot_optimization = true;
-
-                                /* When after S4 and S5, vbios may post edp and previous dpms_off
-                                 * doesn't make sense.
-                                 * Update dpms_off state to align hw and sw state via check
-                                 * vBios scratch register.
-                                 */
-                                if (bios->funcs->is_active_display)     {
-                                        const struct connector_device_tag_info *device_tag = &(edp_link->device_tag);
-
-                                        if (bios->funcs->is_active_display(bios,
-                                                        context->streams[i]->signal,
-                                                        device_tag))
-                                                context->streams[i]->dpms_off = false;
-                                }
                         }
                 }
         }
@@ -1624,8 +1567,8 @@ static uint32_t compute_pstate_blackout_duration(
         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
 
         total_dest_line_time_ns = 1000000UL *
-                stream->timing.h_total /
-                stream->timing.pix_clk_khz +
+                (stream->timing.h_total * 10) /
+                stream->timing.pix_clk_100hz +
                 pstate_blackout_duration_ns;
 
         return total_dest_line_time_ns;
@@ -1813,18 +1756,15 @@ static bool should_enable_fbc(struct dc *dc,
         if (i == dc->res_pool->pipe_count)
                 return false;
 
-        if (!pipe_ctx->stream->sink)
-                return false;
-
-        if (!pipe_ctx->stream->sink->link)
+        if (!pipe_ctx->stream->link)
                 return false;
 
         /* Only supports eDP */
-        if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
+        if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
                 return false;
 
         /* PSR should not be enabled */
-        if (pipe_ctx->stream->sink->link->psr_enabled)
+        if (pipe_ctx->stream->link->psr_enabled)
                 return false;
 
         /* Nothing to compress */
@@ -2573,7 +2513,7 @@ static void dce110_apply_ctx_for_surface(
                                 pipe_ctx->plane_res.mi,
                                 pipe_ctx->stream->timing.h_total,
                                 pipe_ctx->stream->timing.v_total,
-                                pipe_ctx->stream->timing.pix_clk_khz,
+                                pipe_ctx->stream->timing.pix_clk_100hz / 10,
                                 context->stream_count);
 
                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
@@ -2622,13 +2562,35 @@ static void dce110_wait_for_mpcc_disconnect(
         /* do nothing*/
 }
 
+static void program_output_csc(struct dc *dc,
+                struct pipe_ctx *pipe_ctx,
+                enum dc_color_space colorspace,
+                uint16_t *matrix,
+                int opp_id)
+{
+        int i;
+        struct out_csc_color_matrix tbl_entry;
+
+        if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
+                enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
+
+                for (i = 0; i < 12; i++)
+                        tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
+
+                tbl_entry.color_space = color_space;
+
+                pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
+                                pipe_ctx->plane_res.xfm, &tbl_entry);
+        }
+}
+
 void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
 {
         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
         struct mem_input *mi = pipe_ctx->plane_res.mi;
         struct dc_cursor_mi_param param = {
-                .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
+                .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
@@ -2672,6 +2634,7 @@ void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
 
 static const struct hw_sequencer_funcs dce110_funcs = {
         .program_gamut_remap = program_gamut_remap,
+        .program_output_csc = program_output_csc,
         .init_hw = init_hw,
         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index e33d11785b1f..7549adaa1542 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -84,6 +84,7 @@
 
 #ifndef mmBIOS_SCRATCH_2
         #define mmBIOS_SCRATCH_2 0x05CB
+        #define mmBIOS_SCRATCH_3 0x05CC
         #define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
@@ -369,6 +370,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 };
 
 static const struct bios_registers bios_regs = {
+        .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 };
 
@@ -606,7 +608,7 @@ static struct output_pixel_processor *dce110_opp_create(
         return &opp->base;
 }
 
-struct aux_engine *dce110_aux_engine_create(
+struct dce_aux *dce110_aux_engine_create(
         struct dc_context *ctx,
         uint32_t inst)
 {
@@ -779,8 +781,8 @@ static void get_pixel_clock_parameters(
          * the pixel clock normalization for hdmi up to here instead of doing it
          * in pll_adjust_pix_clk
          */
-        pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
-        pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
+        pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
+        pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
         /* TODO: un-hardcode*/
@@ -797,10 +799,10 @@ static void get_pixel_clock_parameters(
                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
         }
         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
-                pixel_clk_params->requested_pix_clk  = pixel_clk_params->requested_pix_clk / 2;
+                pixel_clk_params->requested_pix_clk_100hz  = pixel_clk_params->requested_pix_clk_100hz / 2;
         }
         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
-                pixel_clk_params->requested_pix_clk *= 2;
+                pixel_clk_params->requested_pix_clk_100hz *= 2;
 
 }
 
@@ -874,7 +876,7 @@ static bool dce110_validate_bandwidth(
                         __func__,
                         context->streams[0]->timing.h_addressable,
                         context->streams[0]->timing.v_addressable,
-                        context->streams[0]->timing.pix_clk_khz);
+                        context->streams[0]->timing.pix_clk_100hz / 10);
 
         if (memcmp(&dc->current_state->bw.dce,
                         &context->bw.dce, sizeof(context->bw.dce))) {
@@ -1055,7 +1057,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
                                 stream->timing.h_total,
                                 stream->timing.v_total,
-                                stream->timing.pix_clk_khz,
+                                stream->timing.pix_clk_100hz / 10,
                                 context->stream_count);
 
                 color_space_to_black_color(dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 969d4e72dc94..ea3065d63372 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -76,6 +76,7 @@
 
 #ifndef mmBIOS_SCRATCH_2
         #define mmBIOS_SCRATCH_2 0x05CB
+        #define mmBIOS_SCRATCH_3 0x05CC
         #define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
@@ -376,6 +377,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 };
 
 static const struct bios_registers bios_regs = {
+        .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 };
 
@@ -607,7 +609,7 @@ struct output_pixel_processor *dce112_opp_create(
         return &opp->base;
 }
 
-struct aux_engine *dce112_aux_engine_create(
+struct dce_aux *dce112_aux_engine_create(
         struct dc_context *ctx,
         uint32_t inst)
 {
@@ -763,7 +765,7 @@ static struct clock_source *find_matching_pll(
                 const struct resource_pool *pool,
                 const struct dc_stream_state *const stream)
 {
-        switch (stream->sink->link->link_enc->transmitter) {
+        switch (stream->link->link_enc->transmitter) {
         case TRANSMITTER_UNIPHY_A:
                 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
         case TRANSMITTER_UNIPHY_B:
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
index eb0f5f9a973b..1ca30928025e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
@@ -244,6 +244,21 @@ static void dce120_update_dchub(
         dh_data->dchub_info_valid = false;
 }
 
+/**
+ * dce121_xgmi_enabled() - Check if xGMI is enabled
+ * @hws: DCE hardware sequencer object
+ *
+ * Return true if xGMI is enabled. False otherwise.
+ */
+bool dce121_xgmi_enabled(struct dce_hwseq *hws)
+{
+        uint32_t pf_max_region;
+
+        REG_GET(MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, &pf_max_region);
+        /* PF_MAX_REGION == 0 means xgmi is disabled */
+        return !!pf_max_region;
+}
+
 void dce120_hw_sequencer_construct(struct dc *dc)
 {
         /* All registers used by dce11.2 match those in dce11 in offset and
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
index 77a6b86d7606..c51afbd0b012 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
@@ -30,6 +30,7 @@
 
 struct dc;
 
+bool dce121_xgmi_enabled(struct dce_hwseq *hws);
 void dce120_hw_sequencer_construct(struct dc *dc);
 
 #endif /* __DC_HWSS_DCE112_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index f12696674eb0..312a0aebf91f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -62,6 +62,8 @@
 #include "soc15_hw_ip.h"
 #include "vega10_ip_offset.h"
 #include "nbio/nbio_6_1_offset.h"
+#include "mmhub/mmhub_9_4_0_offset.h"
+#include "mmhub/mmhub_9_4_0_sh_mask.h"
 #include "reg_helper.h"
 
 #include "dce100/dce100_resource.h"
@@ -139,6 +141,17 @@ static const struct dce110_timing_generator_offsets dce120_tg_offsets[] = {
         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
                                         mm ## block ## id ## _ ## reg_name
 
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+        MMHUB_BASE__INST0_SEG ## seg
+
+#define MMHUB_BASE(seg) \
+        MMHUB_BASE_INNER(seg)
+
+#define MMHUB_SR(reg_name)\
+                .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
+                                        mm ## reg_name
+
 /* macros to expend register list macro defined in HW object header file
  * end *********************/
 
@@ -378,7 +391,7 @@ struct output_pixel_processor *dce120_opp_create(
                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
         return &opp->base;
 }
-struct aux_engine *dce120_aux_engine_create(
+struct dce_aux *dce120_aux_engine_create(
         struct dc_context *ctx,
         uint32_t inst)
 {
@@ -429,6 +442,7 @@ struct dce_i2c_hw *dce120_i2c_hw_create(
         return dce_i2c_hw;
 }
 static const struct bios_registers bios_regs = {
+        .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
 };
 
@@ -681,6 +695,19 @@ static const struct dce_hwseq_mask hwseq_mask = {
                 HWSEQ_DCE12_MASK_SH_LIST(_MASK)
 };
 
+/* HWSEQ regs for VG20 */
+static const struct dce_hwseq_registers dce121_hwseq_reg = {
+                HWSEQ_VG20_REG_LIST()
+};
+
+static const struct dce_hwseq_shift dce121_hwseq_shift = {
+                HWSEQ_VG20_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask dce121_hwseq_mask = {
+                HWSEQ_VG20_MASK_SH_LIST(_MASK)
+};
+
 static struct dce_hwseq *dce120_hwseq_create(
         struct dc_context *ctx)
 {
@@ -695,6 +722,20 @@ static struct dce_hwseq *dce120_hwseq_create(
         return hws;
 }
 
+static struct dce_hwseq *dce121_hwseq_create(
+        struct dc_context *ctx)
+{
+        struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+        if (hws) {
+                hws->ctx = ctx;
+                hws->regs = &dce121_hwseq_reg;
+                hws->shifts = &dce121_hwseq_shift;
+                hws->masks = &dce121_hwseq_mask;
+        }
+        return hws;
+}
+
 static const struct resource_create_funcs res_create_funcs = {
         .read_dce_straps = read_dce_straps,
         .create_audio = create_audio,
@@ -702,6 +743,14 @@ static const struct resource_create_funcs res_create_funcs = {
         .create_hwseq = dce120_hwseq_create,
 };
 
+static const struct resource_create_funcs dce121_res_create_funcs = {
+        .read_dce_straps = read_dce_straps,
+        .create_audio = create_audio,
+        .create_stream_encoder = dce120_stream_encoder_create,
+        .create_hwseq = dce121_hwseq_create,
+};
+
+
 #define mi_inst_regs(id) { MI_DCE12_REG_LIST(id) }
 static const struct dce_mem_input_registers mi_regs[] = {
                 mi_inst_regs(0),
@@ -911,7 +960,8 @@ static bool construct(
         int j;
         struct dc_context *ctx = dc->ctx;
         struct irq_service_init_data irq_init_data;
-        bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
+        static const struct resource_create_funcs *res_funcs;
+        bool is_vg20 = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
         uint32_t pipe_fuses;
 
         ctx->dc_bios->regs = &bios_regs;
@@ -975,7 +1025,11 @@ static bool construct(
                 }
         }
 
-        pool->base.clk_mgr = dce120_clk_mgr_create(ctx);
+        if (is_vg20)
+                pool->base.clk_mgr = dce121_clk_mgr_create(ctx);
+        else
+                pool->base.clk_mgr = dce120_clk_mgr_create(ctx);
+
         if (pool->base.clk_mgr == NULL) {
                 dm_error("DC: failed to create display clock!\n");
                 BREAK_TO_DEBUGGER();
@@ -1008,14 +1062,14 @@ static bool construct(
         if (!pool->base.irqs)
                 goto irqs_create_fail;
 
-        /* retrieve valid pipe fuses */
-        if (harvest_enabled)
+        /* VG20: Pipe harvesting enabled, retrieve valid pipe fuses */
+        if (is_vg20)
                 pipe_fuses = read_pipe_fuses(ctx);
 
         /* index to valid pipe resource */
         j = 0;
         for (i = 0; i < pool->base.pipe_count; i++) {
-                if (harvest_enabled) {
+                if (is_vg20) {
                         if ((pipe_fuses & (1 << i)) != 0) {
                                 dm_error("DC: skip invalid pipe %d!\n", i);
                                 continue;
@@ -1093,10 +1147,24 @@ static bool construct(
         pool->base.pipe_count = j;
         pool->base.timing_generator_count = j;
 
-        if (!resource_construct(num_virtual_links, dc, &pool->base,
-                         &res_create_funcs))
+        if (is_vg20)
+                res_funcs = &dce121_res_create_funcs;
+        else
+                res_funcs = &res_create_funcs;
+
+        if (!resource_construct(num_virtual_links, dc, &pool->base, res_funcs))
                 goto res_create_fail;
 
+        /*
+         * This is a bit of a hack. The xGMI enabled info is used to determine
+         * if audio and display clocks need to be adjusted with the WAFL link's
+         * SS info. This is a responsiblity of the clk_mgr. But since MMHUB is
+         * under hwseq, and the relevant register is in MMHUB, we have to do it
+         * here.
+         */
+        if (is_vg20 && dce121_xgmi_enabled(dc->hwseq))
+                dce121_clock_patch_xgmi_ss_info(pool->base.clk_mgr);
+
         /* Create hardware sequencer */
         if (!dce120_hw_sequencer_create(dc))
                 goto controller_create_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index cdd1d6b7b9f2..2eca81b5cf2f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -77,6 +77,7 @@
 
 #ifndef mmBIOS_SCRATCH_2
         #define mmBIOS_SCRATCH_2 0x05CB
+        #define mmBIOS_SCRATCH_3 0x05CC
         #define mmBIOS_SCRATCH_6 0x05CF
 #endif
 
@@ -358,6 +359,7 @@ static const struct dce110_clk_src_mask cs_mask = {
 };
 
 static const struct bios_registers bios_regs = {
+        .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 };
 
@@ -467,7 +469,7 @@ static struct output_pixel_processor *dce80_opp_create(
         return &opp->base;
 }
 
-struct aux_engine *dce80_aux_engine_create(
+struct dce_aux *dce80_aux_engine_create(
         struct dc_context *ctx,
         uint32_t inst)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 3ba4712a35ab..8b5ce557ee71 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -84,17 +84,17 @@ static const struct dce110_timing_generator_offsets reg_offsets[] = {
 #define DCP_REG(reg) (reg + tg110->offsets.dcp)
 #define DMIF_REG(reg) (reg + tg110->offsets.dmif)
 
-static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
+static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
 {
         uint64_t pix_dur;
         uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
                                         + DCE110TG_FROM_TG(tg)->offsets.dmif;
         uint32_t value = dm_read_reg(tg->ctx, addr);
 
-        if (pix_clk_khz == 0)
+        if (pix_clk_100hz == 0)
                 return;
 
-        pix_dur = 1000000000 / pix_clk_khz;
+        pix_dur = div_u64(10000000000ull, pix_clk_100hz);
 
         set_reg_field_value(
                 value,
@@ -110,7 +110,7 @@ static void program_timing(struct timing_generator *tg,
         bool use_vbios)
 {
         if (!use_vbios)
-                program_pix_dur(tg, timing->pix_clk_khz);
+                program_pix_dur(tg, timing->pix_clk_100hz);
 
         dce110_tg_program_timing(tg, timing, use_vbios);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
index 54abedbf1b43..afe8c42211cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
@@ -161,69 +161,17 @@ static int get_active_display_cnt(
         return display_count;
 }
 
-static void notify_deep_sleep_dcfclk_to_smu(
-                struct pp_smu_funcs_rv *pp_smu, int min_dcef_deep_sleep_clk_khz)
-{
-        int min_dcef_deep_sleep_clk_mhz; //minimum required DCEF Deep Sleep clock in mhz
-        /*
-         * if function pointer not set up, this message is
-         * sent as part of pplib_apply_display_requirements.
-         * So just return.
-         */
-        if (!pp_smu || !pp_smu->set_min_deep_sleep_dcfclk)
-                return;
-
-        min_dcef_deep_sleep_clk_mhz = (min_dcef_deep_sleep_clk_khz + 999) / 1000; //Round up
-        pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, min_dcef_deep_sleep_clk_mhz);
-}
-
-static void notify_hard_min_dcfclk_to_smu(
-                struct pp_smu_funcs_rv *pp_smu, int min_dcf_clk_khz)
-{
-        int min_dcf_clk_mhz; //minimum required DCF clock in mhz
-
-        /*
-         * if function pointer not set up, this message is
-         * sent as part of pplib_apply_display_requirements.
-         * So just return.
-         */
-        if (!pp_smu || !pp_smu->set_hard_min_dcfclk_by_freq)
-                return;
-
-        min_dcf_clk_mhz = min_dcf_clk_khz / 1000;
-
-        pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, min_dcf_clk_mhz);
-}
-
-static void notify_hard_min_fclk_to_smu(
-                struct pp_smu_funcs_rv *pp_smu, int min_f_clk_khz)
-{
-        int min_f_clk_mhz; //minimum required F clock in mhz
-
-        /*
-         * if function pointer not set up, this message is
-         * sent as part of pplib_apply_display_requirements.
-         * So just return.
-         */
-        if (!pp_smu || !pp_smu->set_hard_min_fclk_by_freq)
-                return;
-
-        min_f_clk_mhz = min_f_clk_khz / 1000;
-
-        pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, min_f_clk_mhz);
-}
-
 static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
                         struct dc_state *context,
                         bool safe_to_lower)
 {
         struct dc *dc = clk_mgr->ctx->dc;
+        struct dc_debug_options *debug = &dc->debug;
         struct dc_clocks *new_clocks = &context->bw.dcn.clk;
         struct pp_smu_display_requirement_rv *smu_req_cur =
                         &dc->res_pool->pp_smu_req;
         struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
         struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
-        uint32_t requested_dcf_clock_in_khz = 0;
         bool send_request_to_increase = false;
         bool send_request_to_lower = false;
         int display_count;
@@ -243,9 +191,8 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
                  */
                 if (pp_smu->set_display_count)
                         pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
-                else
-                        smu_req.display_count = display_count;
 
+                smu_req.display_count = display_count;
         }
 
         if (new_clocks->dispclk_khz > clk_mgr->clks.dispclk_khz
@@ -261,12 +208,13 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
         }
 
         // F Clock
+        if (debug->force_fclk_khz != 0)
+                new_clocks->fclk_khz = debug->force_fclk_khz;
+
         if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr->clks.fclk_khz)) {
                 clk_mgr->clks.fclk_khz = new_clocks->fclk_khz;
                 smu_req.hard_min_fclk_mhz = new_clocks->fclk_khz / 1000;
 
-                notify_hard_min_fclk_to_smu(pp_smu, new_clocks->fclk_khz);
-
                 send_request_to_lower = true;
         }
 
@@ -281,7 +229,7 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
         if (should_set_clock(safe_to_lower,
                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
                 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
-                smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz / 1000;
+                smu_req.min_deep_sleep_dcefclk_mhz = (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000;
 
                 send_request_to_lower = true;
         }
@@ -291,15 +239,18 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
          */
         if (send_request_to_increase) {
                 /*use dcfclk to request voltage*/
-                requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
-
-                notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz);
-
-                if (pp_smu->set_display_requirement)
-                        pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
-
-                notify_deep_sleep_dcfclk_to_smu(pp_smu, clk_mgr->clks.dcfclk_deep_sleep_khz);
-                dcn1_pplib_apply_display_requirements(dc, context);
+                if (pp_smu->set_hard_min_fclk_by_freq &&
+                                pp_smu->set_hard_min_dcfclk_by_freq &&
+                                pp_smu->set_min_deep_sleep_dcfclk) {
+
+                        pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_fclk_mhz);
+                        pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_dcefclk_mhz);
+                        pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, smu_req.min_deep_sleep_dcefclk_mhz);
+                } else {
+                        if (pp_smu->set_display_requirement)
+                                pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
+                        dcn1_pplib_apply_display_requirements(dc, context);
+                }
         }
 
         /* dcn1 dppclk is tied to dispclk */
@@ -314,18 +265,20 @@ static void dcn1_update_clocks(struct clk_mgr *clk_mgr,
 
         if (!send_request_to_increase && send_request_to_lower) {
                 /*use dcfclk to request voltage*/
-                requested_dcf_clock_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
-
-                notify_hard_min_dcfclk_to_smu(pp_smu, requested_dcf_clock_in_khz);
-
-                if (pp_smu->set_display_requirement)
-                        pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
-
-                notify_deep_sleep_dcfclk_to_smu(pp_smu, clk_mgr->clks.dcfclk_deep_sleep_khz);
-                dcn1_pplib_apply_display_requirements(dc, context);
+                if (pp_smu->set_hard_min_fclk_by_freq &&
+                                pp_smu->set_hard_min_dcfclk_by_freq &&
+                                pp_smu->set_min_deep_sleep_dcfclk) {
+
+                        pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_fclk_mhz);
+                        pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, smu_req.hard_min_dcefclk_mhz);
+                        pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, smu_req.min_deep_sleep_dcefclk_mhz);
+                } else {
+                        if (pp_smu->set_display_requirement)
+                                pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
+                        dcn1_pplib_apply_display_requirements(dc, context);
+                }
         }
 
-
         *smu_req_cur = smu_req;
 }
 static const struct clk_mgr_funcs dcn1_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index dcb3c5530236..cd1ebe57ed59 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -463,7 +463,7 @@ void dpp1_set_cursor_position(
         if (src_y_offset >= (int)param->viewport.height)
                 cur_en = 0;  /* not visible beyond bottom edge*/
 
-        if (src_y_offset < 0)
+        if (src_y_offset + (int)height <= 0)
                 cur_en = 0;  /* not visible beyond top edge*/
 
         REG_UPDATE(CURSOR0_CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 116977eb24e2..41f0f4c912e7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -51,10 +51,6 @@
 
 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
 
-struct dcn10_input_csc_matrix {
-        enum dc_color_space color_space;
-        uint16_t regval[12];
-};
 
 enum dcn10_coef_filter_type_sel {
         SCL_COEF_LUMA_VERT_FILTER = 0,
@@ -99,7 +95,7 @@ enum gamut_remap_select {
         GAMUT_REMAP_COMB_COEFF
 };
 
-static const struct dcn10_input_csc_matrix dcn10_input_csc_matrix[] = {
+static const struct dpp_input_csc_matrix dpp_input_csc_matrix[] = {
         {COLOR_SPACE_SRGB,
                 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
         {COLOR_SPACE_SRGB_LIMITED,
@@ -454,7 +450,7 @@ void dpp1_program_input_csc(
 {
         struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
         int i;
-        int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
+        int arr_size = sizeof(dpp_input_csc_matrix)/sizeof(struct dpp_input_csc_matrix);
         const uint16_t *regval = NULL;
         uint32_t cur_select = 0;
         enum dcn10_input_csc_select select;
@@ -467,8 +463,8 @@ void dpp1_program_input_csc(
 
         if (tbl_entry == NULL) {
                 for (i = 0; i < arr_size; i++)
-                        if (dcn10_input_csc_matrix[i].color_space == color_space) {
-                                regval = dcn10_input_csc_matrix[i].regval;
+                        if (dpp_input_csc_matrix[i].color_space == color_space) {
+                                regval = dpp_input_csc_matrix[i].regval;
                                 break;
                         }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index 4a863a5dab41..c7642e748297 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -597,11 +597,13 @@ static void dpp1_dscl_set_manual_ratio_init(
                 SCL_V_INIT_FRAC, init_frac,
                 SCL_V_INIT_INT, init_int);
 
-        init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
-        init_int = dc_fixpt_floor(data->inits.v_bot);
-        REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
-                SCL_V_INIT_FRAC_BOT, init_frac,
-                SCL_V_INIT_INT_BOT, init_int);
+        if (REG(SCL_VERT_FILTER_INIT_BOT)) {
+                init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
+                init_int = dc_fixpt_floor(data->inits.v_bot);
+                REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
+                        SCL_V_INIT_FRAC_BOT, init_frac,
+                        SCL_V_INIT_INT_BOT, init_int);
+        }
 
         init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
         init_int = dc_fixpt_floor(data->inits.v_c);
@@ -609,11 +611,13 @@ static void dpp1_dscl_set_manual_ratio_init(
                 SCL_V_INIT_FRAC_C, init_frac,
                 SCL_V_INIT_INT_C, init_int);
 
-        init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
-        init_int = dc_fixpt_floor(data->inits.v_c_bot);
-        REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
-                SCL_V_INIT_FRAC_BOT_C, init_frac,
-                SCL_V_INIT_INT_BOT_C, init_int);
+        if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
+                init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
+                init_int = dc_fixpt_floor(data->inits.v_c_bot);
+                REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
+                        SCL_V_INIT_FRAC_BOT_C, init_frac,
+                        SCL_V_INIT_INT_BOT_C, init_int);
+        }
 }
 
 
@@ -688,15 +692,17 @@ void dpp1_dscl_set_scaler_manual_scale(
                 return;
 
         /* Black offsets */
-        if (ycbcr)
-                REG_SET_2(SCL_BLACK_OFFSET, 0,
-                                SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
-                                SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
-        else
+        if (REG(SCL_BLACK_OFFSET)) {
+                if (ycbcr)
+                        REG_SET_2(SCL_BLACK_OFFSET, 0,
+                                        SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
+                                        SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
+                else
 
-                REG_SET_2(SCL_BLACK_OFFSET, 0,
-                                SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
-                                SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
+                        REG_SET_2(SCL_BLACK_OFFSET, 0,
+                                        SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
+                                        SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
+        }
 
         /* Manually calculate scale ratio and init values */
         dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index c7d1e678ebf5..5a4614c371bc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -29,19 +29,20 @@
 #include "reg_helper.h"
 
 #define CTX \
-        hubbub->ctx
+        hubbub1->base.ctx
 #define DC_LOGGER \
-        hubbub->ctx->logger
+        hubbub1->base.ctx->logger
 #define REG(reg)\
-        hubbub->regs->reg
+        hubbub1->regs->reg
 
 #undef FN
 #define FN(reg_name, field_name) \
-        hubbub->shifts->field_name, hubbub->masks->field_name
+        hubbub1->shifts->field_name, hubbub1->masks->field_name
 
 void hubbub1_wm_read_state(struct hubbub *hubbub,
                 struct dcn_hubbub_wm *wm)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
         struct dcn_hubbub_wm_set *s;
 
         memset(wm, 0, sizeof(struct dcn_hubbub_wm));
@@ -89,12 +90,14 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
 
 void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
         REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,
                         DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0);
 }
 
 bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
         uint32_t enable = 0;
 
         REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
@@ -107,6 +110,8 @@ bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
 bool hubbub1_verify_allow_pstate_change_high(
         struct hubbub *hubbub)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
         /* pstate latency is ~20us so if we wait over 40us and pstate allow
          * still not asserted, we are probably stuck and going to hang
          *
@@ -193,7 +198,7 @@ bool hubbub1_verify_allow_pstate_change_high(
          * 31:    SOC pstate change request
          */
 
-        REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);
+        REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate);
 
         for (i = 0; i < pstate_wait_timeout_us; i++) {
                 debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
@@ -244,6 +249,8 @@ static uint32_t convert_and_clamp(
 
 void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
         REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
                         DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
 }
@@ -254,7 +261,9 @@ void hubbub1_program_watermarks(
                 unsigned int refclk_mhz,
                 bool safe_to_lower)
 {
-        uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
+        uint32_t force_en = hubbub1->base.ctx->dc->debug.disable_stutter ? 1 : 0;
         /*
          * Need to clamp to max of the register values (i.e. no wrap)
          * for dcn1, all wm registers are 21-bit wide
@@ -264,8 +273,8 @@ void hubbub1_program_watermarks(
 
         /* Repeat for water mark set A, B, C and D. */
         /* clock state A */
-        if (safe_to_lower || watermarks->a.urgent_ns > hubbub->watermarks.a.urgent_ns) {
-                hubbub->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
+        if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) {
+                hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
                 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
                                 refclk_mhz, 0x1fffff);
                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
@@ -275,20 +284,22 @@ void hubbub1_program_watermarks(
                         watermarks->a.urgent_ns, prog_wm_value);
         }
 
-        if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub->watermarks.a.pte_meta_urgent_ns) {
-                hubbub->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
-                prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
-                                refclk_mhz, 0x1fffff);
-                REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
-                DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
-                        "HW register value = 0x%x\n",
-                        watermarks->a.pte_meta_urgent_ns, prog_wm_value);
+        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) {
+                if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub1->watermarks.a.pte_meta_urgent_ns) {
+                        hubbub1->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
+                        prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
+                                        refclk_mhz, 0x1fffff);
+                        REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
+                        DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
+                                "HW register value = 0x%x\n",
+                                watermarks->a.pte_meta_urgent_ns, prog_wm_value);
+                }
         }
 
         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
                 if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
-                                > hubbub->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
-                        hubbub->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+                                > hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
+                        hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
                                         watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
@@ -300,8 +311,8 @@ void hubbub1_program_watermarks(
                 }
 
                 if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
-                                > hubbub->watermarks.a.cstate_pstate.cstate_exit_ns) {
-                        hubbub->watermarks.a.cstate_pstate.cstate_exit_ns =
+                                > hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) {
+                        hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns =
                                         watermarks->a.cstate_pstate.cstate_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->a.cstate_pstate.cstate_exit_ns,
@@ -314,8 +325,8 @@ void hubbub1_program_watermarks(
         }
 
         if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
-                        > hubbub->watermarks.a.cstate_pstate.pstate_change_ns) {
-                hubbub->watermarks.a.cstate_pstate.pstate_change_ns =
+                        > hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) {
+                hubbub1->watermarks.a.cstate_pstate.pstate_change_ns =
                                 watermarks->a.cstate_pstate.pstate_change_ns;
                 prog_wm_value = convert_and_clamp(
                                 watermarks->a.cstate_pstate.pstate_change_ns,
@@ -327,8 +338,8 @@ void hubbub1_program_watermarks(
         }
 
         /* clock state B */
-        if (safe_to_lower || watermarks->b.urgent_ns > hubbub->watermarks.b.urgent_ns) {
-                hubbub->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
+        if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
+                hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
                 prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
                                 refclk_mhz, 0x1fffff);
                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
@@ -338,20 +349,22 @@ void hubbub1_program_watermarks(
                         watermarks->b.urgent_ns, prog_wm_value);
         }
 
-        if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub->watermarks.b.pte_meta_urgent_ns) {
-                hubbub->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
-                prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
-                                refclk_mhz, 0x1fffff);
-                REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
-                DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
-                        "HW register value = 0x%x\n",
-                        watermarks->b.pte_meta_urgent_ns, prog_wm_value);
+        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) {
+                if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub1->watermarks.b.pte_meta_urgent_ns) {
+                        hubbub1->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
+                        prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
+                                        refclk_mhz, 0x1fffff);
+                        REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
+                        DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
+                                "HW register value = 0x%x\n",
+                                watermarks->b.pte_meta_urgent_ns, prog_wm_value);
+                }
         }
 
         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
                 if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
-                                > hubbub->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
-                        hubbub->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+                                > hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
+                        hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
                                         watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
@@ -363,8 +376,8 @@ void hubbub1_program_watermarks(
                 }
 
                 if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
-                                > hubbub->watermarks.b.cstate_pstate.cstate_exit_ns) {
-                        hubbub->watermarks.b.cstate_pstate.cstate_exit_ns =
+                                > hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) {
+                        hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns =
                                         watermarks->b.cstate_pstate.cstate_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->b.cstate_pstate.cstate_exit_ns,
@@ -377,8 +390,8 @@ void hubbub1_program_watermarks(
         }
 
         if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
-                        > hubbub->watermarks.b.cstate_pstate.pstate_change_ns) {
-                hubbub->watermarks.b.cstate_pstate.pstate_change_ns =
+                        > hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) {
+                hubbub1->watermarks.b.cstate_pstate.pstate_change_ns =
                                 watermarks->b.cstate_pstate.pstate_change_ns;
                 prog_wm_value = convert_and_clamp(
                                 watermarks->b.cstate_pstate.pstate_change_ns,
@@ -390,8 +403,8 @@ void hubbub1_program_watermarks(
         }
 
         /* clock state C */
-        if (safe_to_lower || watermarks->c.urgent_ns > hubbub->watermarks.c.urgent_ns) {
-                hubbub->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
+        if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {
+                hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
                 prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
                                 refclk_mhz, 0x1fffff);
                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
@@ -401,20 +414,22 @@ void hubbub1_program_watermarks(
                         watermarks->c.urgent_ns, prog_wm_value);
         }
 
-        if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub->watermarks.c.pte_meta_urgent_ns) {
-                hubbub->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
-                prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
-                                refclk_mhz, 0x1fffff);
-                REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
-                DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
-                        "HW register value = 0x%x\n",
-                        watermarks->c.pte_meta_urgent_ns, prog_wm_value);
+        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) {
+                if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub1->watermarks.c.pte_meta_urgent_ns) {
+                        hubbub1->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
+                        prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
+                                        refclk_mhz, 0x1fffff);
+                        REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
+                        DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
+                                "HW register value = 0x%x\n",
+                                watermarks->c.pte_meta_urgent_ns, prog_wm_value);
+                }
         }
 
         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
                 if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
-                                > hubbub->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
-                        hubbub->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+                                > hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
+                        hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
                                         watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
@@ -426,8 +441,8 @@ void hubbub1_program_watermarks(
                 }
 
                 if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
-                                > hubbub->watermarks.c.cstate_pstate.cstate_exit_ns) {
-                        hubbub->watermarks.c.cstate_pstate.cstate_exit_ns =
+                                > hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) {
+                        hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns =
                                         watermarks->c.cstate_pstate.cstate_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->c.cstate_pstate.cstate_exit_ns,
@@ -440,8 +455,8 @@ void hubbub1_program_watermarks(
         }
 
         if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
-                        > hubbub->watermarks.c.cstate_pstate.pstate_change_ns) {
-                hubbub->watermarks.c.cstate_pstate.pstate_change_ns =
+                        > hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) {
+                hubbub1->watermarks.c.cstate_pstate.pstate_change_ns =
                                 watermarks->c.cstate_pstate.pstate_change_ns;
                 prog_wm_value = convert_and_clamp(
                                 watermarks->c.cstate_pstate.pstate_change_ns,
@@ -453,8 +468,8 @@ void hubbub1_program_watermarks(
         }
 
         /* clock state D */
-        if (safe_to_lower || watermarks->d.urgent_ns > hubbub->watermarks.d.urgent_ns) {
-                hubbub->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
+        if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {
+                hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
                 prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
                                 refclk_mhz, 0x1fffff);
                 REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
@@ -464,20 +479,22 @@ void hubbub1_program_watermarks(
                         watermarks->d.urgent_ns, prog_wm_value);
         }
 
-        if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub->watermarks.d.pte_meta_urgent_ns) {
-                hubbub->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
-                prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
-                                refclk_mhz, 0x1fffff);
-                REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
-                DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
-                        "HW register value = 0x%x\n",
-                        watermarks->d.pte_meta_urgent_ns, prog_wm_value);
+        if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) {
+                if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub1->watermarks.d.pte_meta_urgent_ns) {
+                        hubbub1->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
+                        prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
+                                        refclk_mhz, 0x1fffff);
+                        REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
+                        DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
+                                "HW register value = 0x%x\n",
+                                watermarks->d.pte_meta_urgent_ns, prog_wm_value);
+                }
         }
 
         if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
                 if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
-                                > hubbub->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
-                        hubbub->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+                                > hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
+                        hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
                                         watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
@@ -489,8 +506,8 @@ void hubbub1_program_watermarks(
                 }
 
                 if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
-                                > hubbub->watermarks.d.cstate_pstate.cstate_exit_ns) {
-                        hubbub->watermarks.d.cstate_pstate.cstate_exit_ns =
+                                > hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) {
+                        hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns =
                                         watermarks->d.cstate_pstate.cstate_exit_ns;
                         prog_wm_value = convert_and_clamp(
                                         watermarks->d.cstate_pstate.cstate_exit_ns,
@@ -503,8 +520,8 @@ void hubbub1_program_watermarks(
         }
 
         if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
-                        > hubbub->watermarks.d.cstate_pstate.pstate_change_ns) {
-                hubbub->watermarks.d.cstate_pstate.pstate_change_ns =
+                        > hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) {
+                hubbub1->watermarks.d.cstate_pstate.pstate_change_ns =
                                 watermarks->d.cstate_pstate.pstate_change_ns;
                 prog_wm_value = convert_and_clamp(
                                 watermarks->d.cstate_pstate.pstate_change_ns,
@@ -535,6 +552,8 @@ void hubbub1_update_dchub(
         struct hubbub *hubbub,
         struct dchub_init_data *dh_data)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
         if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
                 ASSERT(false);
                 /*should not come here*/
@@ -594,6 +613,8 @@ void hubbub1_update_dchub(
 
 void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
         uint32_t watermark_change_req;
 
         REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
@@ -610,6 +631,8 @@ void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
 
 void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)
 {
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
         uint32_t reset_en = reset ? 1 : 0;
 
         REG_UPDATE(DCHUBBUB_SOFT_RESET,
@@ -752,7 +775,9 @@ static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
                 const struct dc_dcc_surface_param *input,
                 struct dc_surface_dcc_cap *output)
 {
-        struct dc *dc = hubbub->ctx->dc;
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+        struct dc *dc = hubbub1->base.ctx->dc;
+
         /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
         enum dcc_control dcc_control;
         unsigned int bpe;
@@ -764,10 +789,10 @@ static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
         if (dc->debug.disable_dcc == DCC_DISABLE)
                 return false;
 
-        if (!hubbub->funcs->dcc_support_pixel_format(input->format, &bpe))
+        if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe))
                 return false;
 
-        if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
+        if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
                         &segment_order_horz, &segment_order_vert))
                 return false;
 
@@ -837,6 +862,7 @@ static const struct hubbub_funcs hubbub1_funcs = {
         .dcc_support_swizzle = hubbub1_dcc_support_swizzle,
         .dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
         .get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
+        .wm_read_state = hubbub1_wm_read_state,
 };
 
 void hubbub1_construct(struct hubbub *hubbub,
@@ -845,18 +871,20 @@ void hubbub1_construct(struct hubbub *hubbub,
         const struct dcn_hubbub_shift *hubbub_shift,
         const struct dcn_hubbub_mask *hubbub_mask)
 {
-        hubbub->ctx = ctx;
+        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
+
+        hubbub1->base.ctx = ctx;
 
-        hubbub->funcs = &hubbub1_funcs;
+        hubbub1->base.funcs = &hubbub1_funcs;
 
-        hubbub->regs = hubbub_regs;
-        hubbub->shifts = hubbub_shift;
-        hubbub->masks = hubbub_mask;
+        hubbub1->regs = hubbub_regs;
+        hubbub1->shifts = hubbub_shift;
+        hubbub1->masks = hubbub_mask;
 
-        hubbub->debug_test_index_pstate = 0x7;
+        hubbub1->debug_test_index_pstate = 0x7;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_01)
         if (ctx->dce_version == DCN_VERSION_1_01)
-                hubbub->debug_test_index_pstate = 0xB;
+                hubbub1->debug_test_index_pstate = 0xB;
 #endif
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index d0f03d152913..c681e1cc9290 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -29,6 +29,9 @@
 #include "core_types.h"
 #include "dchubbub.h"
 
+#define TO_DCN10_HUBBUB(hubbub)\
+        container_of(hubbub, struct dcn10_hubbub, base)
+
 #define HUBHUB_REG_LIST_DCN()\
         SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
         SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
@@ -107,6 +110,12 @@ struct dcn_hubbub_registers {
         uint32_t DCHUBBUB_SDPIF_AGP_TOP;
         uint32_t DCHUBBUB_CRC_CTRL;
         uint32_t DCHUBBUB_SOFT_RESET;
+        uint32_t DCN_VM_FB_LOCATION_BASE;
+        uint32_t DCN_VM_FB_LOCATION_TOP;
+        uint32_t DCN_VM_FB_OFFSET;
+        uint32_t DCN_VM_AGP_BOT;
+        uint32_t DCN_VM_AGP_TOP;
+        uint32_t DCN_VM_AGP_BASE;
 };
 
 /* set field name */
@@ -152,7 +161,13 @@ struct dcn_hubbub_registers {
                 type SDPIF_FB_OFFSET;\
                 type SDPIF_AGP_BASE;\
                 type SDPIF_AGP_BOT;\
-                type SDPIF_AGP_TOP
+                type SDPIF_AGP_TOP;\
+                type FB_BASE;\
+                type FB_TOP;\
+                type FB_OFFSET;\
+                type AGP_BOT;\
+                type AGP_TOP;\
+                type AGP_BASE
 
 
 struct dcn_hubbub_shift {
@@ -165,22 +180,8 @@ struct dcn_hubbub_mask {
 
 struct dc;
 
-struct dcn_hubbub_wm_set {
-        uint32_t wm_set;
-        uint32_t data_urgent;
-        uint32_t pte_meta_urgent;
-        uint32_t sr_enter;
-        uint32_t sr_exit;
-        uint32_t dram_clk_chanage;
-};
-
-struct dcn_hubbub_wm {
-        struct dcn_hubbub_wm_set sets[4];
-};
-
-struct hubbub {
-        const struct hubbub_funcs *funcs;
-        struct dc_context *ctx;
+struct dcn10_hubbub {
+        struct hubbub base;
         const struct dcn_hubbub_registers *regs;
         const struct dcn_hubbub_shift *shifts;
         const struct dcn_hubbub_mask *masks;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 345af015d061..0ba68d41b9c3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -115,7 +115,7 @@ static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
         REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
 }
 
-static void hubp1_vready_workaround(struct hubp *hubp,
+void hubp1_vready_workaround(struct hubp *hubp,
                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 {
         uint32_t value = 0;
@@ -317,7 +317,8 @@ void hubp1_program_pixel_format(
 bool hubp1_program_surface_flip_and_addr(
         struct hubp *hubp,
         const struct dc_plane_address *address,
-        bool flip_immediate)
+        bool flip_immediate,
+        uint8_t vmid)
 {
         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
@@ -1140,7 +1141,7 @@ void hubp1_cursor_set_position(
         if (src_y_offset >= (int)param->viewport.height)
                 cur_en = 0;  /* not visible beyond bottom edge*/
 
-        if (src_y_offset < 0) //+ (int)hubp->curs_attr.height
+        if (src_y_offset + (int)hubp->curs_attr.height <= 0)
                 cur_en = 0;  /* not visible beyond top edge*/
 
         if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 62d4232e7796..a6d6dfe00617 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -707,11 +707,6 @@ void hubp1_dcc_control(struct hubp *hubp,
                 bool enable,
                 bool independent_64b_blks);
 
-bool hubp1_program_surface_flip_and_addr(
-        struct hubp *hubp,
-        const struct dc_plane_address *address,
-        bool flip_immediate);
-
 bool hubp1_is_flip_pending(struct hubp *hubp);
 
 void hubp1_cursor_set_attributes(
@@ -745,5 +740,7 @@ void hubp1_clear_underflow(struct hubp *hubp);
 
 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
 
+void hubp1_vready_workaround(struct hubp *hubp,
+                struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 91e015e14355..9cde24dbdac8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -40,7 +40,6 @@
 #include "ipp.h"
 #include "mpc.h"
 #include "reg_helper.h"
-#include "custom_float.h"
 #include "dcn10_hubp.h"
 #include "dcn10_hubbub.h"
 #include "dcn10_cm_common.h"
@@ -92,10 +91,11 @@ static void log_mpc_crc(struct dc *dc,
 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
 {
         struct dc_context *dc_ctx = dc->ctx;
-        struct dcn_hubbub_wm wm = {0};
+        struct dcn_hubbub_wm wm;
         int i;
 
-        hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
+        memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
+        dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
 
         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
                         "         sr_enter          sr_exit  dram_clk_change\n");
@@ -1202,7 +1202,8 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c
         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
                         pipe_ctx->plane_res.hubp,
                         &plane_state->address,
-                        plane_state->flip_immediate);
+                        plane_state->flip_immediate,
+                        0);
 
         plane_state->status.requested_address = plane_state->address;
 
@@ -2048,7 +2049,7 @@ void update_dchubp_dpp(
                         dc->res_pool->dccg->funcs->update_dpp_dto(
                                         dc->res_pool->dccg,
                                         dpp->inst,
-                                        pipe_ctx->plane_res.bw.calc.dppclk_khz);
+                                        pipe_ctx->plane_res.bw.dppclk_khz);
                 else
                         dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
                                                 dc->res_pool->clk_mgr->clks.dispclk_khz / 2 :
@@ -2125,7 +2126,8 @@ void update_dchubp_dpp(
                 plane_state->update_flags.bits.swizzle_change ||
                 plane_state->update_flags.bits.dcc_change ||
                 plane_state->update_flags.bits.bpp_change ||
-                plane_state->update_flags.bits.scaling_change) {
+                plane_state->update_flags.bits.scaling_change ||
+                plane_state->update_flags.bits.plane_size_change) {
                 hubp->funcs->hubp_program_surface_config(
                         hubp,
                         plane_state->format,
@@ -2252,13 +2254,11 @@ static void program_all_pipe_in_tree(
 
         }
 
-        if (pipe_ctx->plane_state != NULL) {
+        if (pipe_ctx->plane_state != NULL)
                 dcn10_program_pipe(dc, pipe_ctx, context);
-        }
 
-        if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) {
+        if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
-        }
 }
 
 struct pipe_ctx *find_top_pipe_for_stream(
@@ -2355,29 +2355,22 @@ static void dcn10_apply_ctx_for_surface(
                         top_pipe_to_program->plane_state->update_flags.bits.full_update)
                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
+                        tg = pipe_ctx->stream_res.tg;
                         /* Skip inactive pipes and ones already updated */
                         if (!pipe_ctx->stream || pipe_ctx->stream == stream
-                                        || !pipe_ctx->plane_state)
+                                        || !pipe_ctx->plane_state
+                                        || !tg->funcs->is_tg_enabled(tg))
                                 continue;
 
-                        pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
+                        tg->funcs->lock(tg);
 
                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
                                 pipe_ctx->plane_res.hubp,
                                 &pipe_ctx->dlg_regs,
                                 &pipe_ctx->ttu_regs);
-                }
 
-        for (i = 0; i < dc->res_pool->pipe_count; i++) {
-                struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
-
-                if (!pipe_ctx->stream || pipe_ctx->stream == stream
-                                || !pipe_ctx->plane_state)
-                        continue;
-
-                dcn10_pipe_control_lock(dc, pipe_ctx, false);
-        }
+                        tg->funcs->unlock(tg);
+                }
 
         if (num_planes == 0)
                 false_optc_underflow_wa(dc, stream, tg);
@@ -2525,7 +2518,7 @@ static void dcn10_config_stereo_parameters(
                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
                         enum display_dongle_type dongle = \
-                                        stream->sink->link->ddc->dongle_type;
+                                        stream->link->ddc->dongle_type;
                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
@@ -2656,7 +2649,7 @@ static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
         struct hubp *hubp = pipe_ctx->plane_res.hubp;
         struct dpp *dpp = pipe_ctx->plane_res.dpp;
         struct dc_cursor_mi_param param = {
-                .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
+                .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index cd469014baa3..98f41d250978 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -40,7 +40,6 @@
 #include "ipp.h"
 #include "mpc.h"
 #include "reg_helper.h"
-#include "custom_float.h"
 #include "dcn10_hubp.h"
 #include "dcn10_hubbub.h"
 #include "dcn10_cm_common.h"
@@ -72,7 +71,7 @@ static unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt,
 static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned int bufSize)
 {
         struct dc_context *dc_ctx = dc->ctx;
-        struct dcn_hubbub_wm wm = {0};
+        struct dcn_hubbub_wm wm;
         int i;
 
         unsigned int chars_printed = 0;
@@ -81,7 +80,8 @@ static unsigned int dcn10_get_hubbub_state(struct dc *dc, char *pBuf, unsigned i
         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
         static const unsigned int frac = 1000;
 
-        hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
+        memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
+        dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
 
         chars_printed = snprintf_count(pBuf, remaining_buffer, "wm_set_index,data_urgent,pte_meta_urgent,sr_enter,sr_exit,dram_clk_chanage\n");
         remaining_buffer -= chars_printed;
@@ -419,20 +419,22 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int
         unsigned int remaining_buffer = bufSize;
 
         chars_printed = snprintf_count(pBuf, remaining_buffer, "instance,v_bs,v_be,v_ss,v_se,vpol,vmax,vmin,vmax_sel,vmin_sel,"
-                        "h_bs,h_be,h_ss,h_se,hpol,htot,vtot,underflow\n");
+                        "h_bs,h_be,h_ss,h_se,hpol,htot,vtot,underflow,pixelclk[khz]\n");
         remaining_buffer -= chars_printed;
         pBuf += chars_printed;
 
         for (i = 0; i < pool->timing_generator_count; i++) {
                 struct timing_generator *tg = pool->timing_generators[i];
                 struct dcn_otg_state s = {0};
+                int pix_clk = 0;
 
                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
+                pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
 
                 //only print if OTG master is enabled
                 if (s.otg_enabled & 1) {
                         chars_printed = snprintf_count(pBuf, remaining_buffer, "%x,%d,%d,%d,%d,%d,%d,%d,%d,%d,"
-                                "%d,%d,%d,%d,%d,%d,%d,%d"
+                                "%d,%d,%d,%d,%d,%d,%d,%d,%d"
                                 "\n",
                                 tg->inst,
                                 s.v_blank_start,
@@ -451,7 +453,8 @@ static unsigned int dcn10_get_otg_states(struct dc *dc, char *pBuf, unsigned int
                                 s.h_sync_a_pol,
                                 s.h_total,
                                 s.v_total,
-                                s.underflow_occurred_status);
+                                s.underflow_occurred_status,
+                                pix_clk);
 
                         remaining_buffer -= chars_printed;
                         pBuf += chars_printed;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index 477ab9222216..771449f8984f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -440,7 +440,7 @@ static uint8_t get_frontend_source(
         }
 }
 
-void configure_encoder(
+void enc1_configure_encoder(
         struct dcn10_link_encoder *enc10,
         const struct dc_link_settings *link_settings)
 {
@@ -543,12 +543,12 @@ bool dcn10_link_encoder_validate_dvi_output(
         if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
                 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
                 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
-                crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
+                crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
                 return false;
-        if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
+        if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
                 return false;
 
-        if (crtc_timing->pix_clk_khz > max_pixel_clock)
+        if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
                 return false;
 
         /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
@@ -571,7 +571,7 @@ bool dcn10_link_encoder_validate_dvi_output(
 static bool dcn10_link_encoder_validate_hdmi_output(
         const struct dcn10_link_encoder *enc10,
         const struct dc_crtc_timing *crtc_timing,
-        int adjusted_pix_clk_khz)
+        int adjusted_pix_clk_100hz)
 {
         enum dc_color_depth max_deep_color =
                         enc10->base.features.max_hdmi_deep_color;
@@ -581,11 +581,11 @@ static bool dcn10_link_encoder_validate_hdmi_output(
 
         if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
                 return false;
-        if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
+        if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
                 return false;
 
-        if ((adjusted_pix_clk_khz == 0) ||
-                (adjusted_pix_clk_khz > enc10->base.features.max_hdmi_pixel_clock))
+        if ((adjusted_pix_clk_100hz == 0) ||
+                (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
                 return false;
 
         /* DCE11 HW does not support 420 */
@@ -594,7 +594,7 @@ static bool dcn10_link_encoder_validate_hdmi_output(
                 return false;
 
         if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
-                adjusted_pix_clk_khz >= 300000)
+                adjusted_pix_clk_100hz >= 3000000)
                 return false;
         if (enc10->base.ctx->dc->debug.hdmi20_disable &&
                 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
@@ -738,7 +738,7 @@ bool dcn10_link_encoder_validate_output_with_stream(
         case SIGNAL_TYPE_DVI_DUAL_LINK:
                 is_valid = dcn10_link_encoder_validate_dvi_output(
                         enc10,
-                        stream->sink->link->connector_signal,
+                        stream->link->connector_signal,
                         stream->signal,
                         &stream->timing);
         break;
@@ -746,7 +746,7 @@ bool dcn10_link_encoder_validate_output_with_stream(
                 is_valid = dcn10_link_encoder_validate_hdmi_output(
                                 enc10,
                                 &stream->timing,
-                                stream->phy_pix_clk);
+                                stream->phy_pix_clk * 10);
         break;
         case SIGNAL_TYPE_DISPLAY_PORT:
         case SIGNAL_TYPE_DISPLAY_PORT_MST:
@@ -910,7 +910,7 @@ void dcn10_link_encoder_enable_dp_output(
          * but it's not passed to asic_control.
          * We need to set number of lanes manually.
          */
-        configure_encoder(enc10, link_settings);
+        enc1_configure_encoder(enc10, link_settings);
 
         cntl.action = TRANSMITTER_CONTROL_ENABLE;
         cntl.engine_id = enc->preferred_engine;
@@ -949,7 +949,7 @@ void dcn10_link_encoder_enable_dp_mst_output(
          * but it's not passed to asic_control.
          * We need to set number of lanes manually.
          */
-        configure_encoder(enc10, link_settings);
+        enc1_configure_encoder(enc10, link_settings);
 
         cntl.action = TRANSMITTER_CONTROL_ENABLE;
         cntl.engine_id = ENGINE_ID_UNKNOWN;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 49ead12b2532..670b46e887ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -271,7 +271,7 @@ void dcn10_link_encoder_setup(
         struct link_encoder *enc,
         enum signal_type signal);
 
-void configure_encoder(
+void enc1_configure_encoder(
         struct dcn10_link_encoder *enc10,
         const struct dc_link_settings *link_settings);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 7c138615f17d..eb019d404928 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -102,14 +102,6 @@ static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_c
         patched_crtc_timing = *dc_crtc_timing;
         optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
 
-        vesa_sync_start = patched_crtc_timing.h_addressable +
-                        patched_crtc_timing.h_border_right +
-                        patched_crtc_timing.h_front_porch;
-
-        asic_blank_end = patched_crtc_timing.h_total -
-                        vesa_sync_start -
-                        patched_crtc_timing.h_border_left;
-
         vesa_sync_start = patched_crtc_timing.v_addressable +
                         patched_crtc_timing.v_border_bottom +
                         patched_crtc_timing.v_front_porch;
@@ -119,10 +111,8 @@ static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_c
                         patched_crtc_timing.v_border_top);
 
         vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
-        if (vertical_line_start < 0) {
-                ASSERT(0);
+        if (vertical_line_start < 0)
                 vertical_line_start = 0;
-        }
 
         return vertical_line_start;
 }
@@ -136,14 +126,14 @@ void optc1_program_vline_interrupt(
         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
         unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
-        unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
+        unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_100hz + 999), 1000);
         uint32_t req_delta_lines = (uint32_t) div64_u64(
                         (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
                                                                 dc_crtc_timing->h_total);
 
         uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);
         uint32_t start_line = 0;
-        uint32_t endLine = 0;
+        uint32_t end_line = 0;
 
         if (req_delta_lines != 0)
                 req_delta_lines--;
@@ -153,14 +143,17 @@ void optc1_program_vline_interrupt(
         else
                 start_line = vsync_line - req_delta_lines;
 
-        endLine = start_line + 2;
+        end_line = start_line + 2;
 
-        if (endLine >= dc_crtc_timing->v_total)
-                endLine = 2;
+        if (start_line >= dc_crtc_timing->v_total)
+                start_line = start_line % dc_crtc_timing->v_total;
+
+        if (end_line >= dc_crtc_timing->v_total)
+                end_line = end_line % dc_crtc_timing->v_total;
 
         REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
                         OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
-                        OTG_VERTICAL_INTERRUPT0_LINE_END, endLine);
+                        OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
 }
 
 /**
@@ -299,16 +292,17 @@ void optc1_program_timing(
         }
 
         /* Interlace */
-        if (patched_crtc_timing.flags.INTERLACE == 1) {
-                REG_UPDATE(OTG_INTERLACE_CONTROL,
-                                OTG_INTERLACE_ENABLE, 1);
-                v_init = v_init / 2;
-                if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
-                        v_fp2 = v_fp2 / 2;
-        } else
-                REG_UPDATE(OTG_INTERLACE_CONTROL,
-                                OTG_INTERLACE_ENABLE, 0);
-
+        if (REG(OTG_INTERLACE_CONTROL)) {
+                if (patched_crtc_timing.flags.INTERLACE == 1) {
+                        REG_UPDATE(OTG_INTERLACE_CONTROL,
+                                        OTG_INTERLACE_ENABLE, 1);
+                        v_init = v_init / 2;
+                        if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)
+                                v_fp2 = v_fp2 / 2;
+                } else
+                        REG_UPDATE(OTG_INTERLACE_CONTROL,
+                                        OTG_INTERLACE_ENABLE, 0);
+        }
 
         /* VTG enable set to 0 first VInit */
         REG_UPDATE(CONTROL,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 5d4772dec0ba..09d74070a49b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -70,7 +70,7 @@
 const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
         .rob_buffer_size_kbytes = 64,
         .det_buffer_size_kbytes = 164,
-        .dpte_buffer_size_in_pte_reqs = 42,
+        .dpte_buffer_size_in_pte_reqs_luma = 42,
         .dpp_output_buffer_pixels = 2560,
         .opp_output_buffer_lines = 1,
         .pixel_chunk_size_kbytes = 8,
@@ -436,7 +436,6 @@ static const struct dcn_optc_mask tg_mask = {
 };
 
 static const struct bios_registers bios_regs = {
-                NBIO_SR(BIOS_SCRATCH_0),
                 NBIO_SR(BIOS_SCRATCH_3),
                 NBIO_SR(BIOS_SCRATCH_6)
 };
@@ -609,7 +608,7 @@ static struct output_pixel_processor *dcn10_opp_create(
         return &opp->base;
 }
 
-struct aux_engine *dcn10_aux_engine_create(
+struct dce_aux *dcn10_aux_engine_create(
         struct dc_context *ctx,
         uint32_t inst)
 {
@@ -678,18 +677,18 @@ static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
 
 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
 {
-        struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),
+        struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
                                           GFP_KERNEL);
 
-        if (!hubbub)
+        if (!dcn10_hubbub)
                 return NULL;
 
-        hubbub1_construct(hubbub, ctx,
+        hubbub1_construct(&dcn10_hubbub->base, ctx,
                         &hubbub_reg,
                         &hubbub_shift,
                         &hubbub_mask);
 
-        return hubbub;
+        return &dcn10_hubbub->base;
 }
 
 static struct timing_generator *dcn10_timing_generator_create(
@@ -911,7 +910,7 @@ static void destruct(struct dcn10_resource_pool *pool)
 
         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
                 if (pool->base.engines[i] != NULL)
-                        pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]);
+                        dce110_engine_destroy(&pool->base.engines[i]);
                 if (pool->base.hw_i2cs[i] != NULL) {
                         kfree(pool->base.hw_i2cs[i]);
                         pool->base.hw_i2cs[i] = NULL;
@@ -974,8 +973,8 @@ static void get_pixel_clock_parameters(
         struct pixel_clk_params *pixel_clk_params)
 {
         const struct dc_stream_state *stream = pipe_ctx->stream;
-        pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
-        pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
+        pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
+        pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
         /* TODO: un-hardcode*/
@@ -991,9 +990,9 @@ static void get_pixel_clock_parameters(
                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
 
         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
-                pixel_clk_params->requested_pix_clk  /= 2;
+                pixel_clk_params->requested_pix_clk_100hz  /= 2;
         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
-                pixel_clk_params->requested_pix_clk *= 2;
+                pixel_clk_params->requested_pix_clk_100hz *= 2;
 
 }
 
@@ -1131,6 +1130,56 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st
         return DC_OK;
 }
 
+static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
+{
+        int i, j;
+        bool video_down_scaled = false;
+        bool video_large = false;
+        bool desktop_large = false;
+        bool dcc_disabled = false;
+
+        for (i = 0; i < context->stream_count; i++) {
+                if (context->stream_status[i].plane_count == 0)
+                        continue;
+
+                if (context->stream_status[i].plane_count > 2)
+                        return false;
+
+                for (j = 0; j < context->stream_status[i].plane_count; j++) {
+                        struct dc_plane_state *plane =
+                                context->stream_status[i].plane_states[j];
+
+
+                        if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
+
+                                if (plane->src_rect.width > plane->dst_rect.width ||
+                                                plane->src_rect.height > plane->dst_rect.height)
+                                        video_down_scaled = true;
+
+                                if (plane->src_rect.width >= 3840)
+                                        video_large = true;
+
+                        } else {
+                                if (plane->src_rect.width >= 3840)
+                                        desktop_large = true;
+                                if (!plane->dcc.enable)
+                                        dcc_disabled = true;
+                        }
+                }
+        }
+
+        /*
+         * Workaround: On DCN10 there is UMC issue that causes underflow when
+         * playing 4k video on 4k desktop with video downscaled and single channel
+         * memory
+         */
+        if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
+                        dc->dcn_soc->number_of_channels == 1)
+                return DC_FAIL_SURFACE_VALIDATE;
+
+        return DC_OK;
+}
+
 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state)
 {
         enum dc_status result = DC_OK;
@@ -1159,6 +1208,7 @@ static const struct resource_funcs dcn10_res_pool_funcs = {
         .validate_bandwidth = dcn_validate_bandwidth,
         .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
         .validate_plane = dcn10_validate_plane,
+        .validate_global = dcn10_validate_global,
         .add_stream_to_ctx = dcn10_add_stream_to_ctx,
         .get_default_swizzle_mode = dcn10_get_default_swizzle_mode
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index b8b5525a389a..b08254121251 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -261,17 +261,29 @@ void enc1_stream_encoder_dp_set_stream_attribute(
         uint8_t dp_component_depth = 0;
 
         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+        struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
+
+        if (hw_crtc_timing.flags.INTERLACE) {
+                /*the input timing is in VESA spec format with Interlace flag =1*/
+                hw_crtc_timing.v_total /= 2;
+                hw_crtc_timing.v_border_top /= 2;
+                hw_crtc_timing.v_addressable /= 2;
+                hw_crtc_timing.v_border_bottom /= 2;
+                hw_crtc_timing.v_front_porch /= 2;
+                hw_crtc_timing.v_sync_width /= 2;
+        }
+
 
         /* set pixel encoding */
-        switch (crtc_timing->pixel_encoding) {
+        switch (hw_crtc_timing.pixel_encoding) {
         case PIXEL_ENCODING_YCBCR422:
                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
                 break;
         case PIXEL_ENCODING_YCBCR444:
                 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
 
-                if (crtc_timing->flags.Y_ONLY)
-                        if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
+                if (hw_crtc_timing.flags.Y_ONLY)
+                        if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
                                 /* HW testing only, no use case yet.
                                  * Color depth of Y-only could be
                                  * 8, 10, 12, 16 bits
@@ -299,7 +311,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
          * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
          * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
          */
-        if ((crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
+        if ((hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
                         (output_color_space == COLOR_SPACE_2020_YCBCR) ||
                         (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) ||
                         (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE))
@@ -308,7 +320,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
                 misc1 = misc1 & ~0x40;
 
         /* set color depth */
-        switch (crtc_timing->display_color_depth) {
+        switch (hw_crtc_timing.display_color_depth) {
         case COLOR_DEPTH_666:
                 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
                 break;
@@ -336,7 +348,7 @@ void enc1_stream_encoder_dp_set_stream_attribute(
 
         /* set dynamic range and YCbCr range */
 
-        switch (crtc_timing->display_color_depth) {
+        switch (hw_crtc_timing.display_color_depth) {
         case COLOR_DEPTH_666:
                 colorimetry_bpc = 0;
                 break;
@@ -372,9 +384,9 @@ void enc1_stream_encoder_dp_set_stream_attribute(
                 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
                 dynamic_range_ycbcr = 0; /*bt601*/
-                if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+                if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
-                else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+                else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
                 break;
         case COLOR_SPACE_YCBCR709:
@@ -382,9 +394,9 @@ void enc1_stream_encoder_dp_set_stream_attribute(
                 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
                 misc1 = misc1 & ~0x80; /* bit7 = 0*/
                 dynamic_range_ycbcr = 1; /*bt709*/
-                if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+                if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
                         misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
-                else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
+                else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
                         misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
                 break;
         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
@@ -414,26 +426,26 @@ void enc1_stream_encoder_dp_set_stream_attribute(
          * dc_crtc_timing is vesa dmt struct. data from edid
          */
         REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
-                        DP_MSA_HTOTAL, crtc_timing->h_total,
-                        DP_MSA_VTOTAL, crtc_timing->v_total);
+                        DP_MSA_HTOTAL, hw_crtc_timing.h_total,
+                        DP_MSA_VTOTAL, hw_crtc_timing.v_total);
 
         /* calculate from vesa timing parameters
          * h_active_start related to leading edge of sync
          */
 
-        h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
-                        crtc_timing->h_addressable - crtc_timing->h_border_right;
+        h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
+                        hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
 
-        h_back_porch = h_blank - crtc_timing->h_front_porch -
-                        crtc_timing->h_sync_width;
+        h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
+                        hw_crtc_timing.h_sync_width;
 
         /* start at beginning of left border */
-        h_active_start = crtc_timing->h_sync_width + h_back_porch;
+        h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
 
 
-        v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
-                        crtc_timing->v_addressable - crtc_timing->v_border_bottom -
-                        crtc_timing->v_front_porch;
+        v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
+                        hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
+                        hw_crtc_timing.v_front_porch;
 
 
         /* start at beginning of left border */
@@ -443,20 +455,20 @@ void enc1_stream_encoder_dp_set_stream_attribute(
 
         REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
                         DP_MSA_HSYNCWIDTH,
-                        crtc_timing->h_sync_width,
+                        hw_crtc_timing.h_sync_width,
                         DP_MSA_HSYNCPOLARITY,
-                        !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
+                        !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
                         DP_MSA_VSYNCWIDTH,
-                        crtc_timing->v_sync_width,
+                        hw_crtc_timing.v_sync_width,
                         DP_MSA_VSYNCPOLARITY,
-                        !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
+                        !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
 
         /* HWDITH include border or overscan */
         REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
-                DP_MSA_HWIDTH, crtc_timing->h_border_left +
-                crtc_timing->h_addressable + crtc_timing->h_border_right,
-                DP_MSA_VHEIGHT, crtc_timing->v_border_top +
-                crtc_timing->v_addressable + crtc_timing->v_border_bottom);
+                DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
+                hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
+                DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
+                hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
 }
 
 static void enc1_stream_encoder_set_stream_attribute_helper(
@@ -594,7 +606,7 @@ void enc1_stream_encoder_dvi_set_stream_attribute(
         cntl.signal = is_dual_link ?
                         SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
         cntl.enable_dp_audio = false;
-        cntl.pixel_clock = crtc_timing->pix_clk_khz;
+        cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
         cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
 
         if (enc1->base.bp->funcs->encoder_control(
@@ -1413,6 +1425,14 @@ void enc1_setup_stereo_sync(
         REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
 }
 
+void enc1_dig_connect_to_otg(
+        struct stream_encoder *enc,
+        int tg_inst)
+{
+        struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+
+        REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
+}
 
 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
         .dp_set_stream_attribute =
@@ -1445,6 +1465,7 @@ static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
         .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
         .setup_stereo_sync  = enc1_setup_stereo_sync,
         .set_avmute = enc1_stream_encoder_set_avmute,
+        .dig_connect_to_otg  = enc1_dig_connect_to_otg,
 };
 
 void dcn10_stream_encoder_construct(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
index 67f3e4dd95c1..b7c800e10a32 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
@@ -274,7 +274,8 @@ struct dcn10_stream_enc_registers {
         SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
         SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
         SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
-        SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
+        SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
+        SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
 
 #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
         SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
@@ -426,7 +427,8 @@ struct dcn10_stream_enc_registers {
         type DP_MSA_VHEIGHT;\
         type HDMI_DB_DISABLE;\
         type DP_VID_N_MUL;\
-        type DP_VID_M_DOUBLE_VALUE_EN
+        type DP_VID_M_DOUBLE_VALUE_EN;\
+        type DIG_SOURCE_SELECT
 
 struct dcn10_stream_encoder_shift {
         SE_REG_FIELD_LIST_DCN1_0(uint8_t);
@@ -523,4 +525,8 @@ void enc1_se_hdmi_audio_setup(
 void enc1_se_hdmi_audio_disable(
         struct stream_encoder *enc);
 
+void enc1_dig_connect_to_otg(
+        struct stream_encoder *enc,
+        int tg_inst);
+
 #endif /* __DC_STREAM_ENCODER_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index 0029a39efb1c..14bed5b1fa97 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -38,7 +38,8 @@ enum pp_smu_ver {
          * of interface sharing between families of ASIcs.
          */
         PP_SMU_UNSUPPORTED,
-        PP_SMU_VER_RV
+        PP_SMU_VER_RV,
+        PP_SMU_VER_MAX
 };
 
 struct pp_smu {
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index 1af8c777b3ac..77200711abbe 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -82,9 +82,17 @@ enum dm_pp_clock_type {
 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
         (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
         (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
-        (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
-
-#define DM_PP_MAX_CLOCK_LEVELS 8
+        (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
+        (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
+        (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
+        (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
+        (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
+        (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
+        (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
+        (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
+        "Invalid"
+
+#define DM_PP_MAX_CLOCK_LEVELS 16
 
 struct dm_pp_clock_levels {
         uint32_t num_levels;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index d97ca6528f9d..33c7d7588712 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -30,7 +30,7 @@ else ifneq ($(call cc-option, -mstack-alignment=16),)
         cc_stack_align := -mstack-alignment=16
 endif
 
-dml_ccflags := -mhard-float -msse $(cc_stack_align)
+dml_ccflags := -mhard-float -msse -msse2 $(cc_stack_align)
 
 CFLAGS_display_mode_lib.o := $(dml_ccflags)
 CFLAGS_display_pipe_clocks.o := $(dml_ccflags)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index bea4e61b94c7..c59e582c1f40 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -121,4 +121,30 @@ enum self_refresh_affinity {
         dm_neither_self_refresh_nor_mclk_switch
 };
 
+enum dm_validation_status {
+        DML_VALIDATION_OK,
+        DML_FAIL_SCALE_RATIO_TAP,
+        DML_FAIL_SOURCE_PIXEL_FORMAT,
+        DML_FAIL_VIEWPORT_SIZE,
+        DML_FAIL_TOTAL_V_ACTIVE_BW,
+        DML_FAIL_DIO_SUPPORT,
+        DML_FAIL_NOT_ENOUGH_DSC,
+        DML_FAIL_DSC_CLK_REQUIRED,
+        DML_FAIL_URGENT_LATENCY,
+        DML_FAIL_REORDERING_BUFFER,
+        DML_FAIL_DISPCLK_DPPCLK,
+        DML_FAIL_TOTAL_AVAILABLE_PIPES,
+        DML_FAIL_NUM_OTG,
+        DML_FAIL_WRITEBACK_MODE,
+        DML_FAIL_WRITEBACK_LATENCY,
+        DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
+        DML_FAIL_CURSOR_SUPPORT,
+        DML_FAIL_PITCH_SUPPORT,
+        DML_FAIL_PTE_BUFFER_SIZE,
+        DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
+        DML_FAIL_DSC_INPUT_BPC,
+        DML_FAIL_PREFETCH_SUPPORT,
+        DML_FAIL_V_RATIO_PREFETCH,
+};
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index dddeb0d4db8f..d303b789adfe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -62,3 +62,31 @@ void dml_init_instance(struct display_mode_lib *lib, enum dml_project project)
         }
 }
 
+const char *dml_get_status_message(enum dm_validation_status status)
+{
+        switch (status) {
+        case DML_VALIDATION_OK:                   return "Validation OK";
+        case DML_FAIL_SCALE_RATIO_TAP:            return "Scale ratio/tap";
+        case DML_FAIL_SOURCE_PIXEL_FORMAT:        return "Source pixel format";
+        case DML_FAIL_VIEWPORT_SIZE:              return "Viewport size";
+        case DML_FAIL_TOTAL_V_ACTIVE_BW:          return "Total vertical active bandwidth";
+        case DML_FAIL_DIO_SUPPORT:                return "DIO support";
+        case DML_FAIL_NOT_ENOUGH_DSC:             return "Not enough DSC Units";
+        case DML_FAIL_DSC_CLK_REQUIRED:           return "DSC clock required";
+        case DML_FAIL_URGENT_LATENCY:             return "Urgent latency";
+        case DML_FAIL_REORDERING_BUFFER:          return "Re-ordering buffer";
+        case DML_FAIL_DISPCLK_DPPCLK:             return "Dispclk and Dppclk";
+        case DML_FAIL_TOTAL_AVAILABLE_PIPES:      return "Total available pipes";
+        case DML_FAIL_NUM_OTG:                    return "Number of OTG";
+        case DML_FAIL_WRITEBACK_MODE:             return "Writeback mode";
+        case DML_FAIL_WRITEBACK_LATENCY:          return "Writeback latency";
+        case DML_FAIL_WRITEBACK_SCALE_RATIO_TAP:  return "Writeback scale ratio/tap";
+        case DML_FAIL_CURSOR_SUPPORT:             return "Cursor support";
+        case DML_FAIL_PITCH_SUPPORT:              return "Pitch support";
+        case DML_FAIL_PTE_BUFFER_SIZE:            return "PTE buffer size";
+        case DML_FAIL_DSC_INPUT_BPC:              return "DSC input bpc";
+        case DML_FAIL_PREFETCH_SUPPORT:           return "Prefetch support";
+        case DML_FAIL_V_RATIO_PREFETCH:           return "Vertical ratio prefetch";
+        default:                                  return "Unknown Status";
+        }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 635206248889..a730e0209c05 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -43,4 +43,6 @@ struct display_mode_lib {
 
 void dml_init_instance(struct display_mode_lib *lib, enum dml_project project);
 
+const char *dml_get_status_message(enum dm_validation_status status);
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 5dd04520ceca..391183e3428f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -30,22 +30,15 @@ typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
 typedef struct _vcs_dpi_ip_params_st ip_params_st;
 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
-typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st;
 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
-typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st;
-typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st;
-typedef struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_watermarks_st;
-typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st;
-typedef struct _vcs_dpi_vratio_pre_st vratio_pre_st;
 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_cur_rq_dlg_params_st display_cur_rq_dlg_params_st;
 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
@@ -55,8 +48,6 @@ typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
-typedef struct _vcs_dpi_display_dlg_prefetch_param_st display_dlg_prefetch_param_st;
-typedef struct _vcs_dpi_display_pipe_clock_st display_pipe_clock_st;
 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
 
 struct _vcs_dpi_voltage_scaling_st {
@@ -111,8 +102,6 @@ struct _vcs_dpi_soc_bounding_box_st {
         double xfc_bus_transport_time_us;
         double xfc_xbuf_latency_tolerance_us;
         int use_urgent_burst_bw;
-        double max_hscl_ratio;
-        double max_vscl_ratio;
         unsigned int num_states;
         struct _vcs_dpi_voltage_scaling_st clock_limits[8];
 };
@@ -129,7 +118,8 @@ struct _vcs_dpi_ip_params_st {
         unsigned int odm_capable;
         unsigned int rob_buffer_size_kbytes;
         unsigned int det_buffer_size_kbytes;
-        unsigned int dpte_buffer_size_in_pte_reqs;
+        unsigned int dpte_buffer_size_in_pte_reqs_luma;
+        unsigned int dpte_buffer_size_in_pte_reqs_chroma;
         unsigned int pde_proc_buffer_size_64k_reqs;
         unsigned int dpp_output_buffer_pixels;
         unsigned int opp_output_buffer_lines;
@@ -192,7 +182,6 @@ struct _vcs_dpi_display_xfc_params_st {
 struct _vcs_dpi_display_pipe_source_params_st {
         int source_format;
         unsigned char dcc;
-        unsigned int dcc_override;
         unsigned int dcc_rate;
         unsigned char dcc_use_global;
         unsigned char vm;
@@ -205,7 +194,6 @@ struct _vcs_dpi_display_pipe_source_params_st {
         int source_scan;
         int sw_mode;
         int macro_tile_size;
-        unsigned char is_display_sw;
         unsigned int viewport_width;
         unsigned int viewport_height;
         unsigned int viewport_y_y;
@@ -252,16 +240,10 @@ struct _vcs_dpi_display_output_params_st {
         int output_bpc;
         int output_type;
         int output_format;
-        int output_standard;
         int dsc_slices;
         struct writeback_st wb;
 };
 
-struct _vcs_dpi_display_bandwidth_st {
-        double total_bw_consumed_gbps;
-        double guaranteed_urgent_return_bw_gbps;
-};
-
 struct _vcs_dpi_scaler_ratio_depth_st {
         double hscl_ratio;
         double vscl_ratio;
@@ -300,11 +282,9 @@ struct _vcs_dpi_display_pipe_dest_params_st {
         unsigned int vupdate_width;
         unsigned int vready_offset;
         unsigned char interlaced;
-        unsigned char underscan;
         double pixel_rate_mhz;
         unsigned char synchronized_vblank_all_planes;
         unsigned char otg_inst;
-        unsigned char odm_split_cnt;
         unsigned char odm_combine;
         unsigned char use_maximum_vstartup;
 };
@@ -331,65 +311,6 @@ struct _vcs_dpi_display_e2e_pipe_params_st {
         display_clocks_and_cfg_st clks_cfg;
 };
 
-struct _vcs_dpi_dchub_buffer_sizing_st {
-        unsigned int swath_width_y;
-        unsigned int swath_height_y;
-        unsigned int swath_height_c;
-        unsigned int detail_buffer_size_y;
-};
-
-struct _vcs_dpi_watermarks_perf_st {
-        double stutter_eff_in_active_region_percent;
-        double urgent_latency_supported_us;
-        double non_urgent_latency_supported_us;
-        double dram_clock_change_margin_us;
-        double dram_access_eff_percent;
-};
-
-struct _vcs_dpi_cstate_pstate_watermarks_st {
-        double cstate_exit_us;
-        double cstate_enter_plus_exit_us;
-        double pstate_change_us;
-};
-
-struct _vcs_dpi_wm_calc_pipe_params_st {
-        unsigned int num_dpp;
-        int voltage;
-        int output_type;
-        double dcfclk_mhz;
-        double socclk_mhz;
-        double dppclk_mhz;
-        double pixclk_mhz;
-        unsigned char interlace_en;
-        unsigned char pte_enable;
-        unsigned char dcc_enable;
-        double dcc_rate;
-        double bytes_per_pixel_c;
-        double bytes_per_pixel_y;
-        unsigned int swath_width_y;
-        unsigned int swath_height_y;
-        unsigned int swath_height_c;
-        unsigned int det_buffer_size_y;
-        double h_ratio;
-        double v_ratio;
-        unsigned int h_taps;
-        unsigned int h_total;
-        unsigned int v_total;
-        unsigned int v_active;
-        unsigned int e2e_index;
-        double display_pipe_line_delivery_time;
-        double read_bw;
-        unsigned int lines_in_det_y;
-        unsigned int lines_in_det_y_rounded_down_to_swath;
-        double full_det_buffering_time;
-        double dcfclk_deepsleep_mhz_per_plane;
-};
-
-struct _vcs_dpi_vratio_pre_st {
-        double vratio_pre_l;
-        double vratio_pre_c;
-};
-
 struct _vcs_dpi_display_data_rq_misc_params_st {
         unsigned int full_swath_bytes;
         unsigned int stored_swath_bytes;
@@ -423,16 +344,9 @@ struct _vcs_dpi_display_data_rq_dlg_params_st {
         unsigned int meta_bytes_per_row_ub;
 };
 
-struct _vcs_dpi_display_cur_rq_dlg_params_st {
-        unsigned char enable;
-        unsigned int swath_height;
-        unsigned int req_per_line;
-};
-
 struct _vcs_dpi_display_rq_dlg_params_st {
         display_data_rq_dlg_params_st rq_l;
         display_data_rq_dlg_params_st rq_c;
-        display_cur_rq_dlg_params_st rq_cur0;
 };
 
 struct _vcs_dpi_display_rq_sizing_params_st {
@@ -498,6 +412,10 @@ struct _vcs_dpi_display_dlg_regs_st {
         unsigned int xfc_reg_remote_surface_flip_latency;
         unsigned int xfc_reg_prefetch_margin;
         unsigned int dst_y_delta_drq_limit;
+        unsigned int refcyc_per_vm_group_vblank;
+        unsigned int refcyc_per_vm_group_flip;
+        unsigned int refcyc_per_vm_req_vblank;
+        unsigned int refcyc_per_vm_req_flip;
 };
 
 struct _vcs_dpi_display_ttu_regs_st {
@@ -556,19 +474,6 @@ struct _vcs_dpi_display_dlg_sys_params_st {
         unsigned int total_flip_bytes;
 };
 
-struct _vcs_dpi_display_dlg_prefetch_param_st {
-        double prefetch_bw;
-        unsigned int flip_bytes;
-};
-
-struct _vcs_dpi_display_pipe_clock_st {
-        double dcfclk_mhz;
-        double dispclk_mhz;
-        double socclk_mhz;
-        double dscclk_mhz[6];
-        double dppclk_mhz[6];
-};
-
 struct _vcs_dpi_display_arb_params_st {
         int max_req_outstanding;
         int min_req_outstanding;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
index c2037daa8e66..ad8571f5a142 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
@@ -459,7 +459,7 @@ static void dml1_rq_dlg_get_row_heights(
         /* dpte   */
         /* ------ */
         log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
-        dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
+        dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma;
 
         log2_vmpg_height = 0;
         log2_vmpg_width = 0;
@@ -776,7 +776,7 @@ static void get_surf_rq_param(
         /* dpte   */
         /* ------ */
         log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
-        dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
+        dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma;
 
         log2_vmpg_height = 0;
         log2_vmpg_width = 0;
@@ -881,7 +881,7 @@ static void get_surf_rq_param(
         /* the dpte_group_bytes is reduced for the specific case of vertical
          * access of a tile surface that has dpte request of 8x1 ptes.
          */
-        if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) /*reduced, in this case, will have page fault within a group */
+        if (!surf_linear && (log2_dpte_req_height_ptes == 0) && surf_vert) /*reduced, in this case, will have page fault within a group */
                 rq_sizing_param->dpte_group_bytes = 512;
         else
                 /*full size */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
deleted file mode 100644
index 352885cb4d07..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile
+++ /dev/null
@@ -1,99 +0,0 @@
-#
-# Copyright 2017 Advanced Micro Devices, Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
-# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-# OTHER DEALINGS IN THE SOFTWARE.
-#
-#
-# Makefile for the 'i2c' sub-component of DAL.
-# It provides the control and status of HW i2c engine of the adapter.
-
-I2CAUX = aux_engine.o engine_base.o i2caux.o i2c_engine.o \
-         i2c_generic_hw_engine.o i2c_hw_engine.o i2c_sw_engine.o
-
-AMD_DAL_I2CAUX = $(addprefix $(AMDDALPATH)/dc/i2caux/,$(I2CAUX))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX)
-
-###############################################################################
-# DCE 8x family
-###############################################################################
-I2CAUX_DCE80 = i2caux_dce80.o i2c_hw_engine_dce80.o \
-        i2c_sw_engine_dce80.o
-
-AMD_DAL_I2CAUX_DCE80 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce80/,$(I2CAUX_DCE80))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE80)
-
-###############################################################################
-# DCE 100 family
-###############################################################################
-I2CAUX_DCE100 = i2caux_dce100.o
-
-AMD_DAL_I2CAUX_DCE100 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce100/,$(I2CAUX_DCE100))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE100)
-
-###############################################################################
-# DCE 110 family
-###############################################################################
-I2CAUX_DCE110 = i2caux_dce110.o i2c_sw_engine_dce110.o i2c_hw_engine_dce110.o \
-        aux_engine_dce110.o
-
-AMD_DAL_I2CAUX_DCE110 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce110/,$(I2CAUX_DCE110))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE110)
-
-###############################################################################
-# DCE 112 family
-###############################################################################
-I2CAUX_DCE112 = i2caux_dce112.o
-
-AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE112))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112)
-
-###############################################################################
-# DCN 1.0 family
-###############################################################################
-ifdef CONFIG_DRM_AMD_DC_DCN1_0
-I2CAUX_DCN1 = i2caux_dcn10.o
-
-AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCN1)
-endif
-
-###############################################################################
-# DCE 120 family
-###############################################################################
-I2CAUX_DCE120 = i2caux_dce120.o
-
-AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120)
-
-###############################################################################
-# Diagnostics on FPGA
-###############################################################################
-I2CAUX_DIAG = i2caux_diag.o
-
-AMD_DAL_I2CAUX_DIAG = $(addprefix $(AMDDALPATH)/dc/i2caux/diagnostics/,$(I2CAUX_DIAG))
-
-AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DIAG)
-
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
deleted file mode 100644
index 8cbf38b2470d..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c
+++ /dev/null
@@ -1,606 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dm_event_log.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "aux_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "include/link_service_types.h"
-
-/*
- * This unit
- */
-
-enum {
-        AUX_INVALID_REPLY_RETRY_COUNTER = 1,
-        AUX_TIMED_OUT_RETRY_COUNTER = 2,
-        AUX_DEFER_RETRY_COUNTER = 6
-};
-
-#define FROM_ENGINE(ptr) \
-        container_of((ptr), struct aux_engine, base)
-#define DC_LOGGER \
-        engine->base.ctx->logger
-
-enum i2caux_engine_type dal_aux_engine_get_engine_type(
-        const struct engine *engine)
-{
-        return I2CAUX_ENGINE_TYPE_AUX;
-}
-
-bool dal_aux_engine_acquire(
-        struct engine *engine,
-        struct ddc *ddc)
-{
-        struct aux_engine *aux_engine = FROM_ENGINE(engine);
-
-        enum gpio_result result;
-        if (aux_engine->funcs->is_engine_available) {
-                /*check whether SW could use the engine*/
-                if (!aux_engine->funcs->is_engine_available(aux_engine)) {
-                        return false;
-                }
-        }
-
-        result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-                GPIO_DDC_CONFIG_TYPE_MODE_AUX);
-
-        if (result != GPIO_RESULT_OK)
-                return false;
-
-        if (!aux_engine->funcs->acquire_engine(aux_engine)) {
-                dal_ddc_close(ddc);
-                return false;
-        }
-
-        engine->ddc = ddc;
-
-        return true;
-}
-
-struct read_command_context {
-        uint8_t *buffer;
-        uint32_t current_read_length;
-        uint32_t offset;
-        enum i2caux_transaction_status status;
-
-        struct aux_request_transaction_data request;
-        struct aux_reply_transaction_data reply;
-
-        uint8_t returned_byte;
-
-        uint32_t timed_out_retry_aux;
-        uint32_t invalid_reply_retry_aux;
-        uint32_t defer_retry_aux;
-        uint32_t defer_retry_i2c;
-        uint32_t invalid_reply_retry_aux_on_ack;
-
-        bool transaction_complete;
-        bool operation_succeeded;
-};
-
-static void process_read_reply(
-        struct aux_engine *engine,
-        struct read_command_context *ctx)
-{
-        engine->funcs->process_channel_reply(engine, &ctx->reply);
-
-        switch (ctx->reply.status) {
-        case AUX_TRANSACTION_REPLY_AUX_ACK:
-                ctx->defer_retry_aux = 0;
-                if (ctx->returned_byte > ctx->current_read_length) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else if (ctx->returned_byte < ctx->current_read_length) {
-                        ctx->current_read_length -= ctx->returned_byte;
-
-                        ctx->offset += ctx->returned_byte;
-
-                        ++ctx->invalid_reply_retry_aux_on_ack;
-
-                        if (ctx->invalid_reply_retry_aux_on_ack >
-                                AUX_INVALID_REPLY_RETRY_COUNTER) {
-                                ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                                ctx->operation_succeeded = false;
-                        }
-                } else {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-                        ctx->transaction_complete = true;
-                        ctx->operation_succeeded = true;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_NACK:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-                ctx->operation_succeeded = false;
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_DEFER:
-                ++ctx->defer_retry_aux;
-
-                if (ctx->defer_retry_aux > AUX_DEFER_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_I2C_DEFER:
-                ctx->defer_retry_aux = 0;
-
-                ++ctx->defer_retry_i2c;
-
-                if (ctx->defer_retry_i2c > AUX_DEFER_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-
-static void process_read_request(
-        struct aux_engine *engine,
-        struct read_command_context *ctx)
-{
-        enum aux_channel_operation_result operation_result;
-
-        engine->funcs->submit_channel_request(engine, &ctx->request);
-
-        operation_result = engine->funcs->get_channel_status(
-                engine, &ctx->returned_byte);
-
-        switch (operation_result) {
-        case AUX_CHANNEL_OPERATION_SUCCEEDED:
-                if (ctx->returned_byte > ctx->current_read_length) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else {
-                        ctx->timed_out_retry_aux = 0;
-                        ctx->invalid_reply_retry_aux = 0;
-
-                        ctx->reply.length = ctx->returned_byte;
-                        ctx->reply.data = ctx->buffer;
-
-                        process_read_reply(engine, ctx);
-                }
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-                ++ctx->invalid_reply_retry_aux;
-
-                if (ctx->invalid_reply_retry_aux >
-                        AUX_INVALID_REPLY_RETRY_COUNTER) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else
-                        udelay(400);
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-                ++ctx->timed_out_retry_aux;
-
-                if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                } else {
-                        /* DP 1.2a, table 2-58:
-                         * "S3: AUX Request CMD PENDING:
-                         * retry 3 times, with 400usec wait on each"
-                         * The HW timeout is set to 550usec,
-                         * so we should not wait here */
-                }
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-
-static bool read_command(
-        struct aux_engine *engine,
-        struct i2caux_transaction_request *request,
-        bool middle_of_transaction)
-{
-        struct read_command_context ctx;
-
-        ctx.buffer = request->payload.data;
-        ctx.current_read_length = request->payload.length;
-        ctx.offset = 0;
-        ctx.timed_out_retry_aux = 0;
-        ctx.invalid_reply_retry_aux = 0;
-        ctx.defer_retry_aux = 0;
-        ctx.defer_retry_i2c = 0;
-        ctx.invalid_reply_retry_aux_on_ack = 0;
-        ctx.transaction_complete = false;
-        ctx.operation_succeeded = true;
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-                ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_READ;
-                ctx.request.address = request->payload.address;
-        } else if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-                ctx.request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ;
-                ctx.request.address = request->payload.address >> 1;
-        } else {
-                /* in DAL2, there was no return in such case */
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        ctx.request.delay = 0;
-
-        do {
-                memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
-
-                ctx.request.data = ctx.buffer + ctx.offset;
-                ctx.request.length = ctx.current_read_length;
-
-                process_read_request(engine, &ctx);
-
-                request->status = ctx.status;
-
-                if (ctx.operation_succeeded && !ctx.transaction_complete)
-                        if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-                                msleep(engine->delay);
-        } while (ctx.operation_succeeded && !ctx.transaction_complete);
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                DC_LOG_I2C_AUX("READ: addr:0x%x  value:0x%x Result:%d",
-                                request->payload.address,
-                                request->payload.data[0],
-                                ctx.operation_succeeded);
-        }
-
-        return ctx.operation_succeeded;
-}
-
-struct write_command_context {
-        bool mot;
-
-        uint8_t *buffer;
-        uint32_t current_write_length;
-        enum i2caux_transaction_status status;
-
-        struct aux_request_transaction_data request;
-        struct aux_reply_transaction_data reply;
-
-        uint8_t returned_byte;
-
-        uint32_t timed_out_retry_aux;
-        uint32_t invalid_reply_retry_aux;
-        uint32_t defer_retry_aux;
-        uint32_t defer_retry_i2c;
-        uint32_t max_defer_retry;
-        uint32_t ack_m_retry;
-
-        uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
-
-        bool transaction_complete;
-        bool operation_succeeded;
-};
-
-static void process_write_reply(
-        struct aux_engine *engine,
-        struct write_command_context *ctx)
-{
-        engine->funcs->process_channel_reply(engine, &ctx->reply);
-
-        switch (ctx->reply.status) {
-        case AUX_TRANSACTION_REPLY_AUX_ACK:
-                ctx->operation_succeeded = true;
-
-                if (ctx->returned_byte) {
-                        ctx->request.action = ctx->mot ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-
-                        ctx->current_write_length = 0;
-
-                        ++ctx->ack_m_retry;
-
-                        if (ctx->ack_m_retry > AUX_DEFER_RETRY_COUNTER) {
-                                ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                                ctx->operation_succeeded = false;
-                        } else
-                                udelay(300);
-                } else {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-                        ctx->defer_retry_aux = 0;
-                        ctx->ack_m_retry = 0;
-                        ctx->transaction_complete = true;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_NACK:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-                ctx->operation_succeeded = false;
-        break;
-        case AUX_TRANSACTION_REPLY_AUX_DEFER:
-                ++ctx->defer_retry_aux;
-
-                if (ctx->defer_retry_aux > ctx->max_defer_retry) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_I2C_DEFER:
-                ctx->defer_retry_aux = 0;
-                ctx->current_write_length = 0;
-
-                ctx->request.action = ctx->mot ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
-
-                ++ctx->defer_retry_i2c;
-
-                if (ctx->defer_retry_i2c > ctx->max_defer_retry) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                }
-        break;
-        case AUX_TRANSACTION_REPLY_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-
-static void process_write_request(
-        struct aux_engine *engine,
-        struct write_command_context *ctx)
-{
-        enum aux_channel_operation_result operation_result;
-
-        engine->funcs->submit_channel_request(engine, &ctx->request);
-
-        operation_result = engine->funcs->get_channel_status(
-                engine, &ctx->returned_byte);
-
-        switch (operation_result) {
-        case AUX_CHANNEL_OPERATION_SUCCEEDED:
-                ctx->timed_out_retry_aux = 0;
-                ctx->invalid_reply_retry_aux = 0;
-
-                ctx->reply.length = ctx->returned_byte;
-                ctx->reply.data = ctx->reply_data;
-
-                process_write_reply(engine, ctx);
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
-                ++ctx->invalid_reply_retry_aux;
-
-                if (ctx->invalid_reply_retry_aux >
-                        AUX_INVALID_REPLY_RETRY_COUNTER) {
-                        ctx->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
-                        ctx->operation_succeeded = false;
-                } else
-                        udelay(400);
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
-                ++ctx->timed_out_retry_aux;
-
-                if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
-                        ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        ctx->operation_succeeded = false;
-                } else {
-                        /* DP 1.2a, table 2-58:
-                         * "S3: AUX Request CMD PENDING:
-                         * retry 3 times, with 400usec wait on each"
-                         * The HW timeout is set to 550usec,
-                         * so we should not wait here */
-                }
-        break;
-        case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
-                ctx->operation_succeeded = false;
-        break;
-        default:
-                ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
-                ctx->operation_succeeded = false;
-        }
-}
-
-static bool write_command(
-        struct aux_engine *engine,
-        struct i2caux_transaction_request *request,
-        bool middle_of_transaction)
-{
-        struct write_command_context ctx;
-
-        ctx.mot = middle_of_transaction;
-        ctx.buffer = request->payload.data;
-        ctx.current_write_length = request->payload.length;
-        ctx.timed_out_retry_aux = 0;
-        ctx.invalid_reply_retry_aux = 0;
-        ctx.defer_retry_aux = 0;
-        ctx.defer_retry_i2c = 0;
-        ctx.ack_m_retry = 0;
-        ctx.transaction_complete = false;
-        ctx.operation_succeeded = true;
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_DP;
-                ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_WRITE;
-                ctx.request.address = request->payload.address;
-        } else if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
-                ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
-                ctx.request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-                ctx.request.address = request->payload.address >> 1;
-        } else {
-                /* in DAL2, there was no return in such case */
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        ctx.request.delay = 0;
-
-        ctx.max_defer_retry =
-                (engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
-                        engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
-
-        do {
-                ctx.request.data = ctx.buffer;
-                ctx.request.length = ctx.current_write_length;
-
-                process_write_request(engine, &ctx);
-
-                request->status = ctx.status;
-
-                if (ctx.operation_succeeded && !ctx.transaction_complete)
-                        if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
-                                msleep(engine->delay);
-        } while (ctx.operation_succeeded && !ctx.transaction_complete);
-
-        if (request->payload.address_space ==
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
-                DC_LOG_I2C_AUX("WRITE: addr:0x%x  value:0x%x Result:%d",
-                                request->payload.address,
-                                request->payload.data[0],
-                                ctx.operation_succeeded);
-        }
-
-        return ctx.operation_succeeded;
-}
-
-static bool end_of_transaction_command(
-        struct aux_engine *engine,
-        struct i2caux_transaction_request *request)
-{
-        struct i2caux_transaction_request dummy_request;
-        uint8_t dummy_data;
-
-        /* [tcheng] We only need to send the stop (read with MOT = 0)
-         * for I2C-over-Aux, not native AUX */
-
-        if (request->payload.address_space !=
-                I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C)
-                return false;
-
-        dummy_request.operation = request->operation;
-        dummy_request.payload.address_space = request->payload.address_space;
-        dummy_request.payload.address = request->payload.address;
-
-        /*
-         * Add a dummy byte due to some receiver quirk
-         * where one byte is sent along with MOT = 0.
-         * Ideally this should be 0.
-         */
-
-        dummy_request.payload.length = 0;
-        dummy_request.payload.data = &dummy_data;
-
-        if (request->operation == I2CAUX_TRANSACTION_READ)
-                return read_command(engine, &dummy_request, false);
-        else
-                return write_command(engine, &dummy_request, false);
-
-        /* according Syed, it does not need now DoDummyMOT */
-}
-
-bool dal_aux_engine_submit_request(
-        struct engine *engine,
-        struct i2caux_transaction_request *request,
-        bool middle_of_transaction)
-{
-        struct aux_engine *aux_engine = FROM_ENGINE(engine);
-
-        bool result;
-        bool mot_used = true;
-
-        switch (request->operation) {
-        case I2CAUX_TRANSACTION_READ:
-                result = read_command(aux_engine, request, mot_used);
-        break;
-        case I2CAUX_TRANSACTION_WRITE:
-                result = write_command(aux_engine, request, mot_used);
-        break;
-        default:
-                result = false;
-        }
-
-        /* [tcheng]
-         * need to send stop for the last transaction to free up the AUX
-         * if the above command fails, this would be the last transaction */
-
-        if (!middle_of_transaction || !result)
-                end_of_transaction_command(aux_engine, request);
-
-        /* mask AUX interrupt */
-
-        return result;
-}
-
-void dal_aux_engine_construct(
-        struct aux_engine *engine,
-        struct dc_context *ctx)
-{
-        dal_i2caux_construct_engine(&engine->base, ctx);
-        engine->delay = 0;
-        engine->max_defer_write_retry = 0;
-}
-
-void dal_aux_engine_destruct(
-        struct aux_engine *engine)
-{
-        dal_i2caux_destruct_engine(&engine->base);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h b/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
deleted file mode 100644
index c33a2898d967..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_AUX_ENGINE_H__
-#define __DAL_AUX_ENGINE_H__
-
-#include "dc_ddc_types.h"
-
-struct aux_engine;
-
-struct aux_engine_funcs {
-        void (*destroy)(
-                struct aux_engine **ptr);
-        bool (*acquire_engine)(
-                struct aux_engine *engine);
-        void (*configure)(
-                struct aux_engine *engine,
-                union aux_config cfg);
-        void (*submit_channel_request)(
-                struct aux_engine *engine,
-                struct aux_request_transaction_data *request);
-        void (*process_channel_reply)(
-                struct aux_engine *engine,
-                struct aux_reply_transaction_data *reply);
-        int (*read_channel_reply)(
-                struct aux_engine *engine,
-                uint32_t size,
-                uint8_t *buffer,
-                uint8_t *reply_result,
-                uint32_t *sw_status);
-        enum aux_channel_operation_result (*get_channel_status)(
-                struct aux_engine *engine,
-                uint8_t *returned_bytes);
-        bool (*is_engine_available) (
-                struct aux_engine *engine);
-};
-
-struct aux_engine {
-        struct engine base;
-        const struct aux_engine_funcs *funcs;
-        /* following values are expressed in milliseconds */
-        uint32_t delay;
-        uint32_t max_defer_write_retry;
-
-        bool acquire_reset;
-};
-
-void dal_aux_engine_construct(
-        struct aux_engine *engine,
-        struct dc_context *ctx);
-
-void dal_aux_engine_destruct(
-        struct aux_engine *engine);
-bool dal_aux_engine_submit_request(
-        struct engine *ptr,
-        struct i2caux_transaction_request *request,
-        bool middle_of_transaction);
-bool dal_aux_engine_acquire(
-        struct engine *ptr,
-        struct ddc *ddc);
-enum i2caux_engine_type dal_aux_engine_get_engine_type(
-        const struct engine *engine);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
deleted file mode 100644
index 8b704ab0471c..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2c_hw_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dce/dce_10_0_d.h"
-#include "dce/dce_10_0_sh_mask.h"
-
-/* set register offset */
-#define SR(reg_name)\
-        .reg_name = mm ## reg_name
-
-/* set register offset with instance */
-#define SRI(reg_name, block, id)\
-        .reg_name = mm ## block ## id ## _ ## reg_name
-
-#define aux_regs(id)\
-[id] = {\
-        AUX_COMMON_REG_LIST(id), \
-        .AUX_RESET_MASK = 0 \
-}
-
-#define hw_engine_regs(id)\
-{\
-                I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_aux_registers dce100_aux_regs[] = {
-                aux_regs(0),
-                aux_regs(1),
-                aux_regs(2),
-                aux_regs(3),
-                aux_regs(4),
-                aux_regs(5),
-};
-
-static const struct dce110_i2c_hw_engine_registers dce100_hw_engine_regs[] = {
-                hw_engine_regs(1),
-                hw_engine_regs(2),
-                hw_engine_regs(3),
-                hw_engine_regs(4),
-                hw_engine_regs(5),
-                hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-                I2C_COMMON_MASK_SH_LIST_DCE100(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-                I2C_COMMON_MASK_SH_LIST_DCE100(_MASK)
-};
-
-struct i2caux *dal_i2caux_dce100_create(
-        struct dc_context *ctx)
-{
-        struct i2caux_dce110 *i2caux_dce110 =
-                kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
-        if (!i2caux_dce110) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        dal_i2caux_dce110_construct(i2caux_dce110,
-                                    ctx,
-                                    ARRAY_SIZE(dce100_aux_regs),
-                                    dce100_aux_regs,
-                                    dce100_hw_engine_regs,
-                                    &i2c_shift,
-                                    &i2c_mask);
-        return &i2caux_dce110->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.h
deleted file mode 100644
index 2b508d3e0ef4..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCE100_H__
-#define __DAL_I2C_AUX_DCE100_H__
-
-struct i2caux *dal_i2caux_dce100_create(
-        struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DCE100_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
deleted file mode 100644
index 59c3ed43d609..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dm_event_log.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../aux_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "aux_engine_dce110.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-#include "dce/dce_11_0_sh_mask.h"
-
-#define CTX \
-        aux110->base.base.ctx
-#define REG(reg_name)\
-        (aux110->regs->reg_name)
-#include "reg_helper.h"
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct aux_engine *'
- * to 'struct aux_engine_dce110 *'
- */
-#define FROM_AUX_ENGINE(ptr) \
-        container_of((ptr), struct aux_engine_dce110, base)
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct aux_engine_dce110 *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_AUX_ENGINE(container_of((ptr), struct aux_engine, base))
-
-static void release_engine(
-        struct engine *engine)
-{
-        struct aux_engine_dce110 *aux110 = FROM_ENGINE(engine);
-
-        REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
-}
-
-static void destruct(
-        struct aux_engine_dce110 *engine);
-
-static void destroy(
-        struct aux_engine **aux_engine)
-{
-        struct aux_engine_dce110 *engine = FROM_AUX_ENGINE(*aux_engine);
-
-        destruct(engine);
-
-        kfree(engine);
-
-        *aux_engine = NULL;
-}
-
-#define SW_CAN_ACCESS_AUX 1
-#define DMCU_CAN_ACCESS_AUX 2
-
-static bool is_engine_available(
-        struct aux_engine *engine)
-{
-        struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-
-        uint32_t value = REG_READ(AUX_ARB_CONTROL);
-        uint32_t field = get_reg_field_value(
-                        value,
-                        AUX_ARB_CONTROL,
-                        AUX_REG_RW_CNTL_STATUS);
-
-        return (field != DMCU_CAN_ACCESS_AUX);
-}
-static bool acquire_engine(
-        struct aux_engine *engine)
-{
-        struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-
-        uint32_t value = REG_READ(AUX_ARB_CONTROL);
-        uint32_t field = get_reg_field_value(
-                        value,
-                        AUX_ARB_CONTROL,
-                        AUX_REG_RW_CNTL_STATUS);
-        if (field == DMCU_CAN_ACCESS_AUX)
-         return false;
-        /* enable AUX before request SW to access AUX */
-        value = REG_READ(AUX_CONTROL);
-        field = get_reg_field_value(value,
-                                AUX_CONTROL,
-                                AUX_EN);
-
-        if (field == 0) {
-                set_reg_field_value(
-                                value,
-                                1,
-                                AUX_CONTROL,
-                                AUX_EN);
-
-                if (REG(AUX_RESET_MASK)) {
-                        /*DP_AUX block as part of the enable sequence*/
-                        set_reg_field_value(
-                                value,
-                                1,
-                                AUX_CONTROL,
-                                AUX_RESET);
-                }
-
-                REG_WRITE(AUX_CONTROL, value);
-
-                if (REG(AUX_RESET_MASK)) {
-                        /*poll HW to make sure reset it done*/
-
-                        REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
-                                        1, 11);
-
-                        set_reg_field_value(
-                                value,
-                                0,
-                                AUX_CONTROL,
-                                AUX_RESET);
-
-                        REG_WRITE(AUX_CONTROL, value);
-
-                        REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
-                                        1, 11);
-                }
-        } /*if (field)*/
-
-        /* request SW to access AUX */
-        REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);
-
-        value = REG_READ(AUX_ARB_CONTROL);
-        field = get_reg_field_value(
-                        value,
-                        AUX_ARB_CONTROL,
-                        AUX_REG_RW_CNTL_STATUS);
-
-        return (field == SW_CAN_ACCESS_AUX);
-}
-
-#define COMPOSE_AUX_SW_DATA_16_20(command, address) \
-        ((command) | ((0xF0000 & (address)) >> 16))
-
-#define COMPOSE_AUX_SW_DATA_8_15(address) \
-        ((0xFF00 & (address)) >> 8)
-
-#define COMPOSE_AUX_SW_DATA_0_7(address) \
-        (0xFF & (address))
-
-static void submit_channel_request(
-        struct aux_engine *engine,
-        struct aux_request_transaction_data *request)
-{
-        struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-        uint32_t value;
-        uint32_t length;
-
-        bool is_write =
-                ((request->type == AUX_TRANSACTION_TYPE_DP) &&
-                 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
-                ((request->type == AUX_TRANSACTION_TYPE_I2C) &&
-                ((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-                 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
-        if (REG(AUXN_IMPCAL)) {
-                /* clear_aux_error */
-                REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
-                                1,
-                                0);
-
-                REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
-                                1,
-                                0);
-
-                /* force_default_calibrate */
-                REG_UPDATE_1BY1_2(AUXN_IMPCAL,
-                                AUXN_IMPCAL_ENABLE, 1,
-                                AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
-
-                /* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
-
-                REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
-                                1,
-                                0);
-        }
-        /* set the delay and the number of bytes to write */
-
-        /* The length include
-         * the 4 bit header and the 20 bit address
-         * (that is 3 byte).
-         * If the requested length is non zero this means
-         * an addition byte specifying the length is required. */
-
-        length = request->length ? 4 : 3;
-        if (is_write)
-                length += request->length;
-
-        REG_UPDATE_2(AUX_SW_CONTROL,
-                        AUX_SW_START_DELAY, request->delay,
-                        AUX_SW_WR_BYTES, length);
-
-        /* program action and address and payload data (if 'is_write') */
-        value = REG_UPDATE_4(AUX_SW_DATA,
-                        AUX_SW_INDEX, 0,
-                        AUX_SW_DATA_RW, 0,
-                        AUX_SW_AUTOINCREMENT_DISABLE, 1,
-                        AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));
-
-        value = REG_SET_2(AUX_SW_DATA, value,
-                        AUX_SW_AUTOINCREMENT_DISABLE, 0,
-                        AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));
-
-        value = REG_SET(AUX_SW_DATA, value,
-                        AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));
-
-        if (request->length) {
-                value = REG_SET(AUX_SW_DATA, value,
-                                AUX_SW_DATA, request->length - 1);
-        }
-
-        if (is_write) {
-                /* Load the HW buffer with the Data to be sent.
-                 * This is relevant for write operation.
-                 * For read, the data recived data will be
-                 * processed in process_channel_reply(). */
-                uint32_t i = 0;
-
-                while (i < request->length) {
-                        value = REG_SET(AUX_SW_DATA, value,
-                                        AUX_SW_DATA, request->data[i]);
-
-                        ++i;
-                }
-        }
-
-        REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
-        REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
-                                10, aux110->timeout_period/10);
-        REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
-        EVENT_LOG_AUX_REQ(engine->base.ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
-                                        request->action, request->address, request->length, request->data);
-}
-
-static int read_channel_reply(struct aux_engine *engine, uint32_t size,
-                              uint8_t *buffer, uint8_t *reply_result,
-                              uint32_t *sw_status)
-{
-        struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-        uint32_t bytes_replied;
-        uint32_t reply_result_32;
-
-        *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,
-                             &bytes_replied);
-
-        /* In case HPD is LOW, exit AUX transaction */
-        if ((*sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-                return -1;
-
-        /* Need at least the status byte */
-        if (!bytes_replied)
-                return -1;
-
-        REG_UPDATE_1BY1_3(AUX_SW_DATA,
-                          AUX_SW_INDEX, 0,
-                          AUX_SW_AUTOINCREMENT_DISABLE, 1,
-                          AUX_SW_DATA_RW, 1);
-
-        REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
-        reply_result_32 = reply_result_32 >> 4;
-        *reply_result = (uint8_t)reply_result_32;
-
-        if (reply_result_32 == 0) { /* ACK */
-                uint32_t i = 0;
-
-                /* First byte was already used to get the command status */
-                --bytes_replied;
-
-                /* Do not overflow buffer */
-                if (bytes_replied > size)
-                        return -1;
-
-                while (i < bytes_replied) {
-                        uint32_t aux_sw_data_val;
-
-                        REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
-                        buffer[i] = aux_sw_data_val;
-                        ++i;
-                }
-
-                return i;
-        }
-
-        return 0;
-}
-
-static void process_channel_reply(
-        struct aux_engine *engine,
-        struct aux_reply_transaction_data *reply)
-{
-        int bytes_replied;
-        uint8_t reply_result;
-        uint32_t sw_status;
-
-        bytes_replied = read_channel_reply(engine, reply->length, reply->data,
-                                                &reply_result, &sw_status);
-        EVENT_LOG_AUX_REP(engine->base.ddc->pin_data->en,
-                                        EVENT_LOG_AUX_ORIGIN_NATIVE, reply_result,
-                                        bytes_replied, reply->data);
-
-        /* in case HPD is LOW, exit AUX transaction */
-        if ((sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
-                reply->status = AUX_TRANSACTION_REPLY_HPD_DISCON;
-                return;
-        }
-
-        if (bytes_replied < 0) {
-                /* Need to handle an error case...
-                 * Hopefully, upper layer function won't call this function if
-                 * the number of bytes in the reply was 0, because there was
-                 * surely an error that was asserted that should have been
-                 * handled for hot plug case, this could happens
-                 */
-                if (!(sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
-                        reply->status = AUX_TRANSACTION_REPLY_INVALID;
-                        ASSERT_CRITICAL(false);
-                        return;
-                }
-        } else {
-
-                switch (reply_result) {
-                case 0: /* ACK */
-                        reply->status = AUX_TRANSACTION_REPLY_AUX_ACK;
-                break;
-                case 1: /* NACK */
-                        reply->status = AUX_TRANSACTION_REPLY_AUX_NACK;
-                break;
-                case 2: /* DEFER */
-                        reply->status = AUX_TRANSACTION_REPLY_AUX_DEFER;
-                break;
-                case 4: /* AUX ACK / I2C NACK */
-                        reply->status = AUX_TRANSACTION_REPLY_I2C_NACK;
-                break;
-                case 8: /* AUX ACK / I2C DEFER */
-                        reply->status = AUX_TRANSACTION_REPLY_I2C_DEFER;
-                break;
-                default:
-                        reply->status = AUX_TRANSACTION_REPLY_INVALID;
-                }
-        }
-}
-
-static enum aux_channel_operation_result get_channel_status(
-        struct aux_engine *engine,
-        uint8_t *returned_bytes)
-{
-        struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
-
-        uint32_t value;
-
-        if (returned_bytes == NULL) {
-                /*caller pass NULL pointer*/
-                ASSERT_CRITICAL(false);
-                return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN;
-        }
-        *returned_bytes = 0;
-
-        /* poll to make sure that SW_DONE is asserted */
-        value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
-                                10, aux110->timeout_period/10);
-
-        /* in case HPD is LOW, exit AUX transaction */
-        if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
-                return AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
-
-        /* Note that the following bits are set in 'status.bits'
-         * during CTS 4.2.1.2 (FW 3.3.1):
-         * AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
-         * AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
-         *
-         * AUX_SW_RX_MIN_COUNT_VIOL is an internal,
-         * HW debugging bit and should be ignored. */
-        if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) {
-                if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) ||
-                        (value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK))
-                        return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-
-                else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) ||
-                        (value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) ||
-                        (value &
-                                AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) ||
-                        (value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
-                        return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-
-                *returned_bytes = get_reg_field_value(value,
-                                AUX_SW_STATUS,
-                                AUX_SW_REPLY_BYTE_COUNT);
-
-                if (*returned_bytes == 0)
-                        return
-                        AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
-                else {
-                        *returned_bytes -= 1;
-                        return AUX_CHANNEL_OPERATION_SUCCEEDED;
-                }
-        } else {
-                /*time_elapsed >= aux_engine->timeout_period
-                 *  AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point
-                 */
-                ASSERT_CRITICAL(false);
-                return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
-        }
-}
-
-static const struct aux_engine_funcs aux_engine_funcs = {
-        .destroy = destroy,
-        .acquire_engine = acquire_engine,
-        .submit_channel_request = submit_channel_request,
-        .process_channel_reply = process_channel_reply,
-        .read_channel_reply = read_channel_reply,
-        .get_channel_status = get_channel_status,
-        .is_engine_available = is_engine_available,
-};
-
-static const struct engine_funcs engine_funcs = {
-        .release_engine = release_engine,
-        .submit_request = dal_aux_engine_submit_request,
-        .get_engine_type = dal_aux_engine_get_engine_type,
-        .acquire = dal_aux_engine_acquire,
-};
-
-static void construct(
-        struct aux_engine_dce110 *engine,
-        const struct aux_engine_dce110_init_data *aux_init_data)
-{
-        dal_aux_engine_construct(&engine->base, aux_init_data->ctx);
-        engine->base.base.funcs = &engine_funcs;
-        engine->base.funcs = &aux_engine_funcs;
-
-        engine->timeout_period = aux_init_data->timeout_period;
-        engine->regs = aux_init_data->regs;
-}
-
-static void destruct(
-        struct aux_engine_dce110 *engine)
-{
-        dal_aux_engine_destruct(&engine->base);
-}
-
-struct aux_engine *dal_aux_engine_dce110_create(
-        const struct aux_engine_dce110_init_data *aux_init_data)
-{
-        struct aux_engine_dce110 *engine;
-
-        if (!aux_init_data) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        engine = kzalloc(sizeof(*engine), GFP_KERNEL);
-
-        if (!engine) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        construct(engine, aux_init_data);
-        return &engine->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
deleted file mode 100644
index 85ee82162590..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_AUX_ENGINE_DCE110_H__
-#define __DAL_AUX_ENGINE_DCE110_H__
-
-#include "../aux_engine.h"
-
-#define AUX_COMMON_REG_LIST(id)\
-        SRI(AUX_CONTROL, DP_AUX, id), \
-        SRI(AUX_ARB_CONTROL, DP_AUX, id), \
-        SRI(AUX_SW_DATA, DP_AUX, id), \
-        SRI(AUX_SW_CONTROL, DP_AUX, id), \
-        SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
-        SRI(AUX_SW_STATUS, DP_AUX, id), \
-        SR(AUXN_IMPCAL), \
-        SR(AUXP_IMPCAL)
-
-struct dce110_aux_registers {
-        uint32_t AUX_CONTROL;
-        uint32_t AUX_ARB_CONTROL;
-        uint32_t AUX_SW_DATA;
-        uint32_t AUX_SW_CONTROL;
-        uint32_t AUX_INTERRUPT_CONTROL;
-        uint32_t AUX_SW_STATUS;
-        uint32_t AUXN_IMPCAL;
-        uint32_t AUXP_IMPCAL;
-
-        uint32_t AUX_RESET_MASK;
-};
-
-struct aux_engine_dce110 {
-        struct aux_engine base;
-        const struct dce110_aux_registers *regs;
-        struct {
-                uint32_t aux_control;
-                uint32_t aux_arb_control;
-                uint32_t aux_sw_data;
-                uint32_t aux_sw_control;
-                uint32_t aux_interrupt_control;
-                uint32_t aux_sw_status;
-        } addr;
-        uint32_t timeout_period;
-};
-
-struct aux_engine_dce110_init_data {
-        uint32_t engine_id;
-        uint32_t timeout_period;
-        struct dc_context *ctx;
-        const struct dce110_aux_registers *regs;
-};
-
-struct aux_engine *dal_aux_engine_dce110_create(
-        const struct aux_engine_dce110_init_data *aux_init_data);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
deleted file mode 100644
index 9cbe1a7a6bcb..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
+++ /dev/null
@@ -1,574 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/logger_interface.h"
-/*
- * Pre-requisites: headers required by header of this unit
- */
-
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_hw_engine.h"
-#include "../i2c_generic_hw_engine.h"
-/*
- * Header of this unit
- */
-
-#include "i2c_hw_engine_dce110.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-#include "reg_helper.h"
-
-/*
- * This unit
- */
-#define DC_LOGGER \
-                hw_engine->base.base.base.ctx->logger
-
-enum dc_i2c_status {
-        DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
-        DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
-        DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
-};
-
-enum dc_i2c_arbitration {
-        DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-        DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
-};
-
-
-
-/*
- * @brief
- * Cast pointer to 'struct i2c_hw_engine *'
- * to pointer 'struct i2c_hw_engine_dce110 *'
- */
-#define FROM_I2C_HW_ENGINE(ptr) \
-        container_of((ptr), struct i2c_hw_engine_dce110, base)
-/*
- * @brief
- * Cast pointer to 'struct i2c_engine *'
- * to pointer to 'struct i2c_hw_engine_dce110 *'
- */
-#define FROM_I2C_ENGINE(ptr) \
-        FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-
-/*
- * @brief
- * Cast pointer to 'struct engine *'
- * to 'pointer to struct i2c_hw_engine_dce110 *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-#define CTX \
-                hw_engine->base.base.base.ctx
-
-#define REG(reg_name)\
-        (hw_engine->regs->reg_name)
-
-#undef FN
-#define FN(reg_name, field_name) \
-        hw_engine->i2c_shift->field_name, hw_engine->i2c_mask->field_name
-
-#include "reg_helper.h"
-
-static void disable_i2c_hw_engine(
-        struct i2c_hw_engine_dce110 *hw_engine)
-{
-        REG_UPDATE_N(SETUP, 1, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 0);
-}
-
-static void release_engine(
-        struct engine *engine)
-{
-        struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-
-        struct i2c_engine *base = NULL;
-        bool safe_to_reset;
-
-        base = &hw_engine->base.base;
-
-        /* Restore original HW engine speed */
-
-        base->funcs->set_speed(base, hw_engine->base.original_speed);
-
-        /* Release I2C */
-        REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1);
-
-        /* Reset HW engine */
-        {
-                uint32_t i2c_sw_status = 0;
-                REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-                /* if used by SW, safe to reset */
-                safe_to_reset = (i2c_sw_status == 1);
-        }
-
-        if (safe_to_reset)
-                REG_UPDATE_2(
-                        DC_I2C_CONTROL,
-                        DC_I2C_SOFT_RESET, 1,
-                        DC_I2C_SW_STATUS_RESET, 1);
-        else
-                REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
-
-        /* HW I2c engine - clock gating feature */
-        if (!hw_engine->engine_keep_power_up_count)
-                disable_i2c_hw_engine(hw_engine);
-}
-
-static bool setup_engine(
-        struct i2c_engine *i2c_engine)
-{
-        struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-        uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
-        uint32_t  reset_length = 0;
-
-        if (hw_engine->base.base.setup_limit != 0)
-                i2c_setup_limit = hw_engine->base.base.setup_limit;
-
-        /* Program pin select */
-        REG_UPDATE_6(
-                        DC_I2C_CONTROL,
-                        DC_I2C_GO, 0,
-                        DC_I2C_SOFT_RESET, 0,
-                        DC_I2C_SEND_RESET, 0,
-                        DC_I2C_SW_STATUS_RESET, 1,
-                        DC_I2C_TRANSACTION_COUNT, 0,
-                        DC_I2C_DDC_SELECT, hw_engine->engine_id);
-
-        /* Program time limit */
-        if (hw_engine->base.base.send_reset_length == 0) {
-                /*pre-dcn*/
-                REG_UPDATE_N(
-                                SETUP, 2,
-                                FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
-                                FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
-        } else {
-                reset_length = hw_engine->base.base.send_reset_length;
-        }
-        /* Program HW priority
-         * set to High - interrupt software I2C at any time
-         * Enable restart of SW I2C that was interrupted by HW
-         * disable queuing of software while I2C is in use by HW */
-        REG_UPDATE_2(
-                        DC_I2C_ARBITRATION,
-                        DC_I2C_NO_QUEUED_SW_GO, 0,
-                        DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL);
-
-        return true;
-}
-
-static uint32_t get_speed(
-        const struct i2c_engine *i2c_engine)
-{
-        const struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-        uint32_t pre_scale = 0;
-
-        REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale);
-
-        /* [anaumov] it seems following is unnecessary */
-        /*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-        return pre_scale ?
-                hw_engine->reference_frequency / pre_scale :
-                hw_engine->base.default_speed;
-}
-
-static void set_speed(
-        struct i2c_engine *i2c_engine,
-        uint32_t speed)
-{
-        struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-
-        if (speed) {
-                if (hw_engine->i2c_mask->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
-                        REG_UPDATE_N(
-                                SPEED, 3,
-                                FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), hw_engine->reference_frequency / speed,
-                                FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2,
-                                FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
-                else
-                        REG_UPDATE_N(
-                                SPEED, 2,
-                                FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), hw_engine->reference_frequency / speed,
-                                FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
-        }
-}
-
-static inline void reset_hw_engine(struct engine *engine)
-{
-        struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-
-        REG_UPDATE_2(
-                        DC_I2C_CONTROL,
-                        DC_I2C_SW_STATUS_RESET, 1,
-                        DC_I2C_SW_STATUS_RESET, 1);
-}
-
-static bool is_hw_busy(struct engine *engine)
-{
-        struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
-        uint32_t i2c_sw_status = 0;
-
-        REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-        if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
-                return false;
-
-        reset_hw_engine(engine);
-
-        REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-        return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-}
-
-
-#define STOP_TRANS_PREDICAT \
-                ((hw_engine->transaction_count == 3) || \
-                                (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||     \
-                                (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ))
-
-#define SET_I2C_TRANSACTION(id) \
-                do {    \
-                        REG_UPDATE_N(DC_I2C_TRANSACTION##id, 5, \
-                                FN(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0), 1,       \
-                                FN(DC_I2C_TRANSACTION0, DC_I2C_START0), 1,      \
-                                FN(DC_I2C_TRANSACTION0, DC_I2C_STOP0), STOP_TRANS_PREDICAT ? 1:0,       \
-                                FN(DC_I2C_TRANSACTION0, DC_I2C_RW0), (0 != (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)),     \
-                                FN(DC_I2C_TRANSACTION0, DC_I2C_COUNT0), length);        \
-                                if (STOP_TRANS_PREDICAT)        \
-                                        last_transaction = true;        \
-                } while (false)
-
-
-static bool process_transaction(
-        struct i2c_hw_engine_dce110 *hw_engine,
-        struct i2c_request_transaction_data *request)
-{
-        uint32_t length = request->length;
-        uint8_t *buffer = request->data;
-        uint32_t value = 0;
-
-        bool last_transaction = false;
-
-        struct dc_context *ctx = NULL;
-
-        ctx = hw_engine->base.base.base.ctx;
-
-
-
-        switch (hw_engine->transaction_count) {
-        case 0:
-                SET_I2C_TRANSACTION(0);
-                break;
-        case 1:
-                SET_I2C_TRANSACTION(1);
-                break;
-        case 2:
-                SET_I2C_TRANSACTION(2);
-                break;
-        case 3:
-                SET_I2C_TRANSACTION(3);
-                break;
-        default:
-                /* TODO Warning ? */
-                break;
-        }
-
-
-        /* Write the I2C address and I2C data
-         * into the hardware circular buffer, one byte per entry.
-         * As an example, the 7-bit I2C slave address for CRT monitor
-         * for reading DDC/EDID information is 0b1010001.
-         * For an I2C send operation, the LSB must be programmed to 0;
-         * for I2C receive operation, the LSB must be programmed to 1. */
-        if (hw_engine->transaction_count == 0) {
-                value = REG_SET_4(DC_I2C_DATA, 0,
-                                  DC_I2C_DATA_RW, false,
-                                  DC_I2C_DATA, request->address,
-                                  DC_I2C_INDEX, 0,
-                                  DC_I2C_INDEX_WRITE, 1);
-                hw_engine->buffer_used_write = 0;
-        } else
-                value = REG_SET_2(DC_I2C_DATA, 0,
-                                  DC_I2C_DATA_RW, false,
-                                  DC_I2C_DATA, request->address);
-
-        hw_engine->buffer_used_write++;
-
-        if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-                while (length) {
-                        REG_SET_2(DC_I2C_DATA, value,
-                                        DC_I2C_INDEX_WRITE, 0,
-                                        DC_I2C_DATA, *buffer++);
-                        hw_engine->buffer_used_write++;
-                        --length;
-                }
-        }
-
-        ++hw_engine->transaction_count;
-        hw_engine->buffer_used_bytes += length + 1;
-
-        return last_transaction;
-}
-
-static void execute_transaction(
-        struct i2c_hw_engine_dce110 *hw_engine)
-{
-        REG_UPDATE_N(SETUP, 5,
-                FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0,
-                FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0,
-                FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0,
-                FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0,
-                FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0);
-
-
-        REG_UPDATE_5(DC_I2C_CONTROL,
-                DC_I2C_SOFT_RESET, 0,
-                DC_I2C_SW_STATUS_RESET, 0,
-                DC_I2C_SEND_RESET, 0,
-                DC_I2C_GO, 0,
-                DC_I2C_TRANSACTION_COUNT, hw_engine->transaction_count - 1);
-
-        /* start I2C transfer */
-        REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
-
-        /* all transactions were executed and HW buffer became empty
-         * (even though it actually happens when status becomes DONE) */
-        hw_engine->transaction_count = 0;
-        hw_engine->buffer_used_bytes = 0;
-}
-
-static void submit_channel_request(
-        struct i2c_engine *engine,
-        struct i2c_request_transaction_data *request)
-{
-        request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
-
-        if (!process_transaction(FROM_I2C_ENGINE(engine), request))
-                return;
-
-        if (is_hw_busy(&engine->base)) {
-                request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-                return;
-        }
-
-        execute_transaction(FROM_I2C_ENGINE(engine));
-}
-
-static void process_channel_reply(
-        struct i2c_engine *engine,
-        struct i2c_reply_transaction_data *reply)
-{
-        uint32_t length = reply->length;
-        uint8_t *buffer = reply->data;
-
-        struct i2c_hw_engine_dce110 *hw_engine =
-                FROM_I2C_ENGINE(engine);
-
-
-        REG_SET_3(DC_I2C_DATA, 0,
-                        DC_I2C_INDEX, hw_engine->buffer_used_write,
-                        DC_I2C_DATA_RW, 1,
-                        DC_I2C_INDEX_WRITE, 1);
-
-        while (length) {
-                /* after reading the status,
-                 * if the I2C operation executed successfully
-                 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
-                 * should read data bytes from I2C circular data buffer */
-
-                uint32_t i2c_data;
-
-                REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
-                *buffer++ = i2c_data;
-
-                --length;
-        }
-}
-
-static enum i2c_channel_operation_result get_channel_status(
-        struct i2c_engine *i2c_engine,
-        uint8_t *returned_bytes)
-{
-        uint32_t i2c_sw_status = 0;
-        struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine);
-        uint32_t value =
-                        REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-
-        if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
-                return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-        else if (value & hw_engine->i2c_mask->DC_I2C_SW_STOPPED_ON_NACK)
-                return I2C_CHANNEL_OPERATION_NO_RESPONSE;
-        else if (value & hw_engine->i2c_mask->DC_I2C_SW_TIMEOUT)
-                return I2C_CHANNEL_OPERATION_TIMEOUT;
-        else if (value & hw_engine->i2c_mask->DC_I2C_SW_ABORTED)
-                return I2C_CHANNEL_OPERATION_FAILED;
-        else if (value & hw_engine->i2c_mask->DC_I2C_SW_DONE)
-                return I2C_CHANNEL_OPERATION_SUCCEEDED;
-
-        /*
-         * this is the case when HW used for communication, I2C_SW_STATUS
-         * could be zero
-         */
-        return I2C_CHANNEL_OPERATION_SUCCEEDED;
-}
-
-static uint32_t get_hw_buffer_available_size(
-        const struct i2c_hw_engine *engine)
-{
-        return I2C_HW_BUFFER_SIZE -
-                FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
-}
-
-static uint32_t get_transaction_timeout(
-        const struct i2c_hw_engine *engine,
-        uint32_t length)
-{
-        uint32_t speed = engine->base.funcs->get_speed(&engine->base);
-
-        uint32_t period_timeout;
-        uint32_t num_of_clock_stretches;
-
-        if (!speed)
-                return 0;
-
-        period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
-
-        num_of_clock_stretches = 1 + (length << 3) + 1;
-        num_of_clock_stretches +=
-                (FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
-                (FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
-
-        return period_timeout * num_of_clock_stretches;
-}
-
-static void destroy(
-        struct i2c_engine **i2c_engine)
-{
-        struct i2c_hw_engine_dce110 *engine_dce110 =
-                        FROM_I2C_ENGINE(*i2c_engine);
-
-        dal_i2c_hw_engine_destruct(&engine_dce110->base);
-
-        kfree(engine_dce110);
-
-        *i2c_engine = NULL;
-}
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
-        .destroy = destroy,
-        .get_speed = get_speed,
-        .set_speed = set_speed,
-        .setup_engine = setup_engine,
-        .submit_channel_request = submit_channel_request,
-        .process_channel_reply = process_channel_reply,
-        .get_channel_status = get_channel_status,
-        .acquire_engine = dal_i2c_hw_engine_acquire_engine,
-};
-
-static const struct engine_funcs engine_funcs = {
-        .release_engine = release_engine,
-        .get_engine_type = dal_i2c_hw_engine_get_engine_type,
-        .acquire = dal_i2c_engine_acquire,
-        .submit_request = dal_i2c_hw_engine_submit_request,
-};
-
-static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
-        .get_hw_buffer_available_size = get_hw_buffer_available_size,
-        .get_transaction_timeout = get_transaction_timeout,
-        .wait_on_operation_result = dal_i2c_hw_engine_wait_on_operation_result,
-};
-
-static void construct(
-        struct i2c_hw_engine_dce110 *hw_engine,
-        const struct i2c_hw_engine_dce110_create_arg *arg)
-{
-        uint32_t xtal_ref_div = 0;
-
-        dal_i2c_hw_engine_construct(&hw_engine->base, arg->ctx);
-
-        hw_engine->base.base.base.funcs = &engine_funcs;
-        hw_engine->base.base.funcs = &i2c_engine_funcs;
-        hw_engine->base.funcs = &i2c_hw_engine_funcs;
-        hw_engine->base.default_speed = arg->default_speed;
-
-        hw_engine->regs = arg->regs;
-        hw_engine->i2c_shift = arg->i2c_shift;
-        hw_engine->i2c_mask = arg->i2c_mask;
-
-        hw_engine->engine_id = arg->engine_id;
-
-        hw_engine->buffer_used_bytes = 0;
-        hw_engine->transaction_count = 0;
-        hw_engine->engine_keep_power_up_count = 1;
-
-
-        REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
-
-        if (xtal_ref_div == 0) {
-                DC_LOG_WARNING("Invalid base timer divider [%s]\n",
-                                __func__);
-                xtal_ref_div = 2;
-        }
-
-        /*Calculating Reference Clock by divding original frequency by
-         * XTAL_REF_DIV.
-         * At upper level, uint32_t reference_frequency =
-         *  dal_i2caux_get_reference_clock(as) >> 1
-         *  which already divided by 2. So we need x2 to get original
-         *  reference clock from ppll_info
-         */
-        hw_engine->reference_frequency =
-                (arg->reference_frequency * 2) / xtal_ref_div;
-}
-
-struct i2c_engine *dal_i2c_hw_engine_dce110_create(
-        const struct i2c_hw_engine_dce110_create_arg *arg)
-{
-        struct i2c_hw_engine_dce110 *engine_dce10;
-
-        if (!arg) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-        if (!arg->reference_frequency) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        engine_dce10 = kzalloc(sizeof(struct i2c_hw_engine_dce110),
-                               GFP_KERNEL);
-
-        if (!engine_dce10) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        construct(engine_dce10, arg);
-        return &engine_dce10->base.base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
deleted file mode 100644
index fea2946906ed..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_HW_ENGINE_DCE110_H__
-#define __DAL_I2C_HW_ENGINE_DCE110_H__
-
-#define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
-        SRI(SETUP, DC_I2C_DDC, id),\
-        SRI(SPEED, DC_I2C_DDC, id),\
-        SR(DC_I2C_ARBITRATION),\
-        SR(DC_I2C_CONTROL),\
-        SR(DC_I2C_SW_STATUS),\
-        SR(DC_I2C_TRANSACTION0),\
-        SR(DC_I2C_TRANSACTION1),\
-        SR(DC_I2C_TRANSACTION2),\
-        SR(DC_I2C_TRANSACTION3),\
-        SR(DC_I2C_DATA),\
-        SR(MICROSECOND_TIME_BASE_DIV)
-
-#define I2C_SF(reg_name, field_name, post_fix)\
-        .field_name = reg_name ## __ ## field_name ## post_fix
-
-#define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\
-        I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
-        I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
-        I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
-        I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\
-        I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\
-        I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\
-        I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\
-        I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\
-        I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\
-        I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\
-        I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\
-        I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\
-        I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\
-        I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\
-        I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\
-        I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\
-        I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\
-        I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\
-        I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\
-        I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\
-        I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\
-        I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\
-        I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\
-        I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\
-        I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh)
-
-#define I2C_COMMON_MASK_SH_LIST_DCE100(mask_sh)\
-        I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)
-
-#define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\
-        I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\
-        I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh)
-
-struct dce110_i2c_hw_engine_shift {
-        uint8_t DC_I2C_DDC1_ENABLE;
-        uint8_t DC_I2C_DDC1_TIME_LIMIT;
-        uint8_t DC_I2C_DDC1_DATA_DRIVE_EN;
-        uint8_t DC_I2C_DDC1_CLK_DRIVE_EN;
-        uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
-        uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
-        uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
-        uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
-        uint8_t DC_I2C_NO_QUEUED_SW_GO;
-        uint8_t DC_I2C_SW_PRIORITY;
-        uint8_t DC_I2C_SOFT_RESET;
-        uint8_t DC_I2C_SW_STATUS_RESET;
-        uint8_t DC_I2C_GO;
-        uint8_t DC_I2C_SEND_RESET;
-        uint8_t DC_I2C_TRANSACTION_COUNT;
-        uint8_t DC_I2C_DDC_SELECT;
-        uint8_t DC_I2C_DDC1_PRESCALE;
-        uint8_t DC_I2C_DDC1_THRESHOLD;
-        uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
-        uint8_t DC_I2C_SW_STOPPED_ON_NACK;
-        uint8_t DC_I2C_SW_TIMEOUT;
-        uint8_t DC_I2C_SW_ABORTED;
-        uint8_t DC_I2C_SW_DONE;
-        uint8_t DC_I2C_SW_STATUS;
-        uint8_t DC_I2C_STOP_ON_NACK0;
-        uint8_t DC_I2C_START0;
-        uint8_t DC_I2C_RW0;
-        uint8_t DC_I2C_STOP0;
-        uint8_t DC_I2C_COUNT0;
-        uint8_t DC_I2C_DATA_RW;
-        uint8_t DC_I2C_DATA;
-        uint8_t DC_I2C_INDEX;
-        uint8_t DC_I2C_INDEX_WRITE;
-        uint8_t XTAL_REF_DIV;
-};
-
-struct dce110_i2c_hw_engine_mask {
-        uint32_t DC_I2C_DDC1_ENABLE;
-        uint32_t DC_I2C_DDC1_TIME_LIMIT;
-        uint32_t DC_I2C_DDC1_DATA_DRIVE_EN;
-        uint32_t DC_I2C_DDC1_CLK_DRIVE_EN;
-        uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
-        uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
-        uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
-        uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
-        uint32_t DC_I2C_NO_QUEUED_SW_GO;
-        uint32_t DC_I2C_SW_PRIORITY;
-        uint32_t DC_I2C_SOFT_RESET;
-        uint32_t DC_I2C_SW_STATUS_RESET;
-        uint32_t DC_I2C_GO;
-        uint32_t DC_I2C_SEND_RESET;
-        uint32_t DC_I2C_TRANSACTION_COUNT;
-        uint32_t DC_I2C_DDC_SELECT;
-        uint32_t DC_I2C_DDC1_PRESCALE;
-        uint32_t DC_I2C_DDC1_THRESHOLD;
-        uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL;
-        uint32_t DC_I2C_SW_STOPPED_ON_NACK;
-        uint32_t DC_I2C_SW_TIMEOUT;
-        uint32_t DC_I2C_SW_ABORTED;
-        uint32_t DC_I2C_SW_DONE;
-        uint32_t DC_I2C_SW_STATUS;
-        uint32_t DC_I2C_STOP_ON_NACK0;
-        uint32_t DC_I2C_START0;
-        uint32_t DC_I2C_RW0;
-        uint32_t DC_I2C_STOP0;
-        uint32_t DC_I2C_COUNT0;
-        uint32_t DC_I2C_DATA_RW;
-        uint32_t DC_I2C_DATA;
-        uint32_t DC_I2C_INDEX;
-        uint32_t DC_I2C_INDEX_WRITE;
-        uint32_t XTAL_REF_DIV;
-};
-
-struct dce110_i2c_hw_engine_registers {
-        uint32_t SETUP;
-        uint32_t SPEED;
-        uint32_t DC_I2C_ARBITRATION;
-        uint32_t DC_I2C_CONTROL;
-        uint32_t DC_I2C_SW_STATUS;
-        uint32_t DC_I2C_TRANSACTION0;
-        uint32_t DC_I2C_TRANSACTION1;
-        uint32_t DC_I2C_TRANSACTION2;
-        uint32_t DC_I2C_TRANSACTION3;
-        uint32_t DC_I2C_DATA;
-        uint32_t MICROSECOND_TIME_BASE_DIV;
-};
-
-struct i2c_hw_engine_dce110 {
-        struct i2c_hw_engine base;
-        const struct dce110_i2c_hw_engine_registers *regs;
-        const struct dce110_i2c_hw_engine_shift *i2c_shift;
-        const struct dce110_i2c_hw_engine_mask *i2c_mask;
-        struct {
-                uint32_t DC_I2C_DDCX_SETUP;
-                uint32_t DC_I2C_DDCX_SPEED;
-        } addr;
-        uint32_t engine_id;
-        /* expressed in kilohertz */
-        uint32_t reference_frequency;
-        /* number of bytes currently used in HW buffer */
-        uint32_t buffer_used_bytes;
-        /* number of bytes used for write transaction in HW buffer
-         * - this will be used as the index to read from*/
-        uint32_t buffer_used_write;
-        /* number of pending transactions (before GO) */
-        uint32_t transaction_count;
-        uint32_t engine_keep_power_up_count;
-        uint32_t i2_setup_time_limit;
-};
-
-struct i2c_hw_engine_dce110_create_arg {
-        uint32_t engine_id;
-        uint32_t reference_frequency;
-        uint32_t default_speed;
-        struct dc_context *ctx;
-        const struct dce110_i2c_hw_engine_registers *regs;
-        const struct dce110_i2c_hw_engine_shift *i2c_shift;
-        const struct dce110_i2c_hw_engine_mask *i2c_mask;
-};
-
-struct i2c_engine *dal_i2c_hw_engine_dce110_create(
-        const struct i2c_hw_engine_dce110_create_arg *arg);
-
-enum {
-        I2C_SETUP_TIME_LIMIT_DCE = 255,
-        I2C_SETUP_TIME_LIMIT_DCN = 3,
-        I2C_HW_BUFFER_SIZE = 538,
-        I2C_SEND_RESET_LENGTH_9 = 9,
-        I2C_SEND_RESET_LENGTH_10 = 10,
-};
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
deleted file mode 100644
index 3aa7f791e523..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_sw_engine_dce110.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct i2c_sw_engine *'
- * to 'struct i2c_sw_engine_dce110 *'
- */
-#define FROM_I2C_SW_ENGINE(ptr) \
-        container_of((ptr), struct i2c_sw_engine_dce110, base)
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_sw_engine_dce80 *'
- */
-#define FROM_I2C_ENGINE(ptr) \
-        FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_sw_engine_dce80 *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-static void release_engine(
-        struct engine *engine)
-{
-}
-
-static void destruct(
-        struct i2c_sw_engine_dce110 *engine)
-{
-        dal_i2c_sw_engine_destruct(&engine->base);
-}
-
-static void destroy(
-        struct i2c_engine **engine)
-{
-        struct i2c_sw_engine_dce110 *sw_engine = FROM_I2C_ENGINE(*engine);
-
-        destruct(sw_engine);
-
-        kfree(sw_engine);
-
-        *engine = NULL;
-}
-
-static bool acquire_engine(
-        struct i2c_engine *engine,
-        struct ddc *ddc_handle)
-{
-        return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
-}
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
-        .acquire_engine = acquire_engine,
-        .destroy = destroy,
-        .get_speed = dal_i2c_sw_engine_get_speed,
-        .set_speed = dal_i2c_sw_engine_set_speed,
-        .setup_engine = dal_i2c_engine_setup_i2c_engine,
-        .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-        .process_channel_reply = dal_i2c_engine_process_channel_reply,
-        .get_channel_status = dal_i2c_sw_engine_get_channel_status,
-};
-
-static const struct engine_funcs engine_funcs = {
-        .release_engine = release_engine,
-        .get_engine_type = dal_i2c_sw_engine_get_engine_type,
-        .acquire = dal_i2c_engine_acquire,
-        .submit_request = dal_i2c_sw_engine_submit_request,
-};
-
-static void construct(
-        struct i2c_sw_engine_dce110 *engine_dce110,
-        const struct i2c_sw_engine_dce110_create_arg *arg_dce110)
-{
-        struct i2c_sw_engine_create_arg arg_base;
-
-        arg_base.ctx = arg_dce110->ctx;
-        arg_base.default_speed = arg_dce110->default_speed;
-
-        dal_i2c_sw_engine_construct(&engine_dce110->base, &arg_base);
-
-        /*struct engine   struct engine_funcs*/
-        engine_dce110->base.base.base.funcs = &engine_funcs;
-        /*struct i2c_engine  struct i2c_engine_funcs*/
-        engine_dce110->base.base.funcs = &i2c_engine_funcs;
-        engine_dce110->base.default_speed = arg_dce110->default_speed;
-        engine_dce110->engine_id = arg_dce110->engine_id;
-}
-
-struct i2c_engine *dal_i2c_sw_engine_dce110_create(
-        const struct i2c_sw_engine_dce110_create_arg *arg)
-{
-        struct i2c_sw_engine_dce110 *engine_dce110;
-
-        if (!arg) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        engine_dce110 = kzalloc(sizeof(struct i2c_sw_engine_dce110),
-                                GFP_KERNEL);
-
-        if (!engine_dce110) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        construct(engine_dce110, arg);
-        return &engine_dce110->base.base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
deleted file mode 100644
index 1d748ac1d6d6..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-/*
- * Header of this unit
- */
-#include "i2caux_dce110.h"
-
-#include "i2c_sw_engine_dce110.h"
-#include "i2c_hw_engine_dce110.h"
-#include "aux_engine_dce110.h"
-#include "../../dc.h"
-#include "dc_types.h"
-
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-/*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
-#define FROM_I2C_AUX(ptr) \
-        container_of((ptr), struct i2caux_dce110, base)
-
-static void destruct(
-        struct i2caux_dce110 *i2caux_dce110)
-{
-        dal_i2caux_destruct(&i2caux_dce110->base);
-}
-
-static void destroy(
-        struct i2caux **i2c_engine)
-{
-        struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
-
-        destruct(i2caux_dce110);
-
-        kfree(i2caux_dce110);
-
-        *i2c_engine = NULL;
-}
-
-static struct i2c_engine *acquire_i2c_hw_engine(
-        struct i2caux *i2caux,
-        struct ddc *ddc)
-{
-        struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-
-        struct i2c_engine *engine = NULL;
-        /* generic hw engine is not used for EDID read
-         * It may be needed for external i2c device, like thermal chip,
-         * TODO will be implemented when needed.
-         * check dce80 bool non_generic for generic hw engine;
-         */
-
-        if (!ddc)
-                return NULL;
-
-        if (ddc->hw_info.hw_supported) {
-                enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-
-                if (line < GPIO_DDC_LINE_COUNT)
-                        engine = i2caux->i2c_hw_engines[line];
-        }
-
-        if (!engine)
-                return NULL;
-
-        if (!i2caux_dce110->i2c_hw_buffer_in_use &&
-                engine->base.funcs->acquire(&engine->base, ddc)) {
-                i2caux_dce110->i2c_hw_buffer_in_use = true;
-                return engine;
-        }
-
-        return NULL;
-}
-
-static void release_engine(
-        struct i2caux *i2caux,
-        struct engine *engine)
-{
-        struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
-
-        if (engine->funcs->get_engine_type(engine) ==
-                I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
-                i2caux_dce110->i2c_hw_buffer_in_use = false;
-
-        dal_i2caux_release_engine(i2caux, engine);
-}
-
-static const enum gpio_ddc_line hw_ddc_lines[] = {
-        GPIO_DDC_LINE_DDC1,
-        GPIO_DDC_LINE_DDC2,
-        GPIO_DDC_LINE_DDC3,
-        GPIO_DDC_LINE_DDC4,
-        GPIO_DDC_LINE_DDC5,
-        GPIO_DDC_LINE_DDC6,
-};
-
-static const enum gpio_ddc_line hw_aux_lines[] = {
-        GPIO_DDC_LINE_DDC1,
-        GPIO_DDC_LINE_DDC2,
-        GPIO_DDC_LINE_DDC3,
-        GPIO_DDC_LINE_DDC4,
-        GPIO_DDC_LINE_DDC5,
-        GPIO_DDC_LINE_DDC6,
-};
-
-/* function table */
-static const struct i2caux_funcs i2caux_funcs = {
-        .destroy = destroy,
-        .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
-        .release_engine = release_engine,
-        .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
-        .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-};
-
-#include "dce/dce_11_0_d.h"
-#include "dce/dce_11_0_sh_mask.h"
-
-/* set register offset */
-#define SR(reg_name)\
-        .reg_name = mm ## reg_name
-
-/* set register offset with instance */
-#define SRI(reg_name, block, id)\
-        .reg_name = mm ## block ## id ## _ ## reg_name
-
-#define aux_regs(id)\
-[id] = {\
-        AUX_COMMON_REG_LIST(id), \
-        .AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
-}
-
-#define hw_engine_regs(id)\
-{\
-                I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_aux_registers dce110_aux_regs[] = {
-                aux_regs(0),
-                aux_regs(1),
-                aux_regs(2),
-                aux_regs(3),
-                aux_regs(4),
-                aux_regs(5)
-};
-
-static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
-                hw_engine_regs(1),
-                hw_engine_regs(2),
-                hw_engine_regs(3),
-                hw_engine_regs(4),
-                hw_engine_regs(5),
-                hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-};
-
-void dal_i2caux_dce110_construct(
-        struct i2caux_dce110 *i2caux_dce110,
-        struct dc_context *ctx,
-        unsigned int num_i2caux_inst,
-        const struct dce110_aux_registers aux_regs[],
-        const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],
-        const struct dce110_i2c_hw_engine_shift *i2c_shift,
-        const struct dce110_i2c_hw_engine_mask *i2c_mask)
-{
-        uint32_t i = 0;
-        uint32_t reference_frequency = 0;
-        bool use_i2c_sw_engine = false;
-        struct i2caux *base = NULL;
-        /*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
-         * does not return 48KHz, we need hard coded for 48Khz.
-         * Some BIOS setting incorrect cause this
-         * For production, we always get value from BIOS*/
-        reference_frequency =
-                dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
-
-        base = &i2caux_dce110->base;
-
-        dal_i2caux_construct(base, ctx);
-
-        i2caux_dce110->base.funcs = &i2caux_funcs;
-        i2caux_dce110->i2c_hw_buffer_in_use = false;
-        /* Create I2C engines (DDC lines per connector)
-         * different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
-         */
-        do {
-                enum gpio_ddc_line line_id = hw_ddc_lines[i];
-
-                struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
-
-                if (use_i2c_sw_engine) {
-                        struct i2c_sw_engine_dce110_create_arg sw_arg;
-
-                        sw_arg.engine_id = i;
-                        sw_arg.default_speed = base->default_i2c_sw_speed;
-                        sw_arg.ctx = ctx;
-                        base->i2c_sw_engines[line_id] =
-                                dal_i2c_sw_engine_dce110_create(&sw_arg);
-                }
-
-                hw_arg_dce110.engine_id = i;
-                hw_arg_dce110.reference_frequency = reference_frequency;
-                hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
-                hw_arg_dce110.ctx = ctx;
-                hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
-                hw_arg_dce110.i2c_shift = i2c_shift;
-                hw_arg_dce110.i2c_mask = i2c_mask;
-
-                base->i2c_hw_engines[line_id] =
-                        dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
-                if (base->i2c_hw_engines[line_id] != NULL) {
-                        switch (ctx->dce_version) {
-                        case DCN_VERSION_1_0:
-                                base->i2c_hw_engines[line_id]->setup_limit =
-                                        I2C_SETUP_TIME_LIMIT_DCN;
-                                base->i2c_hw_engines[line_id]->send_reset_length  = 0;
-                        break;
-                        default:
-                                base->i2c_hw_engines[line_id]->setup_limit =
-                                        I2C_SETUP_TIME_LIMIT_DCE;
-                                base->i2c_hw_engines[line_id]->send_reset_length  = 0;
-                                break;
-                        }
-                }
-                ++i;
-        } while (i < num_i2caux_inst);
-
-        /* Create AUX engines for all lines which has assisted HW AUX
-         * 'i' (loop counter) used as DDC/AUX engine_id */
-
-        i = 0;
-
-        do {
-                enum gpio_ddc_line line_id = hw_aux_lines[i];
-
-                struct aux_engine_dce110_init_data aux_init_data;
-
-                aux_init_data.engine_id = i;
-                aux_init_data.timeout_period = base->aux_timeout_period;
-                aux_init_data.ctx = ctx;
-                aux_init_data.regs = &aux_regs[i];
-
-                base->aux_engines[line_id] =
-                        dal_aux_engine_dce110_create(&aux_init_data);
-
-                ++i;
-        } while (i < num_i2caux_inst);
-
-        /*TODO Generic I2C SW and HW*/
-}
-
-/*
- * dal_i2caux_dce110_create
- *
- * @brief
- * public interface to allocate memory for DCE11 I2CAUX
- *
- * @param
- * struct adapter_service *as - [in]
- * struct dc_context *ctx - [in]
- *
- * @return
- * pointer to the base struct of DCE11 I2CAUX
- */
-struct i2caux *dal_i2caux_dce110_create(
-        struct dc_context *ctx)
-{
-        struct i2caux_dce110 *i2caux_dce110 =
-                kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
-        if (!i2caux_dce110) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        dal_i2caux_dce110_construct(i2caux_dce110,
-                                    ctx,
-                                    ARRAY_SIZE(dce110_aux_regs),
-                                    dce110_aux_regs,
-                                    i2c_hw_engine_regs,
-                                    &i2c_shift,
-                                    &i2c_mask);
-        return &i2caux_dce110->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h
deleted file mode 100644
index d3d8cc58666a..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCE110_H__
-#define __DAL_I2C_AUX_DCE110_H__
-
-#include "../i2caux.h"
-
-struct i2caux_dce110 {
-        struct i2caux base;
-        /* indicate the I2C HW circular buffer is in use */
-        bool i2c_hw_buffer_in_use;
-};
-
-struct dce110_aux_registers;
-struct dce110_i2c_hw_engine_registers;
-struct dce110_i2c_hw_engine_shift;
-struct dce110_i2c_hw_engine_mask;
-
-struct i2caux *dal_i2caux_dce110_create(
-        struct dc_context *ctx);
-
-void dal_i2caux_dce110_construct(
-        struct i2caux_dce110 *i2caux_dce110,
-        struct dc_context *ctx,
-        unsigned int num_i2caux_inst,
-        const struct dce110_aux_registers *aux_regs,
-        const struct dce110_i2c_hw_engine_registers *i2c_hw_engine_regs,
-        const struct dce110_i2c_hw_engine_shift *i2c_shift,
-        const struct dce110_i2c_hw_engine_mask *i2c_mask);
-
-#endif /* __DAL_I2C_AUX_DCE110_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c
deleted file mode 100644
index a9db04738724..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-#include "../dce110/i2caux_dce110.h"
-#include "i2caux_dce112.h"
-
-#include "../dce110/aux_engine_dce110.h"
-
-#include "../dce110/i2c_hw_engine_dce110.h"
-
-#include "dce/dce_11_2_d.h"
-#include "dce/dce_11_2_sh_mask.h"
-
-/* set register offset */
-#define SR(reg_name)\
-        .reg_name = mm ## reg_name
-
-/* set register offset with instance */
-#define SRI(reg_name, block, id)\
-        .reg_name = mm ## block ## id ## _ ## reg_name
-
-#define aux_regs(id)\
-[id] = {\
-        AUX_COMMON_REG_LIST(id), \
-        .AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
-}
-
-#define hw_engine_regs(id)\
-{\
-                I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_aux_registers dce112_aux_regs[] = {
-                aux_regs(0),
-                aux_regs(1),
-                aux_regs(2),
-                aux_regs(3),
-                aux_regs(4),
-                aux_regs(5),
-};
-
-static const struct dce110_i2c_hw_engine_registers dce112_hw_engine_regs[] = {
-                hw_engine_regs(1),
-                hw_engine_regs(2),
-                hw_engine_regs(3),
-                hw_engine_regs(4),
-                hw_engine_regs(5),
-                hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-};
-
-static void construct(
-        struct i2caux_dce110 *i2caux_dce110,
-        struct dc_context *ctx)
-{
-        dal_i2caux_dce110_construct(i2caux_dce110,
-                                    ctx,
-                                    ARRAY_SIZE(dce112_aux_regs),
-                                    dce112_aux_regs,
-                                    dce112_hw_engine_regs,
-                                    &i2c_shift,
-                                    &i2c_mask);
-}
-
-/*
- * dal_i2caux_dce110_create
- *
- * @brief
- * public interface to allocate memory for DCE11 I2CAUX
- *
- * @param
- * struct adapter_service *as - [in]
- * struct dc_context *ctx - [in]
- *
- * @return
- * pointer to the base struct of DCE11 I2CAUX
- */
-struct i2caux *dal_i2caux_dce112_create(
-        struct dc_context *ctx)
-{
-        struct i2caux_dce110 *i2caux_dce110 =
-                kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
-        if (!i2caux_dce110) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        construct(i2caux_dce110, ctx);
-        return &i2caux_dce110->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.h
deleted file mode 100644
index 8d35453c25b6..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCE112_H__
-#define __DAL_I2C_AUX_DCE112_H__
-
-struct i2caux *dal_i2caux_dce112_create(
-        struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DCE112_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
deleted file mode 100644
index 6a4f344c1db4..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-#include "../dce110/i2c_hw_engine_dce110.h"
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dce/dce_12_0_offset.h"
-#include "dce/dce_12_0_sh_mask.h"
-#include "soc15_hw_ip.h"
-#include "vega10_ip_offset.h"
-
-/* begin *********************
- * macros to expend register list macro defined in HW object header file */
-
-#define BASE_INNER(seg) \
-        DCE_BASE__INST0_SEG ## seg
-
-/* compile time expand base address. */
-#define BASE(seg) \
-        BASE_INNER(seg)
-
-#define SR(reg_name)\
-                .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-                                        mm ## reg_name
-
-#define SRI(reg_name, block, id)\
-        .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-                                        mm ## block ## id ## _ ## reg_name
-/* macros to expend register list macro defined in HW object header file
- * end *********************/
-
-#define aux_regs(id)\
-[id] = {\
-        AUX_COMMON_REG_LIST(id), \
-        .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
-}
-
-static const struct dce110_aux_registers dce120_aux_regs[] = {
-                aux_regs(0),
-                aux_regs(1),
-                aux_regs(2),
-                aux_regs(3),
-                aux_regs(4),
-                aux_regs(5),
-};
-
-#define hw_engine_regs(id)\
-{\
-                I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_i2c_hw_engine_registers dce120_hw_engine_regs[] = {
-                hw_engine_regs(1),
-                hw_engine_regs(2),
-                hw_engine_regs(3),
-                hw_engine_regs(4),
-                hw_engine_regs(5),
-                hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-};
-
-struct i2caux *dal_i2caux_dce120_create(
-        struct dc_context *ctx)
-{
-        struct i2caux_dce110 *i2caux_dce110 =
-                kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
-        if (!i2caux_dce110) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        dal_i2caux_dce110_construct(i2caux_dce110,
-                                    ctx,
-                                    ARRAY_SIZE(dce120_aux_regs),
-                                    dce120_aux_regs,
-                                    dce120_hw_engine_regs,
-                                    &i2c_shift,
-                                    &i2c_mask);
-        return &i2caux_dce110->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
deleted file mode 100644
index fd0832dd2c75..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
+++ /dev/null
@@ -1,875 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_hw_engine.h"
-#include "../i2c_generic_hw_engine.h"
-/*
- * Header of this unit
- */
-
-#include "i2c_hw_engine_dce80.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-/*
- * This unit
- */
-
-enum dc_i2c_status {
-        DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
-        DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
-        DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
-};
-
-enum dc_i2c_arbitration {
-        DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-        DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
-};
-
-enum {
-        /* No timeout in HW
-         * (timeout implemented in SW by querying status) */
-        I2C_SETUP_TIME_LIMIT = 255,
-        I2C_HW_BUFFER_SIZE = 144
-};
-
-/*
- * @brief
- * Cast 'struct i2c_hw_engine *'
- * to 'struct i2c_hw_engine_dce80 *'
- */
-#define FROM_I2C_HW_ENGINE(ptr) \
-        container_of((ptr), struct i2c_hw_engine_dce80, base)
-
-/*
- * @brief
- * Cast pointer to 'struct i2c_engine *'
- * to pointer to 'struct i2c_hw_engine_dce80 *'
- */
-#define FROM_I2C_ENGINE(ptr) \
-        FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-
-/*
- * @brief
- * Cast pointer to 'struct engine *'
- * to 'pointer to struct i2c_hw_engine_dce80 *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-static void disable_i2c_hw_engine(
-        struct i2c_hw_engine_dce80 *engine)
-{
-        const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-        uint32_t value = 0;
-
-        struct dc_context *ctx = NULL;
-
-        ctx = engine->base.base.base.ctx;
-
-        value = dm_read_reg(ctx, addr);
-
-        set_reg_field_value(
-                value,
-                0,
-                DC_I2C_DDC1_SETUP,
-                DC_I2C_DDC1_ENABLE);
-
-        dm_write_reg(ctx, addr, value);
-}
-
-static void release_engine(
-        struct engine *engine)
-{
-        struct i2c_hw_engine_dce80 *hw_engine = FROM_ENGINE(engine);
-
-        struct i2c_engine *base = NULL;
-        bool safe_to_reset;
-        uint32_t value = 0;
-
-        base = &hw_engine->base.base;
-
-        /* Restore original HW engine speed */
-
-        base->funcs->set_speed(base, hw_engine->base.original_speed);
-
-        /* Release I2C */
-        {
-                value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
-
-                set_reg_field_value(
-                                value,
-                                1,
-                                DC_I2C_ARBITRATION,
-                                DC_I2C_SW_DONE_USING_I2C_REG);
-
-                dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
-        }
-
-        /* Reset HW engine */
-        {
-                uint32_t i2c_sw_status = 0;
-
-                value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-
-                i2c_sw_status = get_reg_field_value(
-                                value,
-                                DC_I2C_SW_STATUS,
-                                DC_I2C_SW_STATUS);
-                /* if used by SW, safe to reset */
-                safe_to_reset = (i2c_sw_status == 1);
-        }
-        {
-                value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-
-                if (safe_to_reset)
-                        set_reg_field_value(
-                                value,
-                                1,
-                                DC_I2C_CONTROL,
-                                DC_I2C_SOFT_RESET);
-
-                set_reg_field_value(
-                        value,
-                        1,
-                        DC_I2C_CONTROL,
-                        DC_I2C_SW_STATUS_RESET);
-
-                dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-        }
-
-        /* HW I2c engine - clock gating feature */
-        if (!hw_engine->engine_keep_power_up_count)
-                disable_i2c_hw_engine(hw_engine);
-}
-
-static void destruct(
-        struct i2c_hw_engine_dce80 *engine)
-{
-        dal_i2c_hw_engine_destruct(&engine->base);
-}
-
-static void destroy(
-        struct i2c_engine **i2c_engine)
-{
-        struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(*i2c_engine);
-
-        destruct(engine);
-
-        kfree(engine);
-
-        *i2c_engine = NULL;
-}
-
-static bool setup_engine(
-        struct i2c_engine *i2c_engine)
-{
-        uint32_t value = 0;
-        struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-
-        /* Program pin select */
-        {
-                const uint32_t addr = mmDC_I2C_CONTROL;
-
-                value = dm_read_reg(i2c_engine->base.ctx, addr);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_GO);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_SOFT_RESET);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_SEND_RESET);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_SW_STATUS_RESET);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_TRANSACTION_COUNT);
-
-                set_reg_field_value(
-                        value,
-                        engine->engine_id,
-                        DC_I2C_CONTROL,
-                        DC_I2C_DDC_SELECT);
-
-                dm_write_reg(i2c_engine->base.ctx, addr, value);
-        }
-
-        /* Program time limit */
-        {
-                const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-
-                value = dm_read_reg(i2c_engine->base.ctx, addr);
-
-                set_reg_field_value(
-                        value,
-                        I2C_SETUP_TIME_LIMIT,
-                        DC_I2C_DDC1_SETUP,
-                        DC_I2C_DDC1_TIME_LIMIT);
-
-                set_reg_field_value(
-                        value,
-                        1,
-                        DC_I2C_DDC1_SETUP,
-                        DC_I2C_DDC1_ENABLE);
-
-                dm_write_reg(i2c_engine->base.ctx, addr, value);
-        }
-
-        /* Program HW priority
-         * set to High - interrupt software I2C at any time
-         * Enable restart of SW I2C that was interrupted by HW
-         * disable queuing of software while I2C is in use by HW */
-        {
-                value = dm_read_reg(i2c_engine->base.ctx,
-                                mmDC_I2C_ARBITRATION);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_ARBITRATION,
-                        DC_I2C_NO_QUEUED_SW_GO);
-
-                set_reg_field_value(
-                        value,
-                        DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
-                        DC_I2C_ARBITRATION,
-                        DC_I2C_SW_PRIORITY);
-
-                dm_write_reg(i2c_engine->base.ctx,
-                                mmDC_I2C_ARBITRATION, value);
-        }
-
-        return true;
-}
-
-static uint32_t get_speed(
-        const struct i2c_engine *i2c_engine)
-{
-        const struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-
-        const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-
-        uint32_t pre_scale = 0;
-
-        uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-
-        pre_scale = get_reg_field_value(
-                        value,
-                        DC_I2C_DDC1_SPEED,
-                        DC_I2C_DDC1_PRESCALE);
-
-        /* [anaumov] it seems following is unnecessary */
-        /*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
-
-        return pre_scale ?
-                engine->reference_frequency / pre_scale :
-                engine->base.default_speed;
-}
-
-static void set_speed(
-        struct i2c_engine *i2c_engine,
-        uint32_t speed)
-{
-        struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
-
-        if (speed) {
-                const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
-
-                uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
-
-                set_reg_field_value(
-                        value,
-                        engine->reference_frequency / speed,
-                        DC_I2C_DDC1_SPEED,
-                        DC_I2C_DDC1_PRESCALE);
-
-                set_reg_field_value(
-                        value,
-                        2,
-                        DC_I2C_DDC1_SPEED,
-                        DC_I2C_DDC1_THRESHOLD);
-
-                dm_write_reg(i2c_engine->base.ctx, addr, value);
-        }
-}
-
-static inline void reset_hw_engine(struct engine *engine)
-{
-        uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
-
-        set_reg_field_value(
-                value,
-                1,
-                DC_I2C_CONTROL,
-                DC_I2C_SOFT_RESET);
-
-        set_reg_field_value(
-                value,
-                1,
-                DC_I2C_CONTROL,
-                DC_I2C_SW_STATUS_RESET);
-
-        dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
-}
-
-static bool is_hw_busy(struct engine *engine)
-{
-        uint32_t i2c_sw_status = 0;
-
-        uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-
-        i2c_sw_status = get_reg_field_value(
-                        value,
-                        DC_I2C_SW_STATUS,
-                        DC_I2C_SW_STATUS);
-
-        if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
-                return false;
-
-        reset_hw_engine(engine);
-
-        value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
-
-        i2c_sw_status = get_reg_field_value(
-                        value,
-                        DC_I2C_SW_STATUS,
-                        DC_I2C_SW_STATUS);
-
-        return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-}
-
-/*
- * @brief
- * DC_GPIO_DDC MM register offsets
- */
-static const uint32_t transaction_addr[] = {
-        mmDC_I2C_TRANSACTION0,
-        mmDC_I2C_TRANSACTION1,
-        mmDC_I2C_TRANSACTION2,
-        mmDC_I2C_TRANSACTION3
-};
-
-static bool process_transaction(
-        struct i2c_hw_engine_dce80 *engine,
-        struct i2c_request_transaction_data *request)
-{
-        uint32_t length = request->length;
-        uint8_t *buffer = request->data;
-
-        bool last_transaction = false;
-        uint32_t value = 0;
-
-        struct dc_context *ctx = NULL;
-
-        ctx = engine->base.base.base.ctx;
-
-        {
-                const uint32_t addr =
-                        transaction_addr[engine->transaction_count];
-
-                value = dm_read_reg(ctx, addr);
-
-                set_reg_field_value(
-                        value,
-                        1,
-                        DC_I2C_TRANSACTION0,
-                        DC_I2C_STOP_ON_NACK0);
-
-                set_reg_field_value(
-                        value,
-                        1,
-                        DC_I2C_TRANSACTION0,
-                        DC_I2C_START0);
-
-                if ((engine->transaction_count == 3) ||
-                (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-                (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-
-                        set_reg_field_value(
-                                value,
-                                1,
-                                DC_I2C_TRANSACTION0,
-                                DC_I2C_STOP0);
-
-                        last_transaction = true;
-                } else
-                        set_reg_field_value(
-                                value,
-                                0,
-                                DC_I2C_TRANSACTION0,
-                                DC_I2C_STOP0);
-
-                set_reg_field_value(
-                        value,
-                        (0 != (request->action &
-                                        I2CAUX_TRANSACTION_ACTION_I2C_READ)),
-                        DC_I2C_TRANSACTION0,
-                        DC_I2C_RW0);
-
-                set_reg_field_value(
-                        value,
-                        length,
-                        DC_I2C_TRANSACTION0,
-                        DC_I2C_COUNT0);
-
-                dm_write_reg(ctx, addr, value);
-        }
-
-        /* Write the I2C address and I2C data
-         * into the hardware circular buffer, one byte per entry.
-         * As an example, the 7-bit I2C slave address for CRT monitor
-         * for reading DDC/EDID information is 0b1010001.
-         * For an I2C send operation, the LSB must be programmed to 0;
-         * for I2C receive operation, the LSB must be programmed to 1. */
-
-        {
-                value = 0;
-
-                set_reg_field_value(
-                        value,
-                        false,
-                        DC_I2C_DATA,
-                        DC_I2C_DATA_RW);
-
-                set_reg_field_value(
-                        value,
-                        request->address,
-                        DC_I2C_DATA,
-                        DC_I2C_DATA);
-
-                if (engine->transaction_count == 0) {
-                        set_reg_field_value(
-                                value,
-                                0,
-                                DC_I2C_DATA,
-                                DC_I2C_INDEX);
-
-                        /*enable index write*/
-                        set_reg_field_value(
-                                value,
-                                1,
-                                DC_I2C_DATA,
-                                DC_I2C_INDEX_WRITE);
-                }
-
-                dm_write_reg(ctx, mmDC_I2C_DATA, value);
-
-                if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
-
-                        set_reg_field_value(
-                                value,
-                                0,
-                                DC_I2C_DATA,
-                                DC_I2C_INDEX_WRITE);
-
-                        while (length) {
-
-                                set_reg_field_value(
-                                        value,
-                                        *buffer++,
-                                        DC_I2C_DATA,
-                                        DC_I2C_DATA);
-
-                                dm_write_reg(ctx, mmDC_I2C_DATA, value);
-                                --length;
-                        }
-                }
-        }
-
-        ++engine->transaction_count;
-        engine->buffer_used_bytes += length + 1;
-
-        return last_transaction;
-}
-
-static void execute_transaction(
-        struct i2c_hw_engine_dce80 *engine)
-{
-        uint32_t value = 0;
-        struct dc_context *ctx = NULL;
-
-        ctx = engine->base.base.base.ctx;
-
-        {
-                const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
-
-                value = dm_read_reg(ctx, addr);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_DDC1_SETUP,
-                        DC_I2C_DDC1_DATA_DRIVE_EN);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_DDC1_SETUP,
-                        DC_I2C_DDC1_CLK_DRIVE_EN);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_DDC1_SETUP,
-                        DC_I2C_DDC1_DATA_DRIVE_SEL);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_DDC1_SETUP,
-                        DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_DDC1_SETUP,
-                        DC_I2C_DDC1_INTRA_BYTE_DELAY);
-
-                dm_write_reg(ctx, addr, value);
-        }
-
-        {
-                const uint32_t addr = mmDC_I2C_CONTROL;
-
-                value = dm_read_reg(ctx, addr);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_SOFT_RESET);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_SW_STATUS_RESET);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_SEND_RESET);
-
-                set_reg_field_value(
-                        value,
-                        0,
-                        DC_I2C_CONTROL,
-                        DC_I2C_GO);
-
-                set_reg_field_value(
-                        value,
-                        engine->transaction_count - 1,
-                        DC_I2C_CONTROL,
-                        DC_I2C_TRANSACTION_COUNT);
-
-                dm_write_reg(ctx, addr, value);
-        }
-
-        /* start I2C transfer */
-        {
-                const uint32_t addr = mmDC_I2C_CONTROL;
-
-                value   = dm_read_reg(ctx, addr);
-
-                set_reg_field_value(
-                        value,
-                        1,
-                        DC_I2C_CONTROL,
-                        DC_I2C_GO);
-
-                dm_write_reg(ctx, addr, value);
-        }
-
-        /* all transactions were executed and HW buffer became empty
-         * (even though it actually happens when status becomes DONE) */
-        engine->transaction_count = 0;
-        engine->buffer_used_bytes = 0;
-}
-
-static void submit_channel_request(
-        struct i2c_engine *engine,
-        struct i2c_request_transaction_data *request)
-{
-        request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
-
-        if (!process_transaction(FROM_I2C_ENGINE(engine), request))
-                return;
-
-        if (is_hw_busy(&engine->base)) {
-                request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-                return;
-        }
-
-        execute_transaction(FROM_I2C_ENGINE(engine));
-}
-
-static void process_channel_reply(
-        struct i2c_engine *engine,
-        struct i2c_reply_transaction_data *reply)
-{
-        uint32_t length = reply->length;
-        uint8_t *buffer = reply->data;
-
-        uint32_t value = 0;
-
-        /*set index*/
-        set_reg_field_value(
-                value,
-                length - 1,
-                DC_I2C_DATA,
-                DC_I2C_INDEX);
-
-        set_reg_field_value(
-                value,
-                1,
-                DC_I2C_DATA,
-                DC_I2C_DATA_RW);
-
-        set_reg_field_value(
-                value,
-                1,
-                DC_I2C_DATA,
-                DC_I2C_INDEX_WRITE);
-
-        dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
-
-        while (length) {
-                /* after reading the status,
-                 * if the I2C operation executed successfully
-                 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
-                 * should read data bytes from I2C circular data buffer */
-
-                value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
-
-                *buffer++ = get_reg_field_value(
-                                value,
-                                DC_I2C_DATA,
-                                DC_I2C_DATA);
-
-                --length;
-        }
-}
-
-static enum i2c_channel_operation_result get_channel_status(
-        struct i2c_engine *engine,
-        uint8_t *returned_bytes)
-{
-        uint32_t i2c_sw_status = 0;
-        uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
-
-        i2c_sw_status = get_reg_field_value(
-                        value,
-                        DC_I2C_SW_STATUS,
-                        DC_I2C_SW_STATUS);
-
-        if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
-                return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
-        else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
-                return I2C_CHANNEL_OPERATION_NO_RESPONSE;
-        else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
-                return I2C_CHANNEL_OPERATION_TIMEOUT;
-        else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
-                return I2C_CHANNEL_OPERATION_FAILED;
-        else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
-                return I2C_CHANNEL_OPERATION_SUCCEEDED;
-
-        /*
-         * this is the case when HW used for communication, I2C_SW_STATUS
-         * could be zero
-         */
-        return I2C_CHANNEL_OPERATION_SUCCEEDED;
-}
-
-static uint32_t get_hw_buffer_available_size(
-        const struct i2c_hw_engine *engine)
-{
-        return I2C_HW_BUFFER_SIZE -
-                FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
-}
-
-static uint32_t get_transaction_timeout(
-        const struct i2c_hw_engine *engine,
-        uint32_t length)
-{
-        uint32_t speed = engine->base.funcs->get_speed(&engine->base);
-
-        uint32_t period_timeout;
-        uint32_t num_of_clock_stretches;
-
-        if (!speed)
-                return 0;
-
-        period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
-
-        num_of_clock_stretches = 1 + (length << 3) + 1;
-        num_of_clock_stretches +=
-                (FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
-                (FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
-
-        return period_timeout * num_of_clock_stretches;
-}
-
-/*
- * @brief
- * DC_I2C_DDC1_SETUP MM register offsets
- *
- * @note
- * The indices of this offset array are DDC engine IDs
- */
-static const int32_t ddc_setup_offset[] = {
-
-        mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
-        mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
-        mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
-        mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
-        mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
-        mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
-        mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
-};
-
-/*
- * @brief
- * DC_I2C_DDC1_SPEED MM register offsets
- *
- * @note
- * The indices of this offset array are DDC engine IDs
- */
-static const int32_t ddc_speed_offset[] = {
-        mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
-        mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
-        mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
-        mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
-        mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
-        mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
-        mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
-};
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
-        .destroy = destroy,
-        .get_speed = get_speed,
-        .set_speed = set_speed,
-        .setup_engine = setup_engine,
-        .submit_channel_request = submit_channel_request,
-        .process_channel_reply = process_channel_reply,
-        .get_channel_status = get_channel_status,
-        .acquire_engine = dal_i2c_hw_engine_acquire_engine,
-};
-
-static const struct engine_funcs engine_funcs = {
-        .release_engine = release_engine,
-        .get_engine_type = dal_i2c_hw_engine_get_engine_type,
-        .acquire = dal_i2c_engine_acquire,
-        .submit_request = dal_i2c_hw_engine_submit_request,
-};
-
-static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
-        .get_hw_buffer_available_size =
-                get_hw_buffer_available_size,
-        .get_transaction_timeout =
-                get_transaction_timeout,
-        .wait_on_operation_result =
-                dal_i2c_hw_engine_wait_on_operation_result,
-};
-
-static void construct(
-        struct i2c_hw_engine_dce80 *engine,
-        const struct i2c_hw_engine_dce80_create_arg *arg)
-{
-        dal_i2c_hw_engine_construct(&engine->base, arg->ctx);
-
-        engine->base.base.base.funcs = &engine_funcs;
-        engine->base.base.funcs = &i2c_engine_funcs;
-        engine->base.funcs = &i2c_hw_engine_funcs;
-        engine->base.default_speed = arg->default_speed;
-        engine->addr.DC_I2C_DDCX_SETUP =
-                mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
-        engine->addr.DC_I2C_DDCX_SPEED =
-                mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
-
-        engine->engine_id = arg->engine_id;
-        engine->reference_frequency = arg->reference_frequency;
-        engine->buffer_used_bytes = 0;
-        engine->transaction_count = 0;
-        engine->engine_keep_power_up_count = 1;
-}
-
-struct i2c_engine *dal_i2c_hw_engine_dce80_create(
-        const struct i2c_hw_engine_dce80_create_arg *arg)
-{
-        struct i2c_hw_engine_dce80 *engine;
-
-        if (!arg) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        if ((arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t)) ||
-            (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t)) ||
-            !arg->reference_frequency) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL);
-
-        if (!engine) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        construct(engine, arg);
-        return &engine->base.base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.h b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.h
deleted file mode 100644
index 5c6116fb5479..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_HW_ENGINE_DCE80_H__
-#define __DAL_I2C_HW_ENGINE_DCE80_H__
-
-struct i2c_hw_engine_dce80 {
-        struct i2c_hw_engine base;
-        struct {
-                uint32_t DC_I2C_DDCX_SETUP;
-                uint32_t DC_I2C_DDCX_SPEED;
-        } addr;
-        uint32_t engine_id;
-        /* expressed in kilohertz */
-        uint32_t reference_frequency;
-        /* number of bytes currently used in HW buffer */
-        uint32_t buffer_used_bytes;
-        /* number of pending transactions (before GO) */
-        uint32_t transaction_count;
-        uint32_t engine_keep_power_up_count;
-};
-
-struct i2c_hw_engine_dce80_create_arg {
-        uint32_t engine_id;
-        uint32_t reference_frequency;
-        uint32_t default_speed;
-        struct dc_context *ctx;
-};
-
-struct i2c_engine *dal_i2c_hw_engine_dce80_create(
-        const struct i2c_hw_engine_dce80_create_arg *arg);
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
deleted file mode 100644
index 4853ee26096a..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_sw_engine_dce80.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-/*
- * This unit
- */
-
-static const uint32_t ddc_hw_status_addr[] = {
-        mmDC_I2C_DDC1_HW_STATUS,
-        mmDC_I2C_DDC2_HW_STATUS,
-        mmDC_I2C_DDC3_HW_STATUS,
-        mmDC_I2C_DDC4_HW_STATUS,
-        mmDC_I2C_DDC5_HW_STATUS,
-        mmDC_I2C_DDC6_HW_STATUS,
-        mmDC_I2C_DDCVGA_HW_STATUS
-};
-
-/*
- * @brief
- * Cast 'struct i2c_sw_engine *'
- * to 'struct i2c_sw_engine_dce80 *'
- */
-#define FROM_I2C_SW_ENGINE(ptr) \
-        container_of((ptr), struct i2c_sw_engine_dce80, base)
-
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_sw_engine_dce80 *'
- */
-#define FROM_I2C_ENGINE(ptr) \
-        FROM_I2C_SW_ENGINE(container_of((ptr), struct i2c_sw_engine, base))
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_sw_engine_dce80 *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-static void release_engine(
-        struct engine *engine)
-{
-
-}
-
-static void destruct(
-        struct i2c_sw_engine_dce80 *engine)
-{
-        dal_i2c_sw_engine_destruct(&engine->base);
-}
-
-static void destroy(
-        struct i2c_engine **engine)
-{
-        struct i2c_sw_engine_dce80 *sw_engine = FROM_I2C_ENGINE(*engine);
-
-        destruct(sw_engine);
-
-        kfree(sw_engine);
-
-        *engine = NULL;
-}
-
-static bool acquire_engine(
-        struct i2c_engine *engine,
-        struct ddc *ddc_handle)
-{
-        return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
-}
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
-        .acquire_engine = acquire_engine,
-        .destroy = destroy,
-        .get_speed = dal_i2c_sw_engine_get_speed,
-        .set_speed = dal_i2c_sw_engine_set_speed,
-        .setup_engine = dal_i2c_engine_setup_i2c_engine,
-        .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-        .process_channel_reply = dal_i2c_engine_process_channel_reply,
-        .get_channel_status = dal_i2c_sw_engine_get_channel_status,
-};
-
-static const struct engine_funcs engine_funcs = {
-        .release_engine = release_engine,
-        .get_engine_type = dal_i2c_sw_engine_get_engine_type,
-        .acquire = dal_i2c_engine_acquire,
-        .submit_request = dal_i2c_sw_engine_submit_request,
-};
-
-static void construct(
-        struct i2c_sw_engine_dce80 *engine,
-        const struct i2c_sw_engine_dce80_create_arg *arg)
-{
-        struct i2c_sw_engine_create_arg arg_base;
-
-        arg_base.ctx = arg->ctx;
-        arg_base.default_speed = arg->default_speed;
-
-        dal_i2c_sw_engine_construct(&engine->base, &arg_base);
-
-        engine->base.base.base.funcs = &engine_funcs;
-        engine->base.base.funcs = &i2c_engine_funcs;
-        engine->base.default_speed = arg->default_speed;
-        engine->engine_id = arg->engine_id;
-}
-
-struct i2c_engine *dal_i2c_sw_engine_dce80_create(
-        const struct i2c_sw_engine_dce80_create_arg *arg)
-{
-        struct i2c_sw_engine_dce80 *engine;
-
-        if (!arg) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        engine = kzalloc(sizeof(struct i2c_sw_engine_dce80), GFP_KERNEL);
-
-        if (!engine) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        construct(engine, arg);
-        return &engine->base.base;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
deleted file mode 100644
index ed48596dd2a5..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2caux_dce80.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "i2c_sw_engine_dce80.h"
-#include "../i2c_hw_engine.h"
-#include "i2c_hw_engine_dce80.h"
-#include "../i2c_generic_hw_engine.h"
-#include "../aux_engine.h"
-
-
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dce/dce_8_0_d.h"
-#include "dce/dce_8_0_sh_mask.h"
-
-
-/* set register offset */
-#define SR(reg_name)\
-        .reg_name = mm ## reg_name
-
-/* set register offset with instance */
-#define SRI(reg_name, block, id)\
-        .reg_name = mm ## block ## id ## _ ## reg_name
-
-#define aux_regs(id)\
-[id] = {\
-        AUX_COMMON_REG_LIST(id), \
-        .AUX_RESET_MASK = 0 \
-}
-
-static const struct dce110_aux_registers dce80_aux_regs[] = {
-                aux_regs(0),
-                aux_regs(1),
-                aux_regs(2),
-                aux_regs(3),
-                aux_regs(4),
-                aux_regs(5)
-};
-
-/*
- * This unit
- */
-
-#define FROM_I2C_AUX(ptr) \
-        container_of((ptr), struct i2caux_dce80, base)
-
-static void destruct(
-        struct i2caux_dce80 *i2caux_dce80)
-{
-        dal_i2caux_destruct(&i2caux_dce80->base);
-}
-
-static void destroy(
-        struct i2caux **i2c_engine)
-{
-        struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(*i2c_engine);
-
-        destruct(i2caux_dce80);
-
-        kfree(i2caux_dce80);
-
-        *i2c_engine = NULL;
-}
-
-static struct i2c_engine *acquire_i2c_hw_engine(
-        struct i2caux *i2caux,
-        struct ddc *ddc)
-{
-        struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(i2caux);
-
-        struct i2c_engine *engine = NULL;
-        bool non_generic;
-
-        if (!ddc)
-                return NULL;
-
-        if (ddc->hw_info.hw_supported) {
-                enum gpio_ddc_line line = dal_ddc_get_line(ddc);
-
-                if (line < GPIO_DDC_LINE_COUNT) {
-                        non_generic = true;
-                        engine = i2caux->i2c_hw_engines[line];
-                }
-        }
-
-        if (!engine) {
-                non_generic = false;
-                engine = i2caux->i2c_generic_hw_engine;
-        }
-
-        if (!engine)
-                return NULL;
-
-        if (non_generic) {
-                if (!i2caux_dce80->i2c_hw_buffer_in_use &&
-                        engine->base.funcs->acquire(&engine->base, ddc)) {
-                        i2caux_dce80->i2c_hw_buffer_in_use = true;
-                        return engine;
-                }
-        } else {
-                if (engine->base.funcs->acquire(&engine->base, ddc))
-                        return engine;
-        }
-
-        return NULL;
-}
-
-static void release_engine(
-        struct i2caux *i2caux,
-        struct engine *engine)
-{
-        if (engine->funcs->get_engine_type(engine) ==
-                I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
-                FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
-
-        dal_i2caux_release_engine(i2caux, engine);
-}
-
-static const enum gpio_ddc_line hw_ddc_lines[] = {
-        GPIO_DDC_LINE_DDC1,
-        GPIO_DDC_LINE_DDC2,
-        GPIO_DDC_LINE_DDC3,
-        GPIO_DDC_LINE_DDC4,
-        GPIO_DDC_LINE_DDC5,
-        GPIO_DDC_LINE_DDC6,
-        GPIO_DDC_LINE_DDC_VGA
-};
-
-static const enum gpio_ddc_line hw_aux_lines[] = {
-        GPIO_DDC_LINE_DDC1,
-        GPIO_DDC_LINE_DDC2,
-        GPIO_DDC_LINE_DDC3,
-        GPIO_DDC_LINE_DDC4,
-        GPIO_DDC_LINE_DDC5,
-        GPIO_DDC_LINE_DDC6
-};
-
-static const struct i2caux_funcs i2caux_funcs = {
-        .destroy = destroy,
-        .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
-        .release_engine = release_engine,
-        .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
-        .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
-};
-
-static void construct(
-        struct i2caux_dce80 *i2caux_dce80,
-        struct dc_context *ctx)
-{
-        /* Entire family have I2C engine reference clock frequency
-         * changed from XTALIN (27) to XTALIN/2 (13.5) */
-
-        struct i2caux *base = &i2caux_dce80->base;
-
-        uint32_t reference_frequency =
-                dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
-
-        /*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
-                FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
-
-        /* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
-        bool use_i2c_sw_engine = true;
-
-        uint32_t i;
-
-        dal_i2caux_construct(base, ctx);
-
-        i2caux_dce80->base.funcs = &i2caux_funcs;
-        i2caux_dce80->i2c_hw_buffer_in_use = false;
-
-        /* Create I2C HW engines (HW + SW pairs)
-         * for all lines which has assisted HW DDC
-         * 'i' (loop counter) used as DDC/AUX engine_id */
-
-        i = 0;
-
-        do {
-                enum gpio_ddc_line line_id = hw_ddc_lines[i];
-
-                struct i2c_hw_engine_dce80_create_arg hw_arg;
-
-                if (use_i2c_sw_engine) {
-                        struct i2c_sw_engine_dce80_create_arg sw_arg;
-
-                        sw_arg.engine_id = i;
-                        sw_arg.default_speed = base->default_i2c_sw_speed;
-                        sw_arg.ctx = ctx;
-                        base->i2c_sw_engines[line_id] =
-                                dal_i2c_sw_engine_dce80_create(&sw_arg);
-                }
-
-                hw_arg.engine_id = i;
-                hw_arg.reference_frequency = reference_frequency;
-                hw_arg.default_speed = base->default_i2c_hw_speed;
-                hw_arg.ctx = ctx;
-
-                base->i2c_hw_engines[line_id] =
-                        dal_i2c_hw_engine_dce80_create(&hw_arg);
-
-                ++i;
-        } while (i < ARRAY_SIZE(hw_ddc_lines));
-
-        /* Create AUX engines for all lines which has assisted HW AUX
-         * 'i' (loop counter) used as DDC/AUX engine_id */
-
-        i = 0;
-
-        do {
-                enum gpio_ddc_line line_id = hw_aux_lines[i];
-
-                struct aux_engine_dce110_init_data arg;
-
-                arg.engine_id = i;
-                arg.timeout_period = base->aux_timeout_period;
-                arg.ctx = ctx;
-                arg.regs = &dce80_aux_regs[i];
-
-                base->aux_engines[line_id] =
-                        dal_aux_engine_dce110_create(&arg);
-
-                ++i;
-        } while (i < ARRAY_SIZE(hw_aux_lines));
-
-        /* TODO Generic I2C SW and HW */
-}
-
-struct i2caux *dal_i2caux_dce80_create(
-        struct dc_context *ctx)
-{
-        struct i2caux_dce80 *i2caux_dce80 =
-                kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL);
-
-        if (!i2caux_dce80) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        construct(i2caux_dce80, ctx);
-        return &i2caux_dce80->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
deleted file mode 100644
index a59c1f50c1e8..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-#include "../dce110/aux_engine_dce110.h"
-#include "../dce110/i2c_hw_engine_dce110.h"
-#include "../dce110/i2caux_dce110.h"
-
-#include "dcn/dcn_1_0_offset.h"
-#include "dcn/dcn_1_0_sh_mask.h"
-#include "soc15_hw_ip.h"
-#include "vega10_ip_offset.h"
-
-/* begin *********************
- * macros to expend register list macro defined in HW object header file */
-
-#define BASE_INNER(seg) \
-        DCE_BASE__INST0_SEG ## seg
-
-/* compile time expand base address. */
-#define BASE(seg) \
-        BASE_INNER(seg)
-
-#define SR(reg_name)\
-                .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-                                        mm ## reg_name
-
-#define SRI(reg_name, block, id)\
-        .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-                                        mm ## block ## id ## _ ## reg_name
-/* macros to expend register list macro defined in HW object header file
- * end *********************/
-
-#define aux_regs(id)\
-[id] = {\
-        AUX_COMMON_REG_LIST(id), \
-        .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK \
-}
-
-#define hw_engine_regs(id)\
-{\
-                I2C_HW_ENGINE_COMMON_REG_LIST(id) \
-}
-
-static const struct dce110_aux_registers dcn10_aux_regs[] = {
-                aux_regs(0),
-                aux_regs(1),
-                aux_regs(2),
-                aux_regs(3),
-                aux_regs(4),
-                aux_regs(5),
-};
-
-static const struct dce110_i2c_hw_engine_registers dcn10_hw_engine_regs[] = {
-                hw_engine_regs(1),
-                hw_engine_regs(2),
-                hw_engine_regs(3),
-                hw_engine_regs(4),
-                hw_engine_regs(5),
-                hw_engine_regs(6)
-};
-
-static const struct dce110_i2c_hw_engine_shift i2c_shift = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
-};
-
-static const struct dce110_i2c_hw_engine_mask i2c_mask = {
-                I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
-};
-
-struct i2caux *dal_i2caux_dcn10_create(
-        struct dc_context *ctx)
-{
-        struct i2caux_dce110 *i2caux_dce110 =
-                kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
-
-        if (!i2caux_dce110) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        dal_i2caux_dce110_construct(i2caux_dce110,
-                                    ctx,
-                                    ARRAY_SIZE(dcn10_aux_regs),
-                                    dcn10_aux_regs,
-                                    dcn10_hw_engine_regs,
-                                    &i2c_shift,
-                                    &i2c_mask);
-        return &i2caux_dce110->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
deleted file mode 100644
index aeb4a86463d4..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DCN10_H__
-#define __DAL_I2C_AUX_DCN10_H__
-
-struct i2caux *dal_i2caux_dcn10_create(
-        struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c
deleted file mode 100644
index e6408f644086..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "../i2caux.h"
-#include "../engine.h"
-#include "../i2c_engine.h"
-#include "../i2c_sw_engine.h"
-#include "../i2c_hw_engine.h"
-
-/*
- * Header of this unit
- */
-#include "i2caux_diag.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-static void destruct(
-        struct i2caux *i2caux)
-{
-        dal_i2caux_destruct(i2caux);
-}
-
-static void destroy(
-        struct i2caux **i2c_engine)
-{
-        destruct(*i2c_engine);
-
-        kfree(*i2c_engine);
-
-        *i2c_engine = NULL;
-}
-
-/* function table */
-static const struct i2caux_funcs i2caux_funcs = {
-        .destroy = destroy,
-        .acquire_i2c_hw_engine = NULL,
-        .release_engine = NULL,
-        .acquire_i2c_sw_engine = NULL,
-        .acquire_aux_engine = NULL,
-};
-
-static void construct(
-        struct i2caux *i2caux,
-        struct dc_context *ctx)
-{
-        dal_i2caux_construct(i2caux, ctx);
-        i2caux->funcs = &i2caux_funcs;
-}
-
-struct i2caux *dal_i2caux_diag_fpga_create(
-        struct dc_context *ctx)
-{
-        struct i2caux *i2caux = kzalloc(sizeof(struct i2caux),
-                                               GFP_KERNEL);
-
-        if (!i2caux) {
-                ASSERT_CRITICAL(false);
-                return NULL;
-        }
-
-        construct(i2caux, ctx);
-        return i2caux;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.h b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.h
deleted file mode 100644
index a83eeb748283..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_DIAG_FPGA_H__
-#define __DAL_I2C_AUX_DIAG_FPGA_H__
-
-struct i2caux *dal_i2caux_diag_fpga_create(
-        struct dc_context *ctx);
-
-#endif /* __DAL_I2C_AUX_DIAG_FPGA_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/engine.h b/drivers/gpu/drm/amd/display/dc/i2caux/engine.h
deleted file mode 100644
index b16fb1ff687d..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/engine.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_ENGINE_H__
-#define __DAL_ENGINE_H__
-
-#include "dc_ddc_types.h"
-
-enum i2caux_transaction_operation {
-        I2CAUX_TRANSACTION_READ,
-        I2CAUX_TRANSACTION_WRITE
-};
-
-enum i2caux_transaction_address_space {
-        I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
-        I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
-};
-
-struct i2caux_transaction_payload {
-        enum i2caux_transaction_address_space address_space;
-        uint32_t address;
-        uint32_t length;
-        uint8_t *data;
-};
-
-enum i2caux_transaction_status {
-        I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
-        I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
-        I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
-        I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
-        I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
-        I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
-        I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
-        I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
-        I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
-        I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW,
-        I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
-};
-
-struct i2caux_transaction_request {
-        enum i2caux_transaction_operation operation;
-        struct i2caux_transaction_payload payload;
-        enum i2caux_transaction_status status;
-};
-
-enum i2caux_engine_type {
-        I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
-        I2CAUX_ENGINE_TYPE_AUX,
-        I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
-        I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
-        I2CAUX_ENGINE_TYPE_I2C_SW
-};
-
-enum i2c_default_speed {
-        I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
-        I2CAUX_DEFAULT_I2C_SW_SPEED = 50
-};
-
-struct engine;
-
-struct engine_funcs {
-        enum i2caux_engine_type (*get_engine_type)(
-                const struct engine *engine);
-        bool (*acquire)(
-                struct engine *engine,
-                struct ddc *ddc);
-        bool (*submit_request)(
-                struct engine *engine,
-                struct i2caux_transaction_request *request,
-                bool middle_of_transaction);
-        void (*release_engine)(
-                struct engine *engine);
-};
-
-struct engine {
-        const struct engine_funcs *funcs;
-        uint32_t inst;
-        struct ddc *ddc;
-        struct dc_context *ctx;
-};
-
-void dal_i2caux_construct_engine(
-        struct engine *engine,
-        struct dc_context *ctx);
-
-void dal_i2caux_destruct_engine(
-        struct engine *engine);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c
deleted file mode 100644
index 70e20bd47ce4..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-#define FROM_ENGINE(ptr) \
-        container_of((ptr), struct i2c_engine, base)
-
-bool dal_i2c_engine_acquire(
-        struct engine *engine,
-        struct ddc *ddc_handle)
-{
-        struct i2c_engine *i2c_engine = FROM_ENGINE(engine);
-
-        uint32_t counter = 0;
-        bool result;
-
-        do {
-                result = i2c_engine->funcs->acquire_engine(
-                        i2c_engine, ddc_handle);
-
-                if (result)
-                        break;
-
-                /* i2c_engine is busy by VBios, lets wait and retry */
-
-                udelay(10);
-
-                ++counter;
-        } while (counter < 2);
-
-        if (result) {
-                if (!i2c_engine->funcs->setup_engine(i2c_engine)) {
-                        engine->funcs->release_engine(engine);
-                        result = false;
-                }
-        }
-
-        return result;
-}
-
-bool dal_i2c_engine_setup_i2c_engine(
-        struct i2c_engine *engine)
-{
-        /* Derivative classes do not have to override this */
-
-        return true;
-}
-
-void dal_i2c_engine_submit_channel_request(
-        struct i2c_engine *engine,
-        struct i2c_request_transaction_data *request)
-{
-
-}
-
-void dal_i2c_engine_process_channel_reply(
-        struct i2c_engine *engine,
-        struct i2c_reply_transaction_data *reply)
-{
-
-}
-
-void dal_i2c_engine_construct(
-        struct i2c_engine *engine,
-        struct dc_context *ctx)
-{
-        dal_i2caux_construct_engine(&engine->base, ctx);
-        engine->timeout_delay = 0;
-}
-
-void dal_i2c_engine_destruct(
-        struct i2c_engine *engine)
-{
-        dal_i2caux_destruct_engine(&engine->base);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h
deleted file mode 100644
index ded6ea34b714..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_ENGINE_H__
-#define __DAL_I2C_ENGINE_H__
-
-enum i2c_channel_operation_result {
-        I2C_CHANNEL_OPERATION_SUCCEEDED,
-        I2C_CHANNEL_OPERATION_FAILED,
-        I2C_CHANNEL_OPERATION_NOT_GRANTED,
-        I2C_CHANNEL_OPERATION_IS_BUSY,
-        I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED,
-        I2C_CHANNEL_OPERATION_CHANNEL_IN_USE,
-        I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED,
-        I2C_CHANNEL_OPERATION_ENGINE_BUSY,
-        I2C_CHANNEL_OPERATION_TIMEOUT,
-        I2C_CHANNEL_OPERATION_NO_RESPONSE,
-        I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS,
-        I2C_CHANNEL_OPERATION_WRONG_PARAMETER,
-        I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES,
-        I2C_CHANNEL_OPERATION_NOT_STARTED
-};
-
-struct i2c_request_transaction_data {
-        enum i2caux_transaction_action action;
-        enum i2c_channel_operation_result status;
-        uint8_t address;
-        uint32_t length;
-        uint8_t *data;
-};
-
-struct i2c_reply_transaction_data {
-        uint32_t length;
-        uint8_t *data;
-};
-
-struct i2c_engine;
-
-struct i2c_engine_funcs {
-        void (*destroy)(
-                struct i2c_engine **ptr);
-        uint32_t (*get_speed)(
-                const struct i2c_engine *engine);
-        void (*set_speed)(
-                struct i2c_engine *engine,
-                uint32_t speed);
-        bool (*acquire_engine)(
-                struct i2c_engine *engine,
-                struct ddc *ddc);
-        bool (*setup_engine)(
-                struct i2c_engine *engine);
-        void (*submit_channel_request)(
-                struct i2c_engine *engine,
-                struct i2c_request_transaction_data *request);
-        void (*process_channel_reply)(
-                struct i2c_engine *engine,
-                struct i2c_reply_transaction_data *reply);
-        enum i2c_channel_operation_result (*get_channel_status)(
-                struct i2c_engine *engine,
-                uint8_t *returned_bytes);
-};
-
-struct i2c_engine {
-        struct engine base;
-        const struct i2c_engine_funcs *funcs;
-        uint32_t timeout_delay;
-        uint32_t setup_limit;
-        uint32_t send_reset_length;
-};
-
-void dal_i2c_engine_construct(
-        struct i2c_engine *engine,
-        struct dc_context *ctx);
-
-void dal_i2c_engine_destruct(
-        struct i2c_engine *engine);
-
-bool dal_i2c_engine_setup_i2c_engine(
-        struct i2c_engine *engine);
-
-void dal_i2c_engine_submit_channel_request(
-        struct i2c_engine *engine,
-        struct i2c_request_transaction_data *request);
-
-void dal_i2c_engine_process_channel_reply(
-        struct i2c_engine *engine,
-        struct i2c_reply_transaction_data *reply);
-
-bool dal_i2c_engine_acquire(
-        struct engine *ptr,
-        struct ddc *ddc_handle);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
deleted file mode 100644
index 5a4295e0fae5..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-#include "i2c_engine.h"
-#include "i2c_hw_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_generic_hw_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct i2c_hw_engine *'
- * to 'struct i2c_generic_hw_engine *'
- */
-#define FROM_I2C_HW_ENGINE(ptr) \
-        container_of((ptr), struct i2c_generic_hw_engine, base)
-
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_generic_hw_engine *'
- */
-#define FROM_I2C_ENGINE(ptr) \
-        FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_generic_hw_engine *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
-        const struct engine *engine)
-{
-        return I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW;
-}
-
-/*
- * @brief
- * Single transaction handling.
- * Since transaction may be bigger than HW buffer size,
- * it divides transaction to sub-transactions
- * and uses batch transaction feature of the engine.
- */
-bool dal_i2c_generic_hw_engine_submit_request(
-        struct engine *engine,
-        struct i2caux_transaction_request *i2caux_request,
-        bool middle_of_transaction)
-{
-        struct i2c_generic_hw_engine *hw_engine = FROM_ENGINE(engine);
-
-        struct i2c_hw_engine *base = &hw_engine->base;
-
-        uint32_t max_payload_size =
-                base->funcs->get_hw_buffer_available_size(base);
-
-        bool initial_stop_bit = !middle_of_transaction;
-
-        struct i2c_generic_transaction_attributes attributes;
-
-        enum i2c_channel_operation_result operation_result =
-                I2C_CHANNEL_OPERATION_FAILED;
-
-        bool result = false;
-
-        /* setup transaction initial properties */
-
-        uint8_t address = i2caux_request->payload.address;
-        uint8_t *current_payload = i2caux_request->payload.data;
-        uint32_t remaining_payload_size = i2caux_request->payload.length;
-
-        bool first_iteration = true;
-
-        if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-                attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_READ;
-        else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-                attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-        else {
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-                return false;
-        }
-
-        /* Do batch transaction.
-         * Divide read/write data into payloads which fit HW buffer size.
-         * 1. Single transaction:
-         *    start_bit = 1, stop_bit depends on session state, ack_on_read = 0;
-         * 2. Start of batch transaction:
-         *    start_bit = 1, stop_bit = 0, ack_on_read = 1;
-         * 3. Middle of batch transaction:
-         *    start_bit = 0, stop_bit = 0, ack_on_read = 1;
-         * 4. End of batch transaction:
-         *    start_bit = 0, stop_bit depends on session state, ack_on_read = 0.
-         * Session stop bit is set if 'middle_of_transaction' = 0. */
-
-        while (remaining_payload_size) {
-                uint32_t current_transaction_size;
-                uint32_t current_payload_size;
-
-                bool last_iteration;
-                bool stop_bit;
-
-                /* Calculate current transaction size and payload size.
-                 * Transaction size = total number of bytes in transaction,
-                 * including slave's address;
-                 * Payload size = number of data bytes in transaction. */
-
-                if (first_iteration) {
-                        /* In the first sub-transaction we send slave's address
-                         * thus we need to reserve one byte for it */
-                        current_transaction_size =
-                        (remaining_payload_size > max_payload_size - 1) ?
-                                max_payload_size :
-                                remaining_payload_size + 1;
-
-                        current_payload_size = current_transaction_size - 1;
-                } else {
-                        /* Second and further sub-transactions will have
-                         * entire buffer reserved for data */
-                        current_transaction_size =
-                                (remaining_payload_size > max_payload_size) ?
-                                max_payload_size :
-                                remaining_payload_size;
-
-                        current_payload_size = current_transaction_size;
-                }
-
-                last_iteration =
-                        (remaining_payload_size == current_payload_size);
-
-                stop_bit = last_iteration ? initial_stop_bit : false;
-
-                /* write slave device address */
-
-                if (first_iteration)
-                        hw_engine->funcs->write_address(hw_engine, address);
-
-                /* write current portion of data, if requested */
-
-                if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-                        hw_engine->funcs->write_data(
-                                hw_engine,
-                                current_payload,
-                                current_payload_size);
-
-                /* execute transaction */
-
-                attributes.start_bit = first_iteration;
-                attributes.stop_bit = stop_bit;
-                attributes.last_read = last_iteration;
-                attributes.transaction_size = current_transaction_size;
-
-                hw_engine->funcs->execute_transaction(hw_engine, &attributes);
-
-                /* wait until transaction is processed; if it fails - quit */
-
-                operation_result = base->funcs->wait_on_operation_result(
-                        base,
-                        base->funcs->get_transaction_timeout(
-                                base, current_transaction_size),
-                        I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-
-                if (operation_result != I2C_CHANNEL_OPERATION_SUCCEEDED)
-                        break;
-
-                /* read current portion of data, if requested */
-
-                /* the read offset should be 1 for first sub-transaction,
-                 * and 0 for any next one */
-
-                if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-                        hw_engine->funcs->read_data(hw_engine, current_payload,
-                                current_payload_size, first_iteration ? 1 : 0);
-
-                /* update loop variables */
-
-                first_iteration = false;
-                current_payload += current_payload_size;
-                remaining_payload_size -= current_payload_size;
-        }
-
-        /* update transaction status */
-
-        switch (operation_result) {
-        case I2C_CHANNEL_OPERATION_SUCCEEDED:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-                result = true;
-        break;
-        case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-        break;
-        case I2C_CHANNEL_OPERATION_TIMEOUT:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-        break;
-        case I2C_CHANNEL_OPERATION_FAILED:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-        break;
-        default:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-        }
-
-        return result;
-}
-
-/*
- * @brief
- * Returns number of microseconds to wait until timeout to be considered
- */
-uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
-        const struct i2c_hw_engine *engine,
-        uint32_t length)
-{
-        const struct i2c_engine *base = &engine->base;
-
-        uint32_t speed = base->funcs->get_speed(base);
-
-        if (!speed)
-                return 0;
-
-        /* total timeout = period_timeout * (start + data bits count + stop) */
-
-        return ((1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed) *
-                (1 + (length << 3) + 1);
-}
-
-void dal_i2c_generic_hw_engine_construct(
-        struct i2c_generic_hw_engine *engine,
-        struct dc_context *ctx)
-{
-        dal_i2c_hw_engine_construct(&engine->base, ctx);
-}
-
-void dal_i2c_generic_hw_engine_destruct(
-        struct i2c_generic_hw_engine *engine)
-{
-        dal_i2c_hw_engine_destruct(&engine->base);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
deleted file mode 100644
index 1da0397b04a2..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_GENERIC_HW_ENGINE_H__
-#define __DAL_I2C_GENERIC_HW_ENGINE_H__
-
-struct i2c_generic_transaction_attributes {
-        enum i2caux_transaction_action action;
-        uint32_t transaction_size;
-        bool start_bit;
-        bool stop_bit;
-        bool last_read;
-};
-
-struct i2c_generic_hw_engine;
-
-struct i2c_generic_hw_engine_funcs {
-        void (*write_address)(
-                struct i2c_generic_hw_engine *engine,
-                uint8_t address);
-        void (*write_data)(
-                struct i2c_generic_hw_engine *engine,
-                const uint8_t *buffer,
-                uint32_t length);
-        void (*read_data)(
-                struct i2c_generic_hw_engine *engine,
-                uint8_t *buffer,
-                uint32_t length,
-                uint32_t offset);
-        void (*execute_transaction)(
-                struct i2c_generic_hw_engine *engine,
-                struct i2c_generic_transaction_attributes *attributes);
-};
-
-struct i2c_generic_hw_engine {
-        struct i2c_hw_engine base;
-        const struct i2c_generic_hw_engine_funcs *funcs;
-};
-
-void dal_i2c_generic_hw_engine_construct(
-        struct i2c_generic_hw_engine *engine,
-        struct dc_context *ctx);
-
-void dal_i2c_generic_hw_engine_destruct(
-        struct i2c_generic_hw_engine *engine);
-enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
-        const struct engine *engine);
-bool dal_i2c_generic_hw_engine_submit_request(
-        struct engine *ptr,
-        struct i2caux_transaction_request *i2caux_request,
-        bool middle_of_transaction);
-uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
-        const struct i2c_hw_engine *engine,
-        uint32_t length);
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c
deleted file mode 100644
index 141898533e8e..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "dm_event_log.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-#include "i2c_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_hw_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_hw_engine *'
- */
-#define FROM_I2C_ENGINE(ptr) \
-        container_of((ptr), struct i2c_hw_engine, base)
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_hw_engine *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
-        const struct engine *engine)
-{
-        return I2CAUX_ENGINE_TYPE_I2C_DDC_HW;
-}
-
-bool dal_i2c_hw_engine_submit_request(
-        struct engine *engine,
-        struct i2caux_transaction_request *i2caux_request,
-        bool middle_of_transaction)
-{
-        struct i2c_hw_engine *hw_engine = FROM_ENGINE(engine);
-
-        struct i2c_request_transaction_data request;
-
-        uint32_t transaction_timeout;
-
-        enum i2c_channel_operation_result operation_result;
-
-        bool result = false;
-
-        /* We need following:
-         * transaction length will not exceed
-         * the number of free bytes in HW buffer (minus one for address)*/
-
-        if (i2caux_request->payload.length >=
-                hw_engine->funcs->get_hw_buffer_available_size(hw_engine)) {
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW;
-                return false;
-        }
-
-        if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-                request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ;
-        else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-                request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-        else {
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-                /* [anaumov] in DAL2, there was no "return false" */
-                return false;
-        }
-
-        request.address = (uint8_t)i2caux_request->payload.address;
-        request.length = i2caux_request->payload.length;
-        request.data = i2caux_request->payload.data;
-
-        /* obtain timeout value before submitting request */
-
-        transaction_timeout = hw_engine->funcs->get_transaction_timeout(
-                hw_engine, i2caux_request->payload.length + 1);
-
-        hw_engine->base.funcs->submit_channel_request(
-                &hw_engine->base, &request);
-        /* EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_I2C, */
-        /* request.action, request.address, request.length, request.data); */
-
-        if ((request.status == I2C_CHANNEL_OPERATION_FAILED) ||
-                (request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY)) {
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
-                return false;
-        }
-
-        /* wait until transaction proceed */
-
-        operation_result = hw_engine->funcs->wait_on_operation_result(
-                hw_engine,
-                transaction_timeout,
-                I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-
-        /* update transaction status */
-
-        switch (operation_result) {
-        case I2C_CHANNEL_OPERATION_SUCCEEDED:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-                result = true;
-        break;
-        case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-        break;
-        case I2C_CHANNEL_OPERATION_TIMEOUT:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-        break;
-        case I2C_CHANNEL_OPERATION_FAILED:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-        break;
-        default:
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-        }
-
-        if (result && (i2caux_request->operation == I2CAUX_TRANSACTION_READ)) {
-                struct i2c_reply_transaction_data reply;
-
-                reply.data = i2caux_request->payload.data;
-                reply.length = i2caux_request->payload.length;
-
-                hw_engine->base.funcs->
-                        process_channel_reply(&hw_engine->base, &reply);
-                /* EVENT_LOG_AUX_REP(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_I2C, */
-                /* AUX_TRANSACTION_REPLY_I2C_ACK, reply.length, reply.data); */
-        }
-
-
-
-        return result;
-}
-
-bool dal_i2c_hw_engine_acquire_engine(
-        struct i2c_engine *engine,
-        struct ddc *ddc)
-{
-        enum gpio_result result;
-        uint32_t current_speed;
-
-        result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
-                GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-
-        if (result != GPIO_RESULT_OK)
-                return false;
-
-        engine->base.ddc = ddc;
-
-        current_speed = engine->funcs->get_speed(engine);
-
-        if (current_speed)
-                FROM_I2C_ENGINE(engine)->original_speed = current_speed;
-
-        return true;
-}
-/*
- * @brief
- * Queries in a loop for current engine status
- * until retrieved status matches 'expected_result', or timeout occurs.
- * Timeout given in microseconds
- * and the status query frequency is also one per microsecond.
- */
-enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
-        struct i2c_hw_engine *engine,
-        uint32_t timeout,
-        enum i2c_channel_operation_result expected_result)
-{
-        enum i2c_channel_operation_result result;
-        uint32_t i = 0;
-
-        if (!timeout)
-                return I2C_CHANNEL_OPERATION_SUCCEEDED;
-
-        do {
-                result = engine->base.funcs->get_channel_status(
-                        &engine->base, NULL);
-
-                if (result != expected_result)
-                        break;
-
-                udelay(1);
-
-                ++i;
-        } while (i < timeout);
-
-        return result;
-}
-
-void dal_i2c_hw_engine_construct(
-        struct i2c_hw_engine *engine,
-        struct dc_context *ctx)
-{
-        dal_i2c_engine_construct(&engine->base, ctx);
-        engine->original_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
-        engine->default_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
-}
-
-void dal_i2c_hw_engine_destruct(
-        struct i2c_hw_engine *engine)
-{
-        dal_i2c_engine_destruct(&engine->base);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h
deleted file mode 100644
index 8936a994804a..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_HW_ENGINE_H__
-#define __DAL_I2C_HW_ENGINE_H__
-
-enum {
-        TRANSACTION_TIMEOUT_IN_I2C_CLOCKS = 32
-};
-
-struct i2c_hw_engine;
-
-struct i2c_hw_engine_funcs {
-        uint32_t (*get_hw_buffer_available_size)(
-                const struct i2c_hw_engine *engine);
-        enum i2c_channel_operation_result (*wait_on_operation_result)(
-                struct i2c_hw_engine *engine,
-                uint32_t timeout,
-                enum i2c_channel_operation_result expected_result);
-        uint32_t (*get_transaction_timeout)(
-                const struct i2c_hw_engine *engine,
-                uint32_t length);
-};
-
-struct i2c_hw_engine {
-        struct i2c_engine base;
-        const struct i2c_hw_engine_funcs *funcs;
-
-        /* Values below are in kilohertz */
-        uint32_t original_speed;
-        uint32_t default_speed;
-};
-
-void dal_i2c_hw_engine_construct(
-        struct i2c_hw_engine *engine,
-        struct dc_context *ctx);
-
-void dal_i2c_hw_engine_destruct(
-        struct i2c_hw_engine *engine);
-
-enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(
-        struct i2c_hw_engine *engine,
-        uint32_t timeout,
-        enum i2c_channel_operation_result expected_result);
-
-bool dal_i2c_hw_engine_acquire_engine(
-        struct i2c_engine *engine,
-        struct ddc *ddc);
-
-bool dal_i2c_hw_engine_submit_request(
-        struct engine *ptr,
-        struct i2caux_transaction_request *i2caux_request,
-        bool middle_of_transaction);
-
-enum i2caux_engine_type dal_i2c_hw_engine_get_engine_type(
-        const struct engine *engine);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c
deleted file mode 100644
index 8e19bb629394..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c
+++ /dev/null
@@ -1,601 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "engine.h"
-#include "i2c_engine.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2c_sw_engine.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-/*
- * This unit
- */
-
-#define SCL false
-#define SDA true
-
-static inline bool read_bit_from_ddc(
-        struct ddc *ddc,
-        bool data_nor_clock)
-{
-        uint32_t value = 0;
-
-        if (data_nor_clock)
-                dal_gpio_get_value(ddc->pin_data, &value);
-        else
-                dal_gpio_get_value(ddc->pin_clock, &value);
-
-        return (value != 0);
-}
-
-static inline void write_bit_to_ddc(
-        struct ddc *ddc,
-        bool data_nor_clock,
-        bool bit)
-{
-        uint32_t value = bit ? 1 : 0;
-
-        if (data_nor_clock)
-                dal_gpio_set_value(ddc->pin_data, value);
-        else
-                dal_gpio_set_value(ddc->pin_clock, value);
-}
-
-static bool wait_for_scl_high(
-        struct dc_context *ctx,
-        struct ddc *ddc,
-        uint16_t clock_delay_div_4)
-{
-        uint32_t scl_retry = 0;
-        uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
-
-        udelay(clock_delay_div_4);
-
-        /* 3 milliseconds delay
-         * to wake up some displays from "low power" state.
-         */
-
-        do {
-                if (read_bit_from_ddc(ddc, SCL))
-                        return true;
-
-                udelay(clock_delay_div_4);
-
-                ++scl_retry;
-        } while (scl_retry <= scl_retry_max);
-
-        return false;
-}
-
-static bool start_sync(
-        struct dc_context *ctx,
-        struct ddc *ddc_handle,
-        uint16_t clock_delay_div_4)
-{
-        uint32_t retry = 0;
-
-        /* The I2C communications start signal is:
-         * the SDA going low from high, while the SCL is high. */
-
-        write_bit_to_ddc(ddc_handle, SCL, true);
-
-        udelay(clock_delay_div_4);
-
-        do {
-                write_bit_to_ddc(ddc_handle, SDA, true);
-
-                if (!read_bit_from_ddc(ddc_handle, SDA)) {
-                        ++retry;
-                        continue;
-                }
-
-                udelay(clock_delay_div_4);
-
-                write_bit_to_ddc(ddc_handle, SCL, true);
-
-                if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-                        break;
-
-                write_bit_to_ddc(ddc_handle, SDA, false);
-
-                udelay(clock_delay_div_4);
-
-                write_bit_to_ddc(ddc_handle, SCL, false);
-
-                udelay(clock_delay_div_4);
-
-                return true;
-        } while (retry <= I2C_SW_RETRIES);
-
-        return false;
-}
-
-static bool stop_sync(
-        struct dc_context *ctx,
-        struct ddc *ddc_handle,
-        uint16_t clock_delay_div_4)
-{
-        uint32_t retry = 0;
-
-        /* The I2C communications stop signal is:
-         * the SDA going high from low, while the SCL is high. */
-
-        write_bit_to_ddc(ddc_handle, SCL, false);
-
-        udelay(clock_delay_div_4);
-
-        write_bit_to_ddc(ddc_handle, SDA, false);
-
-        udelay(clock_delay_div_4);
-
-        write_bit_to_ddc(ddc_handle, SCL, true);
-
-        if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-                return false;
-
-        write_bit_to_ddc(ddc_handle, SDA, true);
-
-        do {
-                udelay(clock_delay_div_4);
-
-                if (read_bit_from_ddc(ddc_handle, SDA))
-                        return true;
-
-                ++retry;
-        } while (retry <= 2);
-
-        return false;
-}
-
-static bool write_byte(
-        struct dc_context *ctx,
-        struct ddc *ddc_handle,
-        uint16_t clock_delay_div_4,
-        uint8_t byte)
-{
-        int32_t shift = 7;
-        bool ack;
-
-        /* bits are transmitted serially, starting from MSB */
-
-        do {
-                udelay(clock_delay_div_4);
-
-                write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
-
-                udelay(clock_delay_div_4);
-
-                write_bit_to_ddc(ddc_handle, SCL, true);
-
-                if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-                        return false;
-
-                write_bit_to_ddc(ddc_handle, SCL, false);
-
-                --shift;
-        } while (shift >= 0);
-
-        /* The display sends ACK by preventing the SDA from going high
-         * after the SCL pulse we use to send our last data bit.
-         * If the SDA goes high after that bit, it's a NACK */
-
-        udelay(clock_delay_div_4);
-
-        write_bit_to_ddc(ddc_handle, SDA, true);
-
-        udelay(clock_delay_div_4);
-
-        write_bit_to_ddc(ddc_handle, SCL, true);
-
-        if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-                return false;
-
-        /* read ACK bit */
-
-        ack = !read_bit_from_ddc(ddc_handle, SDA);
-
-        udelay(clock_delay_div_4 << 1);
-
-        write_bit_to_ddc(ddc_handle, SCL, false);
-
-        udelay(clock_delay_div_4 << 1);
-
-        return ack;
-}
-
-static bool read_byte(
-        struct dc_context *ctx,
-        struct ddc *ddc_handle,
-        uint16_t clock_delay_div_4,
-        uint8_t *byte,
-        bool more)
-{
-        int32_t shift = 7;
-
-        uint8_t data = 0;
-
-        /* The data bits are read from MSB to LSB;
-         * bit is read while SCL is high */
-
-        do {
-                write_bit_to_ddc(ddc_handle, SCL, true);
-
-                if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-                        return false;
-
-                if (read_bit_from_ddc(ddc_handle, SDA))
-                        data |= (1 << shift);
-
-                write_bit_to_ddc(ddc_handle, SCL, false);
-
-                udelay(clock_delay_div_4 << 1);
-
-                --shift;
-        } while (shift >= 0);
-
-        /* read only whole byte */
-
-        *byte = data;
-
-        udelay(clock_delay_div_4);
-
-        /* send the acknowledge bit:
-         * SDA low means ACK, SDA high means NACK */
-
-        write_bit_to_ddc(ddc_handle, SDA, !more);
-
-        udelay(clock_delay_div_4);
-
-        write_bit_to_ddc(ddc_handle, SCL, true);
-
-        if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
-                return false;
-
-        write_bit_to_ddc(ddc_handle, SCL, false);
-
-        udelay(clock_delay_div_4);
-
-        write_bit_to_ddc(ddc_handle, SDA, true);
-
-        udelay(clock_delay_div_4);
-
-        return true;
-}
-
-static bool i2c_write(
-        struct dc_context *ctx,
-        struct ddc *ddc_handle,
-        uint16_t clock_delay_div_4,
-        uint8_t address,
-        uint32_t length,
-        const uint8_t *data)
-{
-        uint32_t i = 0;
-
-        if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
-                return false;
-
-        while (i < length) {
-                if (!write_byte(ctx, ddc_handle, clock_delay_div_4, data[i]))
-                        return false;
-                ++i;
-        }
-
-        return true;
-}
-
-static bool i2c_read(
-        struct dc_context *ctx,
-        struct ddc *ddc_handle,
-        uint16_t clock_delay_div_4,
-        uint8_t address,
-        uint32_t length,
-        uint8_t *data)
-{
-        uint32_t i = 0;
-
-        if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
-                return false;
-
-        while (i < length) {
-                if (!read_byte(ctx, ddc_handle, clock_delay_div_4, data + i,
-                        i < length - 1))
-                        return false;
-                ++i;
-        }
-
-        return true;
-}
-
-/*
- * @brief
- * Cast 'struct i2c_engine *'
- * to 'struct i2c_sw_engine *'
- */
-#define FROM_I2C_ENGINE(ptr) \
-        container_of((ptr), struct i2c_sw_engine, base)
-
-/*
- * @brief
- * Cast 'struct engine *'
- * to 'struct i2c_sw_engine *'
- */
-#define FROM_ENGINE(ptr) \
-        FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
-
-enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
-        const struct engine *engine)
-{
-        return I2CAUX_ENGINE_TYPE_I2C_SW;
-}
-
-bool dal_i2c_sw_engine_submit_request(
-        struct engine *engine,
-        struct i2caux_transaction_request *i2caux_request,
-        bool middle_of_transaction)
-{
-        struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
-
-        struct i2c_engine *base = &sw_engine->base;
-
-        struct i2c_request_transaction_data request;
-        bool operation_succeeded = false;
-
-        if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
-                request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_READ;
-        else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
-                request.action = middle_of_transaction ?
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
-                        I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
-        else {
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
-                /* in DAL2, there was no "return false" */
-                return false;
-        }
-
-        request.address = (uint8_t)i2caux_request->payload.address;
-        request.length = i2caux_request->payload.length;
-        request.data = i2caux_request->payload.data;
-
-        base->funcs->submit_channel_request(base, &request);
-
-        if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
-                (request.status == I2C_CHANNEL_OPERATION_FAILED))
-                i2caux_request->status =
-                        I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
-        else {
-                enum i2c_channel_operation_result operation_result;
-
-                do {
-                        operation_result =
-                                base->funcs->get_channel_status(base, NULL);
-
-                        switch (operation_result) {
-                        case I2C_CHANNEL_OPERATION_SUCCEEDED:
-                                i2caux_request->status =
-                                        I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
-                                operation_succeeded = true;
-                        break;
-                        case I2C_CHANNEL_OPERATION_NO_RESPONSE:
-                                i2caux_request->status =
-                                        I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
-                        break;
-                        case I2C_CHANNEL_OPERATION_TIMEOUT:
-                                i2caux_request->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
-                        break;
-                        case I2C_CHANNEL_OPERATION_FAILED:
-                                i2caux_request->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
-                        break;
-                        default:
-                                i2caux_request->status =
-                                I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
-                        break;
-                        }
-                } while (operation_result == I2C_CHANNEL_OPERATION_ENGINE_BUSY);
-        }
-
-        return operation_succeeded;
-}
-
-uint32_t dal_i2c_sw_engine_get_speed(
-        const struct i2c_engine *engine)
-{
-        return FROM_I2C_ENGINE(engine)->speed;
-}
-
-void dal_i2c_sw_engine_set_speed(
-        struct i2c_engine *engine,
-        uint32_t speed)
-{
-        struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-
-        ASSERT(speed);
-
-        sw_engine->speed = speed ? speed : I2CAUX_DEFAULT_I2C_SW_SPEED;
-
-        sw_engine->clock_delay = 1000 / sw_engine->speed;
-
-        if (sw_engine->clock_delay < 12)
-                sw_engine->clock_delay = 12;
-}
-
-bool dal_i2caux_i2c_sw_engine_acquire_engine(
-        struct i2c_engine *engine,
-        struct ddc *ddc)
-{
-        enum gpio_result result;
-
-        result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
-                GPIO_DDC_CONFIG_TYPE_MODE_I2C);
-
-        if (result != GPIO_RESULT_OK)
-                return false;
-
-        engine->base.ddc = ddc;
-
-        return true;
-}
-
-void dal_i2c_sw_engine_submit_channel_request(
-        struct i2c_engine *engine,
-        struct i2c_request_transaction_data *req)
-{
-        struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
-
-        struct ddc *ddc = engine->base.ddc;
-        uint16_t clock_delay_div_4 = sw_engine->clock_delay >> 2;
-
-        /* send sync (start / repeated start) */
-
-        bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
-
-        /* process payload */
-
-        if (result) {
-                switch (req->action) {
-                case I2CAUX_TRANSACTION_ACTION_I2C_WRITE:
-                case I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT:
-                        result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
-                                req->address, req->length, req->data);
-                break;
-                case I2CAUX_TRANSACTION_ACTION_I2C_READ:
-                case I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT:
-                        result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
-                                req->address, req->length, req->data);
-                break;
-                default:
-                        result = false;
-                break;
-                }
-        }
-
-        /* send stop if not 'mot' or operation failed */
-
-        if (!result ||
-                (req->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
-                (req->action == I2CAUX_TRANSACTION_ACTION_I2C_READ))
-                if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
-                        result = false;
-
-        req->status = result ?
-                I2C_CHANNEL_OPERATION_SUCCEEDED :
-                I2C_CHANNEL_OPERATION_FAILED;
-}
-
-enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
-        struct i2c_engine *engine,
-        uint8_t *returned_bytes)
-{
-        /* No arbitration with VBIOS is performed since DCE 6.0 */
-        return I2C_CHANNEL_OPERATION_SUCCEEDED;
-}
-
-void dal_i2c_sw_engine_destruct(
-        struct i2c_sw_engine *engine)
-{
-        dal_i2c_engine_destruct(&engine->base);
-}
-
-static void destroy(
-        struct i2c_engine **ptr)
-{
-        dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
-
-        kfree(*ptr);
-        *ptr = NULL;
-}
-
-static const struct i2c_engine_funcs i2c_engine_funcs = {
-        .acquire_engine = dal_i2caux_i2c_sw_engine_acquire_engine,
-        .destroy = destroy,
-        .get_speed = dal_i2c_sw_engine_get_speed,
-        .set_speed = dal_i2c_sw_engine_set_speed,
-        .setup_engine = dal_i2c_engine_setup_i2c_engine,
-        .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
-        .process_channel_reply = dal_i2c_engine_process_channel_reply,
-        .get_channel_status = dal_i2c_sw_engine_get_channel_status,
-};
-
-static void release_engine(
-        struct engine *engine)
-{
-
-}
-
-static const struct engine_funcs engine_funcs = {
-        .release_engine = release_engine,
-        .get_engine_type = dal_i2c_sw_engine_get_engine_type,
-        .acquire = dal_i2c_engine_acquire,
-        .submit_request = dal_i2c_sw_engine_submit_request,
-};
-
-void dal_i2c_sw_engine_construct(
-        struct i2c_sw_engine *engine,
-        const struct i2c_sw_engine_create_arg *arg)
-{
-        dal_i2c_engine_construct(&engine->base, arg->ctx);
-        dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
-        engine->base.funcs = &i2c_engine_funcs;
-        engine->base.base.funcs = &engine_funcs;
-}
-
-struct i2c_engine *dal_i2c_sw_engine_create(
-        const struct i2c_sw_engine_create_arg *arg)
-{
-        struct i2c_sw_engine *engine;
-
-        if (!arg) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL);
-
-        if (!engine) {
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-
-        dal_i2c_sw_engine_construct(engine, arg);
-        return &engine->base;
-}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h
deleted file mode 100644
index 546f15b0d3f1..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_SW_ENGINE_H__
-#define __DAL_I2C_SW_ENGINE_H__
-
-enum {
-        I2C_SW_RETRIES = 10,
-        I2C_SW_SCL_READ_RETRIES = 128,
-        /* following value is in microseconds */
-        I2C_SW_TIMEOUT_DELAY = 3000
-};
-
-struct i2c_sw_engine;
-
-struct i2c_sw_engine {
-        struct i2c_engine base;
-        uint32_t clock_delay;
-        /* Values below are in KHz */
-        uint32_t speed;
-        uint32_t default_speed;
-};
-
-struct i2c_sw_engine_create_arg {
-        uint32_t default_speed;
-        struct dc_context *ctx;
-};
-
-void dal_i2c_sw_engine_construct(
-        struct i2c_sw_engine *engine,
-        const struct i2c_sw_engine_create_arg *arg);
-
-bool dal_i2caux_i2c_sw_engine_acquire_engine(
-        struct i2c_engine *engine,
-        struct ddc *ddc_handle);
-
-void dal_i2c_sw_engine_destruct(
-        struct i2c_sw_engine *engine);
-
-struct i2c_engine *dal_i2c_sw_engine_create(
-        const struct i2c_sw_engine_create_arg *arg);
-enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
-        const struct engine *engine);
-bool dal_i2c_sw_engine_submit_request(
-        struct engine *ptr,
-        struct i2caux_transaction_request *i2caux_request,
-        bool middle_of_transaction);
-uint32_t dal_i2c_sw_engine_get_speed(
-        const struct i2c_engine *engine);
-void dal_i2c_sw_engine_set_speed(
-        struct i2c_engine *ptr,
-        uint32_t speed);
-void dal_i2c_sw_engine_submit_channel_request(
-        struct i2c_engine *ptr,
-        struct i2c_request_transaction_data *req);
-enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
-        struct i2c_engine *engine,
-        uint8_t *returned_bytes);
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
deleted file mode 100644
index 1ad6e49102ff..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-#include "dc_bios_types.h"
-
-/*
- * Header of this unit
- */
-
-#include "i2caux.h"
-
-/*
- * Post-requisites: headers required by this unit
- */
-
-#include "engine.h"
-#include "i2c_engine.h"
-#include "aux_engine.h"
-
-/*
- * This unit
- */
-
-#include "dce80/i2caux_dce80.h"
-
-#include "dce100/i2caux_dce100.h"
-
-#include "dce110/i2caux_dce110.h"
-
-#include "dce112/i2caux_dce112.h"
-
-#include "dce120/i2caux_dce120.h"
-
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-#include "dcn10/i2caux_dcn10.h"
-#endif
-
-#include "diagnostics/i2caux_diag.h"
-
-/*
- * @brief
- * Plain API, available publicly
- */
-
-struct i2caux *dal_i2caux_create(
-        struct dc_context *ctx)
-{
-        if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
-                return dal_i2caux_diag_fpga_create(ctx);
-        }
-
-        switch (ctx->dce_version) {
-        case DCE_VERSION_8_0:
-        case DCE_VERSION_8_1:
-        case DCE_VERSION_8_3:
-                return dal_i2caux_dce80_create(ctx);
-        case DCE_VERSION_11_2:
-        case DCE_VERSION_11_22:
-                return dal_i2caux_dce112_create(ctx);
-        case DCE_VERSION_11_0:
-                return dal_i2caux_dce110_create(ctx);
-        case DCE_VERSION_10_0:
-                return dal_i2caux_dce100_create(ctx);
-        case DCE_VERSION_12_0:
-        case DCE_VERSION_12_1:
-                return dal_i2caux_dce120_create(ctx);
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-        case DCN_VERSION_1_0:
-                return dal_i2caux_dcn10_create(ctx);
-#endif
-
-#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
-        case DCN_VERSION_1_01:
-                return dal_i2caux_dcn10_create(ctx);
-#endif
-        default:
-                BREAK_TO_DEBUGGER();
-                return NULL;
-        }
-}
-
-bool dal_i2caux_submit_i2c_command(
-        struct i2caux *i2caux,
-        struct ddc *ddc,
-        struct i2c_command *cmd)
-{
-        struct i2c_engine *engine;
-        uint8_t index_of_payload = 0;
-        bool result;
-
-        if (!ddc) {
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        if (!cmd) {
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        /*
-         * default will be SW, however there is a feature flag in adapter
-         * service that determines whether SW i2c_engine will be available or
-         * not, if sw i2c is not available we will fallback to hw. This feature
-         * flag is set to not creating sw i2c engine for every dce except dce80
-         * currently
-         */
-        switch (cmd->engine) {
-        case I2C_COMMAND_ENGINE_DEFAULT:
-        case I2C_COMMAND_ENGINE_SW:
-                /* try to acquire SW engine first,
-                 * acquire HW engine if SW engine not available */
-                engine = i2caux->funcs->acquire_i2c_sw_engine(i2caux, ddc);
-
-                if (!engine)
-                        engine = i2caux->funcs->acquire_i2c_hw_engine(
-                                i2caux, ddc);
-        break;
-        case I2C_COMMAND_ENGINE_HW:
-        default:
-                /* try to acquire HW engine first,
-                 * acquire SW engine if HW engine not available */
-                engine = i2caux->funcs->acquire_i2c_hw_engine(i2caux, ddc);
-
-                if (!engine)
-                        engine = i2caux->funcs->acquire_i2c_sw_engine(
-                                i2caux, ddc);
-        }
-
-        if (!engine)
-                return false;
-
-        engine->funcs->set_speed(engine, cmd->speed);
-
-        result = true;
-
-        while (index_of_payload < cmd->number_of_payloads) {
-                bool mot = (index_of_payload != cmd->number_of_payloads - 1);
-
-                struct i2c_payload *payload = cmd->payloads + index_of_payload;
-
-                struct i2caux_transaction_request request = { 0 };
-
-                request.operation = payload->write ?
-                        I2CAUX_TRANSACTION_WRITE :
-                        I2CAUX_TRANSACTION_READ;
-
-                request.payload.address_space =
-                        I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
-                request.payload.address = (payload->address << 1) |
-                        !payload->write;
-                request.payload.length = payload->length;
-                request.payload.data = payload->data;
-
-                if (!engine->base.funcs->submit_request(
-                        &engine->base, &request, mot)) {
-                        result = false;
-                        break;
-                }
-
-                ++index_of_payload;
-        }
-
-        i2caux->funcs->release_engine(i2caux, &engine->base);
-
-        return result;
-}
-
-bool dal_i2caux_submit_aux_command(
-        struct i2caux *i2caux,
-        struct ddc *ddc,
-        struct aux_command *cmd)
-{
-        struct aux_engine *engine;
-        uint8_t index_of_payload = 0;
-        bool result;
-        bool mot;
-
-        if (!ddc) {
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        if (!cmd) {
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc);
-
-        if (!engine)
-                return false;
-
-        engine->delay = cmd->defer_delay;
-        engine->max_defer_write_retry = cmd->max_defer_write_retry;
-
-        result = true;
-
-        while (index_of_payload < cmd->number_of_payloads) {
-                struct aux_payload *payload = cmd->payloads + index_of_payload;
-                struct i2caux_transaction_request request = { 0 };
-
-                if (cmd->mot == I2C_MOT_UNDEF)
-                        mot = (index_of_payload != cmd->number_of_payloads - 1);
-                else
-                        mot = (cmd->mot == I2C_MOT_TRUE);
-
-                request.operation = payload->write ?
-                        I2CAUX_TRANSACTION_WRITE :
-                        I2CAUX_TRANSACTION_READ;
-
-                if (payload->i2c_over_aux) {
-                        request.payload.address_space =
-                                I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C;
-
-                        request.payload.address = (payload->address << 1) |
-                                !payload->write;
-                } else {
-                        request.payload.address_space =
-                                I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD;
-
-                        request.payload.address = payload->address;
-                }
-
-                request.payload.length = payload->length;
-                request.payload.data = payload->data;
-
-                if (!engine->base.funcs->submit_request(
-                        &engine->base, &request, mot)) {
-                        result = false;
-                        break;
-                }
-
-                ++index_of_payload;
-        }
-
-        i2caux->funcs->release_engine(i2caux, &engine->base);
-
-        return result;
-}
-
-static bool get_hw_supported_ddc_line(
-        struct ddc *ddc,
-        enum gpio_ddc_line *line)
-{
-        enum gpio_ddc_line line_found;
-
-        *line = GPIO_DDC_LINE_UNKNOWN;
-
-        if (!ddc) {
-                BREAK_TO_DEBUGGER();
-                return false;
-        }
-
-        if (!ddc->hw_info.hw_supported)
-                return false;
-
-        line_found = dal_ddc_get_line(ddc);
-
-        if (line_found >= GPIO_DDC_LINE_COUNT)
-                return false;
-
-        *line = line_found;
-
-        return true;
-}
-
-void dal_i2caux_configure_aux(
-        struct i2caux *i2caux,
-        struct ddc *ddc,
-        union aux_config cfg)
-{
-        struct aux_engine *engine =
-                i2caux->funcs->acquire_aux_engine(i2caux, ddc);
-
-        if (!engine)
-                return;
-
-        engine->funcs->configure(engine, cfg);
-
-        i2caux->funcs->release_engine(i2caux, &engine->base);
-}
-
-void dal_i2caux_destroy(
-        struct i2caux **i2caux)
-{
-        if (!i2caux || !*i2caux) {
-                BREAK_TO_DEBUGGER();
-                return;
-        }
-
-        (*i2caux)->funcs->destroy(i2caux);
-
-        *i2caux = NULL;
-}
-
-/*
- * @brief
- * An utility function used by 'struct i2caux' and its descendants
- */
-
-uint32_t dal_i2caux_get_reference_clock(
-                struct dc_bios *bios)
-{
-        struct dc_firmware_info info = { { 0 } };
-
-        if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
-                return 0;
-
-        return info.pll_info.crystal_frequency;
-}
-
-/*
- * @brief
- * i2caux
- */
-
-enum {
-        /* following are expressed in KHz */
-        DEFAULT_I2C_SW_SPEED = 50,
-        DEFAULT_I2C_HW_SPEED = 50,
-
-        DEFAULT_I2C_SW_SPEED_100KHZ = 100,
-        DEFAULT_I2C_HW_SPEED_100KHZ = 100,
-
-        /* This is the timeout as defined in DP 1.2a,
-         * 2.3.4 "Detailed uPacket TX AUX CH State Description". */
-        AUX_TIMEOUT_PERIOD = 400,
-
-        /* Ideally, the SW timeout should be just above 550usec
-         * which is programmed in HW.
-         * But the SW timeout of 600usec is not reliable,
-         * because on some systems, delay_in_microseconds()
-         * returns faster than it should.
-         * EPR #379763: by trial-and-error on different systems,
-         * 700usec is the minimum reliable SW timeout for polling
-         * the AUX_SW_STATUS.AUX_SW_DONE bit.
-         * This timeout expires *only* when there is
-         * AUX Error or AUX Timeout conditions - not during normal operation.
-         * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set
-         * at most within ~240usec. That means,
-         * increasing this timeout will not affect normal operation,
-         * and we'll timeout after
-         * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 1600usec.
-         * This timeout is especially important for
-         * resume from S3 and CTS. */
-        SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 4
-};
-
-struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
-        struct i2caux *i2caux,
-        struct ddc *ddc)
-{
-        enum gpio_ddc_line line;
-        struct i2c_engine *engine = NULL;
-
-        if (get_hw_supported_ddc_line(ddc, &line))
-                engine = i2caux->i2c_sw_engines[line];
-
-        if (!engine)
-                engine = i2caux->i2c_generic_sw_engine;
-
-        if (!engine)
-                return NULL;
-
-        if (!engine->base.funcs->acquire(&engine->base, ddc))
-                return NULL;
-
-        return engine;
-}
-
-struct aux_engine *dal_i2caux_acquire_aux_engine(
-        struct i2caux *i2caux,
-        struct ddc *ddc)
-{
-        enum gpio_ddc_line line;
-        struct aux_engine *engine;
-
-        if (!get_hw_supported_ddc_line(ddc, &line))
-                return NULL;
-
-        engine = i2caux->aux_engines[line];
-
-        if (!engine)
-                return NULL;
-
-        if (!engine->base.funcs->acquire(&engine->base, ddc))
-                return NULL;
-
-        return engine;
-}
-
-void dal_i2caux_release_engine(
-        struct i2caux *i2caux,
-        struct engine *engine)
-{
-        engine->funcs->release_engine(engine);
-
-        dal_ddc_close(engine->ddc);
-
-        engine->ddc = NULL;
-}
-
-void dal_i2caux_construct(
-        struct i2caux *i2caux,
-        struct dc_context *ctx)
-{
-        uint32_t i = 0;
-
-        i2caux->ctx = ctx;
-        do {
-                i2caux->i2c_sw_engines[i] = NULL;
-                i2caux->i2c_hw_engines[i] = NULL;
-                i2caux->aux_engines[i] = NULL;
-
-                ++i;
-        } while (i < GPIO_DDC_LINE_COUNT);
-
-        i2caux->i2c_generic_sw_engine = NULL;
-        i2caux->i2c_generic_hw_engine = NULL;
-
-        i2caux->aux_timeout_period =
-                SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD;
-
-        if (ctx->dce_version >= DCE_VERSION_11_2) {
-                i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED_100KHZ;
-                i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED_100KHZ;
-        } else {
-                i2caux->default_i2c_hw_speed = DEFAULT_I2C_HW_SPEED;
-                i2caux->default_i2c_sw_speed = DEFAULT_I2C_SW_SPEED;
-        }
-}
-
-void dal_i2caux_destruct(
-        struct i2caux *i2caux)
-{
-        uint32_t i = 0;
-
-        if (i2caux->i2c_generic_hw_engine)
-                i2caux->i2c_generic_hw_engine->funcs->destroy(
-                        &i2caux->i2c_generic_hw_engine);
-
-        if (i2caux->i2c_generic_sw_engine)
-                i2caux->i2c_generic_sw_engine->funcs->destroy(
-                        &i2caux->i2c_generic_sw_engine);
-
-        do {
-                if (i2caux->aux_engines[i])
-                        i2caux->aux_engines[i]->funcs->destroy(
-                                &i2caux->aux_engines[i]);
-
-                if (i2caux->i2c_hw_engines[i])
-                        i2caux->i2c_hw_engines[i]->funcs->destroy(
-                                &i2caux->i2c_hw_engines[i]);
-
-                if (i2caux->i2c_sw_engines[i])
-                        i2caux->i2c_sw_engines[i]->funcs->destroy(
-                                &i2caux->i2c_sw_engines[i]);
-
-                ++i;
-        } while (i < GPIO_DDC_LINE_COUNT);
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h
deleted file mode 100644
index 64f51bb06915..000000000000
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#ifndef __DAL_I2C_AUX_H__
-#define __DAL_I2C_AUX_H__
-
-uint32_t dal_i2caux_get_reference_clock(
-        struct dc_bios *bios);
-
-struct i2caux;
-
-struct engine;
-
-struct i2caux_funcs {
-        void (*destroy)(struct i2caux **ptr);
-        struct i2c_engine * (*acquire_i2c_sw_engine)(
-                struct i2caux *i2caux,
-                struct ddc *ddc);
-        struct i2c_engine * (*acquire_i2c_hw_engine)(
-                struct i2caux *i2caux,
-                struct ddc *ddc);
-        struct aux_engine * (*acquire_aux_engine)(
-                struct i2caux *i2caux,
-                struct ddc *ddc);
-        void (*release_engine)(
-                struct i2caux *i2caux,
-                struct engine *engine);
-};
-
-struct i2c_engine;
-struct aux_engine;
-
-struct i2caux {
-        struct dc_context *ctx;
-        const struct i2caux_funcs *funcs;
-        /* On ASIC we have certain amount of lines with HW DDC engine
-         * (4, 6, or maybe more in the future).
-         * For every such line, we create separate HW DDC engine
-         * (since we have these engines in HW) and separate SW DDC engine
-         * (to allow concurrent use of few lines).
-         * In similar way we have AUX engines. */
-
-        /* I2C SW engines, per DDC line.
-         * Only lines with HW DDC support will be initialized */
-        struct i2c_engine *i2c_sw_engines[GPIO_DDC_LINE_COUNT];
-
-        /* I2C HW engines, per DDC line.
-         * Only lines with HW DDC support will be initialized */
-        struct i2c_engine *i2c_hw_engines[GPIO_DDC_LINE_COUNT];
-
-        /* AUX engines, per DDC line.
-         * Only lines with HW AUX support will be initialized */
-        struct aux_engine *aux_engines[GPIO_DDC_LINE_COUNT];
-
-        /* For all other lines, we can use
-         * single instance of generic I2C HW engine
-         * (since in HW, there is single instance of it)
-         * or single instance of generic I2C SW engine.
-         * AUX is not supported for other lines. */
-
-        /* General-purpose I2C SW engine.
-         * Can be assigned dynamically to any line per transaction */
-        struct i2c_engine *i2c_generic_sw_engine;
-
-        /* General-purpose I2C generic HW engine.
-         * Can be assigned dynamically to almost any line per transaction */
-        struct i2c_engine *i2c_generic_hw_engine;
-
-        /* [anaumov] in DAL2, there is a Mutex */
-
-        uint32_t aux_timeout_period;
-
-        /* expressed in KHz */
-        uint32_t default_i2c_sw_speed;
-        uint32_t default_i2c_hw_speed;
-};
-
-void dal_i2caux_construct(
-        struct i2caux *i2caux,
-        struct dc_context *ctx);
-
-void dal_i2caux_release_engine(
-        struct i2caux *i2caux,
-        struct engine *engine);
-
-void dal_i2caux_destruct(
-        struct i2caux *i2caux);
-
-void dal_i2caux_destroy(
-        struct i2caux **ptr);
-
-struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine(
-        struct i2caux *i2caux,
-        struct ddc *ddc);
-
-struct aux_engine *dal_i2caux_acquire_aux_engine(
-        struct i2caux *i2caux,
-        struct ddc *ddc);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
index 47ef90495376..43d1fbd8ace5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h
@@ -78,7 +78,7 @@ struct csdp_ref_clk_ds_params {
 };
 
 struct pixel_clk_params {
-        uint32_t requested_pix_clk; /* in KHz */
+        uint32_t requested_pix_clk_100hz;
 /*> Requested Pixel Clock
  * (based on Video Timing standard used for requested mode)*/
         uint32_t requested_sym_clk; /* in KHz */
@@ -104,9 +104,9 @@ struct pixel_clk_params {
  *  with actually calculated Clock and reference Crystal frequency
  */
 struct pll_settings {
-        uint32_t actual_pix_clk;
-        uint32_t adjusted_pix_clk;
-        uint32_t calculated_pix_clk;
+        uint32_t actual_pix_clk_100hz;
+        uint32_t adjusted_pix_clk_100hz;
+        uint32_t calculated_pix_clk_100hz;
         uint32_t vco_freq;
         uint32_t reference_freq;
         uint32_t reference_divider;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
index 94fc31080fda..2e61a22ef4b2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h
@@ -30,7 +30,7 @@ enum dc_status {
         DC_OK = 1,
 
         DC_NO_CONTROLLER_RESOURCE = 2,
-        DC_NO_STREAM_ENG_RESOURCE = 3,
+        DC_NO_STREAM_ENC_RESOURCE = 3,
         DC_NO_CLOCK_SOURCE_RESOURCE = 4,
         DC_FAIL_CONTROLLER_VALIDATE = 5,
         DC_FAIL_ENC_VALIDATE = 6,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index b168a5e9dd9d..986ed1728644 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -146,7 +146,7 @@ struct resource_pool {
         struct mpc *mpc;
         struct pp_smu_funcs_rv *pp_smu;
         struct pp_smu_display_requirement_rv pp_smu_req;
-        struct aux_engine *engines[MAX_PIPES];
+        struct dce_aux *engines[MAX_PIPES];
         struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
         struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
         bool i2c_hw_buffer_in_use;
@@ -180,13 +180,8 @@ struct resource_pool {
         const struct resource_caps *res_cap;
 };
 
-struct dcn_fe_clocks {
-        int dppclk_khz;
-};
-
 struct dcn_fe_bandwidth {
-        struct dcn_fe_clocks calc;
-        struct dcn_fe_clocks cur;
+        int dppclk_khz;
 };
 
 struct stream_resource {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 538b83303b86..16fd4dc6c4dd 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -64,13 +64,6 @@ void dal_ddc_i2c_payloads_add(
                 uint8_t *data,
                 bool write);
 
-void dal_ddc_aux_payloads_add(
-                struct aux_payloads *payloads,
-                uint32_t address,
-                uint32_t len,
-                uint8_t *data,
-                bool write);
-
 struct ddc_service_init_data {
         struct graphics_object_id id;
         struct dc_context *ctx;
@@ -103,12 +96,10 @@ bool dal_ddc_service_query_ddc_data(
                 uint32_t read_size);
 
 int dc_link_aux_transfer(struct ddc_service *ddc,
-                             unsigned int address,
-                             uint8_t *reply,
-                             void *buffer,
-                             unsigned int size,
-                             enum aux_transaction_type type,
-                             enum i2caux_transaction_action action);
+                struct aux_payload *payload);
+
+bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
+                struct aux_payload *payload);
 
 void dal_ddc_service_write_scdc_data(
                 struct ddc_service *ddc_service,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index 02f757dd70d4..9d2d8e51306c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -39,6 +39,18 @@ enum segment_order {
         segment_order__non_contiguous,
 };
 
+struct dcn_hubbub_wm_set {
+        uint32_t wm_set;
+        uint32_t data_urgent;
+        uint32_t pte_meta_urgent;
+        uint32_t sr_enter;
+        uint32_t sr_exit;
+        uint32_t dram_clk_chanage;
+};
+
+struct dcn_hubbub_wm {
+        struct dcn_hubbub_wm_set sets[4];
+};
 
 struct hubbub_funcs {
         void (*update_dchub)(
@@ -58,7 +70,14 @@ struct hubbub_funcs {
         bool (*dcc_support_pixel_format)(
                         enum surface_pixel_format format,
                         unsigned int *bytes_per_element);
+
+        void (*wm_read_state)(struct hubbub *hubbub,
+                        struct dcn_hubbub_wm *wm);
 };
 
+struct hubbub {
+        const struct hubbub_funcs *funcs;
+        struct dc_context *ctx;
+};
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index cb85eaa9857f..cbaa43853611 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -27,16 +27,22 @@
 
 #include "dm_services_types.h"
 
+/* If HW itself ever powered down it will be 0.
+ * fwDmcuInit will write to 1.
+ * Driver will only call MCP init if current state is 1,
+ * and the MCP command will transition this to 2.
+ */
 enum dmcu_state {
-        DMCU_NOT_INITIALIZED = 0,
-        DMCU_RUNNING = 1
+        DMCU_UNLOADED = 0,
+        DMCU_LOADED_UNINITIALIZED = 1,
+        DMCU_RUNNING = 2,
 };
 
 struct dmcu_version {
-        unsigned int date;
-        unsigned int month;
-        unsigned int year;
         unsigned int interface_version;
+        unsigned int abm_version;
+        unsigned int psr_version;
+        unsigned int build_version;
 };
 
 struct dmcu {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
index e894e649ce5a..fb7967b39edb 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
@@ -39,6 +39,11 @@ struct dpp {
 
 };
 
+struct dpp_input_csc_matrix {
+        enum dc_color_space color_space;
+        uint16_t regval[12];
+};
+
 struct dpp_grph_csc_adjustment {
         struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
         enum graphics_gamut_adjust_type gamut_adjust_type;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 04c6989aac58..1cd07e94ee63 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -78,7 +78,8 @@ struct hubp_funcs {
         bool (*hubp_program_surface_flip_and_addr)(
                 struct hubp *hubp,
                 const struct dc_plane_address *address,
-                bool flip_immediate);
+                bool flip_immediate,
+                uint8_t vmid);
 
         void (*hubp_program_pte_vm)(
                 struct hubp *hubp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 06df02ddff6a..da89c2edb07c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -31,7 +31,7 @@
 #include "dml/display_mode_structs.h"
 
 struct dchub_init_data;
-struct cstate_pstate_watermarks_st1 {
+struct cstate_pstate_watermarks_st {
         uint32_t cstate_exit_ns;
         uint32_t cstate_enter_plus_exit_ns;
         uint32_t pstate_change_ns;
@@ -40,7 +40,7 @@ struct cstate_pstate_watermarks_st1 {
 struct dcn_watermarks {
         uint32_t pte_meta_urgent_ns;
         uint32_t urgent_ns;
-        struct cstate_pstate_watermarks_st1 cstate_pstate;
+        struct cstate_pstate_watermarks_st cstate_pstate;
 };
 
 struct dcn_watermark_set {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 53a9b64df11a..4051493557bc 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -161,6 +161,10 @@ struct stream_encoder_funcs {
         void (*set_avmute)(
                 struct stream_encoder *enc, bool enable);
 
+        void (*dig_connect_to_otg)(
+                struct stream_encoder *enc,
+                int tg_inst);
+
 };
 
 #endif /* STREAM_ENCODER_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/engine_base.c b/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h
index 5d155d36d353..037beb0a2a27 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/engine_base.c
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,30 +23,27 @@
  *
  */
 
-#include "dm_services.h"
+#ifndef DAL_DC_INC_HW_VMID_H_
+#define DAL_DC_INC_HW_VMID_H_
 
-/*
- * Pre-requisites: headers required by header of this unit
- */
-#include "include/i2caux_interface.h"
-
-/*
- * Header of this unit
- */
-
-#include "engine.h"
+#include "core_types.h"
+#include "dchubbub.h"
 
-void dal_i2caux_construct_engine(
-        struct engine *engine,
-        struct dc_context *ctx)
-{
-        engine->ddc = NULL;
-        engine->ctx = ctx;
-}
+struct dcn_vmid_registers {
+        uint32_t CNTL;
+        uint32_t PAGE_TABLE_BASE_ADDR_HI32;
+        uint32_t PAGE_TABLE_BASE_ADDR_LO32;
+        uint32_t PAGE_TABLE_START_ADDR_HI32;
+        uint32_t PAGE_TABLE_START_ADDR_LO32;
+        uint32_t PAGE_TABLE_END_ADDR_HI32;
+        uint32_t PAGE_TABLE_END_ADDR_LO32;
+};
 
-void dal_i2caux_destruct_engine(
-        struct engine *engine)
-{
-        /* nothing to do */
-}
+struct dcn_vmid_page_table_config {
+        uint64_t        page_table_start_addr;
+        uint64_t        page_table_end_addr;
+        enum dcn_hubbub_page_table_depth        depth;
+        enum dcn_hubbub_page_table_block_size   block_size;
+};
 
+#endif /* DAL_DC_INC_HW_VMID_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.h b/drivers/gpu/drm/amd/display/dc/inc/vm_helper.h
index c48c61f540a8..a202206e22a3 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/vm_helper.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,21 +23,33 @@
  *
  */
 
-#ifndef __DAL_I2C_SW_ENGINE_DCE110_H__
-#define __DAL_I2C_SW_ENGINE_DCE110_H__
+#ifndef DC_INC_VM_HELPER_H_
+#define DC_INC_VM_HELPER_H_
 
-struct i2c_sw_engine_dce110 {
-        struct i2c_sw_engine base;
-        uint32_t engine_id;
+#include "dc_types.h"
+
+#define MAX_VMID 16
+#define MAX_HUBP 6
+
+struct vmid_usage {
+        uint16_t vmid_usage[2];
 };
 
-struct i2c_sw_engine_dce110_create_arg {
-        uint32_t engine_id;
-        uint32_t default_speed;
-        struct dc_context *ctx;
+struct vm_helper {
+        unsigned int num_vmid;
+        unsigned int num_hubp;
+        unsigned int num_vmids_available;
+        uint64_t *ptb_assigned_to_vmid;
+        struct vmid_usage *hubp_vmid_usage;
 };
 
-struct i2c_engine *dal_i2c_sw_engine_dce110_create(
-        const struct i2c_sw_engine_dce110_create_arg *arg);
+uint8_t get_vmid_for_ptb(
+                struct vm_helper *vm_helper,
+                int64_t ptb,
+                uint8_t pipe_idx);
+
+struct vm_helper init_vm_helper(
+        unsigned int num_vmid,
+        unsigned int num_hubp);
 
-#endif
+#endif /* DC_INC_VM_HELPER_H_ */
diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
index 7fd78a696800..01bf01a34a08 100644
--- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h
+++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h
@@ -211,8 +211,8 @@ struct bp_pixel_clock_parameters {
         /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
         enum signal_type signal_type;
         /* Adjusted Pixel Clock (after VBIOS exec table)
-         * that becomes Target Pixel Clock (KHz) */
-        uint32_t target_pixel_clock;
+         * that becomes Target Pixel Clock (100 Hz units) */
+        uint32_t target_pixel_clock_100hz;
         /* Calculated Reference divider of Display PLL */
         uint32_t reference_divider;
         /* Calculated Feedback divider of Display PLL */
diff --git a/drivers/gpu/drm/amd/display/include/i2caux_interface.h b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
index 13a3c82d118f..bb012cb1a9f5 100644
--- a/drivers/gpu/drm/amd/display/include/i2caux_interface.h
+++ b/drivers/gpu/drm/amd/display/include/i2caux_interface.h
@@ -40,9 +40,19 @@ struct aux_payload {
         /* set following flag to write data,
          * reset it to read data */
         bool write;
+        bool mot;
         uint32_t address;
         uint8_t length;
         uint8_t *data;
+        /*
+         * used to return the reply type of the transaction
+         * ignored if NULL
+         */
+        uint8_t *reply;
+        /* expressed in milliseconds
+         * zero means "use default value"
+         */
+        uint32_t defer_delay;
 };
 
 struct aux_command {
@@ -66,27 +76,4 @@ union aux_config {
         uint32_t raw;
 };
 
-struct i2caux;
-
-struct i2caux *dal_i2caux_create(
-        struct dc_context *ctx);
-
-bool dal_i2caux_submit_i2c_command(
-        struct i2caux *i2caux,
-        struct ddc *ddc,
-        struct i2c_command *cmd);
-
-bool dal_i2caux_submit_aux_command(
-        struct i2caux *i2caux,
-        struct ddc *ddc,
-        struct aux_command *cmd);
-
-void dal_i2caux_configure_aux(
-        struct i2caux *i2caux,
-        struct ddc *ddc,
-        union aux_config cfg);
-
-void dal_i2caux_destroy(
-        struct i2caux **ptr);
-
 #endif
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 479b77c2e89e..eefb85928298 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -823,7 +823,7 @@ static bool build_freesync_hdr(struct pwl_float_data_ex *rgb_regamma,
         bool is_clipped = false;
         struct fixed31_32 sdr_white_level;
 
-        if (fs_params == NULL || fs_params->max_content == 0 ||
+        if (fs_params->max_content == 0 ||
                         fs_params->max_display == 0)
                 return false;
 
@@ -1508,7 +1508,7 @@ static bool map_regamma_hw_to_x_user(
         struct hw_x_point *coords = coords_x;
         const struct pwl_float_data_ex *regamma = rgb_regamma;
 
-        if (mapUserRamp) {
+        if (ramp && mapUserRamp) {
                 copy_rgb_regamma_to_coordinates_x(coords,
                                 hw_points_num,
                                 rgb_regamma);
@@ -1545,7 +1545,7 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 
         struct pwl_float_data *rgb_user = NULL;
         struct pwl_float_data_ex *rgb_regamma = NULL;
-        struct gamma_pixel *axix_x = NULL;
+        struct gamma_pixel *axis_x = NULL;
         struct pixel_gamma_point *coeff = NULL;
         enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
         bool ret = false;
@@ -1555,47 +1555,54 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 
         /* we can use hardcoded curve for plain SRGB TF */
         if (output_tf->type == TF_TYPE_PREDEFINED && canRomBeUsed == true &&
-                        output_tf->tf == TRANSFER_FUNCTION_SRGB &&
-                        (ramp->is_identity || (!mapUserRamp && ramp->type == GAMMA_RGB_256)))
-                return true;
+                        output_tf->tf == TRANSFER_FUNCTION_SRGB) {
+                if (ramp == NULL)
+                        return true;
+                if (ramp->is_identity || (!mapUserRamp && ramp->type == GAMMA_RGB_256))
+                        return true;
+        }
 
         output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
 
-        rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
+        if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
+                rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
                             sizeof(*rgb_user),
                             GFP_KERNEL);
-        if (!rgb_user)
-                goto rgb_user_alloc_fail;
+                if (!rgb_user)
+                        goto rgb_user_alloc_fail;
+
+                axis_x = kvcalloc(ramp->num_entries + 3, sizeof(*axis_x),
+                                GFP_KERNEL);
+                if (!axis_x)
+                        goto axis_x_alloc_fail;
+
+                dividers.divider1 = dc_fixpt_from_fraction(3, 2);
+                dividers.divider2 = dc_fixpt_from_int(2);
+                dividers.divider3 = dc_fixpt_from_fraction(5, 2);
+
+                build_evenly_distributed_points(
+                                axis_x,
+                                ramp->num_entries,
+                                dividers);
+
+                if (ramp->type == GAMMA_RGB_256 && mapUserRamp)
+                        scale_gamma(rgb_user, ramp, dividers);
+                else if (ramp->type == GAMMA_RGB_FLOAT_1024)
+                        scale_gamma_dx(rgb_user, ramp, dividers);
+        }
+
         rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
                                sizeof(*rgb_regamma),
                                GFP_KERNEL);
         if (!rgb_regamma)
                 goto rgb_regamma_alloc_fail;
-        axix_x = kvcalloc(ramp->num_entries + 3, sizeof(*axix_x),
-                          GFP_KERNEL);
-        if (!axix_x)
-                goto axix_x_alloc_fail;
+
         coeff = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS, sizeof(*coeff),
                          GFP_KERNEL);
         if (!coeff)
                 goto coeff_alloc_fail;
 
-        dividers.divider1 = dc_fixpt_from_fraction(3, 2);
-        dividers.divider2 = dc_fixpt_from_int(2);
-        dividers.divider3 = dc_fixpt_from_fraction(5, 2);
-
         tf = output_tf->tf;
-
-        build_evenly_distributed_points(
-                        axix_x,
-                        ramp->num_entries,
-                        dividers);
-
-        if (ramp->type == GAMMA_RGB_256 && mapUserRamp)
-                scale_gamma(rgb_user, ramp, dividers);
-        else if (ramp->type == GAMMA_RGB_FLOAT_1024)
-                scale_gamma_dx(rgb_user, ramp, dividers);
-
         if (tf == TRANSFER_FUNCTION_PQ) {
                 tf_pts->end_exponent = 7;
                 tf_pts->x_point_at_y1_red = 125;
@@ -1623,22 +1630,22 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
                                 coordinates_x, tf == TRANSFER_FUNCTION_SRGB ? true:false);
         }
         map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
-                        coordinates_x, axix_x, rgb_regamma,
+                        coordinates_x, axis_x, rgb_regamma,
                         MAX_HW_POINTS, tf_pts,
-                        (mapUserRamp || ramp->type != GAMMA_RGB_256) &&
-                        ramp->type != GAMMA_CS_TFM_1D);
+                        (mapUserRamp || (ramp && ramp->type != GAMMA_RGB_256)) &&
+                        (ramp && ramp->type != GAMMA_CS_TFM_1D));
 
-        if (ramp->type == GAMMA_CS_TFM_1D)
+        if (ramp && ramp->type == GAMMA_CS_TFM_1D)
                 apply_lut_1d(ramp, MAX_HW_POINTS, tf_pts);
 
         ret = true;
 
         kvfree(coeff);
 coeff_alloc_fail:
-        kvfree(axix_x);
-axix_x_alloc_fail:
         kvfree(rgb_regamma);
 rgb_regamma_alloc_fail:
+        kvfree(axis_x);
+axis_x_alloc_fail:
         kvfree(rgb_user);
 rgb_user_alloc_fail:
         return ret;
@@ -1772,8 +1779,7 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
         /* we can use hardcoded curve for plain SRGB TF */
         if (input_tf->type == TF_TYPE_PREDEFINED &&
                         input_tf->tf == TRANSFER_FUNCTION_SRGB &&
-                        (!mapUserRamp &&
-                        (ramp->type == GAMMA_RGB_256 || ramp->num_entries == 0)))
+                        !mapUserRamp)
                 return true;
 
         input_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 1544ed3f1747..94a84bc57c7a 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -108,8 +108,8 @@ static unsigned int calc_duration_in_us_from_v_total(
 {
         unsigned int duration_in_us =
                         (unsigned int)(div64_u64(((unsigned long long)(v_total)
-                                * 1000) * stream->timing.h_total,
-                                        stream->timing.pix_clk_khz));
+                                * 10000) * stream->timing.h_total,
+                                        stream->timing.pix_clk_100hz));
 
         return duration_in_us;
 }
@@ -126,7 +126,7 @@ static unsigned int calc_v_total_from_refresh(
                                         refresh_in_uhz)));
 
         v_total = div64_u64(div64_u64(((unsigned long long)(
-                        frame_duration_in_ns) * stream->timing.pix_clk_khz),
+                        frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
                         stream->timing.h_total), 1000000);
 
         /* v_total cannot be less than nominal */
@@ -152,7 +152,7 @@ static unsigned int calc_v_total_from_duration(
                 duration_in_us = vrr->max_duration_in_us;
 
         v_total = div64_u64(div64_u64(((unsigned long long)(
-                                duration_in_us) * stream->timing.pix_clk_khz),
+                                duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
                                 stream->timing.h_total), 1000);
 
         /* v_total cannot be less than nominal */
@@ -227,7 +227,7 @@ static void update_v_total_for_static_ramp(
         }
 
         v_total = div64_u64(div64_u64(((unsigned long long)(
-                        current_duration_in_us) * stream->timing.pix_clk_khz),
+                        current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
                                 stream->timing.h_total), 1000);
 
         in_out_vrr->adjust.v_total_min = v_total;
@@ -461,6 +461,26 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
         return false;
 }
 
+static void build_vrr_infopacket_header_vtem(enum signal_type signal,
+                struct dc_info_packet *infopacket)
+{
+        // HEADER
+
+        // HB0, HB1, HB2 indicates PacketType VTEMPacket
+        infopacket->hb0 = 0x7F;
+        infopacket->hb1 = 0xC0;
+        infopacket->hb2 = 0x00;
+        /* HB3 Bit Fields
+         * Reserved :1 = 0
+         * Sync     :1 = 0
+         * VFR      :1 = 1
+         * Ds_Type  :2 = 0
+         * End      :1 = 0
+         * New      :1 = 0
+         */
+        infopacket->hb3 = 0x20;
+}
+
 static void build_vrr_infopacket_header_v1(enum signal_type signal,
                 struct dc_info_packet *infopacket,
                 unsigned int *payload_size)
@@ -559,6 +579,54 @@ static void build_vrr_infopacket_header_v2(enum signal_type signal,
         }
 }
 
+static void build_vrr_vtem_infopacket_data(const struct dc_stream_state *stream,
+                const struct mod_vrr_params *vrr,
+                struct dc_info_packet *infopacket)
+{
+        /* dc_info_packet to VtemPacket Translation of Bit-fields,
+         * SB[6]
+         * unsigned char VRR_EN        :1
+         * unsigned char M_CONST       :1
+         * unsigned char Reserved2     :2
+         * unsigned char FVA_Factor_M1 :4
+         * SB[7]
+         * unsigned char Base_Vfront   :8
+         * SB[8]
+         * unsigned char Base_Refresh_Rate_98 :2
+         * unsigned char RB                   :1
+         * unsigned char Reserved3            :5
+         * SB[9]
+         * unsigned char Base_RefreshRate_07  :8
+         */
+        unsigned int fieldRateInHz;
+
+        if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+                                vrr->state == VRR_STATE_ACTIVE_FIXED){
+                infopacket->sb[6] |= 0x80; //VRR_EN Bit = 1
+        } else {
+                infopacket->sb[6] &= 0x7F; //VRR_EN Bit = 0
+        }
+
+        if (!stream->timing.vic) {
+                infopacket->sb[7] = stream->timing.v_front_porch;
+
+                /* TODO: In dal2, we check mode flags for a reduced blanking timing.
+                 * Need a way to relay that information to this function.
+                 * if("ReducedBlanking")
+                 * {
+                 *   infopacket->sb[8] |= 0x20; //Set 3rd bit to 1
+                 * }
+                 */
+                fieldRateInHz = (stream->timing.pix_clk_100hz * 100)/
+                                (stream->timing.h_total * stream->timing.v_total);
+
+                infopacket->sb[8] |= ((fieldRateInHz & 0x300) >> 2);
+                infopacket->sb[9] |= fieldRateInHz & 0xFF;
+
+        }
+        infopacket->valid = true;
+}
+
 static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
                 struct dc_info_packet *infopacket)
 {
@@ -672,6 +740,19 @@ static void build_vrr_infopacket_v2(enum signal_type signal,
         infopacket->valid = true;
 }
 
+static void build_vrr_infopacket_vtem(const struct dc_stream_state *stream,
+                const struct mod_vrr_params *vrr,
+                struct dc_info_packet *infopacket)
+{
+        //VTEM info packet for HdmiVrr
+
+        //VTEM Packet is structured differently
+        build_vrr_infopacket_header_vtem(stream->signal, infopacket);
+        build_vrr_vtem_infopacket_data(stream, vrr, infopacket);
+
+        infopacket->valid = true;
+}
+
 void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
                 const struct dc_stream_state *stream,
                 const struct mod_vrr_params *vrr,
@@ -679,18 +760,21 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
                 const enum color_transfer_func *app_tf,
                 struct dc_info_packet *infopacket)
 {
-        /* SPD info packet for FreeSync */
-
-        /* Check if Freesync is supported. Return if false. If true,
+        /* SPD info packet for FreeSync
+         * VTEM info packet for HdmiVRR
+         * Check if Freesync is supported. Return if false. If true,
          * set the corresponding bit in the info packet
          */
-        if (!vrr->supported || !vrr->send_vsif)
+        if (!vrr->supported || (!vrr->send_info_frame && packet_type != PACKET_TYPE_VTEM))
                 return;
 
         switch (packet_type) {
         case PACKET_TYPE_FS2:
                 build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket);
                 break;
+        case PACKET_TYPE_VTEM:
+                build_vrr_infopacket_vtem(stream, vrr, infopacket);
+                break;
         case PACKET_TYPE_VRR:
         case PACKET_TYPE_FS1:
         default:
@@ -739,7 +823,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
                 return;
 
         in_out_vrr->state = in_config->state;
-        in_out_vrr->send_vsif = in_config->vsif_supported;
+        in_out_vrr->send_info_frame = in_config->vsif_supported;
 
         if (in_config->state == VRR_STATE_UNSUPPORTED) {
                 in_out_vrr->state = VRR_STATE_UNSUPPORTED;
@@ -972,7 +1056,7 @@ unsigned long long mod_freesync_calc_nominal_field_rate(
         unsigned long long nominal_field_rate_in_uhz = 0;
 
         /* Calculate nominal field rate for stream */
-        nominal_field_rate_in_uhz = stream->timing.pix_clk_khz;
+        nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz / 10;
         nominal_field_rate_in_uhz *= 1000ULL * 1000ULL * 1000ULL;
         nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz,
                                                 stream->timing.h_total);
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index 949a8b62aa98..4222e403b151 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -104,7 +104,7 @@ struct mod_vrr_params_fixed_refresh {
 
 struct mod_vrr_params {
         bool supported;
-        bool send_vsif;
+        bool send_info_frame;
         enum mod_vrr_state state;
 
         uint32_t min_refresh_in_uhz;
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
index 1bd02c0ac30c..b711e7e6c204 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_shared.h
@@ -41,7 +41,8 @@ enum color_transfer_func {
 enum vrr_packet_type {
         PACKET_TYPE_VRR,
         PACKET_TYPE_FS1,
-        PACKET_TYPE_FS2
+        PACKET_TYPE_FS2,
+        PACKET_TYPE_VTEM
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 00f63b7dd32f..baab6c4ae191 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -41,6 +41,17 @@ static const unsigned char min_reduction_table[13] = {
 static const unsigned char max_reduction_table[13] = {
 0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32};
 
+/* ABM 2.2 Min Reduction effectively disabled (100% for all configs)*/
+static const unsigned char min_reduction_table_v_2_2[13] = {
+0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+/* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive
+ *  0    1     2     3     4     5     6     7     8     9     10    11   12
+ * 96.1 89.8 85.1  80.3  69.4  64.7  54.9  45.1  30.2  25.1  19.6  12.5  12.5 %
+ */
+static const unsigned char max_reduction_table_v_2_2[13] = {
+0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0x8c, 0x73, 0x4d, 0x40, 0x32, 0x20, 0x20};
+
 /* Predefined ABM configuration sets. We may have different configuration sets
  * in order to satisfy different power/quality requirements.
  */
@@ -56,7 +67,10 @@ static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_le
 #define NUM_AGGR_LEVEL    4
 #define NUM_POWER_FN_SEGS 8
 #define NUM_BL_CURVE_SEGS 16
+#define IRAM_RESERVE_AREA_START 0xF0  // reserve 0xF0~0xFF are write by DMCU only
+#define IRAM_SIZE 256
 
+#pragma pack(push, 1)
 /* NOTE: iRAM is 256B in size */
 struct iram_table_v_2 {
         /* flags                      */
@@ -85,11 +99,10 @@ struct iram_table_v_2 {
 
         /* For reading PSR State directly from IRAM */
         uint8_t psr_state;                                              /* 0xf0       */
-        uint8_t dmcu_interface_version;                                 /* 0xf1       */
-        uint8_t dmcu_date_version_year_b0;                              /* 0xf2       */
-        uint8_t dmcu_date_version_year_b1;                              /* 0xf3       */
-        uint8_t dmcu_date_version_month;                                /* 0xf4       */
-        uint8_t dmcu_date_version_day;                                  /* 0xf5       */
+        uint8_t dmcu_mcp_interface_version;                                                     /* 0xf1       */
+        uint8_t dmcu_abm_feature_version;                                                       /* 0xf2       */
+        uint8_t dmcu_psr_feature_version;                                                       /* 0xf3       */
+        uint16_t dmcu_version;                                                                          /* 0xf4       */
         uint8_t dmcu_state;                                             /* 0xf6       */
 
         uint16_t blRampReduction;                                       /* 0xf7       */
@@ -101,6 +114,50 @@ struct iram_table_v_2 {
         uint8_t dummy9;                                                 /* 0xff       */
 };
 
+struct iram_table_v_2_2 {
+        /* flags                      */
+        uint16_t flags;                                                 /* 0x00 U16  */
+
+        /* parameters for ABM2.2 algorithm */
+        uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x02 U0.8 */
+        uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x16 U0.8 */
+        uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];        /* 0x2a U2.6 */
+        uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];          /* 0x3e U2.6 */
+        uint8_t hybridFactor[NUM_AGGR_LEVEL];                                           /* 0x52 U0.8 */
+        uint8_t contrastFactor[NUM_AGGR_LEVEL];                                         /* 0x56 U0.8 */
+        uint8_t deviation_gain[NUM_AGGR_LEVEL];                                         /* 0x5a U0.8 */
+        uint8_t iir_curve[NUM_AMBI_LEVEL];                                                      /* 0x5e U0.8 */
+        uint8_t pad[29];                                                                                        /* 0x63 U0.8 */
+
+        /* parameters for crgb conversion */
+        uint16_t crgb_thresh[NUM_POWER_FN_SEGS];                                        /* 0x80 U3.13 */
+        uint16_t crgb_offset[NUM_POWER_FN_SEGS];                                        /* 0x90 U1.15 */
+        uint16_t crgb_slope[NUM_POWER_FN_SEGS];                                         /* 0xa0 U4.12 */
+
+        /* parameters for custom curve */
+        /* thresholds for brightness --> backlight */
+        uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS];                       /* 0xb0 U16.0 */
+        /* offsets for brightness --> backlight */
+        uint16_t backlight_offsets[NUM_BL_CURVE_SEGS];                          /* 0xd0 U16.0 */
+
+        /* For reading PSR State directly from IRAM */
+        uint8_t psr_state;                                                                                      /* 0xf0       */
+        uint8_t dmcu_mcp_interface_version;                                                     /* 0xf1       */
+        uint8_t dmcu_abm_feature_version;                                                       /* 0xf2       */
+        uint8_t dmcu_psr_feature_version;                                                       /* 0xf3       */
+        uint16_t dmcu_version;                                                                          /* 0xf4       */
+        uint8_t dmcu_state;                                                                                     /* 0xf6       */
+
+        uint16_t blRampReduction;                                                                       /* 0xf7       */
+        uint16_t blRampStart;                                                                           /* 0xf9       */
+        uint8_t dummy5;                                                                                         /* 0xfb       */
+        uint8_t dummy6;                                                                                         /* 0xfc       */
+        uint8_t dummy7;                                                                                         /* 0xfd       */
+        uint8_t dummy8;                                                                                         /* 0xfe       */
+        uint8_t dummy9;                                                                                         /* 0xff       */
+};
+#pragma pack(pop)
+
 static uint16_t backlight_8_to_16(unsigned int backlight_8bit)
 {
         return (uint16_t)(backlight_8bit * 0x101);
@@ -143,11 +200,367 @@ static void fill_backlight_transform_table(struct dmcu_iram_parameters params,
         }
 }
 
+static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params,
+                struct iram_table_v_2_2 *table)
+{
+        unsigned int i;
+        unsigned int num_entries = NUM_BL_CURVE_SEGS;
+        unsigned int query_input_8bit;
+        unsigned int query_output_8bit;
+        unsigned int lut_index;
+
+        table->backlight_thresholds[0] = 0;
+        table->backlight_offsets[0] = params.backlight_lut_array[0];
+        table->backlight_thresholds[num_entries-1] = 0xFFFF;
+        table->backlight_offsets[num_entries-1] =
+                params.backlight_lut_array[params.backlight_lut_array_size - 1];
+
+        /* Setup all brightness levels between 0% and 100% exclusive
+         * Fills brightness-to-backlight transform table. Backlight custom curve
+         * describes transform from brightness to backlight. It will be defined
+         * as set of thresholds and set of offsets, together, implying
+         * extrapolation of custom curve into 16 uniformly spanned linear
+         * segments.  Each threshold/offset represented by 16 bit entry in
+         * format U4.10.
+         */
+        for (i = 1; i+1 < num_entries; i++) {
+                query_input_8bit = DIV_ROUNDUP((i * 256), num_entries);
+
+                lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1);
+                ASSERT(lut_index < params.backlight_lut_array_size);
+                query_output_8bit = params.backlight_lut_array[lut_index] >> 8;
+
+                table->backlight_thresholds[i] =
+                                backlight_8_to_16(query_input_8bit);
+                table->backlight_offsets[i] =
+                                backlight_8_to_16(query_output_8bit);
+        }
+}
+
+void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params)
+{
+        unsigned int set = params.set;
+
+        ram_table->flags = 0x0;
+        ram_table->deviation_gain = 0xb3;
+
+        ram_table->blRampReduction =
+                cpu_to_be16(params.backlight_ramping_reduction);
+        ram_table->blRampStart =
+                cpu_to_be16(params.backlight_ramping_start);
+
+        ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]];
+        ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]];
+        ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]];
+        ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]];
+        ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]];
+        ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]];
+        ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]];
+        ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]];
+        ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]];
+        ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]];
+
+        ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]];
+        ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]];
+        ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]];
+        ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]];
+        ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]];
+        ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]];
+        ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]];
+        ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]];
+        ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]];
+        ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]];
+
+        ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]];
+        ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]];
+        ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]];
+        ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]];
+        ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]];
+        ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]];
+        ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]];
+        ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]];
+        ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]];
+        ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]];
+
+        ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]];
+        ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]];
+        ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]];
+        ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]];
+        ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]];
+        ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]];
+        ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]];
+        ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]];
+        ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]];
+        ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]];
+
+        ram_table->bright_pos_gain[0][0] = 0x20;
+        ram_table->bright_pos_gain[0][1] = 0x20;
+        ram_table->bright_pos_gain[0][2] = 0x20;
+        ram_table->bright_pos_gain[0][3] = 0x20;
+        ram_table->bright_pos_gain[1][0] = 0x20;
+        ram_table->bright_pos_gain[1][1] = 0x20;
+        ram_table->bright_pos_gain[1][2] = 0x20;
+        ram_table->bright_pos_gain[1][3] = 0x20;
+        ram_table->bright_pos_gain[2][0] = 0x20;
+        ram_table->bright_pos_gain[2][1] = 0x20;
+        ram_table->bright_pos_gain[2][2] = 0x20;
+        ram_table->bright_pos_gain[2][3] = 0x20;
+        ram_table->bright_pos_gain[3][0] = 0x20;
+        ram_table->bright_pos_gain[3][1] = 0x20;
+        ram_table->bright_pos_gain[3][2] = 0x20;
+        ram_table->bright_pos_gain[3][3] = 0x20;
+        ram_table->bright_pos_gain[4][0] = 0x20;
+        ram_table->bright_pos_gain[4][1] = 0x20;
+        ram_table->bright_pos_gain[4][2] = 0x20;
+        ram_table->bright_pos_gain[4][3] = 0x20;
+        ram_table->bright_neg_gain[0][1] = 0x00;
+        ram_table->bright_neg_gain[0][2] = 0x00;
+        ram_table->bright_neg_gain[0][3] = 0x00;
+        ram_table->bright_neg_gain[1][0] = 0x00;
+        ram_table->bright_neg_gain[1][1] = 0x00;
+        ram_table->bright_neg_gain[1][2] = 0x00;
+        ram_table->bright_neg_gain[1][3] = 0x00;
+        ram_table->bright_neg_gain[2][0] = 0x00;
+        ram_table->bright_neg_gain[2][1] = 0x00;
+        ram_table->bright_neg_gain[2][2] = 0x00;
+        ram_table->bright_neg_gain[2][3] = 0x00;
+        ram_table->bright_neg_gain[3][0] = 0x00;
+        ram_table->bright_neg_gain[3][1] = 0x00;
+        ram_table->bright_neg_gain[3][2] = 0x00;
+        ram_table->bright_neg_gain[3][3] = 0x00;
+        ram_table->bright_neg_gain[4][0] = 0x00;
+        ram_table->bright_neg_gain[4][1] = 0x00;
+        ram_table->bright_neg_gain[4][2] = 0x00;
+        ram_table->bright_neg_gain[4][3] = 0x00;
+        ram_table->dark_pos_gain[0][0] = 0x00;
+        ram_table->dark_pos_gain[0][1] = 0x00;
+        ram_table->dark_pos_gain[0][2] = 0x00;
+        ram_table->dark_pos_gain[0][3] = 0x00;
+        ram_table->dark_pos_gain[1][0] = 0x00;
+        ram_table->dark_pos_gain[1][1] = 0x00;
+        ram_table->dark_pos_gain[1][2] = 0x00;
+        ram_table->dark_pos_gain[1][3] = 0x00;
+        ram_table->dark_pos_gain[2][0] = 0x00;
+        ram_table->dark_pos_gain[2][1] = 0x00;
+        ram_table->dark_pos_gain[2][2] = 0x00;
+        ram_table->dark_pos_gain[2][3] = 0x00;
+        ram_table->dark_pos_gain[3][0] = 0x00;
+        ram_table->dark_pos_gain[3][1] = 0x00;
+        ram_table->dark_pos_gain[3][2] = 0x00;
+        ram_table->dark_pos_gain[3][3] = 0x00;
+        ram_table->dark_pos_gain[4][0] = 0x00;
+        ram_table->dark_pos_gain[4][1] = 0x00;
+        ram_table->dark_pos_gain[4][2] = 0x00;
+        ram_table->dark_pos_gain[4][3] = 0x00;
+        ram_table->dark_neg_gain[0][0] = 0x00;
+        ram_table->dark_neg_gain[0][1] = 0x00;
+        ram_table->dark_neg_gain[0][2] = 0x00;
+        ram_table->dark_neg_gain[0][3] = 0x00;
+        ram_table->dark_neg_gain[1][0] = 0x00;
+        ram_table->dark_neg_gain[1][1] = 0x00;
+        ram_table->dark_neg_gain[1][2] = 0x00;
+        ram_table->dark_neg_gain[1][3] = 0x00;
+        ram_table->dark_neg_gain[2][0] = 0x00;
+        ram_table->dark_neg_gain[2][1] = 0x00;
+        ram_table->dark_neg_gain[2][2] = 0x00;
+        ram_table->dark_neg_gain[2][3] = 0x00;
+        ram_table->dark_neg_gain[3][0] = 0x00;
+        ram_table->dark_neg_gain[3][1] = 0x00;
+        ram_table->dark_neg_gain[3][2] = 0x00;
+        ram_table->dark_neg_gain[3][3] = 0x00;
+        ram_table->dark_neg_gain[4][0] = 0x00;
+        ram_table->dark_neg_gain[4][1] = 0x00;
+        ram_table->dark_neg_gain[4][2] = 0x00;
+        ram_table->dark_neg_gain[4][3] = 0x00;
+
+        ram_table->iir_curve[0] = 0x65;
+        ram_table->iir_curve[1] = 0x65;
+        ram_table->iir_curve[2] = 0x65;
+        ram_table->iir_curve[3] = 0x65;
+        ram_table->iir_curve[4] = 0x65;
+
+        //Gamma 2.4
+        ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6);
+        ram_table->crgb_thresh[1] = cpu_to_be16(0x1648);
+        ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3);
+        ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41);
+        ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46);
+        ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21);
+        ram_table->crgb_thresh[6] = cpu_to_be16(0x2167);
+        ram_table->crgb_thresh[7] = cpu_to_be16(0x2384);
+        ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
+        ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
+        ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
+        ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
+        ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
+        ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
+        ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
+        ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
+        ram_table->crgb_slope[0]  = cpu_to_be16(0x3147);
+        ram_table->crgb_slope[1]  = cpu_to_be16(0x2978);
+        ram_table->crgb_slope[2]  = cpu_to_be16(0x23a2);
+        ram_table->crgb_slope[3]  = cpu_to_be16(0x1f55);
+        ram_table->crgb_slope[4]  = cpu_to_be16(0x1c63);
+        ram_table->crgb_slope[5]  = cpu_to_be16(0x1a0f);
+        ram_table->crgb_slope[6]  = cpu_to_be16(0x178d);
+        ram_table->crgb_slope[7]  = cpu_to_be16(0x15ab);
+
+        fill_backlight_transform_table(
+                        params, ram_table);
+}
+
+void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
+{
+        unsigned int set = params.set;
+
+        ram_table->flags = 0x0;
+
+        ram_table->deviation_gain[0] = 0xb3;
+        ram_table->deviation_gain[1] = 0xb3;
+        ram_table->deviation_gain[2] = 0xb3;
+        ram_table->deviation_gain[3] = 0xb3;
+
+        ram_table->blRampReduction =
+                cpu_to_be16(params.backlight_ramping_reduction);
+        ram_table->blRampStart =
+                cpu_to_be16(params.backlight_ramping_start);
+
+        ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+        ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]];
+
+        ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+        ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]];
+
+        ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+        ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]];
+
+        ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+        ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]];
+
+        ram_table->bright_pos_gain[0][0] = 0x20;
+        ram_table->bright_pos_gain[0][1] = 0x20;
+        ram_table->bright_pos_gain[0][2] = 0x20;
+        ram_table->bright_pos_gain[0][3] = 0x20;
+        ram_table->bright_pos_gain[1][0] = 0x20;
+        ram_table->bright_pos_gain[1][1] = 0x20;
+        ram_table->bright_pos_gain[1][2] = 0x20;
+        ram_table->bright_pos_gain[1][3] = 0x20;
+        ram_table->bright_pos_gain[2][0] = 0x20;
+        ram_table->bright_pos_gain[2][1] = 0x20;
+        ram_table->bright_pos_gain[2][2] = 0x20;
+        ram_table->bright_pos_gain[2][3] = 0x20;
+        ram_table->bright_pos_gain[3][0] = 0x20;
+        ram_table->bright_pos_gain[3][1] = 0x20;
+        ram_table->bright_pos_gain[3][2] = 0x20;
+        ram_table->bright_pos_gain[3][3] = 0x20;
+        ram_table->bright_pos_gain[4][0] = 0x20;
+        ram_table->bright_pos_gain[4][1] = 0x20;
+        ram_table->bright_pos_gain[4][2] = 0x20;
+        ram_table->bright_pos_gain[4][3] = 0x20;
+
+        ram_table->dark_pos_gain[0][0] = 0x00;
+        ram_table->dark_pos_gain[0][1] = 0x00;
+        ram_table->dark_pos_gain[0][2] = 0x00;
+        ram_table->dark_pos_gain[0][3] = 0x00;
+        ram_table->dark_pos_gain[1][0] = 0x00;
+        ram_table->dark_pos_gain[1][1] = 0x00;
+        ram_table->dark_pos_gain[1][2] = 0x00;
+        ram_table->dark_pos_gain[1][3] = 0x00;
+        ram_table->dark_pos_gain[2][0] = 0x00;
+        ram_table->dark_pos_gain[2][1] = 0x00;
+        ram_table->dark_pos_gain[2][2] = 0x00;
+        ram_table->dark_pos_gain[2][3] = 0x00;
+        ram_table->dark_pos_gain[3][0] = 0x00;
+        ram_table->dark_pos_gain[3][1] = 0x00;
+        ram_table->dark_pos_gain[3][2] = 0x00;
+        ram_table->dark_pos_gain[3][3] = 0x00;
+        ram_table->dark_pos_gain[4][0] = 0x00;
+        ram_table->dark_pos_gain[4][1] = 0x00;
+        ram_table->dark_pos_gain[4][2] = 0x00;
+        ram_table->dark_pos_gain[4][3] = 0x00;
+
+        ram_table->hybridFactor[0] = 0xff;
+        ram_table->hybridFactor[1] = 0xff;
+        ram_table->hybridFactor[2] = 0xff;
+        ram_table->hybridFactor[3] = 0xc0;
+
+        ram_table->contrastFactor[0] = 0x99;
+        ram_table->contrastFactor[1] = 0x99;
+        ram_table->contrastFactor[2] = 0x99;
+        ram_table->contrastFactor[3] = 0x80;
+
+        ram_table->iir_curve[0] = 0x65;
+        ram_table->iir_curve[1] = 0x65;
+        ram_table->iir_curve[2] = 0x65;
+        ram_table->iir_curve[3] = 0x65;
+        ram_table->iir_curve[4] = 0x65;
+
+        //Gamma 2.2
+        ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
+        ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
+        ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
+        ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
+        ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
+        ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
+        ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
+        ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
+        ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
+        ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
+        ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
+        ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
+        ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
+        ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
+        ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
+        ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
+        ram_table->crgb_slope[0]  = cpu_to_be16(0x3609);
+        ram_table->crgb_slope[1]  = cpu_to_be16(0x2dfa);
+        ram_table->crgb_slope[2]  = cpu_to_be16(0x27ea);
+        ram_table->crgb_slope[3]  = cpu_to_be16(0x235d);
+        ram_table->crgb_slope[4]  = cpu_to_be16(0x2042);
+        ram_table->crgb_slope[5]  = cpu_to_be16(0x1dc3);
+        ram_table->crgb_slope[6]  = cpu_to_be16(0x1b1a);
+        ram_table->crgb_slope[7]  = cpu_to_be16(0x1910);
+
+        fill_backlight_transform_table_v_2_2(
+                        params, ram_table);
+}
+
 bool dmcu_load_iram(struct dmcu *dmcu,
         struct dmcu_iram_parameters params)
 {
-        struct iram_table_v_2 ram_table;
-        unsigned int set = params.set;
+        unsigned char ram_table[IRAM_SIZE];
 
         if (dmcu == NULL)
                 return false;
@@ -157,170 +570,12 @@ bool dmcu_load_iram(struct dmcu *dmcu,
 
         memset(&ram_table, 0, sizeof(ram_table));
 
-        ram_table.flags = 0x0;
-        ram_table.deviation_gain = 0xb3;
-
-        ram_table.blRampReduction =
-                cpu_to_be16(params.backlight_ramping_reduction);
-        ram_table.blRampStart =
-                cpu_to_be16(params.backlight_ramping_start);
-
-        ram_table.min_reduction[0][0] = min_reduction_table[abm_config[set][0]];
-        ram_table.min_reduction[1][0] = min_reduction_table[abm_config[set][0]];
-        ram_table.min_reduction[2][0] = min_reduction_table[abm_config[set][0]];
-        ram_table.min_reduction[3][0] = min_reduction_table[abm_config[set][0]];
-        ram_table.min_reduction[4][0] = min_reduction_table[abm_config[set][0]];
-        ram_table.max_reduction[0][0] = max_reduction_table[abm_config[set][0]];
-        ram_table.max_reduction[1][0] = max_reduction_table[abm_config[set][0]];
-        ram_table.max_reduction[2][0] = max_reduction_table[abm_config[set][0]];
-        ram_table.max_reduction[3][0] = max_reduction_table[abm_config[set][0]];
-        ram_table.max_reduction[4][0] = max_reduction_table[abm_config[set][0]];
-
-        ram_table.min_reduction[0][1] = min_reduction_table[abm_config[set][1]];
-        ram_table.min_reduction[1][1] = min_reduction_table[abm_config[set][1]];
-        ram_table.min_reduction[2][1] = min_reduction_table[abm_config[set][1]];
-        ram_table.min_reduction[3][1] = min_reduction_table[abm_config[set][1]];
-        ram_table.min_reduction[4][1] = min_reduction_table[abm_config[set][1]];
-        ram_table.max_reduction[0][1] = max_reduction_table[abm_config[set][1]];
-        ram_table.max_reduction[1][1] = max_reduction_table[abm_config[set][1]];
-        ram_table.max_reduction[2][1] = max_reduction_table[abm_config[set][1]];
-        ram_table.max_reduction[3][1] = max_reduction_table[abm_config[set][1]];
-        ram_table.max_reduction[4][1] = max_reduction_table[abm_config[set][1]];
-
-        ram_table.min_reduction[0][2] = min_reduction_table[abm_config[set][2]];
-        ram_table.min_reduction[1][2] = min_reduction_table[abm_config[set][2]];
-        ram_table.min_reduction[2][2] = min_reduction_table[abm_config[set][2]];
-        ram_table.min_reduction[3][2] = min_reduction_table[abm_config[set][2]];
-        ram_table.min_reduction[4][2] = min_reduction_table[abm_config[set][2]];
-        ram_table.max_reduction[0][2] = max_reduction_table[abm_config[set][2]];
-        ram_table.max_reduction[1][2] = max_reduction_table[abm_config[set][2]];
-        ram_table.max_reduction[2][2] = max_reduction_table[abm_config[set][2]];
-        ram_table.max_reduction[3][2] = max_reduction_table[abm_config[set][2]];
-        ram_table.max_reduction[4][2] = max_reduction_table[abm_config[set][2]];
-
-        ram_table.min_reduction[0][3] = min_reduction_table[abm_config[set][3]];
-        ram_table.min_reduction[1][3] = min_reduction_table[abm_config[set][3]];
-        ram_table.min_reduction[2][3] = min_reduction_table[abm_config[set][3]];
-        ram_table.min_reduction[3][3] = min_reduction_table[abm_config[set][3]];
-        ram_table.min_reduction[4][3] = min_reduction_table[abm_config[set][3]];
-        ram_table.max_reduction[0][3] = max_reduction_table[abm_config[set][3]];
-        ram_table.max_reduction[1][3] = max_reduction_table[abm_config[set][3]];
-        ram_table.max_reduction[2][3] = max_reduction_table[abm_config[set][3]];
-        ram_table.max_reduction[3][3] = max_reduction_table[abm_config[set][3]];
-        ram_table.max_reduction[4][3] = max_reduction_table[abm_config[set][3]];
-
-        ram_table.bright_pos_gain[0][0] = 0x20;
-        ram_table.bright_pos_gain[0][1] = 0x20;
-        ram_table.bright_pos_gain[0][2] = 0x20;
-        ram_table.bright_pos_gain[0][3] = 0x20;
-        ram_table.bright_pos_gain[1][0] = 0x20;
-        ram_table.bright_pos_gain[1][1] = 0x20;
-        ram_table.bright_pos_gain[1][2] = 0x20;
-        ram_table.bright_pos_gain[1][3] = 0x20;
-        ram_table.bright_pos_gain[2][0] = 0x20;
-        ram_table.bright_pos_gain[2][1] = 0x20;
-        ram_table.bright_pos_gain[2][2] = 0x20;
-        ram_table.bright_pos_gain[2][3] = 0x20;
-        ram_table.bright_pos_gain[3][0] = 0x20;
-        ram_table.bright_pos_gain[3][1] = 0x20;
-        ram_table.bright_pos_gain[3][2] = 0x20;
-        ram_table.bright_pos_gain[3][3] = 0x20;
-        ram_table.bright_pos_gain[4][0] = 0x20;
-        ram_table.bright_pos_gain[4][1] = 0x20;
-        ram_table.bright_pos_gain[4][2] = 0x20;
-        ram_table.bright_pos_gain[4][3] = 0x20;
-        ram_table.bright_neg_gain[0][1] = 0x00;
-        ram_table.bright_neg_gain[0][2] = 0x00;
-        ram_table.bright_neg_gain[0][3] = 0x00;
-        ram_table.bright_neg_gain[1][0] = 0x00;
-        ram_table.bright_neg_gain[1][1] = 0x00;
-        ram_table.bright_neg_gain[1][2] = 0x00;
-        ram_table.bright_neg_gain[1][3] = 0x00;
-        ram_table.bright_neg_gain[2][0] = 0x00;
-        ram_table.bright_neg_gain[2][1] = 0x00;
-        ram_table.bright_neg_gain[2][2] = 0x00;
-        ram_table.bright_neg_gain[2][3] = 0x00;
-        ram_table.bright_neg_gain[3][0] = 0x00;
-        ram_table.bright_neg_gain[3][1] = 0x00;
-        ram_table.bright_neg_gain[3][2] = 0x00;
-        ram_table.bright_neg_gain[3][3] = 0x00;
-        ram_table.bright_neg_gain[4][0] = 0x00;
-        ram_table.bright_neg_gain[4][1] = 0x00;
-        ram_table.bright_neg_gain[4][2] = 0x00;
-        ram_table.bright_neg_gain[4][3] = 0x00;
-        ram_table.dark_pos_gain[0][0] = 0x00;
-        ram_table.dark_pos_gain[0][1] = 0x00;
-        ram_table.dark_pos_gain[0][2] = 0x00;
-        ram_table.dark_pos_gain[0][3] = 0x00;
-        ram_table.dark_pos_gain[1][0] = 0x00;
-        ram_table.dark_pos_gain[1][1] = 0x00;
-        ram_table.dark_pos_gain[1][2] = 0x00;
-        ram_table.dark_pos_gain[1][3] = 0x00;
-        ram_table.dark_pos_gain[2][0] = 0x00;
-        ram_table.dark_pos_gain[2][1] = 0x00;
-        ram_table.dark_pos_gain[2][2] = 0x00;
-        ram_table.dark_pos_gain[2][3] = 0x00;
-        ram_table.dark_pos_gain[3][0] = 0x00;
-        ram_table.dark_pos_gain[3][1] = 0x00;
-        ram_table.dark_pos_gain[3][2] = 0x00;
-        ram_table.dark_pos_gain[3][3] = 0x00;
-        ram_table.dark_pos_gain[4][0] = 0x00;
-        ram_table.dark_pos_gain[4][1] = 0x00;
-        ram_table.dark_pos_gain[4][2] = 0x00;
-        ram_table.dark_pos_gain[4][3] = 0x00;
-        ram_table.dark_neg_gain[0][0] = 0x00;
-        ram_table.dark_neg_gain[0][1] = 0x00;
-        ram_table.dark_neg_gain[0][2] = 0x00;
-        ram_table.dark_neg_gain[0][3] = 0x00;
-        ram_table.dark_neg_gain[1][0] = 0x00;
-        ram_table.dark_neg_gain[1][1] = 0x00;
-        ram_table.dark_neg_gain[1][2] = 0x00;
-        ram_table.dark_neg_gain[1][3] = 0x00;
-        ram_table.dark_neg_gain[2][0] = 0x00;
-        ram_table.dark_neg_gain[2][1] = 0x00;
-        ram_table.dark_neg_gain[2][2] = 0x00;
-        ram_table.dark_neg_gain[2][3] = 0x00;
-        ram_table.dark_neg_gain[3][0] = 0x00;
-        ram_table.dark_neg_gain[3][1] = 0x00;
-        ram_table.dark_neg_gain[3][2] = 0x00;
-        ram_table.dark_neg_gain[3][3] = 0x00;
-        ram_table.dark_neg_gain[4][0] = 0x00;
-        ram_table.dark_neg_gain[4][1] = 0x00;
-        ram_table.dark_neg_gain[4][2] = 0x00;
-        ram_table.dark_neg_gain[4][3] = 0x00;
-        ram_table.iir_curve[0] = 0x65;
-        ram_table.iir_curve[1] = 0x65;
-        ram_table.iir_curve[2] = 0x65;
-        ram_table.iir_curve[3] = 0x65;
-        ram_table.iir_curve[4] = 0x65;
-        ram_table.crgb_thresh[0] = cpu_to_be16(0x13b6);
-        ram_table.crgb_thresh[1] = cpu_to_be16(0x1648);
-        ram_table.crgb_thresh[2] = cpu_to_be16(0x18e3);
-        ram_table.crgb_thresh[3] = cpu_to_be16(0x1b41);
-        ram_table.crgb_thresh[4] = cpu_to_be16(0x1d46);
-        ram_table.crgb_thresh[5] = cpu_to_be16(0x1f21);
-        ram_table.crgb_thresh[6] = cpu_to_be16(0x2167);
-        ram_table.crgb_thresh[7] = cpu_to_be16(0x2384);
-        ram_table.crgb_offset[0] = cpu_to_be16(0x2999);
-        ram_table.crgb_offset[1] = cpu_to_be16(0x3999);
-        ram_table.crgb_offset[2] = cpu_to_be16(0x4666);
-        ram_table.crgb_offset[3] = cpu_to_be16(0x5999);
-        ram_table.crgb_offset[4] = cpu_to_be16(0x6333);
-        ram_table.crgb_offset[5] = cpu_to_be16(0x7800);
-        ram_table.crgb_offset[6] = cpu_to_be16(0x8c00);
-        ram_table.crgb_offset[7] = cpu_to_be16(0xa000);
-        ram_table.crgb_slope[0]  = cpu_to_be16(0x3147);
-        ram_table.crgb_slope[1]  = cpu_to_be16(0x2978);
-        ram_table.crgb_slope[2]  = cpu_to_be16(0x23a2);
-        ram_table.crgb_slope[3]  = cpu_to_be16(0x1f55);
-        ram_table.crgb_slope[4]  = cpu_to_be16(0x1c63);
-        ram_table.crgb_slope[5]  = cpu_to_be16(0x1a0f);
-        ram_table.crgb_slope[6]  = cpu_to_be16(0x178d);
-        ram_table.crgb_slope[7]  = cpu_to_be16(0x15ab);
-
-        fill_backlight_transform_table(
-                        params, &ram_table);
+        if (dmcu->dmcu_version.abm_version == 0x22) {
+                fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
+        } else {
+                fill_iram_v_2((struct iram_table_v_2 *)ram_table, params);
+        }
 
         return dmcu->funcs->load_iram(
-                        dmcu, 0, (char *)(&ram_table), sizeof(ram_table));
+                        dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START);
 }
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
index 13d4de645190..d8e0dd192fdd 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
@@ -2247,6 +2247,8 @@
 
 // addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
 // base address: 0x3480
+#define mmRCC_BIF_STRAP0                                                                               0x0000
+#define mmRCC_BIF_STRAP0_BASE_IDX                                                                      2
 #define mmRCC_DEV0_EPF0_STRAP0                                                                         0x000f
 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX                                                                2
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
index a02b67943372..29af5167cd00 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
@@ -16838,6 +16838,10 @@
 
 
 // addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
+//RCC_BIF_STRAP0
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                               0x7
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                                 0x00000080L
+
 //RCC_DEV0_EPF0_STRAP0
 #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                                  0x0
 #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                               0x10
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
new file mode 100644
index 000000000000..8c75669eb500
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_6_1_SMN_HEADER
+#define _nbio_6_1_SMN_HEADER
+
+
+#define smnCPM_CONTROL                                  0x11180460
+#define smnPCIE_CNTL2                                   0x11180070
+#define smnPCIE_CONFIG_CNTL                             0x11180044
+#define smnPCIE_CI_CNTL                                 0x11180080
+
+
+#define smnPCIE_PERF_COUNT_CNTL                         0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK                         0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK                       0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK                       0x1118020c
+#define smnPCIE_PERF_CNTL_MST_R_CLK                     0x11180210
+#define smnPCIE_PERF_COUNT0_MST_R_CLK                   0x11180214
+#define smnPCIE_PERF_COUNT1_MST_R_CLK                   0x11180218
+#define smnPCIE_PERF_CNTL_MST_C_CLK                     0x1118021c
+#define smnPCIE_PERF_COUNT0_MST_C_CLK                   0x11180220
+#define smnPCIE_PERF_COUNT1_MST_C_CLK                   0x11180224
+#define smnPCIE_PERF_CNTL_SLV_R_CLK                     0x11180228
+#define smnPCIE_PERF_COUNT0_SLV_R_CLK                   0x1118022c
+#define smnPCIE_PERF_COUNT1_SLV_R_CLK                   0x11180230
+#define smnPCIE_PERF_CNTL_SLV_S_C_CLK                   0x11180234
+#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK                 0x11180238
+#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK                 0x1118023c
+#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK                  0x11180240
+#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK                0x11180244
+#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK                0x11180248
+#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL               0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL               0x11180250
+#define smnPCIE_PERF_CNTL_TXCLK2                        0x11180254
+#define smnPCIE_PERF_COUNT0_TXCLK2                      0x11180258
+#define smnPCIE_PERF_COUNT1_TXCLK2                      0x1118025c
+
+#endif  // _nbio_6_1_SMN_HEADER
+
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
new file mode 100644
index 000000000000..5563f0715896
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_7_0_SMN_HEADER
+#define _nbio_7_0_SMN_HEADER
+
+
+#define smnCPM_CONTROL                                  0x11180460
+#define smnPCIE_CNTL2                                   0x11180070
+
+#define smnPCIE_PERF_COUNT_CNTL                         0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK                         0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK                       0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK                       0x1118020c
+#define smnPCIE_PERF_CNTL_MST_R_CLK                     0x11180210
+#define smnPCIE_PERF_COUNT0_MST_R_CLK                   0x11180214
+#define smnPCIE_PERF_COUNT1_MST_R_CLK                   0x11180218
+#define smnPCIE_PERF_CNTL_MST_C_CLK                     0x1118021c
+#define smnPCIE_PERF_COUNT0_MST_C_CLK                   0x11180220
+#define smnPCIE_PERF_COUNT1_MST_C_CLK                   0x11180224
+#define smnPCIE_PERF_CNTL_SLV_R_CLK                     0x11180228
+#define smnPCIE_PERF_COUNT0_SLV_R_CLK                   0x1118022c
+#define smnPCIE_PERF_COUNT1_SLV_R_CLK                   0x11180230
+#define smnPCIE_PERF_CNTL_SLV_S_C_CLK                   0x11180234
+#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK                 0x11180238
+#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK                 0x1118023c
+#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK                  0x11180240
+#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK                0x11180244
+#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK                0x11180248
+#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL               0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL               0x11180250
+#define smnPCIE_PERF_CNTL_TXCLK2                        0x11180254
+#define smnPCIE_PERF_COUNT0_TXCLK2                      0x11180258
+#define smnPCIE_PERF_COUNT1_TXCLK2                      0x1118025c
+
+#endif  // _nbio_7_0_SMN_HEADER
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
new file mode 100644
index 000000000000..c1457d880c4d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_7_4_0_SMN_HEADER
+#define _nbio_7_4_0_SMN_HEADER
+
+
+#define smnNBIF_MGCG_CTRL_LCLK                          0x1013a21c
+#define smnCPM_CONTROL                                  0x11180460
+#define smnPCIE_CNTL2                                   0x11180070
+#define smnPCIE_CI_CNTL                                 0x11180080
+
+#define smnPCIE_PERF_COUNT_CNTL                         0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK1                        0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK1                      0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK1                      0x1118020c
+#define smnPCIE_PERF_CNTL_TXCLK2                        0x11180210
+#define smnPCIE_PERF_COUNT0_TXCLK2                      0x11180214
+#define smnPCIE_PERF_COUNT1_TXCLK2                      0x11180218
+#define smnPCIE_PERF_CNTL_TXCLK3                        0x1118021c
+#define smnPCIE_PERF_COUNT0_TXCLK3                      0x11180220
+#define smnPCIE_PERF_COUNT1_TXCLK3                      0x11180224
+#define smnPCIE_PERF_CNTL_TXCLK4                        0x11180228
+#define smnPCIE_PERF_COUNT0_TXCLK4                      0x1118022c
+#define smnPCIE_PERF_COUNT1_TXCLK4                      0x11180230
+#define smnPCIE_PERF_CNTL_SCLK1                         0x11180234
+#define smnPCIE_PERF_COUNT0_SCLK1                       0x11180238
+#define smnPCIE_PERF_COUNT1_SCLK1                       0x1118023c
+#define smnPCIE_PERF_CNTL_SCLK2                         0x11180240
+#define smnPCIE_PERF_COUNT0_SCLK2                       0x11180244
+#define smnPCIE_PERF_COUNT1_SCLK2                       0x11180248
+#define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL             0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL             0x11180250
+
+#endif  // _nbio_7_4_0_SMN_HEADER
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
index e932213f87f0..994e796a28d7 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h
@@ -2567,6 +2567,8 @@
 
 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
 // base address: 0x0
+#define mmRCC_BIF_STRAP0                                                                               0x0000
+#define mmRCC_BIF_STRAP0_BASE_IDX                                                                      2
 #define mmRCC_DEV0_EPF0_STRAP0                                                                         0x0011
 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX                                                                2
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
index d3704b438f2d..d467b939c971 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h
@@ -19690,6 +19690,9 @@
 
 
 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_BIF_STRAP0
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                               0x7
+#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                                 0x00000080L
 //RCC_DEV0_EPF0_STRAP0
 #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                                  0x0
 #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                               0x10
diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
index a9eb57a53e59..a485526f3a51 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h
@@ -46,4 +46,7 @@
 #define mmTHM_TCON_THERM_TRIP                                                                          0x0002
 #define mmTHM_TCON_THERM_TRIP_BASE_IDX                                                                 0
 
+#define mmTHM_BACO_CNTL                                                                                0x0081
+#define mmTHM_BACO_CNTL_BASE_IDX                                                                       0
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index 7931502fa54f..8ba21747b40a 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -4106,7 +4106,7 @@ typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
 {
   UCHAR ucRecordType;
-  UCHAR ucFakeEDIDLength;       // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
+  UCHAR ucFakeEDIDLength;       // = 128 means EDID length is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
   UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
 } ATOM_FAKE_EDID_PATCH_RECORD;
 
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 8154d67388cc..83d960110d23 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -34,7 +34,6 @@
 
 struct pci_dev;
 
-#define KFD_INTERFACE_VERSION 2
 #define KGD_MAX_QUEUES 128
 
 struct kfd_dev;
@@ -330,56 +329,4 @@ struct kfd2kgd_calls {
 
 };
 
-/**
- * struct kgd2kfd_calls
- *
- * @exit: Notifies amdkfd that kgd module is unloaded
- *
- * @probe: Notifies amdkfd about a probe done on a device in the kgd driver.
- *
- * @device_init: Initialize the newly probed device (if it is a device that
- * amdkfd supports)
- *
- * @device_exit: Notifies amdkfd about a removal of a kgd device
- *
- * @suspend: Notifies amdkfd about a suspend action done to a kgd device
- *
- * @resume: Notifies amdkfd about a resume action done to a kgd device
- *
- * @quiesce_mm: Quiesce all user queue access to specified MM address space
- *
- * @resume_mm: Resume user queue access to specified MM address space
- *
- * @schedule_evict_and_restore_process: Schedules work queue that will prepare
- * for safe eviction of KFD BOs that belong to the specified process.
- *
- * @pre_reset: Notifies amdkfd that amdgpu about to reset the gpu
- *
- * @post_reset: Notify amdkfd that amgpu successfully reseted the gpu
- *
- * This structure contains function callback pointers so the kgd driver
- * will notify to the amdkfd about certain status changes.
- *
- */
-struct kgd2kfd_calls {
-        void (*exit)(void);
-        struct kfd_dev* (*probe)(struct kgd_dev *kgd, struct pci_dev *pdev,
-                const struct kfd2kgd_calls *f2g);
-        bool (*device_init)(struct kfd_dev *kfd,
-                        const struct kgd2kfd_shared_resources *gpu_resources);
-        void (*device_exit)(struct kfd_dev *kfd);
-        void (*interrupt)(struct kfd_dev *kfd, const void *ih_ring_entry);
-        void (*suspend)(struct kfd_dev *kfd);
-        int (*resume)(struct kfd_dev *kfd);
-        int (*quiesce_mm)(struct mm_struct *mm);
-        int (*resume_mm)(struct mm_struct *mm);
-        int (*schedule_evict_and_restore_process)(struct mm_struct *mm,
-                        struct dma_fence *fence);
-        int  (*pre_reset)(struct kfd_dev *kfd);
-        int  (*post_reset)(struct kfd_dev *kfd);
-};
-
-int kgd2kfd_init(unsigned interface_version,
-                const struct kgd2kfd_calls **g2f);
-
 #endif  /* KGD_KFD_INTERFACE_H_INCLUDED */
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 1479ea1dc3e7..2b579ba9b685 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -92,6 +92,9 @@ enum pp_clock_type {
         PP_SCLK,
         PP_MCLK,
         PP_PCIE,
+        PP_SOCCLK,
+        PP_FCLK,
+        PP_DCEFCLK,
         OD_SCLK,
         OD_MCLK,
         OD_VDDC_CURVE,
@@ -127,12 +130,13 @@ enum amd_pp_task {
 };
 
 enum PP_SMC_POWER_PROFILE {
-        PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x0,
-        PP_SMC_POWER_PROFILE_POWERSAVING  = 0x1,
-        PP_SMC_POWER_PROFILE_VIDEO        = 0x2,
-        PP_SMC_POWER_PROFILE_VR           = 0x3,
-        PP_SMC_POWER_PROFILE_COMPUTE      = 0x4,
-        PP_SMC_POWER_PROFILE_CUSTOM       = 0x5,
+        PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
+        PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
+        PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
+        PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
+        PP_SMC_POWER_PROFILE_VR           = 0x4,
+        PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
+        PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 };
 
 enum {
@@ -280,6 +284,11 @@ struct amd_pm_funcs {
         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
+        int (*get_asic_baco_capability)(void *handle, bool *cap);
+        int (*get_asic_baco_state)(void *handle, int *state);
+        int (*set_asic_baco_state)(void *handle, int state);
+        int (*get_ppfeature_status)(void *handle, char *buf);
+        int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 9bc27f468d5b..3f73f7cd18b9 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1404,6 +1404,97 @@ static int pp_set_active_display_count(void *handle, uint32_t count)
         return ret;
 }
 
+static int pp_get_asic_baco_capability(void *handle, bool *cap)
+{
+        struct pp_hwmgr *hwmgr = handle;
+
+        if (!hwmgr)
+                return -EINVAL;
+
+        if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_capability)
+                return 0;
+
+        mutex_lock(&hwmgr->smu_lock);
+        hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
+        mutex_unlock(&hwmgr->smu_lock);
+
+        return 0;
+}
+
+static int pp_get_asic_baco_state(void *handle, int *state)
+{
+        struct pp_hwmgr *hwmgr = handle;
+
+        if (!hwmgr)
+                return -EINVAL;
+
+        if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
+                return 0;
+
+        mutex_lock(&hwmgr->smu_lock);
+        hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
+        mutex_unlock(&hwmgr->smu_lock);
+
+        return 0;
+}
+
+static int pp_set_asic_baco_state(void *handle, int state)
+{
+        struct pp_hwmgr *hwmgr = handle;
+
+        if (!hwmgr)
+                return -EINVAL;
+
+        if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_asic_baco_state)
+                return 0;
+
+        mutex_lock(&hwmgr->smu_lock);
+        hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
+        mutex_unlock(&hwmgr->smu_lock);
+
+        return 0;
+}
+
+static int pp_get_ppfeature_status(void *handle, char *buf)
+{
+        struct pp_hwmgr *hwmgr = handle;
+        int ret = 0;
+
+        if (!hwmgr || !hwmgr->pm_en || !buf)
+                return -EINVAL;
+
+        if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) {
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
+                return -EINVAL;
+        }
+
+        mutex_lock(&hwmgr->smu_lock);
+        ret = hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
+        mutex_unlock(&hwmgr->smu_lock);
+
+        return ret;
+}
+
+static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
+{
+        struct pp_hwmgr *hwmgr = handle;
+        int ret = 0;
+
+        if (!hwmgr || !hwmgr->pm_en)
+                return -EINVAL;
+
+        if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) {
+                pr_info_ratelimited("%s was not implemented.\n", __func__);
+                return -EINVAL;
+        }
+
+        mutex_lock(&hwmgr->smu_lock);
+        ret = hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
+        mutex_unlock(&hwmgr->smu_lock);
+
+        return ret;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
         .load_firmware = pp_dpm_load_fw,
         .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1454,4 +1545,9 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
         .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
         .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
         .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
+        .get_asic_baco_capability = pp_get_asic_baco_capability,
+        .get_asic_baco_state = pp_get_asic_baco_state,
+        .set_asic_baco_state = pp_set_asic_baco_state,
+        .get_ppfeature_status = pp_get_ppfeature_status,
+        .set_ppfeature_status = pp_set_ppfeature_status,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
index ade8973b6f4d..0b3c6d1d52e4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile
@@ -35,7 +35,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \
                 vega12_thermal.o \
                 pp_overdriver.o smu_helper.o \
                 vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \
-                vega20_thermal.o
+                vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o
 
 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
new file mode 100644
index 000000000000..9c57c1f67749
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "common_baco.h"
+
+
+static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        u32 timeout = 5000, data;
+
+        do {
+                msleep(1);
+                data = RREG32(reg);
+                timeout--;
+        } while (value != (data & mask) && (timeout != 0));
+
+        if (timeout == 0)
+                return false;
+
+        return true;
+}
+
+static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,
+                                u32 shift, u32 value, u32 timeout)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        u32 data;
+        bool ret = true;
+
+        switch (command) {
+        case CMD_WRITE:
+                WREG32(reg, value << shift);
+                break;
+        case CMD_READMODIFYWRITE:
+                data = RREG32(reg);
+                data = (data & (~mask)) | (value << shift);
+                WREG32(reg, data);
+                break;
+        case CMD_WAITFOR:
+                ret = baco_wait_register(hwmgr, reg, mask, value);
+                break;
+        case CMD_DELAY_MS:
+                if (timeout)
+                        /* Delay in milli Seconds */
+                        msleep(timeout);
+                break;
+        case CMD_DELAY_US:
+                if (timeout)
+                        /* Delay in micro Seconds */
+                        udelay(timeout);
+                break;
+
+        default:
+                dev_warn(adev->dev, "Invalid BACO command.\n");
+                ret = false;
+        }
+
+        return ret;
+}
+
+bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
+                                 const struct soc15_baco_cmd_entry *entry,
+                                 const u32 array_size)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        u32 i, reg = 0;
+
+        for (i = 0; i < array_size; i++) {
+                if ((entry[i].cmd == CMD_WRITE) ||
+                    (entry[i].cmd == CMD_READMODIFYWRITE) ||
+                    (entry[i].cmd == CMD_WAITFOR))
+                        reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg]
+                                + entry[i].reg_offset;
+                if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
+                                     entry[i].shift, entry[i].val, entry[i].timeout))
+                        return false;
+        }
+
+        return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.h b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
index 26355c088746..95296c916f4e 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,25 +19,32 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: AMD
- *
  */
+#ifndef __COMMON_BOCO_H__
+#define __COMMON_BOCO_H__
+#include "hwmgr.h"
 
-#ifndef __DAL_I2C_SW_ENGINE_DCE80_H__
-#define __DAL_I2C_SW_ENGINE_DCE80_H__
 
-struct i2c_sw_engine_dce80 {
-        struct i2c_sw_engine base;
-        uint32_t engine_id;
+enum baco_cmd_type {
+        CMD_WRITE = 0,
+        CMD_READMODIFYWRITE,
+        CMD_WAITFOR,
+        CMD_DELAY_MS,
+        CMD_DELAY_US,
 };
 
-struct i2c_sw_engine_dce80_create_arg {
-        uint32_t engine_id;
-        uint32_t default_speed;
-        struct dc_context *ctx;
+struct soc15_baco_cmd_entry {
+        enum baco_cmd_type cmd;
+        uint32_t        hwip;
+        uint32_t        inst;
+        uint32_t        seg;
+        uint32_t        reg_offset;
+        uint32_t        mask;
+        uint32_t        shift;
+        uint32_t        timeout;
+        uint32_t        val;
 };
-
-struct i2c_engine *dal_i2c_sw_engine_dce80_create(
-        const struct i2c_sw_engine_dce80_create_arg *arg);
-
+extern bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
+                                        const struct soc15_baco_cmd_entry *entry,
+                                        const u32 array_size);
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 1f92a9f4c9e3..c1c51c115e57 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -154,15 +154,6 @@ int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
-int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
-{
-        PHM_FUNC_CHECK(hwmgr);
-
-        if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
-                return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
-
-        return 0;
-}
 
 int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 0173d0480024..6cd6497c6fc2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -64,17 +64,19 @@ static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
 
 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
 {
-        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 2;
-        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 0;
-        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 1;
-        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 3;
-        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 4;
-
-        hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_POWERSAVING;
-        hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_VIDEO;
-        hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
-        hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VR;
-        hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_COMPUTE;
+        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
+        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
+        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
+        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
+        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
+        hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
+
+        hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+        hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+        hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
+        hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
+        hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
+        hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 }
 
 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
@@ -271,7 +273,7 @@ int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
 
         phm_stop_thermal_controller(hwmgr);
         psm_set_boot_states(hwmgr);
-        psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+        psm_adjust_power_state_dynamic(hwmgr, true, NULL);
         phm_disable_dynamic_state_management(hwmgr);
         phm_disable_clock_power_gatings(hwmgr);
 
@@ -293,7 +295,7 @@ int hwmgr_suspend(struct pp_hwmgr *hwmgr)
         ret = psm_set_boot_states(hwmgr);
         if (ret)
                 return ret;
-        ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+        ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
         if (ret)
                 return ret;
         ret = phm_power_down_asic(hwmgr);
@@ -323,7 +325,7 @@ int hwmgr_resume(struct pp_hwmgr *hwmgr)
         if (ret)
                 return ret;
 
-        ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+        ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
 
         return ret;
 }
@@ -377,12 +379,12 @@ int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
                 ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
                 if (ret)
                         return ret;
-                ret = psm_adjust_power_state_dynamic(hwmgr, false, requested_ps);
+                ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps);
                 break;
         }
         case AMD_PP_TASK_COMPLETE_INIT:
         case AMD_PP_TASK_READJUST_POWER_STATE:
-                ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
+                ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
                 break;
         default:
                 break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 56437866d120..ce177d7f04cb 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -256,16 +256,14 @@ static void power_state_management(struct pp_hwmgr *hwmgr,
         }
 }
 
-int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
+int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_settings,
                                                 struct pp_power_state *new_ps)
 {
         uint32_t index;
         long workload;
 
-        if (skip)
-                return 0;
-
-        phm_display_configuration_changed(hwmgr);
+        if (!skip_display_settings)
+                phm_display_configuration_changed(hwmgr);
 
         if (hwmgr->ps)
                 power_state_management(hwmgr, new_ps);
@@ -276,9 +274,11 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
                  */
                 phm_apply_clock_adjust_rules(hwmgr);
 
-        phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
+        if (!skip_display_settings)
+                phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
 
-        if (!phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level))
+        if ((hwmgr->request_dpm_level != hwmgr->dpm_level) &&
+            !phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level))
                 hwmgr->dpm_level = hwmgr->request_dpm_level;
 
         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h
index fa1b6825036a..b62d55f1f289 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h
@@ -34,7 +34,7 @@ int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
                                         enum PP_StateUILabel label_id,
                                         struct pp_power_state **state);
 int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr,
-                                bool skip,
+                                bool skip_display_settings,
                                 struct pp_power_state *new_ps);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index d91390459326..c8f5c00dd1e7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -77,8 +77,9 @@
 #define PCIE_BUS_CLK                10000
 #define TCLK                        (PCIE_BUS_CLK / 10)
 
-static const struct profile_mode_setting smu7_profiling[6] =
-                                        {{1, 0, 100, 30, 1, 0, 100, 10},
+static const struct profile_mode_setting smu7_profiling[7] =
+                                        {{0, 0, 0, 0, 0, 0, 0, 0},
+                                         {1, 0, 100, 30, 1, 0, 100, 10},
                                          {1, 10, 0, 30, 0, 0, 0, 0},
                                          {0, 0, 0, 0, 1, 10, 16, 31},
                                          {1, 0, 11, 50, 1, 0, 100, 10},
@@ -4889,7 +4890,8 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
         uint32_t i, size = 0;
         uint32_t len;
 
-        static const char *profile_name[6] = {"3D_FULL_SCREEN",
+        static const char *profile_name[7] = {"BOOTUP_DEFAULT",
+                                        "3D_FULL_SCREEN",
                                         "POWER_SAVING",
                                         "VIDEO",
                                         "VR",
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
new file mode 100644
index 000000000000..f94dab27f486
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c
@@ -0,0 +1,136 @@
+#include "amdgpu.h"
+#include "soc15.h"
+#include "soc15_hw_ip.h"
+#include "vega10_ip_offset.h"
+#include "soc15_common.h"
+#include "vega10_inc.h"
+#include "vega10_ppsmc.h"
+#include "vega10_baco.h"
+
+
+
+static const struct soc15_baco_cmd_entry  pre_baco_tbl[] =
+{
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_DOORBELL_CNTL), BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK, BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT, 0, 1},
+        {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIF_FB_EN), 0, 0, 0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DSTATE_BYPASS_MASK, BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_RST_INTR_MASK_MASK, BACO_CNTL__BACO_RST_INTR_MASK__SHIFT, 0, 1}
+};
+
+static const struct soc15_baco_cmd_entry enter_baco_tbl[] =
+{
+        {CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK, THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT, 0xffffffff, 0x80000000},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK, BACO_CNTL__BACO_EN__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK, BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT,0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT,0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK,     THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 1},
+        {CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 5, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 0},
+        {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, BACO_CNTL__BACO_MODE__SHIFT, 0xffffffff, 0x100}
+};
+
+static const struct soc15_baco_cmd_entry exit_baco_tbl[] =
+{
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_POWER_OFF_MASK, BACO_CNTL__BACO_POWER_OFF__SHIFT, 0, 0},
+        {CMD_DELAY_MS, 0, 0, 0, 0, 0, 0, 10,0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK, THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT, 0,0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK, THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT, 0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK, THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT,0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_ISO_EN_MASK, THM_BACO_CNTL__BACO_ISO_EN__SHIFT, 0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK, THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK, THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT, 0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK, THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT, 0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, THM_BACO_CNTL__BACO_EXIT__SHIFT, 0, 1},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_RESET_EN_MASK, THM_BACO_CNTL__BACO_RESET_EN__SHIFT, 0, 0},
+        {CMD_WAITFOR, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_EXIT_MASK, 0, 0xffffffff, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(THM, 0, mmTHM_BACO_CNTL), THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK, THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT, 0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_DUMMY_EN_MASK, BACO_CNTL__BACO_DUMMY_EN__SHIFT,  0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK ,BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT, 0, 0},
+        {CMD_READMODIFYWRITE, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_EN_MASK , BACO_CNTL__BACO_EN__SHIFT, 0,0},
+        {CMD_WAITFOR, SOC15_REG_ENTRY(NBIF, 0, mmBACO_CNTL), BACO_CNTL__BACO_MODE_MASK, 0, 0xffffffff, 0}
+ };
+
+static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
+{
+        {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
+        {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
+};
+
+int vega10_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        uint32_t reg, data;
+
+        *cap = false;
+        if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+                return 0;
+
+        WREG32(0x12074, 0xFFF0003B);
+        data = RREG32(0x12075);
+
+        if (data == 0x1) {
+                reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
+
+                if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
+                        *cap = true;
+        }
+
+        return 0;
+}
+
+int vega10_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        uint32_t reg;
+
+        reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
+
+        if (reg & BACO_CNTL__BACO_MODE_MASK)
+                /* gfx has already entered BACO state */
+                *state = BACO_STATE_IN;
+        else
+                *state = BACO_STATE_OUT;
+        return 0;
+}
+
+int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+{
+        enum BACO_STATE cur_state;
+
+        vega10_baco_get_state(hwmgr, &cur_state);
+
+        if (cur_state == state)
+                /* aisc already in the target state */
+                return 0;
+
+        if (state == BACO_STATE_IN) {
+                if (soc15_baco_program_registers(hwmgr, pre_baco_tbl,
+                                             ARRAY_SIZE(pre_baco_tbl))) {
+                        if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnterBaco))
+                                return -1;
+
+                        if (soc15_baco_program_registers(hwmgr, enter_baco_tbl,
+                                                   ARRAY_SIZE(enter_baco_tbl)))
+                                return 0;
+                }
+        } else if (state == BACO_STATE_OUT) {
+                /* HW requires at least 20ms between regulator off and on */
+                msleep(20);
+                /* Execute Hardware BACO exit sequence */
+                if (soc15_baco_program_registers(hwmgr, exit_baco_tbl,
+                                             ARRAY_SIZE(exit_baco_tbl))) {
+                        if (soc15_baco_program_registers(hwmgr, clean_baco_tbl,
+                                                     ARRAY_SIZE(clean_baco_tbl)))
+                                return 0;
+                }
+        }
+
+        return -1;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h
index 21908629e973..a93b1e6d1c66 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,20 +19,14 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: AMD
- *
  */
+#ifndef __VEGA10_BOCO_H__
+#define __VEGA10_BOCO_H__
+#include "hwmgr.h"
+#include "common_baco.h"
 
-#ifndef __DAL_I2C_AUX_DCE80_H__
-#define __DAL_I2C_AUX_DCE80_H__
-
-struct i2caux_dce80 {
-        struct i2caux base;
-        /* indicate the I2C HW circular buffer is in use */
-        bool i2c_hw_buffer_in_use;
-};
-
-struct i2caux *dal_i2caux_dce80_create(
-        struct dc_context *ctx);
+extern int vega10_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+extern int vega10_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+extern int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 79c86247d0ac..0d38ac2fdbf1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -48,6 +48,7 @@
 #include "ppinterrupt.h"
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
+#include "vega10_baco.h"
 
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
@@ -71,6 +72,21 @@ static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
 
+typedef enum {
+        CLK_SMNCLK = 0,
+        CLK_SOCCLK,
+        CLK_MP0CLK,
+        CLK_MP1CLK,
+        CLK_LCLK,
+        CLK_DCEFCLK,
+        CLK_VCLK,
+        CLK_DCLK,
+        CLK_ECLK,
+        CLK_UCLK,
+        CLK_GFXCLK,
+        CLK_COUNT,
+} CLOCK_ID_e;
+
 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
 
 struct vega10_power_state *cast_phw_vega10_power_state(
@@ -804,9 +820,9 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
         hwmgr->backend = data;
 
-        hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
-        hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
-        hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+        hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
+        hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+        hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 
         vega10_set_default_registry_data(hwmgr);
         data->disable_dpm_mask = 0xff;
@@ -3485,6 +3501,17 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
                 }
         }
 
+        if (!data->registry_data.socclk_dpm_key_disabled) {
+                if (data->smc_state_table.soc_boot_level !=
+                                data->dpm_table.soc_table.dpm_state.soft_min_level) {
+                        smum_send_msg_to_smc_with_parameter(hwmgr,
+                                PPSMC_MSG_SetSoftMinSocclkByIndex,
+                                data->smc_state_table.soc_boot_level);
+                        data->dpm_table.soc_table.dpm_state.soft_min_level =
+                                        data->smc_state_table.soc_boot_level;
+                }
+        }
+
         return 0;
 }
 
@@ -3516,6 +3543,17 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
                 }
         }
 
+        if (!data->registry_data.socclk_dpm_key_disabled) {
+                if (data->smc_state_table.soc_max_level !=
+                        data->dpm_table.soc_table.dpm_state.soft_max_level) {
+                        smum_send_msg_to_smc_with_parameter(hwmgr,
+                                PPSMC_MSG_SetSoftMaxSocclkByIndex,
+                                data->smc_state_table.soc_max_level);
+                        data->dpm_table.soc_table.dpm_state.soft_max_level =
+                                        data->smc_state_table.soc_max_level;
+                }
+        }
+
         return 0;
 }
 
@@ -4028,6 +4066,24 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
 
                 break;
 
+        case PP_SOCCLK:
+                data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
+                data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
+
+                PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
+                        "Failed to upload boot level to lowest!",
+                        return -EINVAL);
+
+                PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
+                        "Failed to upload dpm max level to highest!",
+                        return -EINVAL);
+
+                break;
+
+        case PP_DCEFCLK:
+                pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
+                break;
+
         case PP_PCIE:
         default:
                 break;
@@ -4267,12 +4323,113 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
         return result;
 }
 
+static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
+{
+        static const char *ppfeature_name[] = {
+                                "DPM_PREFETCHER",
+                                "GFXCLK_DPM",
+                                "UCLK_DPM",
+                                "SOCCLK_DPM",
+                                "UVD_DPM",
+                                "VCE_DPM",
+                                "ULV",
+                                "MP0CLK_DPM",
+                                "LINK_DPM",
+                                "DCEFCLK_DPM",
+                                "AVFS",
+                                "GFXCLK_DS",
+                                "SOCCLK_DS",
+                                "LCLK_DS",
+                                "PPT",
+                                "TDC",
+                                "THERMAL",
+                                "GFX_PER_CU_CG",
+                                "RM",
+                                "DCEFCLK_DS",
+                                "ACDC",
+                                "VR0HOT",
+                                "VR1HOT",
+                                "FW_CTF",
+                                "LED_DISPLAY",
+                                "FAN_CONTROL",
+                                "FAST_PPT",
+                                "DIDT",
+                                "ACG",
+                                "PCC_LIMIT"};
+        static const char *output_title[] = {
+                                "FEATURES",
+                                "BITMASK",
+                                "ENABLEMENT"};
+        uint64_t features_enabled;
+        int i;
+        int ret = 0;
+        int size = 0;
+
+        ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
+        PP_ASSERT_WITH_CODE(!ret,
+                        "[EnableAllSmuFeatures] Failed to get enabled smc features!",
+                        return ret);
+
+        size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
+        size += sprintf(buf + size, "%-19s %-22s %s\n",
+                                output_title[0],
+                                output_title[1],
+                                output_title[2]);
+        for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+                size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
+                                        ppfeature_name[i],
+                                        1ULL << i,
+                                        (features_enabled & (1ULL << i)) ? "Y" : "N");
+        }
+
+        return size;
+}
+
+static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
+{
+        uint64_t features_enabled;
+        uint64_t features_to_enable;
+        uint64_t features_to_disable;
+        int ret = 0;
+
+        if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
+                return -EINVAL;
+
+        ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
+        if (ret)
+                return ret;
+
+        features_to_disable =
+                (features_enabled ^ new_ppfeature_masks) & features_enabled;
+        features_to_enable =
+                (features_enabled ^ new_ppfeature_masks) ^ features_to_disable;
+
+        pr_debug("features_to_disable 0x%llx\n", features_to_disable);
+        pr_debug("features_to_enable 0x%llx\n", features_to_enable);
+
+        if (features_to_disable) {
+                ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
+                if (ret)
+                        return ret;
+        }
+
+        if (features_to_enable) {
+                ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, char *buf)
 {
         struct vega10_hwmgr *data = hwmgr->backend;
         struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
         struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
+        struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
+        struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
         struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
         struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
 
@@ -4303,6 +4460,32 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
                                         i, mclk_table->dpm_levels[i].value / 100,
                                         (i == now) ? "*" : "");
                 break;
+        case PP_SOCCLK:
+                if (data->registry_data.socclk_dpm_key_disabled)
+                        break;
+
+                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex);
+                now = smum_get_argument(hwmgr);
+
+                for (i = 0; i < soc_table->count; i++)
+                        size += sprintf(buf + size, "%d: %uMhz %s\n",
+                                        i, soc_table->dpm_levels[i].value / 100,
+                                        (i == now) ? "*" : "");
+                break;
+        case PP_DCEFCLK:
+                if (data->registry_data.dcefclk_dpm_key_disabled)
+                        break;
+
+                smum_send_msg_to_smc_with_parameter(hwmgr,
+                                PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK);
+                now = smum_get_argument(hwmgr);
+
+                for (i = 0; i < dcef_table->count; i++)
+                        size += sprintf(buf + size, "%d: %uMhz %s\n",
+                                        i, dcef_table->dpm_levels[i].value / 100,
+                                        (dcef_table->dpm_levels[i].value / 100 == now) ?
+                                        "*" : "");
+                break;
         case PP_PCIE:
                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
                 now = smum_get_argument(hwmgr);
@@ -4668,13 +4851,15 @@ static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
 {
         struct vega10_hwmgr *data = hwmgr->backend;
         uint32_t i, size = 0;
-        static const uint8_t profile_mode_setting[5][4] = {{70, 60, 1, 3,},
+        static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
+                                                {70, 60, 1, 3,},
                                                 {90, 60, 0, 0,},
                                                 {70, 60, 0, 0,},
                                                 {70, 90, 0, 0,},
                                                 {30, 60, 0, 6,},
                                                 };
-        static const char *profile_name[6] = {"3D_FULL_SCREEN",
+        static const char *profile_name[7] = {"BOOTUP_DEFAULT",
+                                        "3D_FULL_SCREEN",
                                         "POWER_SAVING",
                                         "VIDEO",
                                         "VR",
@@ -4978,6 +5163,12 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
         .set_power_limit = vega10_set_power_limit,
         .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
         .get_performance_level = vega10_get_performance_level,
+        .get_asic_baco_capability = vega10_baco_get_capability,
+        .get_asic_baco_state = vega10_baco_get_state,
+        .set_asic_baco_state = vega10_baco_set_state,
+        .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
+        .get_ppfeature_status = vega10_get_ppfeature_status,
+        .set_ppfeature_status = vega10_set_ppfeature_status,
 };
 
 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 89870556de1b..f752b4ad0c8a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -199,6 +199,7 @@ struct vega10_smc_state_table {
         uint32_t        vce_boot_level;
         uint32_t        gfx_max_level;
         uint32_t        mem_max_level;
+        uint32_t        soc_max_level;
         uint8_t         vr_hot_gpio;
         uint8_t         ac_dc_gpio;
         uint8_t         therm_out_gpio;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
index b3e63003a789..c934e9612c1b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
@@ -282,6 +282,30 @@ typedef struct _ATOM_Vega10_Fan_Table_V2 {
         UCHAR   ucFanMaxRPM;
 } ATOM_Vega10_Fan_Table_V2;
 
+typedef struct _ATOM_Vega10_Fan_Table_V3 {
+        UCHAR   ucRevId;
+        USHORT  usFanOutputSensitivity;
+        USHORT  usFanAcousticLimitRpm;
+        USHORT  usThrottlingRPM;
+        USHORT  usTargetTemperature;
+        USHORT  usMinimumPWMLimit;
+        USHORT  usTargetGfxClk;
+        USHORT  usFanGainEdge;
+        USHORT  usFanGainHotspot;
+        USHORT  usFanGainLiquid;
+        USHORT  usFanGainVrVddc;
+        USHORT  usFanGainVrMvdd;
+        USHORT  usFanGainPlx;
+        USHORT  usFanGainHbm;
+        UCHAR   ucEnableZeroRPM;
+        USHORT  usFanStopTemperature;
+        USHORT  usFanStartTemperature;
+        UCHAR   ucFanParameters;
+        UCHAR   ucFanMinRPM;
+        UCHAR   ucFanMaxRPM;
+        USHORT  usMGpuThrottlingRPM;
+} ATOM_Vega10_Fan_Table_V3;
+
 typedef struct _ATOM_Vega10_Thermal_Controller {
         UCHAR ucRevId;
         UCHAR ucType;           /* one of ATOM_VEGA10_PP_THERMALCONTROLLER_*/
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
index b8747a5c9204..b6767d74dc85 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
@@ -32,6 +32,7 @@
 #include "vega10_pptable.h"
 
 #define NUM_DSPCLK_LEVELS 8
+#define VEGA10_ENGINECLOCK_HARDMAX 198000
 
 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
                 enum phm_platform_caps cap)
@@ -122,6 +123,7 @@ static int init_thermal_controller(
         const Vega10_PPTable_Generic_SubTable_Header *header;
         const ATOM_Vega10_Fan_Table *fan_table_v1;
         const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
+        const ATOM_Vega10_Fan_Table_V3 *fan_table_v3;
 
         thermal_controller = (ATOM_Vega10_Thermal_Controller *)
                         (((unsigned long)powerplay_table) +
@@ -206,7 +208,7 @@ static int init_thermal_controller(
                                 le16_to_cpu(fan_table_v1->usFanStopTemperature);
                 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
                                 le16_to_cpu(fan_table_v1->usFanStartTemperature);
-        } else if (header->ucRevId > 10) {
+        } else if (header->ucRevId == 0xb) {
                 fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
 
                 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
@@ -250,7 +252,54 @@ static int init_thermal_controller(
                                 le16_to_cpu(fan_table_v2->usFanStopTemperature);
                 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
                                 le16_to_cpu(fan_table_v2->usFanStartTemperature);
+        } else if (header->ucRevId > 0xb) {
+                fan_table_v3 = (ATOM_Vega10_Fan_Table_V3 *)header;
+
+                hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
+                                fan_table_v3->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
+                hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v3->ucFanMinRPM * 100UL;
+                hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v3->ucFanMaxRPM * 100UL;
+                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+                                PHM_PlatformCaps_MicrocodeFanControl);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
+                                le16_to_cpu(fan_table_v3->usFanOutputSensitivity);
+                hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
+                                fan_table_v3->ucFanMaxRPM * 100UL;
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
+                                le16_to_cpu(fan_table_v3->usThrottlingRPM);
+                hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
+                                le16_to_cpu(fan_table_v3->usFanAcousticLimitRpm);
+                hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
+                                le16_to_cpu(fan_table_v3->usTargetTemperature);
+                hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
+                                le16_to_cpu(fan_table_v3->usMinimumPWMLimit);
+                hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
+                                le16_to_cpu(fan_table_v3->usTargetGfxClk);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
+                                le16_to_cpu(fan_table_v3->usFanGainEdge);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
+                                le16_to_cpu(fan_table_v3->usFanGainHotspot);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
+                                le16_to_cpu(fan_table_v3->usFanGainLiquid);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
+                                le16_to_cpu(fan_table_v3->usFanGainVrVddc);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
+                                le16_to_cpu(fan_table_v3->usFanGainVrMvdd);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
+                                le16_to_cpu(fan_table_v3->usFanGainPlx);
+                hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
+                                le16_to_cpu(fan_table_v3->usFanGainHbm);
+
+                hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
+                                fan_table_v3->ucEnableZeroRPM;
+                hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
+                                le16_to_cpu(fan_table_v3->usFanStopTemperature);
+                hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
+                                le16_to_cpu(fan_table_v3->usFanStartTemperature);
+                hwmgr->thermal_controller.advanceFanControlParameters.usMGpuThrottlingRPMLimit =
+                                le16_to_cpu(fan_table_v3->usMGpuThrottlingRPM);
         }
+
         return 0;
 }
 
@@ -258,7 +307,26 @@ static int init_over_drive_limits(
                 struct pp_hwmgr *hwmgr,
                 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
 {
-        hwmgr->platform_descriptor.overdriveLimit.engineClock =
+        const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
+                        (const ATOM_Vega10_GFXCLK_Dependency_Table *)
+                        (((unsigned long) powerplay_table) +
+                        le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
+        bool is_acg_enabled = false;
+        ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
+
+        if (gfxclk_dep_table->ucRevId == 1) {
+                patom_record_v2 =
+                        (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
+                is_acg_enabled =
+                        (bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable;
+        }
+
+        if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX &&
+                !is_acg_enabled)
+                hwmgr->platform_descriptor.overdriveLimit.engineClock =
+                        VEGA10_ENGINECLOCK_HARDMAX;
+        else
+                hwmgr->platform_descriptor.overdriveLimit.engineClock =
                         le32_to_cpu(powerplay_table->ulMaxODEngineClock);
         hwmgr->platform_descriptor.overdriveLimit.memoryClock =
                         le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index 3f807d6c95ce..ba8763daa380 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -556,6 +556,43 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
         return ret;
 }
 
+int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
+{
+        struct vega10_hwmgr *data = hwmgr->backend;
+        PPTable_t *table = &(data->smc_state_table.pp_table);
+        int ret;
+
+        if (!data->smu_features[GNLD_FAN_CONTROL].supported)
+                return 0;
+
+        if (!hwmgr->thermal_controller.advanceFanControlParameters.
+                        usMGpuThrottlingRPMLimit)
+                return 0;
+
+        table->FanThrottlingRpm = hwmgr->thermal_controller.
+                        advanceFanControlParameters.usMGpuThrottlingRPMLimit;
+
+        ret = smum_smc_table_manager(hwmgr,
+                                (uint8_t *)(&(data->smc_state_table.pp_table)),
+                                PPTABLE, false);
+        if (ret) {
+                pr_info("Failed to update fan control table in pptable!");
+                return ret;
+        }
+
+        ret = vega10_disable_fan_control_feature(hwmgr);
+        if (ret) {
+                pr_info("Attempt to disable SMC fan control feature failed!");
+                return ret;
+        }
+
+        ret = vega10_enable_fan_control_feature(hwmgr);
+        if (ret)
+                pr_info("Attempt to enable SMC fan control feature failed!");
+
+        return ret;
+}
+
 /**
 * Start the fan control on the SMC.
 * @param    hwmgr  the address of the powerplay hardware manager.
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
index 21e7c4dfa2ca..4a0ede7c1f07 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
@@ -73,6 +73,7 @@ extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr);
 extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
 extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
                                 struct PP_TemperatureRange *range);
+extern int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr);
 
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 54364444ecd1..6c8e78611c03 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -753,6 +753,22 @@ static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
+static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
+{
+        uint32_t result;
+
+        PP_ASSERT_WITH_CODE(
+                smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc) == 0,
+                "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
+                return -EINVAL);
+
+        result = smum_get_argument(hwmgr);
+        PP_ASSERT_WITH_CODE(result == 1,
+                        "Failed to run ACG BTC!", return -EINVAL);
+
+        return 0;
+}
+
 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 {
         struct vega12_hwmgr *data =
@@ -931,6 +947,11 @@ static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
                         "Failed to initialize SMC table!",
                         result = tmp_result);
 
+        tmp_result = vega12_run_acg_btc(hwmgr);
+        PP_ASSERT_WITH_CODE(!tmp_result,
+                        "Failed to run ACG BTC!",
+                        result = tmp_result);
+
         result = vega12_enable_all_smu_features(hwmgr);
         PP_ASSERT_WITH_CODE(!result,
                         "Failed to enable all smu features!",
@@ -1072,6 +1093,16 @@ static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
                                         return ret);
         }
 
+        if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
+                min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
+
+                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+                                        hwmgr, PPSMC_MSG_SetHardMinByFreq,
+                                        (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff))),
+                                        "Failed to set hard min dcefclk!",
+                                        return ret);
+        }
+
         return ret;
 
 }
@@ -1797,7 +1828,7 @@ static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask)
 {
         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
-        uint32_t soft_min_level, soft_max_level;
+        uint32_t soft_min_level, soft_max_level, hard_min_level;
         int ret = 0;
 
         switch (type) {
@@ -1842,6 +1873,56 @@ static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
 
                 break;
 
+        case PP_SOCCLK:
+                soft_min_level = mask ? (ffs(mask) - 1) : 0;
+                soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+                if (soft_max_level >= data->dpm_table.soc_table.count) {
+                        pr_err("Clock level specified %d is over max allowed %d\n",
+                                        soft_max_level,
+                                        data->dpm_table.soc_table.count - 1);
+                        return -EINVAL;
+                }
+
+                data->dpm_table.soc_table.dpm_state.soft_min_level =
+                        data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
+                data->dpm_table.soc_table.dpm_state.soft_max_level =
+                        data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
+
+                ret = vega12_upload_dpm_min_level(hwmgr);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload boot level to lowest!",
+                        return ret);
+
+                ret = vega12_upload_dpm_max_level(hwmgr);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload dpm max level to highest!",
+                        return ret);
+
+                break;
+
+        case PP_DCEFCLK:
+                hard_min_level = mask ? (ffs(mask) - 1) : 0;
+
+                if (hard_min_level >= data->dpm_table.dcef_table.count) {
+                        pr_err("Clock level specified %d is over max allowed %d\n",
+                                        hard_min_level,
+                                        data->dpm_table.dcef_table.count - 1);
+                        return -EINVAL;
+                }
+
+                data->dpm_table.dcef_table.dpm_state.hard_min_level =
+                        data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
+
+                ret = vega12_upload_dpm_min_level(hwmgr);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload boot level to lowest!",
+                        return ret);
+
+                //TODO: Setting DCEFCLK max dpm level is not supported
+
+                break;
+
         case PP_PCIE:
                 break;
 
@@ -1852,6 +1933,104 @@ static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
         return 0;
 }
 
+static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
+{
+        static const char *ppfeature_name[] = {
+                        "DPM_PREFETCHER",
+                        "GFXCLK_DPM",
+                        "UCLK_DPM",
+                        "SOCCLK_DPM",
+                        "UVD_DPM",
+                        "VCE_DPM",
+                        "ULV",
+                        "MP0CLK_DPM",
+                        "LINK_DPM",
+                        "DCEFCLK_DPM",
+                        "GFXCLK_DS",
+                        "SOCCLK_DS",
+                        "LCLK_DS",
+                        "PPT",
+                        "TDC",
+                        "THERMAL",
+                        "GFX_PER_CU_CG",
+                        "RM",
+                        "DCEFCLK_DS",
+                        "ACDC",
+                        "VR0HOT",
+                        "VR1HOT",
+                        "FW_CTF",
+                        "LED_DISPLAY",
+                        "FAN_CONTROL",
+                        "DIDT",
+                        "GFXOFF",
+                        "CG",
+                        "ACG"};
+        static const char *output_title[] = {
+                        "FEATURES",
+                        "BITMASK",
+                        "ENABLEMENT"};
+        uint64_t features_enabled;
+        int i;
+        int ret = 0;
+        int size = 0;
+
+        ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
+        PP_ASSERT_WITH_CODE(!ret,
+                "[EnableAllSmuFeatures] Failed to get enabled smc features!",
+                return ret);
+
+        size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
+        size += sprintf(buf + size, "%-19s %-22s %s\n",
+                                output_title[0],
+                                output_title[1],
+                                output_title[2]);
+        for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+                size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
+                                ppfeature_name[i],
+                                1ULL << i,
+                                (features_enabled & (1ULL << i)) ? "Y" : "N");
+        }
+
+        return size;
+}
+
+static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
+{
+        uint64_t features_enabled;
+        uint64_t features_to_enable;
+        uint64_t features_to_disable;
+        int ret = 0;
+
+        if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
+                return -EINVAL;
+
+        ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
+        if (ret)
+                return ret;
+
+        features_to_disable =
+                (features_enabled ^ new_ppfeature_masks) & features_enabled;
+        features_to_enable =
+                (features_enabled ^ new_ppfeature_masks) ^ features_to_disable;
+
+        pr_debug("features_to_disable 0x%llx\n", features_to_disable);
+        pr_debug("features_to_enable 0x%llx\n", features_to_enable);
+
+        if (features_to_disable) {
+                ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
+                if (ret)
+                        return ret;
+        }
+
+        if (features_to_enable) {
+                ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, char *buf)
 {
@@ -1891,6 +2070,42 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
                                 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
                 break;
 
+        case PP_SOCCLK:
+                PP_ASSERT_WITH_CODE(
+                                smum_send_msg_to_smc_with_parameter(hwmgr,
+                                        PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16)) == 0,
+                                "Attempt to get Current SOCCLK Frequency Failed!",
+                                return -EINVAL);
+                now = smum_get_argument(hwmgr);
+
+                PP_ASSERT_WITH_CODE(
+                                vega12_get_socclocks(hwmgr, &clocks) == 0,
+                                "Attempt to get soc clk levels Failed!",
+                                return -1);
+                for (i = 0; i < clocks.num_levels; i++)
+                        size += sprintf(buf + size, "%d: %uMhz %s\n",
+                                i, clocks.data[i].clocks_in_khz / 1000,
+                                (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
+                break;
+
+        case PP_DCEFCLK:
+                PP_ASSERT_WITH_CODE(
+                                smum_send_msg_to_smc_with_parameter(hwmgr,
+                                        PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16)) == 0,
+                                "Attempt to get Current DCEFCLK Frequency Failed!",
+                                return -EINVAL);
+                now = smum_get_argument(hwmgr);
+
+                PP_ASSERT_WITH_CODE(
+                                vega12_get_dcefclocks(hwmgr, &clocks) == 0,
+                                "Attempt to get dcef clk levels Failed!",
+                                return -1);
+                for (i = 0; i < clocks.num_levels; i++)
+                        size += sprintf(buf + size, "%d: %uMhz %s\n",
+                                i, clocks.data[i].clocks_in_khz / 1000,
+                                (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
+                break;
+
         case PP_PCIE:
                 break;
 
@@ -2411,6 +2626,8 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
         .start_thermal_controller = vega12_start_thermal_controller,
         .powergate_gfx = vega12_gfx_off_control,
         .get_performance_level = vega12_get_performance_level,
+        .get_ppfeature_status = vega12_get_ppfeature_status,
+        .set_ppfeature_status = vega12_set_ppfeature_status,
 };
 
 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
new file mode 100644
index 000000000000..0d883b358df2
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
@@ -0,0 +1,81 @@
+#include "amdgpu.h"
+#include "soc15.h"
+#include "soc15_hw_ip.h"
+#include "soc15_common.h"
+#include "vega20_inc.h"
+#include "vega20_ppsmc.h"
+#include "vega20_baco.h"
+
+
+
+static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
+{
+        {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
+        {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
+};
+
+int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        uint32_t reg;
+
+        *cap = false;
+        if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
+                return 0;
+
+        if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
+                reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
+
+                if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
+                        *cap = true;
+        }
+
+        return 0;
+}
+
+int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        uint32_t reg;
+
+        reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
+
+        if (reg & BACO_CNTL__BACO_MODE_MASK)
+                /* gfx has already entered BACO state */
+                *state = BACO_STATE_IN;
+        else
+                *state = BACO_STATE_OUT;
+        return 0;
+}
+
+int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+        enum BACO_STATE cur_state;
+        uint32_t data;
+
+        vega20_baco_get_state(hwmgr, &cur_state);
+
+        if (cur_state == state)
+                /* aisc already in the target state */
+                return 0;
+
+        if (state == BACO_STATE_IN) {
+                data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+                data |= 0x80000000;
+                WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+
+
+                if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
+                        return -1;
+
+        } else if (state == BACO_STATE_OUT) {
+                if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
+                        return -1;
+                if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
+                                                     ARRAY_SIZE(clean_baco_tbl)))
+                        return -1;
+        }
+
+        return 0;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
index b6ac47617c70..c51988a9ed77 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012-16 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,14 +19,14 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: AMD
- *
  */
+#ifndef __VEGA20_BOCO_H__
+#define __VEGA20_BOCO_H__
+#include "hwmgr.h"
+#include "common_baco.h"
 
-#ifndef __DAL_I2C_AUX_DCE120_H__
-#define __DAL_I2C_AUX_DCE120_H__
-
-struct i2caux *dal_i2caux_dce120_create(
-        struct dc_context *ctx);
+extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
+extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
 
-#endif /* __DAL_I2C_AUX_DCE120_H__ */
+#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 26154f9b2178..7b49a9a13a4a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -47,6 +47,7 @@
 #include "pp_overdriver.h"
 #include "pp_thermal.h"
 #include "soc15_common.h"
+#include "vega20_baco.h"
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 #include "nbio/nbio_7_4_sh_mask.h"
@@ -390,9 +391,9 @@ static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 
         hwmgr->backend = data;
 
-        hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
-        hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
-        hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
+        hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
+        hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+        hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 
         vega20_set_default_registry_data(hwmgr);
 
@@ -803,6 +804,11 @@ static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
+static int vega20_run_btc(struct pp_hwmgr *hwmgr)
+{
+        return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc);
+}
+
 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 {
         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
@@ -980,6 +986,9 @@ static int vega20_od8_set_feature_capabilities(
             pp_table->FanZeroRpmEnable)
                 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
 
+        if (!od_settings->overdrive8_capabilities)
+                hwmgr->od_enabled = false;
+
         return 0;
 }
 
@@ -1561,6 +1570,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
                         "[EnableDPMTasks] Failed to initialize SMC table!",
                         return result);
 
+        result = vega20_run_btc(hwmgr);
+        PP_ASSERT_WITH_CODE(!result,
+                        "[EnableDPMTasks] Failed to run btc!",
+                        return result);
+
         result = vega20_run_btc_afll(hwmgr);
         PP_ASSERT_WITH_CODE(!result,
                         "[EnableDPMTasks] Failed to run btc afll!",
@@ -1689,13 +1703,6 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_
                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
                                         "Failed to set soft min memclk !",
                                         return ret);
-
-                min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
-                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
-                                        hwmgr, PPSMC_MSG_SetHardMinByFreq,
-                                        (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
-                                        "Failed to set hard min memclk !",
-                                        return ret);
         }
 
         if (data->smu_features[GNLD_DPM_UVD].enabled &&
@@ -1739,6 +1746,28 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_
                                         return ret);
         }
 
+        if (data->smu_features[GNLD_DPM_FCLK].enabled &&
+           (feature_mask & FEATURE_DPM_FCLK_MASK)) {
+                min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
+
+                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+                                        hwmgr, PPSMC_MSG_SetSoftMinByFreq,
+                                        (PPCLK_FCLK << 16) | (min_freq & 0xffff))),
+                                        "Failed to set soft min fclk!",
+                                        return ret);
+        }
+
+        if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
+           (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
+                min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
+
+                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+                                        hwmgr, PPSMC_MSG_SetHardMinByFreq,
+                                        (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff))),
+                                        "Failed to set hard min dcefclk!",
+                                        return ret);
+        }
+
         return ret;
 }
 
@@ -1811,6 +1840,17 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_
                                         return ret);
         }
 
+        if (data->smu_features[GNLD_DPM_FCLK].enabled &&
+           (feature_mask & FEATURE_DPM_FCLK_MASK)) {
+                max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
+
+                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
+                                        hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
+                                        (PPCLK_FCLK << 16) | (max_freq & 0xffff))),
+                                        "Failed to set soft max fclk!",
+                                        return ret);
+        }
+
         return ret;
 }
 
@@ -1918,16 +1958,36 @@ static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
         return (mem_clk * 100);
 }
 
+static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
+{
+        struct vega20_hwmgr *data =
+                        (struct vega20_hwmgr *)(hwmgr->backend);
+        int ret = 0;
+
+        if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ / 2)) {
+                ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
+                                TABLE_SMU_METRICS, true);
+                if (ret) {
+                        pr_info("Failed to export SMU metrics table!\n");
+                        return ret;
+                }
+                memcpy(&data->metrics_table, metrics_table, sizeof(SmuMetrics_t));
+                data->metrics_time = jiffies;
+        } else
+                memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
+
+        return ret;
+}
+
 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
                 uint32_t *query)
 {
         int ret = 0;
         SmuMetrics_t metrics_table;
 
-        ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
-        PP_ASSERT_WITH_CODE(!ret,
-                        "Failed to export SMU METRICS table!",
-                        return ret);
+        ret = vega20_get_metrics_table(hwmgr, &metrics_table);
+        if (ret)
+                return ret;
 
         *query = metrics_table.CurrSocketPower << 8;
 
@@ -1958,10 +2018,9 @@ static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
         int ret = 0;
         SmuMetrics_t metrics_table;
 
-        ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
-        PP_ASSERT_WITH_CODE(!ret,
-                        "Failed to export SMU METRICS table!",
-                        return ret);
+        ret = vega20_get_metrics_table(hwmgr, &metrics_table);
+        if (ret)
+                return ret;
 
         *activity_percent = metrics_table.AverageGfxActivity;
 
@@ -1973,16 +2032,18 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 {
         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
         struct amdgpu_device *adev = hwmgr->adev;
+        SmuMetrics_t metrics_table;
         uint32_t val_vid;
         int ret = 0;
 
         switch (idx) {
         case AMDGPU_PP_SENSOR_GFX_SCLK:
-                ret = vega20_get_current_clk_freq(hwmgr,
-                                PPCLK_GFXCLK,
-                                (uint32_t *)value);
-                if (!ret)
-                        *size = 4;
+                ret = vega20_get_metrics_table(hwmgr, &metrics_table);
+                if (ret)
+                        return ret;
+
+                *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
+                *size = 4;
                 break;
         case AMDGPU_PP_SENSOR_GFX_MCLK:
                 ret = vega20_get_current_clk_freq(hwmgr,
@@ -2140,6 +2201,12 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
                 data->dpm_table.mem_table.dpm_state.soft_max_level =
                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
 
+        soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
+
+        data->dpm_table.soc_table.dpm_state.soft_min_level =
+                data->dpm_table.soc_table.dpm_state.soft_max_level =
+                data->dpm_table.soc_table.dpm_levels[soft_level].value;
+
         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
         PP_ASSERT_WITH_CODE(!ret,
                         "Failed to upload boot level to highest!",
@@ -2172,6 +2239,12 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
                 data->dpm_table.mem_table.dpm_state.soft_max_level =
                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
 
+        soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
+
+        data->dpm_table.soc_table.dpm_state.soft_min_level =
+                data->dpm_table.soc_table.dpm_state.soft_max_level =
+                data->dpm_table.soc_table.dpm_levels[soft_level].value;
+
         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
         PP_ASSERT_WITH_CODE(!ret,
                         "Failed to upload boot level to highest!",
@@ -2188,8 +2261,32 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
 
 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
 {
+        struct vega20_hwmgr *data =
+                        (struct vega20_hwmgr *)(hwmgr->backend);
+        uint32_t soft_min_level, soft_max_level;
         int ret = 0;
 
+        soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
+        soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
+        data->dpm_table.gfx_table.dpm_state.soft_min_level =
+                data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
+        data->dpm_table.gfx_table.dpm_state.soft_max_level =
+                data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
+
+        soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
+        soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
+        data->dpm_table.mem_table.dpm_state.soft_min_level =
+                data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
+        data->dpm_table.mem_table.dpm_state.soft_max_level =
+                data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
+
+        soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
+        soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
+        data->dpm_table.soc_table.dpm_state.soft_min_level =
+                data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
+        data->dpm_table.soc_table.dpm_state.soft_max_level =
+                data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
+
         ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
         PP_ASSERT_WITH_CODE(!ret,
                         "Failed to upload DPM Bootup Levels!",
@@ -2240,7 +2337,7 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, uint32_t mask)
 {
         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
-        uint32_t soft_min_level, soft_max_level;
+        uint32_t soft_min_level, soft_max_level, hard_min_level;
         int ret = 0;
 
         switch (type) {
@@ -2248,6 +2345,13 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
                 soft_max_level = mask ? (fls(mask) - 1) : 0;
 
+                if (soft_max_level >= data->dpm_table.gfx_table.count) {
+                        pr_err("Clock level specified %d is over max allowed %d\n",
+                                        soft_max_level,
+                                        data->dpm_table.gfx_table.count - 1);
+                        return -EINVAL;
+                }
+
                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
@@ -2268,6 +2372,13 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
                 soft_max_level = mask ? (fls(mask) - 1) : 0;
 
+                if (soft_max_level >= data->dpm_table.mem_table.count) {
+                        pr_err("Clock level specified %d is over max allowed %d\n",
+                                        soft_max_level,
+                                        data->dpm_table.mem_table.count - 1);
+                        return -EINVAL;
+                }
+
                 data->dpm_table.mem_table.dpm_state.soft_min_level =
                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
                 data->dpm_table.mem_table.dpm_state.soft_max_level =
@@ -2285,6 +2396,84 @@ static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
 
                 break;
 
+        case PP_SOCCLK:
+                soft_min_level = mask ? (ffs(mask) - 1) : 0;
+                soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+                if (soft_max_level >= data->dpm_table.soc_table.count) {
+                        pr_err("Clock level specified %d is over max allowed %d\n",
+                                        soft_max_level,
+                                        data->dpm_table.soc_table.count - 1);
+                        return -EINVAL;
+                }
+
+                data->dpm_table.soc_table.dpm_state.soft_min_level =
+                        data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
+                data->dpm_table.soc_table.dpm_state.soft_max_level =
+                        data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
+
+                ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload boot level to lowest!",
+                        return ret);
+
+                ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload dpm max level to highest!",
+                        return ret);
+
+                break;
+
+        case PP_FCLK:
+                soft_min_level = mask ? (ffs(mask) - 1) : 0;
+                soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+                if (soft_max_level >= data->dpm_table.fclk_table.count) {
+                        pr_err("Clock level specified %d is over max allowed %d\n",
+                                        soft_max_level,
+                                        data->dpm_table.fclk_table.count - 1);
+                        return -EINVAL;
+                }
+
+                data->dpm_table.fclk_table.dpm_state.soft_min_level =
+                        data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
+                data->dpm_table.fclk_table.dpm_state.soft_max_level =
+                        data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
+
+                ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload boot level to lowest!",
+                        return ret);
+
+                ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload dpm max level to highest!",
+                        return ret);
+
+                break;
+
+        case PP_DCEFCLK:
+                hard_min_level = mask ? (ffs(mask) - 1) : 0;
+
+                if (hard_min_level >= data->dpm_table.dcef_table.count) {
+                        pr_err("Clock level specified %d is over max allowed %d\n",
+                                        hard_min_level,
+                                        data->dpm_table.dcef_table.count - 1);
+                        return -EINVAL;
+                }
+
+                data->dpm_table.dcef_table.dpm_state.hard_min_level =
+                        data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
+
+                ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
+                PP_ASSERT_WITH_CODE(!ret,
+                        "Failed to upload boot level to lowest!",
+                        return ret);
+
+                //TODO: Setting DCEFCLK max dpm level is not supported
+
+                break;
+
         case PP_PCIE:
                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
                 soft_max_level = mask ? (fls(mask) - 1) : 0;
@@ -2335,6 +2524,7 @@ static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
                         return ret;
                 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
                 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
+                vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
                 break;
 
         case AMD_DPM_FORCED_LEVEL_MANUAL:
@@ -2765,6 +2955,108 @@ static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
         return 0;
 }
 
+static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
+{
+        static const char *ppfeature_name[] = {
+                                "DPM_PREFETCHER",
+                                "GFXCLK_DPM",
+                                "UCLK_DPM",
+                                "SOCCLK_DPM",
+                                "UVD_DPM",
+                                "VCE_DPM",
+                                "ULV",
+                                "MP0CLK_DPM",
+                                "LINK_DPM",
+                                "DCEFCLK_DPM",
+                                "GFXCLK_DS",
+                                "SOCCLK_DS",
+                                "LCLK_DS",
+                                "PPT",
+                                "TDC",
+                                "THERMAL",
+                                "GFX_PER_CU_CG",
+                                "RM",
+                                "DCEFCLK_DS",
+                                "ACDC",
+                                "VR0HOT",
+                                "VR1HOT",
+                                "FW_CTF",
+                                "LED_DISPLAY",
+                                "FAN_CONTROL",
+                                "GFX_EDC",
+                                "GFXOFF",
+                                "CG",
+                                "FCLK_DPM",
+                                "FCLK_DS",
+                                "MP1CLK_DS",
+                                "MP0CLK_DS",
+                                "XGMI"};
+        static const char *output_title[] = {
+                                "FEATURES",
+                                "BITMASK",
+                                "ENABLEMENT"};
+        uint64_t features_enabled;
+        int i;
+        int ret = 0;
+        int size = 0;
+
+        ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
+        PP_ASSERT_WITH_CODE(!ret,
+                        "[EnableAllSmuFeatures] Failed to get enabled smc features!",
+                        return ret);
+
+        size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
+        size += sprintf(buf + size, "%-19s %-22s %s\n",
+                                output_title[0],
+                                output_title[1],
+                                output_title[2]);
+        for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+                size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
+                                        ppfeature_name[i],
+                                        1ULL << i,
+                                        (features_enabled & (1ULL << i)) ? "Y" : "N");
+        }
+
+        return size;
+}
+
+static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
+{
+        uint64_t features_enabled;
+        uint64_t features_to_enable;
+        uint64_t features_to_disable;
+        int ret = 0;
+
+        if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
+                return -EINVAL;
+
+        ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
+        if (ret)
+                return ret;
+
+        features_to_disable =
+                (features_enabled ^ new_ppfeature_masks) & features_enabled;
+        features_to_enable =
+                (features_enabled ^ new_ppfeature_masks) ^ features_to_disable;
+
+        pr_debug("features_to_disable 0x%llx\n", features_to_disable);
+        pr_debug("features_to_enable 0x%llx\n", features_to_enable);
+
+        if (features_to_disable) {
+                ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
+                if (ret)
+                        return ret;
+        }
+
+        if (features_to_enable) {
+                ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
                 enum pp_clock_type type, char *buf)
 {
@@ -2779,6 +3071,8 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
         PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
         struct amdgpu_device *adev = hwmgr->adev;
         struct pp_clock_levels_with_latency clocks;
+        struct vega20_single_dpm_table *fclk_dpm_table =
+                        &(data->dpm_table.fclk_table);
         int i, now, size = 0;
         int ret = 0;
         uint32_t gen_speed, lane_width;
@@ -2818,6 +3112,52 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
                 break;
 
+        case PP_SOCCLK:
+                ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
+                PP_ASSERT_WITH_CODE(!ret,
+                                "Attempt to get current socclk freq Failed!",
+                                return ret);
+
+                ret = vega20_get_socclocks(hwmgr, &clocks);
+                PP_ASSERT_WITH_CODE(!ret,
+                                "Attempt to get soc clk levels Failed!",
+                                return ret);
+
+                for (i = 0; i < clocks.num_levels; i++)
+                        size += sprintf(buf + size, "%d: %uMhz %s\n",
+                                i, clocks.data[i].clocks_in_khz / 1000,
+                                (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
+                break;
+
+        case PP_FCLK:
+                ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
+                PP_ASSERT_WITH_CODE(!ret,
+                                "Attempt to get current fclk freq Failed!",
+                                return ret);
+
+                for (i = 0; i < fclk_dpm_table->count; i++)
+                        size += sprintf(buf + size, "%d: %uMhz %s\n",
+                                i, fclk_dpm_table->dpm_levels[i].value,
+                                fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
+                break;
+
+        case PP_DCEFCLK:
+                ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
+                PP_ASSERT_WITH_CODE(!ret,
+                                "Attempt to get current dcefclk freq Failed!",
+                                return ret);
+
+                ret = vega20_get_dcefclocks(hwmgr, &clocks);
+                PP_ASSERT_WITH_CODE(!ret,
+                                "Attempt to get dcefclk levels Failed!",
+                                return ret);
+
+                for (i = 0; i < clocks.num_levels; i++)
+                        size += sprintf(buf + size, "%d: %uMhz %s\n",
+                                i, clocks.data[i].clocks_in_khz / 1000,
+                                (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
+                break;
+
         case PP_PCIE:
                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
@@ -3261,6 +3601,9 @@ static int conv_power_profile_to_pplib_workload(int power_profile)
         int pplib_workload = 0;
 
         switch (power_profile) {
+        case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
+                pplib_workload = WORKLOAD_DEFAULT_BIT;
+                break;
         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
                 break;
@@ -3290,6 +3633,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
         uint32_t i, size = 0;
         uint16_t workload_type = 0;
         static const char *profile_name[] = {
+                                        "BOOTUP_DEFAULT",
                                         "3D_FULL_SCREEN",
                                         "POWER_SAVING",
                                         "VIDEO",
@@ -3557,6 +3901,8 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
         .force_clock_level = vega20_force_clock_level,
         .print_clock_levels = vega20_print_clock_levels,
         .read_sensor = vega20_read_sensor,
+        .get_ppfeature_status = vega20_get_ppfeature_status,
+        .set_ppfeature_status = vega20_set_ppfeature_status,
         /* powergate related */
         .powergate_uvd = vega20_power_gate_uvd,
         .powergate_vce = vega20_power_gate_vce,
@@ -3577,6 +3923,10 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
         /* smu memory related */
         .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
         .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
+        /* BACO related */
+        .get_asic_baco_capability = vega20_baco_get_capability,
+        .get_asic_baco_state = vega20_baco_get_state,
+        .set_asic_baco_state = vega20_baco_set_state,
 };
 
 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 25faaa5c5b10..37f5f5e657da 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -520,6 +520,9 @@ struct vega20_hwmgr {
         /* ---- Gfxoff ---- */
         bool                           gfxoff_allowed;
         uint32_t                       counter_gfxoff;
+
+        unsigned long                  metrics_time;
+        SmuMetrics_t                   metrics_table;
 };
 
 #define VEGA20_DPM2_NEAR_TDP_DEC                      10
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h
index 6738bad53602..613cb1989b3d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h
@@ -31,5 +31,6 @@
 #include "asic_reg/mp/mp_9_0_sh_mask.h"
 
 #include "asic_reg/nbio/nbio_7_4_offset.h"
+#include "asic_reg/nbio/nbio_7_4_sh_mask.h"
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index f4dab979a3a1..6e0be6027705 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -397,7 +397,6 @@ struct phm_odn_clock_levels {
 };
 
 extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
-extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
 extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
 extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
 extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 0d298a0409f5..bac3d85e3b82 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -47,6 +47,11 @@ enum DISPLAY_GAP {
 };
 typedef enum DISPLAY_GAP DISPLAY_GAP;
 
+enum BACO_STATE {
+        BACO_STATE_OUT = 0,
+        BACO_STATE_IN,
+};
+
 struct vi_dpm_level {
         bool enabled;
         uint32_t value;
@@ -251,7 +256,6 @@ struct pp_hwmgr_func {
         uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
         int (*power_state_set)(struct pp_hwmgr *hwmgr,
                                                 const void *state);
-        int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
         int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
@@ -334,6 +338,11 @@ struct pp_hwmgr_func {
         int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
         int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
         int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
+        int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
+        int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
+        int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
+        int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
+        int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
 };
 
 struct pp_table_func {
@@ -678,6 +687,7 @@ struct pp_advance_fan_control_parameters {
         uint32_t  ulTargetGfxClk;
         uint16_t  usZeroRPMStartTemperature;
         uint16_t  usZeroRPMStopTemperature;
+        uint16_t  usMGpuThrottlingRPMLimit;
 };
 
 struct pp_thermal_controller_info {
@@ -705,7 +715,7 @@ enum PP_TABLE_VERSION {
 /**
  * The main hardware manager structure.
  */
-#define Workload_Policy_Max 5
+#define Workload_Policy_Max 6
 
 struct pp_hwmgr {
         void *adev;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
index 49a6763693f1..67ae26602024 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
@@ -109,16 +109,19 @@ static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job)
         }
 
         /* block scheduler */
-        kthread_park(gpu->sched.thread);
-        drm_sched_hw_job_reset(&gpu->sched, sched_job);
+        drm_sched_stop(&gpu->sched);
+
+        if(sched_job)
+                drm_sched_increase_karma(sched_job);
 
         /* get the GPU back into the init state */
         etnaviv_core_dump(gpu);
         etnaviv_gpu_recover_hang(gpu);
 
+        drm_sched_resubmit_jobs(&gpu->sched);
+
         /* restart scheduler after GPU is usable again */
-        drm_sched_job_recovery(&gpu->sched);
-        kthread_unpark(gpu->sched.thread);
+        drm_sched_start(&gpu->sched, true);
 }
 
 static void etnaviv_sched_free_job(struct drm_sched_job *sched_job)
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c
index d587779a80b4..a97294ac96d5 100644
--- a/drivers/gpu/drm/radeon/ci_dpm.c
+++ b/drivers/gpu/drm/radeon/ci_dpm.c
@@ -5676,7 +5676,7 @@ int ci_dpm_init(struct radeon_device *rdev)
         u16 data_offset, size;
         u8 frev, crev;
         struct ci_power_info *pi;
-        enum pci_bus_speed speed_cap;
+        enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN;
         struct pci_dev *root = rdev->pdev->bus->self;
         int ret;
 
@@ -5685,7 +5685,8 @@ int ci_dpm_init(struct radeon_device *rdev)
                 return -ENOMEM;
         rdev->pm.dpm.priv = pi;
 
-        speed_cap = pcie_get_speed_cap(root);
+        if (!pci_is_root_bus(rdev->pdev->bus))
+                speed_cap = pcie_get_speed_cap(root);
         if (speed_cap == PCI_SPEED_UNKNOWN) {
                 pi->sys_pcie_mask = 0;
         } else {
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index 8fb60b3af015..0a785ef0ab66 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -6899,7 +6899,7 @@ int si_dpm_init(struct radeon_device *rdev)
         struct ni_power_info *ni_pi;
         struct si_power_info *si_pi;
         struct atom_clock_dividers dividers;
-        enum pci_bus_speed speed_cap;
+        enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN;
         struct pci_dev *root = rdev->pdev->bus->self;
         int ret;
 
@@ -6911,7 +6911,8 @@ int si_dpm_init(struct radeon_device *rdev)
         eg_pi = &ni_pi->eg;
         pi = &eg_pi->rv7xx;
 
-        speed_cap = pcie_get_speed_cap(root);
+        if (!pci_is_root_bus(rdev->pdev->bus))
+                speed_cap = pcie_get_speed_cap(root);
         if (speed_cap == PCI_SPEED_UNKNOWN) {
                 si_pi->sys_pcie_mask = 0;
         } else {
diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
index dbb69063b3d5..19fc601c9eeb 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -60,8 +60,6 @@
 
 static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb);
 
-static void drm_sched_expel_job_unlocked(struct drm_sched_job *s_job);
-
 /**
  * drm_sched_rq_init - initialize a given run queue struct
  *
@@ -286,8 +284,6 @@ static void drm_sched_job_finish(struct work_struct *work)
         cancel_delayed_work_sync(&sched->work_tdr);
 
         spin_lock_irqsave(&sched->job_list_lock, flags);
-        /* remove job from ring_mirror_list */
-        list_del_init(&s_job->node);
         /* queue TDR for next job */
         drm_sched_start_timeout(sched);
         spin_unlock_irqrestore(&sched->job_list_lock, flags);
@@ -295,22 +291,11 @@ static void drm_sched_job_finish(struct work_struct *work)
         sched->ops->free_job(s_job);
 }
 
-static void drm_sched_job_finish_cb(struct dma_fence *f,
-                                    struct dma_fence_cb *cb)
-{
-        struct drm_sched_job *job = container_of(cb, struct drm_sched_job,
-                                                 finish_cb);
-        schedule_work(&job->finish_work);
-}
-
 static void drm_sched_job_begin(struct drm_sched_job *s_job)
 {
         struct drm_gpu_scheduler *sched = s_job->sched;
         unsigned long flags;
 
-        dma_fence_add_callback(&s_job->s_fence->finished, &s_job->finish_cb,
-                               drm_sched_job_finish_cb);
-
         spin_lock_irqsave(&sched->job_list_lock, flags);
         list_add_tail(&s_job->node, &sched->ring_mirror_list);
         drm_sched_start_timeout(sched);
@@ -335,6 +320,51 @@ static void drm_sched_job_timedout(struct work_struct *work)
         spin_unlock_irqrestore(&sched->job_list_lock, flags);
 }
 
+ /**
+  * drm_sched_increase_karma - Update sched_entity guilty flag
+  *
+  * @bad: The job guilty of time out
+  *
+  * Increment on every hang caused by the 'bad' job. If this exceeds the hang
+  * limit of the scheduler then the respective sched entity is marked guilty and
+  * jobs from it will not be scheduled further
+  */
+void drm_sched_increase_karma(struct drm_sched_job *bad)
+{
+        int i;
+        struct drm_sched_entity *tmp;
+        struct drm_sched_entity *entity;
+        struct drm_gpu_scheduler *sched = bad->sched;
+
+        /* don't increase @bad's karma if it's from KERNEL RQ,
+         * because sometimes GPU hang would cause kernel jobs (like VM updating jobs)
+         * corrupt but keep in mind that kernel jobs always considered good.
+         */
+        if (bad->s_priority != DRM_SCHED_PRIORITY_KERNEL) {
+                atomic_inc(&bad->karma);
+                for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_KERNEL;
+                     i++) {
+                        struct drm_sched_rq *rq = &sched->sched_rq[i];
+
+                        spin_lock(&rq->lock);
+                        list_for_each_entry_safe(entity, tmp, &rq->entities, list) {
+                                if (bad->s_fence->scheduled.context ==
+                                    entity->fence_context) {
+                                        if (atomic_read(&bad->karma) >
+                                            bad->sched->hang_limit)
+                                                if (entity->guilty)
+                                                        atomic_set(entity->guilty, 1);
+                                        break;
+                                }
+                        }
+                        spin_unlock(&rq->lock);
+                        if (&entity->list != &rq->entities)
+                                break;
+                }
+        }
+}
+EXPORT_SYMBOL(drm_sched_increase_karma);
+
 /**
  * drm_sched_hw_job_reset - stop the scheduler if it contains the bad job
  *
@@ -342,50 +372,42 @@ static void drm_sched_job_timedout(struct work_struct *work)
  * @bad: bad scheduler job
  *
  */
-void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad)
+void drm_sched_stop(struct drm_gpu_scheduler *sched)
 {
         struct drm_sched_job *s_job;
-        struct drm_sched_entity *entity, *tmp;
         unsigned long flags;
-        int i;
+        struct dma_fence *last_fence =  NULL;
 
+        kthread_park(sched->thread);
+
+        /*
+         * Verify all the signaled jobs in mirror list are removed from the ring
+         * by waiting for the latest job to enter the list. This should insure that
+         * also all the previous jobs that were in flight also already singaled
+         * and removed from the list.
+         */
         spin_lock_irqsave(&sched->job_list_lock, flags);
         list_for_each_entry_reverse(s_job, &sched->ring_mirror_list, node) {
                 if (s_job->s_fence->parent &&
                     dma_fence_remove_callback(s_job->s_fence->parent,
-                                              &s_job->s_fence->cb)) {
+                                              &s_job->cb)) {
                         dma_fence_put(s_job->s_fence->parent);
                         s_job->s_fence->parent = NULL;
                         atomic_dec(&sched->hw_rq_count);
+                } else {
+                         last_fence = dma_fence_get(&s_job->s_fence->finished);
+                         break;
                 }
         }
         spin_unlock_irqrestore(&sched->job_list_lock, flags);
 
-        if (bad && bad->s_priority != DRM_SCHED_PRIORITY_KERNEL) {
-                atomic_inc(&bad->karma);
-                /* don't increase @bad's karma if it's from KERNEL RQ,
-                 * becuase sometimes GPU hang would cause kernel jobs (like VM updating jobs)
-                 * corrupt but keep in mind that kernel jobs always considered good.
-                 */
-                for (i = DRM_SCHED_PRIORITY_MIN; i < DRM_SCHED_PRIORITY_KERNEL; i++ ) {
-                        struct drm_sched_rq *rq = &sched->sched_rq[i];
-
-                        spin_lock(&rq->lock);
-                        list_for_each_entry_safe(entity, tmp, &rq->entities, list) {
-                                if (bad->s_fence->scheduled.context == entity->fence_context) {
-                                    if (atomic_read(&bad->karma) > bad->sched->hang_limit)
-                                                if (entity->guilty)
-                                                        atomic_set(entity->guilty, 1);
-                                        break;
-                                }
-                        }
-                        spin_unlock(&rq->lock);
-                        if (&entity->list != &rq->entities)
-                                break;
-                }
+        if (last_fence) {
+                dma_fence_wait(last_fence, false);
+                dma_fence_put(last_fence);
         }
 }
-EXPORT_SYMBOL(drm_sched_hw_job_reset);
+
+EXPORT_SYMBOL(drm_sched_stop);
 
 /**
  * drm_sched_job_recovery - recover jobs after a reset
@@ -393,18 +415,58 @@ EXPORT_SYMBOL(drm_sched_hw_job_reset);
  * @sched: scheduler instance
  *
  */
-void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
+void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery)
 {
         struct drm_sched_job *s_job, *tmp;
-        bool found_guilty = false;
-        unsigned long flags;
         int r;
 
-        spin_lock_irqsave(&sched->job_list_lock, flags);
+        if (!full_recovery)
+                goto unpark;
+
+        /*
+         * Locking the list is not required here as the sched thread is parked
+         * so no new jobs are being pushed in to HW and in drm_sched_stop we
+         * flushed all the jobs who were still in mirror list but who already
+         * signaled and removed them self from the list. Also concurrent
+         * GPU recovers can't run in parallel.
+         */
+        list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
+                struct dma_fence *fence = s_job->s_fence->parent;
+
+                if (fence) {
+                        r = dma_fence_add_callback(fence, &s_job->cb,
+                                                   drm_sched_process_job);
+                        if (r == -ENOENT)
+                                drm_sched_process_job(fence, &s_job->cb);
+                        else if (r)
+                                DRM_ERROR("fence add callback failed (%d)\n",
+                                          r);
+                } else
+                        drm_sched_process_job(NULL, &s_job->cb);
+        }
+
+        drm_sched_start_timeout(sched);
+
+unpark:
+        kthread_unpark(sched->thread);
+}
+EXPORT_SYMBOL(drm_sched_start);
+
+/**
+ * drm_sched_resubmit_jobs - helper to relunch job from mirror ring list
+ *
+ * @sched: scheduler instance
+ *
+ */
+void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched)
+{
+        struct drm_sched_job *s_job, *tmp;
+        uint64_t guilty_context;
+        bool found_guilty = false;
+
+        /*TODO DO we need spinlock here ? */
         list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
                 struct drm_sched_fence *s_fence = s_job->s_fence;
-                struct dma_fence *fence;
-                uint64_t guilty_context;
 
                 if (!found_guilty && atomic_read(&s_job->karma) > sched->hang_limit) {
                         found_guilty = true;
@@ -414,31 +476,11 @@ void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
                 if (found_guilty && s_job->s_fence->scheduled.context == guilty_context)
                         dma_fence_set_error(&s_fence->finished, -ECANCELED);
 
-                spin_unlock_irqrestore(&sched->job_list_lock, flags);
-                fence = sched->ops->run_job(s_job);
+                s_job->s_fence->parent = sched->ops->run_job(s_job);
                 atomic_inc(&sched->hw_rq_count);
-
-                if (fence) {
-                        s_fence->parent = dma_fence_get(fence);
-                        r = dma_fence_add_callback(fence, &s_fence->cb,
-                                                   drm_sched_process_job);
-                        if (r == -ENOENT)
-                                drm_sched_process_job(fence, &s_fence->cb);
-                        else if (r)
-                                DRM_ERROR("fence add callback failed (%d)\n",
-                                          r);
-                        dma_fence_put(fence);
-                } else {
-                        if (s_fence->finished.error < 0)
-                                drm_sched_expel_job_unlocked(s_job);
-                        drm_sched_process_job(NULL, &s_fence->cb);
-                }
-                spin_lock_irqsave(&sched->job_list_lock, flags);
         }
-        drm_sched_start_timeout(sched);
-        spin_unlock_irqrestore(&sched->job_list_lock, flags);
 }
-EXPORT_SYMBOL(drm_sched_job_recovery);
+EXPORT_SYMBOL(drm_sched_resubmit_jobs);
 
 /**
  * drm_sched_job_init - init a scheduler job
@@ -552,18 +594,27 @@ drm_sched_select_entity(struct drm_gpu_scheduler *sched)
  */
 static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb)
 {
-        struct drm_sched_fence *s_fence =
-                container_of(cb, struct drm_sched_fence, cb);
+        struct drm_sched_job *s_job = container_of(cb, struct drm_sched_job, cb);
+        struct drm_sched_fence *s_fence = s_job->s_fence;
         struct drm_gpu_scheduler *sched = s_fence->sched;
+        unsigned long flags;
+
+        cancel_delayed_work(&sched->work_tdr);
 
-        dma_fence_get(&s_fence->finished);
         atomic_dec(&sched->hw_rq_count);
         atomic_dec(&sched->num_jobs);
+
+        spin_lock_irqsave(&sched->job_list_lock, flags);
+        /* remove job from ring_mirror_list */
+        list_del_init(&s_job->node);
+        spin_unlock_irqrestore(&sched->job_list_lock, flags);
+
         drm_sched_fence_finished(s_fence);
 
         trace_drm_sched_process_job(s_fence);
-        dma_fence_put(&s_fence->finished);
         wake_up_interruptible(&sched->wake_up_worker);
+
+        schedule_work(&s_job->finish_work);
 }
 
 /**
@@ -626,34 +677,22 @@ static int drm_sched_main(void *param)
 
                 if (fence) {
                         s_fence->parent = dma_fence_get(fence);
-                        r = dma_fence_add_callback(fence, &s_fence->cb,
+                        r = dma_fence_add_callback(fence, &sched_job->cb,
                                                    drm_sched_process_job);
                         if (r == -ENOENT)
-                                drm_sched_process_job(fence, &s_fence->cb);
+                                drm_sched_process_job(fence, &sched_job->cb);
                         else if (r)
                                 DRM_ERROR("fence add callback failed (%d)\n",
                                           r);
                         dma_fence_put(fence);
-                } else {
-                        if (s_fence->finished.error < 0)
-                                drm_sched_expel_job_unlocked(sched_job);
-                        drm_sched_process_job(NULL, &s_fence->cb);
-                }
+                } else
+                        drm_sched_process_job(NULL, &sched_job->cb);
 
                 wake_up(&sched->job_scheduled);
         }
         return 0;
 }
 
-static void drm_sched_expel_job_unlocked(struct drm_sched_job *s_job)
-{
-        struct drm_gpu_scheduler *sched = s_job->sched;
-
-        spin_lock(&sched->job_list_lock);
-        list_del_init(&s_job->node);
-        spin_unlock(&sched->job_list_lock);
-}
-
 /**
  * drm_sched_init - Init a gpu scheduler instance
  *
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 0ec08394e17a..de088c8070fb 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -198,19 +198,22 @@ static void ttm_bo_ref_bug(struct kref *list_kref)
 
 void ttm_bo_del_from_lru(struct ttm_buffer_object *bo)
 {
+        struct ttm_bo_device *bdev = bo->bdev;
+        bool notify = false;
+
         if (!list_empty(&bo->swap)) {
                 list_del_init(&bo->swap);
                 kref_put(&bo->list_kref, ttm_bo_ref_bug);
+                notify = true;
         }
         if (!list_empty(&bo->lru)) {
                 list_del_init(&bo->lru);
                 kref_put(&bo->list_kref, ttm_bo_ref_bug);
+                notify = true;
         }
 
-        /*
-         * TODO: Add a driver hook to delete from
-         * driver-specific LRU's here.
-         */
+        if (notify && bdev->driver->del_from_lru_notify)
+                bdev->driver->del_from_lru_notify(bo);
 }
 
 void ttm_bo_del_sub_from_lru(struct ttm_buffer_object *bo)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
index a1d977fbade5..e86a29a1e51f 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_vm.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -71,7 +71,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo,
                 ttm_bo_get(bo);
                 up_read(&vmf->vma->vm_mm->mmap_sem);
                 (void) dma_fence_wait(bo->moving, true);
-                ttm_bo_unreserve(bo);
+                reservation_object_unlock(bo->resv);
                 ttm_bo_put(bo);
                 goto out_unlock;
         }
@@ -131,11 +131,7 @@ static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
          * for reserve, and if it fails, retry the fault after waiting
          * for the buffer to become unreserved.
          */
-        err = ttm_bo_reserve(bo, true, true, NULL);
-        if (unlikely(err != 0)) {
-                if (err != -EBUSY)
-                        return VM_FAULT_NOPAGE;
-
+        if (unlikely(!reservation_object_trylock(bo->resv))) {
                 if (vmf->flags & FAULT_FLAG_ALLOW_RETRY) {
                         if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) {
                                 ttm_bo_get(bo);
@@ -165,6 +161,8 @@ static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
         }
 
         if (bdev->driver->fault_reserve_notify) {
+                struct dma_fence *moving = dma_fence_get(bo->moving);
+
                 err = bdev->driver->fault_reserve_notify(bo);
                 switch (err) {
                 case 0:
@@ -177,6 +175,13 @@ static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
                         ret = VM_FAULT_SIGBUS;
                         goto out_unlock;
                 }
+
+                if (bo->moving != moving) {
+                        spin_lock(&bdev->glob->lru_lock);
+                        ttm_bo_move_to_lru_tail(bo, NULL);
+                        spin_unlock(&bdev->glob->lru_lock);
+                }
+                dma_fence_put(moving);
         }
 
         /*
@@ -291,7 +296,7 @@ static vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf)
 out_io_unlock:
         ttm_mem_io_unlock(man);
 out_unlock:
-        ttm_bo_unreserve(bo);
+        reservation_object_unlock(bo->resv);
         return ret;
 }
 
diff --git a/drivers/gpu/drm/v3d/v3d_sched.c b/drivers/gpu/drm/v3d/v3d_sched.c
index f7508e907536..4704b2df3688 100644
--- a/drivers/gpu/drm/v3d/v3d_sched.c
+++ b/drivers/gpu/drm/v3d/v3d_sched.c
@@ -234,18 +234,21 @@ v3d_gpu_reset_for_timeout(struct v3d_dev *v3d, struct drm_sched_job *sched_job)
         for (q = 0; q < V3D_MAX_QUEUES; q++) {
                 struct drm_gpu_scheduler *sched = &v3d->queue[q].sched;
 
-                kthread_park(sched->thread);
-                drm_sched_hw_job_reset(sched, (sched_job->sched == sched ?
-                                               sched_job : NULL));
+                drm_sched_stop(sched);
+
+                if(sched_job)
+                        drm_sched_increase_karma(sched_job);
         }
 
         /* get the GPU back into the init state */
         v3d_reset(v3d);
 
+        for (q = 0; q < V3D_MAX_QUEUES; q++)
+                drm_sched_resubmit_jobs(sched_job->sched);
+
         /* Unblock schedulers and restart their jobs. */
         for (q = 0; q < V3D_MAX_QUEUES; q++) {
-                drm_sched_job_recovery(&v3d->queue[q].sched);
-                kthread_unpark(v3d->queue[q].sched.thread);
+                drm_sched_start(&v3d->queue[q].sched, true);
         }
 
         mutex_unlock(&v3d->reset_lock);
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index 47e19796c450..0daca4d8dad9 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -138,10 +138,6 @@ struct drm_sched_fence {
         struct dma_fence                finished;
 
         /**
-         * @cb: the callback for the parent fence below.
-         */
-        struct dma_fence_cb             cb;
-        /**
          * @parent: the fence returned by &drm_sched_backend_ops.run_job
          * when scheduling the job on hardware. We signal the
          * &drm_sched_fence.finished fence once parent is signalled.
@@ -181,6 +177,7 @@ struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f);
  *         be scheduled further.
  * @s_priority: the priority of the job.
  * @entity: the entity to which this job belongs.
+ * @cb: the callback for the parent fence in s_fence.
  *
  * A job is created by the driver using drm_sched_job_init(), and
  * should call drm_sched_entity_push_job() once it wants the scheduler
@@ -197,6 +194,7 @@ struct drm_sched_job {
         atomic_t                        karma;
         enum drm_sched_priority         s_priority;
         struct drm_sched_entity  *entity;
+        struct dma_fence_cb             cb;
 };
 
 static inline bool drm_sched_invalidate_job(struct drm_sched_job *s_job,
@@ -298,9 +296,10 @@ int drm_sched_job_init(struct drm_sched_job *job,
                        void *owner);
 void drm_sched_job_cleanup(struct drm_sched_job *job);
 void drm_sched_wakeup(struct drm_gpu_scheduler *sched);
-void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched,
-                            struct drm_sched_job *job);
-void drm_sched_job_recovery(struct drm_gpu_scheduler *sched);
+void drm_sched_stop(struct drm_gpu_scheduler *sched);
+void drm_sched_start(struct drm_gpu_scheduler *sched, bool full_recovery);
+void drm_sched_resubmit_jobs(struct drm_gpu_scheduler *sched);
+void drm_sched_increase_karma(struct drm_sched_job *bad);
 bool drm_sched_dependency_optimized(struct dma_fence* fence,
                                     struct drm_sched_entity *entity);
 void drm_sched_fault(struct drm_gpu_scheduler *sched);
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 1021106438b2..15829b24277c 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -381,6 +381,15 @@ struct ttm_bo_driver {
          */
         int (*access_memory)(struct ttm_buffer_object *bo, unsigned long offset,
                              void *buf, int len, int write);
+
+        /**
+         * struct ttm_bo_driver member del_from_lru_notify
+         *
+         * @bo: the buffer object deleted from lru
+         *
+         * notify driver that a BO was deleted from LRU.
+         */
+        void (*del_from_lru_notify)(struct ttm_buffer_object *bo);
 };
 
 /**