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authorOlof Johansson <olof@lixom.net>2014-01-02 15:10:12 -0500
committerOlof Johansson <olof@lixom.net>2014-01-02 15:10:12 -0500
commite05f9ac42c1b87a1a266e3e83191ed00211576bc (patch)
treeb1c28ec3b64d5f752c97fd4ac93483cb2be19ed7
parentc655479ab89cfad17a773cb55b57199c19f65e9b (diff)
parent48c95841110036a95840c6782f27d841ead9a583 (diff)
Merge tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo: i.MX SoC changes for 3.14: - Add the initial i.MX50 SoC support - Support device tree boot for i.MX35 - Move imx5 clock driver to use macros for clock ID - Some random updates and non-critical fixes on clock drivers - A few defconfig updates and minor cleanups * tag 'imx-soc-3.14' of git://git.linaro.org/people/shawnguo/linux-2.6: (37 commits) ARM: imx: improve the comment of CCM lpm SW workaround ARM: imx: improve status check of clock gate ARM: imx: add necessary interface for pfd ARM: imx_v6_v7_defconfig: Select CONFIG_REGULATOR_PFUZE100 ARM: imx_v6_v7_defconfig: Select MX35 and MX50 device tree support ARM: imx: Add cpu frequency scaling support ARM i.MX35: Add devicetree support. ARM: imx: update imx_v6_v7_defconfig ARM: imx6sl: Add missing spba clock to clock tree ARM: imx6sl: Add missing pll4_audio_div to the clock tree ARM: imx6: Derive spdif clock from pll3_pfd3_454m ARM: imx: use __initconst for const init definition ARM i.MX5: fix obvious typo in ldb_di0_gate clk definition ARM i.MX5: set CAN peripheral clock to 24 MHz parent ARM: imx: pllv1: Fix PLL calculation for i.MX27 ARM i.MX5: fix "shift" value for lp_apm_sel on i.MX50 and i.MX53 ARM: imx: imx53: Add SATA PHY clock ARM: imx_v6_v7_defconfig: Enable STMPE touchscreen ARM: imx: rename IMX6SL_CLK_CLK_END to IMX6SL_CLK_END ARM: imx: select PINCTRL at sub-architecure level ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx35-clock.txt113
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt195
-rw-r--r--arch/arm/Kconfig.debug9
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig2
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig13
-rw-r--r--arch/arm/include/debug/imx-uart.h10
-rw-r--r--arch/arm/mach-imx/Kconfig35
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/avic.c25
-rw-r--r--arch/arm/mach-imx/clk-gate2.c2
-rw-r--r--arch/arm/mach-imx/clk-imx35.c14
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c804
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c5
-rw-r--r--arch/arm/mach-imx/clk-imx6sl.c11
-rw-r--r--arch/arm/mach-imx/clk-pfd.c11
-rw-r--r--arch/arm/mach-imx/clk-pllv1.c23
-rw-r--r--arch/arm/mach-imx/clk-vf610.c5
-rw-r--r--arch/arm/mach-imx/common.h1
-rw-r--r--arch/arm/mach-imx/imx31-dt.c2
-rw-r--r--arch/arm/mach-imx/imx35-dt.c50
-rw-r--r--arch/arm/mach-imx/imx51-dt.c2
-rw-r--r--arch/arm/mach-imx/irq-common.h1
-rw-r--r--arch/arm/mach-imx/mach-imx50.c38
-rw-r--r--arch/arm/mach-imx/mach-imx53.c2
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c32
-rw-r--r--arch/arm/mach-imx/mach-imx6sl.c10
-rw-r--r--arch/arm/mach-imx/mach-vf610.c2
-rw-r--r--arch/arm/mach-imx/mm-imx5.c8
-rw-r--r--arch/arm/mach-imx/pm-imx6q.c16
-rw-r--r--include/dt-bindings/clock/imx5-clock.h203
-rw-r--r--include/dt-bindings/clock/imx6sl-clock.h4
-rw-r--r--include/dt-bindings/clock/vf610-clock.h6
32 files changed, 1002 insertions, 654 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx35-clock.txt b/Documentation/devicetree/bindings/clock/imx35-clock.txt
new file mode 100644
index 000000000000..a70356452a82
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx35-clock.txt
@@ -0,0 +1,113 @@
1* Clock bindings for Freescale i.MX35
2
3Required properties:
4- compatible: Should be "fsl,imx35-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX35
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 ckih 0
16 mpll 1
17 ppll 2
18 mpll_075 3
19 arm 4
20 hsp 5
21 hsp_div 6
22 hsp_sel 7
23 ahb 8
24 ipg 9
25 arm_per_div 10
26 ahb_per_div 11
27 ipg_per 12
28 uart_sel 13
29 uart_div 14
30 esdhc_sel 15
31 esdhc1_div 16
32 esdhc2_div 17
33 esdhc3_div 18
34 spdif_sel 19
35 spdif_div_pre 20
36 spdif_div_post 21
37 ssi_sel 22
38 ssi1_div_pre 23
39 ssi1_div_post 24
40 ssi2_div_pre 25
41 ssi2_div_post 26
42 usb_sel 27
43 usb_div 28
44 nfc_div 29
45 asrc_gate 30
46 pata_gate 31
47 audmux_gate 32
48 can1_gate 33
49 can2_gate 34
50 cspi1_gate 35
51 cspi2_gate 36
52 ect_gate 37
53 edio_gate 38
54 emi_gate 39
55 epit1_gate 40
56 epit2_gate 41
57 esai_gate 42
58 esdhc1_gate 43
59 esdhc2_gate 44
60 esdhc3_gate 45
61 fec_gate 46
62 gpio1_gate 47
63 gpio2_gate 48
64 gpio3_gate 49
65 gpt_gate 50
66 i2c1_gate 51
67 i2c2_gate 52
68 i2c3_gate 53
69 iomuxc_gate 54
70 ipu_gate 55
71 kpp_gate 56
72 mlb_gate 57
73 mshc_gate 58
74 owire_gate 59
75 pwm_gate 60
76 rngc_gate 61
77 rtc_gate 62
78 rtic_gate 63
79 scc_gate 64
80 sdma_gate 65
81 spba_gate 66
82 spdif_gate 67
83 ssi1_gate 68
84 ssi2_gate 69
85 uart1_gate 70
86 uart2_gate 71
87 uart3_gate 72
88 usbotg_gate 73
89 wdog_gate 74
90 max_gate 75
91 admux_gate 76
92 csi_gate 77
93 csi_div 78
94 csi_sel 79
95 iim_gate 80
96 gpu2d_gate 81
97
98Examples:
99
100clks: ccm@53f80000 {
101 compatible = "fsl,imx35-ccm";
102 reg = <0x53f80000 0x4000>;
103 interrupts = <31>;
104 #clock-cells = <1>;
105};
106
107esdhc1: esdhc@53fb4000 {
108 compatible = "fsl,imx35-esdhc";
109 reg = <0x53fb4000 0x4000>;
110 interrupts = <7>;
111 clocks = <&clks 9>, <&clks 8>, <&clks 43>;
112 clock-names = "ipg", "ahb", "per";
113};
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 4c029a8739d3..cadc4d29ada6 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -7,197 +7,8 @@ Required properties:
7- #clock-cells: Should be <1> 7- #clock-cells: Should be <1>
8 8
9The clock consumer should specify the desired clock by having the clock 9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX5 10ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
11clocks and IDs. 11for the full list of i.MX5 clock IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 osc 2
18 ckih1 3
19 ckih2 4
20 ahb 5
21 ipg 6
22 axi_a 7
23 axi_b 8
24 uart_pred 9
25 uart_root 10
26 esdhc_a_pred 11
27 esdhc_b_pred 12
28 esdhc_c_s 13
29 esdhc_d_s 14
30 emi_sel 15
31 emi_slow_podf 16
32 nfc_podf 17
33 ecspi_pred 18
34 ecspi_podf 19
35 usboh3_pred 20
36 usboh3_podf 21
37 usb_phy_pred 22
38 usb_phy_podf 23
39 cpu_podf 24
40 di_pred 25
41 tve_s 27
42 uart1_ipg_gate 28
43 uart1_per_gate 29
44 uart2_ipg_gate 30
45 uart2_per_gate 31
46 uart3_ipg_gate 32
47 uart3_per_gate 33
48 i2c1_gate 34
49 i2c2_gate 35
50 gpt_ipg_gate 36
51 pwm1_ipg_gate 37
52 pwm1_hf_gate 38
53 pwm2_ipg_gate 39
54 pwm2_hf_gate 40
55 gpt_hf_gate 41
56 fec_gate 42
57 usboh3_per_gate 43
58 esdhc1_ipg_gate 44
59 esdhc2_ipg_gate 45
60 esdhc3_ipg_gate 46
61 esdhc4_ipg_gate 47
62 ssi1_ipg_gate 48
63 ssi2_ipg_gate 49
64 ssi3_ipg_gate 50
65 ecspi1_ipg_gate 51
66 ecspi1_per_gate 52
67 ecspi2_ipg_gate 53
68 ecspi2_per_gate 54
69 cspi_ipg_gate 55
70 sdma_gate 56
71 emi_slow_gate 57
72 ipu_s 58
73 ipu_gate 59
74 nfc_gate 60
75 ipu_di1_gate 61
76 vpu_s 62
77 vpu_gate 63
78 vpu_reference_gate 64
79 uart4_ipg_gate 65
80 uart4_per_gate 66
81 uart5_ipg_gate 67
82 uart5_per_gate 68
83 tve_gate 69
84 tve_pred 70
85 esdhc1_per_gate 71
86 esdhc2_per_gate 72
87 esdhc3_per_gate 73
88 esdhc4_per_gate 74
89 usb_phy_gate 75
90 hsi2c_gate 76
91 mipi_hsc1_gate 77
92 mipi_hsc2_gate 78
93 mipi_esc_gate 79
94 mipi_hsp_gate 80
95 ldb_di1_div_3_5 81
96 ldb_di1_div 82
97 ldb_di0_div_3_5 83
98 ldb_di0_div 84
99 ldb_di1_gate 85
100 can2_serial_gate 86
101 can2_ipg_gate 87
102 i2c3_gate 88
103 lp_apm 89
104 periph_apm 90
105 main_bus 91
106 ahb_max 92
107 aips_tz1 93
108 aips_tz2 94
109 tmax1 95
110 tmax2 96
111 tmax3 97
112 spba 98
113 uart_sel 99
114 esdhc_a_sel 100
115 esdhc_b_sel 101
116 esdhc_a_podf 102
117 esdhc_b_podf 103
118 ecspi_sel 104
119 usboh3_sel 105
120 usb_phy_sel 106
121 iim_gate 107
122 usboh3_gate 108
123 emi_fast_gate 109
124 ipu_di0_gate 110
125 gpc_dvfs 111
126 pll1_sw 112
127 pll2_sw 113
128 pll3_sw 114
129 ipu_di0_sel 115
130 ipu_di1_sel 116
131 tve_ext_sel 117
132 mx51_mipi 118
133 pll4_sw 119
134 ldb_di1_sel 120
135 di_pll4_podf 121
136 ldb_di0_sel 122
137 ldb_di0_gate 123
138 usb_phy1_gate 124
139 usb_phy2_gate 125
140 per_lp_apm 126
141 per_pred1 127
142 per_pred2 128
143 per_podf 129
144 per_root 130
145 ssi_apm 131
146 ssi1_root_sel 132
147 ssi2_root_sel 133
148 ssi3_root_sel 134
149 ssi_ext1_sel 135
150 ssi_ext2_sel 136
151 ssi_ext1_com_sel 137
152 ssi_ext2_com_sel 138
153 ssi1_root_pred 139
154 ssi1_root_podf 140
155 ssi2_root_pred 141
156 ssi2_root_podf 142
157 ssi_ext1_pred 143
158 ssi_ext1_podf 144
159 ssi_ext2_pred 145
160 ssi_ext2_podf 146
161 ssi1_root_gate 147
162 ssi2_root_gate 148
163 ssi3_root_gate 149
164 ssi_ext1_gate 150
165 ssi_ext2_gate 151
166 epit1_ipg_gate 152
167 epit1_hf_gate 153
168 epit2_ipg_gate 154
169 epit2_hf_gate 155
170 can_sel 156
171 can1_serial_gate 157
172 can1_ipg_gate 158
173 owire_gate 159
174 gpu3d_s 160
175 gpu2d_s 161
176 gpu3d_gate 162
177 gpu2d_gate 163
178 garb_gate 164
179 cko1_sel 165
180 cko1_podf 166
181 cko1 167
182 cko2_sel 168
183 cko2_podf 169
184 cko2 170
185 srtc_gate 171
186 pata_gate 172
187 sata_gate 173
188 spdif_xtal_sel 174
189 spdif0_sel 175
190 spdif1_sel 176
191 spdif0_pred 177
192 spdif0_podf 178
193 spdif1_pred 179
194 spdif1_podf 180
195 spdif0_com_sel 181
196 spdif1_com_sel 182
197 spdif0_gate 183
198 spdif1_gate 184
199 spdif_ipg_gate 185
200 ocram 186
201 12
202Examples (for mx53): 13Examples (for mx53):
203 14
@@ -212,7 +23,7 @@ can1: can@53fc8000 {
212 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 23 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
213 reg = <0x53fc8000 0x4000>; 24 reg = <0x53fc8000 0x4000>;
214 interrupts = <82>; 25 interrupts = <82>;
215 clocks = <&clks 158>, <&clks 157>; 26 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
216 clock-names = "ipg", "per"; 27 clock-names = "ipg", "per";
217 status = "disabled"; 28 status = "disabled";
218}; 29};
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 257155874bce..bda94e46e8d6 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -263,6 +263,13 @@ choice
263 Say Y here if you want kernel low-level debugging support 263 Say Y here if you want kernel low-level debugging support
264 on i.MX35. 264 on i.MX35.
265 265
266 config DEBUG_IMX50_UART
267 bool "i.MX50 Debug UART"
268 depends on SOC_IMX50
269 help
270 Say Y here if you want kernel low-level debugging support
271 on i.MX50.
272
266 config DEBUG_IMX51_UART 273 config DEBUG_IMX51_UART
267 bool "i.MX51 Debug UART" 274 bool "i.MX51 Debug UART"
268 depends on SOC_IMX51 275 depends on SOC_IMX51
@@ -905,6 +912,7 @@ config DEBUG_IMX_UART_PORT
905 DEBUG_IMX21_IMX27_UART || \ 912 DEBUG_IMX21_IMX27_UART || \
906 DEBUG_IMX31_UART || \ 913 DEBUG_IMX31_UART || \
907 DEBUG_IMX35_UART || \ 914 DEBUG_IMX35_UART || \
915 DEBUG_IMX50_UART || \
908 DEBUG_IMX51_UART || \ 916 DEBUG_IMX51_UART || \
909 DEBUG_IMX53_UART || \ 917 DEBUG_IMX53_UART || \
910 DEBUG_IMX6Q_UART || \ 918 DEBUG_IMX6Q_UART || \
@@ -939,6 +947,7 @@ config DEBUG_LL_INCLUDE
939 DEBUG_IMX21_IMX27_UART || \ 947 DEBUG_IMX21_IMX27_UART || \
940 DEBUG_IMX31_UART || \ 948 DEBUG_IMX31_UART || \
941 DEBUG_IMX35_UART || \ 949 DEBUG_IMX35_UART || \
950 DEBUG_IMX50_UART || \
942 DEBUG_IMX51_UART || \ 951 DEBUG_IMX51_UART || \
943 DEBUG_IMX53_UART ||\ 952 DEBUG_IMX53_UART ||\
944 DEBUG_IMX6Q_UART || \ 953 DEBUG_IMX6Q_UART || \
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e958ebe79779..6309ee52ccfc 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -91,6 +91,7 @@ CONFIG_SMSC911X=y
91CONFIG_SMSC_PHY=y 91CONFIG_SMSC_PHY=y
92# CONFIG_INPUT_MOUSEDEV is not set 92# CONFIG_INPUT_MOUSEDEV is not set
93CONFIG_INPUT_EVDEV=y 93CONFIG_INPUT_EVDEV=y
94CONFIG_KEYBOARD_GPIO=y
94CONFIG_KEYBOARD_IMX=y 95CONFIG_KEYBOARD_IMX=y
95# CONFIG_INPUT_MOUSE is not set 96# CONFIG_INPUT_MOUSE is not set
96CONFIG_INPUT_TOUCHSCREEN=y 97CONFIG_INPUT_TOUCHSCREEN=y
@@ -118,6 +119,7 @@ CONFIG_IMX2_WDT=y
118CONFIG_MFD_MC13XXX_SPI=y 119CONFIG_MFD_MC13XXX_SPI=y
119CONFIG_REGULATOR=y 120CONFIG_REGULATOR=y
120CONFIG_REGULATOR_FIXED_VOLTAGE=y 121CONFIG_REGULATOR_FIXED_VOLTAGE=y
122CONFIG_REGULATOR_GPIO=y
121CONFIG_REGULATOR_MC13783=y 123CONFIG_REGULATOR_MC13783=y
122CONFIG_REGULATOR_MC13892=y 124CONFIG_REGULATOR_MC13892=y
123CONFIG_MEDIA_SUPPORT=y 125CONFIG_MEDIA_SUPPORT=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 8d0c5a018ed7..53e82c2523eb 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -28,11 +28,13 @@ CONFIG_MACH_QONG=y
28CONFIG_MACH_ARMADILLO5X0=y 28CONFIG_MACH_ARMADILLO5X0=y
29CONFIG_MACH_KZM_ARM11_01=y 29CONFIG_MACH_KZM_ARM11_01=y
30CONFIG_MACH_IMX31_DT=y 30CONFIG_MACH_IMX31_DT=y
31CONFIG_MACH_IMX35_DT=y
31CONFIG_MACH_PCM043=y 32CONFIG_MACH_PCM043=y
32CONFIG_MACH_MX35_3DS=y 33CONFIG_MACH_MX35_3DS=y
33CONFIG_MACH_VPR200=y 34CONFIG_MACH_VPR200=y
34CONFIG_MACH_IMX51_DT=y 35CONFIG_MACH_IMX51_DT=y
35CONFIG_MACH_EUKREA_CPUIMX51SD=y 36CONFIG_MACH_EUKREA_CPUIMX51SD=y
37CONFIG_SOC_IMX50=y
36CONFIG_SOC_IMX53=y 38CONFIG_SOC_IMX53=y
37CONFIG_SOC_IMX6Q=y 39CONFIG_SOC_IMX6Q=y
38CONFIG_SOC_IMX6SL=y 40CONFIG_SOC_IMX6SL=y
@@ -41,7 +43,7 @@ CONFIG_SMP=y
41CONFIG_VMSPLIT_2G=y 43CONFIG_VMSPLIT_2G=y
42CONFIG_PREEMPT_VOLUNTARY=y 44CONFIG_PREEMPT_VOLUNTARY=y
43CONFIG_AEABI=y 45CONFIG_AEABI=y
44# CONFIG_OABI_COMPAT is not set 46CONFIG_HIGHMEM=y
45CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" 47CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
46CONFIG_VFP=y 48CONFIG_VFP=y
47CONFIG_NEON=y 49CONFIG_NEON=y
@@ -89,7 +91,6 @@ CONFIG_MTD_UBI=y
89CONFIG_BLK_DEV_LOOP=y 91CONFIG_BLK_DEV_LOOP=y
90CONFIG_BLK_DEV_RAM=y 92CONFIG_BLK_DEV_RAM=y
91CONFIG_BLK_DEV_RAM_SIZE=65536 93CONFIG_BLK_DEV_RAM_SIZE=65536
92CONFIG_SRAM=y
93CONFIG_EEPROM_AT24=y 94CONFIG_EEPROM_AT24=y
94CONFIG_EEPROM_AT25=y 95CONFIG_EEPROM_AT25=y
95# CONFIG_SCSI_PROC_FS is not set 96# CONFIG_SCSI_PROC_FS is not set
@@ -118,6 +119,7 @@ CONFIG_SMC91X=y
118CONFIG_SMC911X=y 119CONFIG_SMC911X=y
119CONFIG_SMSC911X=y 120CONFIG_SMSC911X=y
120# CONFIG_NET_VENDOR_STMICRO is not set 121# CONFIG_NET_VENDOR_STMICRO is not set
122CONFIG_AT803X_PHY=y
121CONFIG_BRCMFMAC=m 123CONFIG_BRCMFMAC=m
122# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 124# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
123CONFIG_INPUT_EVDEV=y 125CONFIG_INPUT_EVDEV=y
@@ -129,6 +131,8 @@ CONFIG_MOUSE_PS2_ELANTECH=y
129CONFIG_INPUT_TOUCHSCREEN=y 131CONFIG_INPUT_TOUCHSCREEN=y
130CONFIG_TOUCHSCREEN_EGALAX=y 132CONFIG_TOUCHSCREEN_EGALAX=y
131CONFIG_TOUCHSCREEN_MC13783=y 133CONFIG_TOUCHSCREEN_MC13783=y
134CONFIG_TOUCHSCREEN_TSC2007=y
135CONFIG_TOUCHSCREEN_STMPE=y
132CONFIG_INPUT_MISC=y 136CONFIG_INPUT_MISC=y
133CONFIG_INPUT_MMA8450=y 137CONFIG_INPUT_MMA8450=y
134CONFIG_SERIO_SERPORT=m 138CONFIG_SERIO_SERPORT=m
@@ -156,14 +160,19 @@ CONFIG_IMX2_WDT=y
156CONFIG_MFD_DA9052_I2C=y 160CONFIG_MFD_DA9052_I2C=y
157CONFIG_MFD_MC13XXX_SPI=y 161CONFIG_MFD_MC13XXX_SPI=y
158CONFIG_MFD_MC13XXX_I2C=y 162CONFIG_MFD_MC13XXX_I2C=y
163CONFIG_MFD_STMPE=y
159CONFIG_REGULATOR=y 164CONFIG_REGULATOR=y
160CONFIG_REGULATOR_FIXED_VOLTAGE=y 165CONFIG_REGULATOR_FIXED_VOLTAGE=y
161CONFIG_REGULATOR_ANATOP=y 166CONFIG_REGULATOR_ANATOP=y
162CONFIG_REGULATOR_DA9052=y 167CONFIG_REGULATOR_DA9052=y
163CONFIG_REGULATOR_MC13783=y 168CONFIG_REGULATOR_MC13783=y
164CONFIG_REGULATOR_MC13892=y 169CONFIG_REGULATOR_MC13892=y
170CONFIG_REGULATOR_PFUZE100=y
165CONFIG_MEDIA_SUPPORT=y 171CONFIG_MEDIA_SUPPORT=y
166CONFIG_MEDIA_CAMERA_SUPPORT=y 172CONFIG_MEDIA_CAMERA_SUPPORT=y
173CONFIG_MEDIA_RC_SUPPORT=y
174CONFIG_RC_DEVICES=y
175CONFIG_IR_GPIO_CIR=y
167CONFIG_V4L_PLATFORM_DRIVERS=y 176CONFIG_V4L_PLATFORM_DRIVERS=y
168CONFIG_SOC_CAMERA=y 177CONFIG_SOC_CAMERA=y
169CONFIG_VIDEO_MX3=y 178CONFIG_VIDEO_MX3=y
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 29da84e183f4..42b823cd2d22 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -43,6 +43,14 @@
43#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR 43#define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR
44#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) 44#define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n)
45 45
46#define IMX50_UART1_BASE_ADDR 0x53fbc000
47#define IMX50_UART2_BASE_ADDR 0x53fc0000
48#define IMX50_UART3_BASE_ADDR 0x5000c000
49#define IMX50_UART4_BASE_ADDR 0x53ff0000
50#define IMX50_UART5_BASE_ADDR 0x63f90000
51#define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR
52#define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n)
53
46#define IMX51_UART1_BASE_ADDR 0x73fbc000 54#define IMX51_UART1_BASE_ADDR 0x73fbc000
47#define IMX51_UART2_BASE_ADDR 0x73fc0000 55#define IMX51_UART2_BASE_ADDR 0x73fc0000
48#define IMX51_UART3_BASE_ADDR 0x7000c000 56#define IMX51_UART3_BASE_ADDR 0x7000c000
@@ -85,6 +93,8 @@
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) 93#define UART_PADDR IMX_DEBUG_UART_BASE(IMX31)
86#elif defined(CONFIG_DEBUG_IMX35_UART) 94#elif defined(CONFIG_DEBUG_IMX35_UART)
87#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) 95#define UART_PADDR IMX_DEBUG_UART_BASE(IMX35)
96#elif defined(CONFIG_DEBUG_IMX50_UART)
97#define UART_PADDR IMX_DEBUG_UART_BASE(IMX50)
88#elif defined(CONFIG_DEBUG_IMX51_UART) 98#elif defined(CONFIG_DEBUG_IMX51_UART)
89#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) 99#define UART_PADDR IMX_DEBUG_UART_BASE(IMX51)
90#elif defined(CONFIG_DEBUG_IMX53_UART) 100#elif defined(CONFIG_DEBUG_IMX53_UART)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7a6e6f710068..b0c6eb35a322 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -11,6 +11,7 @@ config ARCH_MXC
11 select GENERIC_IRQ_CHIP 11 select GENERIC_IRQ_CHIP
12 select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7 12 select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
13 select MULTI_IRQ_HANDLER 13 select MULTI_IRQ_HANDLER
14 select PINCTRL
14 select SOC_BUS 15 select SOC_BUS
15 select SPARSE_IRQ 16 select SPARSE_IRQ
16 select USE_OF 17 select USE_OF
@@ -20,16 +21,6 @@ config ARCH_MXC
20menu "Freescale i.MX support" 21menu "Freescale i.MX support"
21 depends on ARCH_MXC 22 depends on ARCH_MXC
22 23
23config MXC_IRQ_PRIOR
24 bool "Use IRQ priority"
25 help
26 Select this if you want to use prioritized IRQ handling.
27 This feature prevents higher priority ISR to be interrupted
28 by lower priority IRQ.
29 This may be useful in embedded applications, where are strong
30 requirements for timing.
31 Say N here, unless you have a specialized requirement.
32
33config MXC_TZIC 24config MXC_TZIC
34 bool 25 bool
35 26
@@ -109,6 +100,7 @@ config SOC_IMX25
109 select ARCH_MXC_IOMUX_V3 100 select ARCH_MXC_IOMUX_V3
110 select CPU_ARM926T 101 select CPU_ARM926T
111 select MXC_AVIC 102 select MXC_AVIC
103 select PINCTRL_IMX25
112 104
113config SOC_IMX27 105config SOC_IMX27
114 bool 106 bool
@@ -118,6 +110,7 @@ config SOC_IMX27
118 select IMX_HAVE_IOMUX_V1 110 select IMX_HAVE_IOMUX_V1
119 select MACH_MX27 111 select MACH_MX27
120 select MXC_AVIC 112 select MXC_AVIC
113 select PINCTRL_IMX27
121 114
122config SOC_IMX31 115config SOC_IMX31
123 bool 116 bool
@@ -133,6 +126,7 @@ config SOC_IMX35
133 select HAVE_EPIT 126 select HAVE_EPIT
134 select MXC_AVIC 127 select MXC_AVIC
135 select SMP_ON_UP if SMP 128 select SMP_ON_UP if SMP
129 select PINCTRL
136 130
137config SOC_IMX5 131config SOC_IMX5
138 bool 132 bool
@@ -145,7 +139,6 @@ config SOC_IMX5
145config SOC_IMX51 139config SOC_IMX51
146 bool 140 bool
147 select HAVE_IMX_SRC 141 select HAVE_IMX_SRC
148 select PINCTRL
149 select PINCTRL_IMX51 142 select PINCTRL_IMX51
150 select SOC_IMX5 143 select SOC_IMX5
151 144
@@ -619,6 +612,13 @@ config MACH_IMX31_DT
619 612
620comment "MX35 platforms:" 613comment "MX35 platforms:"
621 614
615config MACH_IMX35_DT
616 bool "Support i.MX35 platforms from device tree"
617 select SOC_IMX35
618 help
619 Include support for Freescale i.MX35 based platforms
620 using the device tree for discovery.
621
622config MACH_PCM043 622config MACH_PCM043
623 bool "Support Phytec pcm043 (i.MX35) platforms" 623 bool "Support Phytec pcm043 (i.MX35) platforms"
624 select IMX_HAVE_PLATFORM_FLEXCAN 624 select IMX_HAVE_PLATFORM_FLEXCAN
@@ -766,11 +766,19 @@ endchoice
766 766
767comment "Device tree only" 767comment "Device tree only"
768 768
769config SOC_IMX50
770 bool "i.MX50 support"
771 select HAVE_IMX_SRC
772 select PINCTRL_IMX50
773 select SOC_IMX5
774
775 help
776 This enables support for Freescale i.MX50 processor.
777
769config SOC_IMX53 778config SOC_IMX53
770 bool "i.MX53 support" 779 bool "i.MX53 support"
771 select HAVE_IMX_SRC 780 select HAVE_IMX_SRC
772 select IMX_HAVE_PLATFORM_IMX2_WDT 781 select IMX_HAVE_PLATFORM_IMX2_WDT
773 select PINCTRL
774 select PINCTRL_IMX53 782 select PINCTRL_IMX53
775 select SOC_IMX5 783 select SOC_IMX5
776 784
@@ -796,7 +804,6 @@ config SOC_IMX6Q
796 select MFD_SYSCON 804 select MFD_SYSCON
797 select MIGHT_HAVE_PCI 805 select MIGHT_HAVE_PCI
798 select PCI_DOMAINS if PCI 806 select PCI_DOMAINS if PCI
799 select PINCTRL
800 select PINCTRL_IMX6Q 807 select PINCTRL_IMX6Q
801 select PL310_ERRATA_588369 if CACHE_PL310 808 select PL310_ERRATA_588369 if CACHE_PL310
802 select PL310_ERRATA_727915 if CACHE_PL310 809 select PL310_ERRATA_727915 if CACHE_PL310
@@ -817,7 +824,6 @@ config SOC_IMX6SL
817 select HAVE_IMX_MMDC 824 select HAVE_IMX_MMDC
818 select HAVE_IMX_SRC 825 select HAVE_IMX_SRC
819 select MFD_SYSCON 826 select MFD_SYSCON
820 select PINCTRL
821 select PINCTRL_IMX6SL 827 select PINCTRL_IMX6SL
822 select PL310_ERRATA_588369 if CACHE_PL310 828 select PL310_ERRATA_588369 if CACHE_PL310
823 select PL310_ERRATA_727915 if CACHE_PL310 829 select PL310_ERRATA_727915 if CACHE_PL310
@@ -831,7 +837,6 @@ config SOC_VF610
831 select CPU_V7 837 select CPU_V7
832 select ARM_GIC 838 select ARM_GIC
833 select CLKSRC_OF 839 select CLKSRC_OF
834 select PINCTRL
835 select PINCTRL_VF610 840 select PINCTRL_VF610
836 select VF_PIT_TIMER 841 select VF_PIT_TIMER
837 select PL310_ERRATA_588369 if CACHE_PL310 842 select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 1789e2b31903..befcaf5d0574 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -89,6 +89,7 @@ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
89obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o 89obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
90obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o 90obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
91obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o 91obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
92obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
92 93
93obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o 94obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
94obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o 95obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
@@ -112,6 +113,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
112obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o 113obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
113 114
114obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 115obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
116obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
115obj-$(CONFIG_SOC_IMX53) += mach-imx53.o 117obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
116 118
117obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o 119obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index e163ec7a8441..8d1df2e4b7ac 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -54,28 +54,6 @@
54static void __iomem *avic_base; 54static void __iomem *avic_base;
55static struct irq_domain *domain; 55static struct irq_domain *domain;
56 56
57#ifdef CONFIG_MXC_IRQ_PRIOR
58static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
59{
60 struct irq_data *d = irq_get_irq_data(irq);
61 unsigned int temp;
62 unsigned int mask = 0x0F << irq % 8 * 4;
63
64 irq = d->hwirq;
65
66 if (irq >= AVIC_NUM_IRQS)
67 return -EINVAL;
68
69 temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
70 temp &= ~mask;
71 temp |= prio & mask;
72
73 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
74
75 return 0;
76}
77#endif
78
79#ifdef CONFIG_FIQ 57#ifdef CONFIG_FIQ
80static int avic_set_irq_fiq(unsigned int irq, unsigned int type) 58static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
81{ 59{
@@ -102,9 +80,6 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
102 80
103 81
104static struct mxc_extra_irq avic_extra_irq = { 82static struct mxc_extra_irq avic_extra_irq = {
105#ifdef CONFIG_MXC_IRQ_PRIOR
106 .set_priority = avic_irq_set_priority,
107#endif
108#ifdef CONFIG_FIQ 83#ifdef CONFIG_FIQ
109 .set_irq_fiq = avic_set_irq_fiq, 84 .set_irq_fiq = avic_set_irq_fiq,
110#endif 85#endif
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index a63e415609a8..a2ecc006b322 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -72,7 +72,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
72 72
73 reg = readl(gate->reg); 73 reg = readl(gate->reg);
74 74
75 if (((reg >> gate->bit_idx) & 3) == 3) 75 if (((reg >> gate->bit_idx) & 1) == 1)
76 return 1; 76 return 1;
77 77
78 return 0; 78 return 0;
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 2193c834f55c..a4d5e425cd82 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -45,6 +45,8 @@ static struct arm_ahb_div clk_consumer[] = {
45static char hsp_div_532[] = { 4, 8, 3, 0 }; 45static char hsp_div_532[] = { 4, 8, 3, 0 };
46static char hsp_div_400[] = { 3, 6, 3, 0 }; 46static char hsp_div_400[] = { 3, 6, 3, 0 };
47 47
48static struct clk_onecell_data clk_data;
49
48static const char *std_sel[] = {"ppll", "arm"}; 50static const char *std_sel[] = {"ppll", "arm"};
49static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; 51static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
50 52
@@ -286,3 +288,15 @@ int __init mx35_clocks_init(void)
286 288
287 return 0; 289 return 0;
288} 290}
291
292static int __init mx35_clocks_init_dt(struct device_node *ccm_node)
293{
294 clk_data.clks = clk;
295 clk_data.clk_num = ARRAY_SIZE(clk);
296 of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
297
298 mx35_clocks_init();
299
300 return 0;
301}
302CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index ce37af26ff8c..19fca1fdc6fe 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -12,11 +12,11 @@
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/clkdev.h> 13#include <linux/clkdev.h>
14#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/err.h> 15#include <linux/err.h>
17#include <linux/of.h> 16#include <linux/of.h>
18#include <linux/of_address.h> 17#include <linux/of_address.h>
19#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <dt-bindings/clock/imx5-clock.h>
20 20
21#include "crm-regs-imx5.h" 21#include "crm-regs-imx5.h"
22#include "clk.h" 22#include "clk.h"
@@ -83,50 +83,7 @@ static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_
83static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; 83static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
84static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; 84static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
85 85
86 86static struct clk *clk[IMX5_CLK_END];
87enum imx5_clks {
88 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
89 uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
90 emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
91 usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused,
92 tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
93 uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
94 gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
95 gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
96 esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
97 ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
98 ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
99 ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate,
100 vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate,
101 uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate,
102 esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate,
103 mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate,
104 ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div,
105 ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm,
106 periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
107 tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
108 esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate,
109 usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw,
110 pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw,
111 ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate,
112 usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
113 ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel,
114 ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred,
115 ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
116 ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
117 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
118 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
119 can_sel, can1_serial_gate, can1_ipg_gate,
120 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
121 cko1_sel, cko1_podf, cko1,
122 cko2_sel, cko2_podf, cko2,
123 srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
124 spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
125 spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
126 ocram, clk_max
127};
128
129static struct clk *clk[clk_max];
130static struct clk_onecell_data clk_data; 87static struct clk_onecell_data clk_data;
131 88
132static void __init mx5_clocks_common_init(unsigned long rate_ckil, 89static void __init mx5_clocks_common_init(unsigned long rate_ckil,
@@ -135,236 +92,296 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
135{ 92{
136 int i; 93 int i;
137 94
138 clk[dummy] = imx_clk_fixed("dummy", 0); 95 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
139 clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); 96 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil);
140 clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); 97 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc);
141 clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); 98 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
142 clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); 99 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
143 100
144 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, 101 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
145 lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); 102 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
146 clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, 103 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
147 periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); 104 main_bus_sel, ARRAY_SIZE(main_bus_sel));
148 clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, 105 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
149 main_bus_sel, ARRAY_SIZE(main_bus_sel)); 106 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
150 clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, 107 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
151 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); 108 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
152 clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); 109 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
153 clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); 110 clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
154 clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); 111 per_root_sel, ARRAY_SIZE(per_root_sel));
155 clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, 112 clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
156 per_root_sel, ARRAY_SIZE(per_root_sel)); 113 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
157 clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); 114 clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
158 clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); 115 clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
159 clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); 116 clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
160 clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); 117 clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
161 clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); 118 clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
162 clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); 119 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
163 clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); 120 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
164 clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); 121 clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
165 clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); 122 clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
166 clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); 123 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
167 clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); 124 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
168 clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, 125 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
169 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 126 clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
170 clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); 127
171 clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); 128 clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
172 129 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
173 clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, 130 clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
174 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 131 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
175 clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, 132 clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
176 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 133 clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
177 clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); 134 clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
178 clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); 135 clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
179 clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); 136 clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
180 clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); 137 clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
181 clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); 138
182 clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); 139 clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
183 140 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
184 clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, 141 clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
185 emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); 142 clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
186 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); 143 clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
187 clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); 144 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
188 clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, 145 clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
189 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 146 clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
190 clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); 147 clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
191 clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); 148 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
192 clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, 149 clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
193 standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); 150 clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
194 clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); 151 clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
195 clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); 152 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
196 clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); 153 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
197 clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); 154 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
198 clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, 155 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3);
199 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); 156 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
200 clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); 157 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
201 clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); 158 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
202 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); 159 clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
203 clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); 160 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
204 clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); 161 clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
205 clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); 162 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
206 clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); 163 clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
207 clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); 164 clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
208 clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); 165 clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
209 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); 166 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
210 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); 167 clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
211 clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); 168 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
212 clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); 169 clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
213 clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); 170 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
214 clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); 171 clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
215 clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); 172 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
216 clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); 173 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
217 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); 174 clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
218 clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); 175 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
219 clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); 176 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
220 clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); 177 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
221 clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); 178 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
222 clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); 179 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
223 clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); 180 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
224 clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); 181 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
225 clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); 182 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
226 clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); 183 clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
227 clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); 184 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
228 clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); 185 clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
229 clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); 186 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
230 clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); 187 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
231 clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); 188 clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
232 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); 189 clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
233 clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); 190 clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
234 clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); 191 clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
235 clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); 192 clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
236 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); 193 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
237 clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); 194 clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
238 clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); 195 clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
239 clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); 196 clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
240 clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); 197 clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
241 clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); 198 clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
242 clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); 199 clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
243 clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); 200 clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
244 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); 201 clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
245 clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); 202 clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
246 clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); 203 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
247 clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); 204 clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
248 clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); 205 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
249 clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); 206 clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
250 clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); 207 clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
251 clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); 208
252 clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); 209 clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
253 210 clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
254 clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); 211 clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
255 clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 212 clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
256 clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 213 clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
257 clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); 214 clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
258 clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 215 clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
259 clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); 216 clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
260 clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); 217 clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
261 clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); 218 clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
262 clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); 219 clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
263 clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); 220 clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
264 clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); 221 clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
265 clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); 222 clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
266 clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); 223 clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
267 clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); 224 clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
268 clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); 225 clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
269 clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); 226 clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
270 clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); 227 clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
271 clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); 228 clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
272 clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); 229 clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
273 clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); 230 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
274 clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); 231 clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
275 clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); 232 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
276 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); 233 clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
277 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); 234 clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
278 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); 235 clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
279 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); 236 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
280 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); 237 clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
281 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); 238 clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
282 clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); 239 clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
283 clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); 240 clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
284 clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); 241 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
285 clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, 242 clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
286 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); 243 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
287 clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); 244 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
288 clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); 245 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
289 246
290 for (i = 0; i < ARRAY_SIZE(clk); i++) 247 for (i = 0; i < ARRAY_SIZE(clk); i++)
291 if (IS_ERR(clk[i])) 248 if (IS_ERR(clk[i]))
292 pr_err("i.MX5 clk %d: register failed with %ld\n", 249 pr_err("i.MX5 clk %d: register failed with %ld\n",
293 i, PTR_ERR(clk[i])); 250 i, PTR_ERR(clk[i]));
294 251
295 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0"); 252 clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
296 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); 253 clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
297 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); 254 clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
298 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); 255 clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
299 clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1"); 256 clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
300 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); 257 clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
301 clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2"); 258 clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
302 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); 259 clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
303 clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3"); 260 clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
304 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); 261 clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
305 clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4"); 262 clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
306 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); 263 clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
307 clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0"); 264 clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
308 clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0"); 265 clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
309 clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1"); 266 clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
310 clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1"); 267 clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
311 clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2"); 268 clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
312 clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0"); 269 clk_register_clkdev(clk[IMX5_CLK_PWM1_IPG_GATE], "pwm", "mxc_pwm.0");
313 clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1"); 270 clk_register_clkdev(clk[IMX5_CLK_PWM2_IPG_GATE], "pwm", "mxc_pwm.1");
314 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); 271 clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
315 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); 272 clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
316 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0"); 273 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
317 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0"); 274 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
318 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0"); 275 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
319 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1"); 276 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
320 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1"); 277 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
321 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1"); 278 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
322 clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2"); 279 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
323 clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2"); 280 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
324 clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2"); 281 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
325 clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51"); 282 clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
326 clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51"); 283 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
327 clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51"); 284 clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
328 clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand"); 285 clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
329 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); 286 clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
330 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); 287 clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
331 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); 288 clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
332 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 289 clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
333 clk_register_clkdev(clk[cpu_podf], NULL, "cpu0"); 290 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
334 clk_register_clkdev(clk[iim_gate], "iim", NULL); 291 clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
335 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); 292 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
336 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); 293 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
337 clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); 294 clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
338 clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); 295 clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
339 clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL); 296 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
340 clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); 297 clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
341 clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0"); 298 clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
342 clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1"); 299 clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
343 clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1"); 300 clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
344 301
345 /* Set SDHC parents to be PLL2 */ 302 /* Set SDHC parents to be PLL2 */
346 clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); 303 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
347 clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]); 304 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
348 305
349 /* move usb phy clk to 24MHz */ 306 /* move usb phy clk to 24MHz */
350 clk_set_parent(clk[usb_phy_sel], clk[osc]); 307 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
351 308
352 clk_prepare_enable(clk[gpc_dvfs]); 309 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
353 clk_prepare_enable(clk[ahb_max]); /* esdhc3 */ 310 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
354 clk_prepare_enable(clk[aips_tz1]); 311 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
355 clk_prepare_enable(clk[aips_tz2]); /* fec */ 312 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
356 clk_prepare_enable(clk[spba]); 313 clk_prepare_enable(clk[IMX5_CLK_SPBA]);
357 clk_prepare_enable(clk[emi_fast_gate]); /* fec */ 314 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
358 clk_prepare_enable(clk[emi_slow_gate]); /* eim */ 315 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
359 clk_prepare_enable(clk[mipi_hsc1_gate]); 316 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
360 clk_prepare_enable(clk[mipi_hsc2_gate]); 317 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
361 clk_prepare_enable(clk[mipi_esc_gate]); 318 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
362 clk_prepare_enable(clk[mipi_hsp_gate]); 319 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
363 clk_prepare_enable(clk[tmax1]); 320 clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
364 clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ 321 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
365 clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ 322 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
366} 323}
367 324
325static void __init mx50_clocks_init(struct device_node *np)
326{
327 void __iomem *base;
328 unsigned long r;
329 int i, irq;
330
331 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
332 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
333 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
334
335 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
336 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
337 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
338 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
339 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
340 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
341 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
342 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
343 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
344
345 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
346 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
347 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
348 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
349
350 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
351 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
352 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
353 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
354
355 for (i = 0; i < ARRAY_SIZE(clk); i++)
356 if (IS_ERR(clk[i]))
357 pr_err("i.MX50 clk %d: register failed with %ld\n",
358 i, PTR_ERR(clk[i]));
359
360 clk_data.clks = clk;
361 clk_data.clk_num = ARRAY_SIZE(clk);
362 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
363
364 mx5_clocks_common_init(0, 0, 0, 0);
365
366 /* set SDHC root clock to 200MHZ*/
367 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
368 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
369
370 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
371 imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
372 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
373
374 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
375 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
376
377 np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
378 base = of_iomap(np, 0);
379 WARN_ON(!base);
380 irq = irq_of_parse_and_map(np, 0);
381 mxc_timer_init(base, irq);
382}
383CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
384
368int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, 385int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
369 unsigned long rate_ckih1, unsigned long rate_ckih2) 386 unsigned long rate_ckih1, unsigned long rate_ckih2)
370{ 387{
@@ -372,38 +389,40 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
372 u32 val; 389 u32 val;
373 struct device_node *np; 390 struct device_node *np;
374 391
375 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); 392 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
376 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); 393 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
377 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); 394 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
378 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, 395 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
379 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); 396 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
380 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, 397 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
381 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); 398 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
382 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, 399 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
383 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); 400 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
384 clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, 401 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
385 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); 402 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
386 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); 403 clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
387 clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); 404 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
388 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); 405 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
389 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); 406 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
390 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); 407 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
391 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); 408 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
392 clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); 409 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
393 clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); 410 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
394 clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); 411 clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
395 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); 412 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
396 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); 413 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
397 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); 414 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
398 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, 415 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
399 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); 416 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
400 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, 417 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
401 spdif_sel, ARRAY_SIZE(spdif_sel)); 418 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
402 clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); 419 clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
403 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); 420 spdif_sel, ARRAY_SIZE(spdif_sel));
404 clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, 421 clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
405 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); 422 clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
406 clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); 423 clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
424 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
425 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
407 426
408 for (i = 0; i < ARRAY_SIZE(clk); i++) 427 for (i = 0; i < ARRAY_SIZE(clk); i++)
409 if (IS_ERR(clk[i])) 428 if (IS_ERR(clk[i]))
@@ -417,37 +436,37 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
417 436
418 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); 437 mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
419 438
420 clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2"); 439 clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
421 clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL); 440 clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
422 clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0"); 441 clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
423 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); 442 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
424 clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0"); 443 clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
425 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0"); 444 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
426 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0"); 445 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
427 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0"); 446 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
428 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1"); 447 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
429 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1"); 448 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
430 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1"); 449 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
431 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2"); 450 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
432 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2"); 451 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
433 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2"); 452 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
434 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3"); 453 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
435 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3"); 454 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
436 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3"); 455 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
437 456
438 /* set the usboh3 parent to pll2_sw */ 457 /* set the usboh3 parent to pll2_sw */
439 clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); 458 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
440 459
441 /* set SDHC root clock to 166.25MHZ*/ 460 /* set SDHC root clock to 166.25MHZ*/
442 clk_set_rate(clk[esdhc_a_podf], 166250000); 461 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
443 clk_set_rate(clk[esdhc_b_podf], 166250000); 462 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
444 463
445 /* System timer */ 464 /* System timer */
446 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); 465 mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
447 466
448 clk_prepare_enable(clk[iim_gate]); 467 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
449 imx_print_silicon_rev("i.MX51", mx51_revision()); 468 imx_print_silicon_rev("i.MX51", mx51_revision());
450 clk_disable_unprepare(clk[iim_gate]); 469 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
451 470
452 /* 471 /*
453 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no 472 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
@@ -479,57 +498,59 @@ static void __init mx53_clocks_init(struct device_node *np)
479 unsigned long r; 498 unsigned long r;
480 void __iomem *base; 499 void __iomem *base;
481 500
482 clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); 501 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
483 clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); 502 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
484 clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); 503 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
485 clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); 504 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
486 505
487 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); 506 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
488 clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); 507 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
489 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, 508 clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
490 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); 509 clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
491 clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); 510 clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
492 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); 511 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
493 clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); 512 clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
494 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, 513 clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
495 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); 514 clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
496 clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); 515 clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
497 clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); 516 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
498 clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, 517 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
499 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); 518 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
500 clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, 519 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
501 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); 520 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
502 clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, 521 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
503 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); 522 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
504 clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); 523 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
505 clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); 524 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
506 clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); 525 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
507 clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); 526 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
508 clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); 527 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
509 clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); 528 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
510 clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); 529 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
511 clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); 530 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
512 clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, 531 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
513 mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); 532 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
514 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); 533 clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
515 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); 534 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
516 clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); 535 clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
517 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); 536 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
518 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); 537 clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
519 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 538 clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
520 clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); 539 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
521 540 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
522 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, 541 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
523 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); 542
524 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); 543 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
525 clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); 544 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
526 545 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
527 clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, 546 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
528 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); 547
529 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); 548 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
530 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); 549 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
531 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, 550 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
532 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); 551 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
552 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
553 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
533 554
534 for (i = 0; i < ARRAY_SIZE(clk); i++) 555 for (i = 0; i < ARRAY_SIZE(clk); i++)
535 if (IS_ERR(clk[i])) 556 if (IS_ERR(clk[i]))
@@ -542,33 +563,36 @@ static void __init mx53_clocks_init(struct device_node *np)
542 563
543 mx5_clocks_common_init(0, 0, 0, 0); 564 mx5_clocks_common_init(0, 0, 0, 0);
544 565
545 clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); 566 clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
546 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); 567 clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
547 clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0"); 568 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
548 clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0"); 569 clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
549 clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0"); 570 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
550 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0"); 571 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
551 clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0"); 572 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
552 clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1"); 573 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
553 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1"); 574 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
554 clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1"); 575 clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
555 clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2"); 576 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
556 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2"); 577 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
557 clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2"); 578 clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
558 clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3"); 579 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
559 clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3"); 580 clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
560 clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3"); 581 clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
561 582
562 /* set SDHC root clock to 200MHZ*/ 583 /* set SDHC root clock to 200MHZ*/
563 clk_set_rate(clk[esdhc_a_podf], 200000000); 584 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
564 clk_set_rate(clk[esdhc_b_podf], 200000000); 585 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
586
587 /* move can bus clk to 24MHz */
588 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
565 589
566 clk_prepare_enable(clk[iim_gate]); 590 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
567 imx_print_silicon_rev("i.MX53", mx53_revision()); 591 imx_print_silicon_rev("i.MX53", mx53_revision());
568 clk_disable_unprepare(clk[iim_gate]); 592 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
569 593
570 r = clk_round_rate(clk[usboh3_per_gate], 54000000); 594 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
571 clk_set_rate(clk[usboh3_per_gate], r); 595 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
572 596
573 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); 597 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
574 base = of_iomap(np, 0); 598 base = of_iomap(np, 0);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 04cfd0fcb0e5..af2e582d2b74 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -114,7 +114,7 @@ static struct clk *clk[clk_max];
114static struct clk_onecell_data clk_data; 114static struct clk_onecell_data clk_data;
115 115
116static enum mx6q_clks const clks_init_on[] __initconst = { 116static enum mx6q_clks const clks_init_on[] __initconst = {
117 mmdc_ch0_axi, rom, pll1_sys, 117 mmdc_ch0_axi, rom, arm,
118}; 118};
119 119
120static struct clk_div_table clk_enet_ref_table[] = { 120static struct clk_div_table clk_enet_ref_table[] = {
@@ -475,6 +475,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
475 if (ret) 475 if (ret)
476 pr_warn("failed to set up CLKO: %d\n", ret); 476 pr_warn("failed to set up CLKO: %d\n", ret);
477 477
478 /* Audio-related clocks configuration */
479 clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
480
478 /* All existing boards with PCIe use LVDS1 */ 481 /* All existing boards with PCIe use LVDS1 */
479 if (IS_ENABLED(CONFIG_PCI_IMX6)) 482 if (IS_ENABLED(CONFIG_PCI_IMX6))
480 clk_set_parent(clk[lvds1_sel], clk[sata_ref]); 483 clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index c0c4ef55e35b..3781a1853998 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -29,14 +29,14 @@ static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf"
29static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; 29static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
30static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; 30static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
31static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; 31static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
32static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", }; 32static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
33static const char const *perclk_sels[] = { "ipg", "osc", }; 33static const char const *perclk_sels[] = { "ipg", "osc", };
34static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; 34static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
35static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; 35static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
36static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; 36static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
37static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; 37static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
38static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; 38static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
39static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; 39static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
40static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; 40static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
41static const char const *uart_sels[] = { "pll3_80m", "osc", }; 41static const char const *uart_sels[] = { "pll3_80m", "osc", };
42 42
@@ -63,7 +63,7 @@ static struct clk_div_table video_div_table[] = {
63 { } 63 { }
64}; 64};
65 65
66static struct clk *clks[IMX6SL_CLK_CLK_END]; 66static struct clk *clks[IMX6SL_CLK_END];
67static struct clk_onecell_data clk_data; 67static struct clk_onecell_data clk_data;
68 68
69static void __init imx6sl_clocks_init(struct device_node *ccm_node) 69static void __init imx6sl_clocks_init(struct device_node *ccm_node)
@@ -104,6 +104,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
104 104
105 /* dev name parent_name flags reg shift width div: flags, div_table lock */ 105 /* dev name parent_name flags reg shift width div: flags, div_table lock */
106 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 106 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
107 clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
107 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 108 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
108 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 109 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
109 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); 110 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
@@ -232,6 +233,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
232 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); 233 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
233 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); 234 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
234 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); 235 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
236 clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
235 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); 237 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
236 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); 238 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
237 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); 239 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
@@ -261,6 +263,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
261 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); 263 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
262 } 264 }
263 265
266 /* Audio-related clocks configuration */
267 clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
268
264 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); 269 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
265 base = of_iomap(np, 0); 270 base = of_iomap(np, 0);
266 WARN_ON(!base); 271 WARN_ON(!base);
diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
index e2ed4160f329..0b0f6f66ec56 100644
--- a/arch/arm/mach-imx/clk-pfd.c
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -109,12 +109,23 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
109 return 0; 109 return 0;
110} 110}
111 111
112static int clk_pfd_is_enabled(struct clk_hw *hw)
113{
114 struct clk_pfd *pfd = to_clk_pfd(hw);
115
116 if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1)))
117 return 0;
118
119 return 1;
120}
121
112static const struct clk_ops clk_pfd_ops = { 122static const struct clk_ops clk_pfd_ops = {
113 .enable = clk_pfd_enable, 123 .enable = clk_pfd_enable,
114 .disable = clk_pfd_disable, 124 .disable = clk_pfd_disable,
115 .recalc_rate = clk_pfd_recalc_rate, 125 .recalc_rate = clk_pfd_recalc_rate,
116 .round_rate = clk_pfd_round_rate, 126 .round_rate = clk_pfd_round_rate,
117 .set_rate = clk_pfd_set_rate, 127 .set_rate = clk_pfd_set_rate,
128 .is_enabled = clk_pfd_is_enabled,
118}; 129};
119 130
120struct clk *imx_clk_pfd(const char *name, const char *parent_name, 131struct clk *imx_clk_pfd(const char *name, const char *parent_name,
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index c1eaee346954..d21d14ca46c1 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -18,6 +18,11 @@
18 * 18 *
19 * PLL clock version 1, found on i.MX1/21/25/27/31/35 19 * PLL clock version 1, found on i.MX1/21/25/27/31/35
20 */ 20 */
21
22#define MFN_BITS (10)
23#define MFN_SIGN (BIT(MFN_BITS - 1))
24#define MFN_MASK (MFN_SIGN - 1)
25
21struct clk_pllv1 { 26struct clk_pllv1 {
22 struct clk_hw hw; 27 struct clk_hw hw;
23 void __iomem *base; 28 void __iomem *base;
@@ -25,6 +30,11 @@ struct clk_pllv1 {
25 30
26#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) 31#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
27 32
33static inline bool mfn_is_negative(unsigned int mfn)
34{
35 return !cpu_is_mx1() && !cpu_is_mx21() && (mfn & MFN_SIGN);
36}
37
28static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, 38static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
29 unsigned long parent_rate) 39 unsigned long parent_rate)
30{ 40{
@@ -58,10 +68,15 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
58 68
59 /* 69 /*
60 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit 70 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
61 * 2's complements number 71 * 2's complements number.
72 * On i.MX27 the bit 9 is the sign bit.
62 */ 73 */
63 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) 74 if (mfn_is_negative(mfn)) {
64 mfn_abs = 0x400 - mfn; 75 if (cpu_is_mx27())
76 mfn_abs = mfn & MFN_MASK;
77 else
78 mfn_abs = BIT(MFN_BITS) - mfn;
79 }
65 80
66 rate = parent_rate * 2; 81 rate = parent_rate * 2;
67 rate /= pd + 1; 82 rate /= pd + 1;
@@ -70,7 +85,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
70 85
71 do_div(ll, mfd + 1); 86 do_div(ll, mfd + 1);
72 87
73 if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) 88 if (mfn_is_negative(mfn))
74 ll = -ll; 89 ll = -ll;
75 90
76 ll = (rate * mfi) + ll; 91 ll = (rate * mfi) + ll;
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index b169a396d93b..ecd66d8e20b6 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -298,6 +298,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
298 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); 298 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
299 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); 299 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
300 300
301 clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
302 clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
303 clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
304 clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
305
301 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); 306 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
302 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); 307 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
303 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); 308 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 24a7899e36a8..59c3b9b26bb4 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -108,6 +108,7 @@ void tzic_handle_irq(struct pt_regs *);
108#define imx27_handle_irq avic_handle_irq 108#define imx27_handle_irq avic_handle_irq
109#define imx31_handle_irq avic_handle_irq 109#define imx31_handle_irq avic_handle_irq
110#define imx35_handle_irq avic_handle_irq 110#define imx35_handle_irq avic_handle_irq
111#define imx50_handle_irq tzic_handle_irq
111#define imx51_handle_irq tzic_handle_irq 112#define imx51_handle_irq tzic_handle_irq
112#define imx53_handle_irq tzic_handle_irq 113#define imx53_handle_irq tzic_handle_irq
113 114
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 818a1cc2fe45..e1e70ef7bc2d 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
26} 26}
27 27
28static const char *imx31_dt_board_compat[] __initdata = { 28static const char *imx31_dt_board_compat[] __initconst = {
29 "fsl,imx31", 29 "fsl,imx31",
30 NULL 30 NULL
31}; 31};
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
new file mode 100644
index 000000000000..9d48e0065a63
--- /dev/null
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -0,0 +1,50 @@
1/*
2 * Copyright 2012 Steffen Trumtrar, Pengutronix
3 *
4 * based on imx27-dt.c
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 */
10
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/clk-provider.h>
16#include <linux/clocksource.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/time.h>
19#include <asm/hardware/cache-l2x0.h>
20#include "common.h"
21#include "mx35.h"
22
23static void __init imx35_dt_init(void)
24{
25 mxc_arch_reset_init_dt();
26
27 of_platform_populate(NULL, of_default_bus_match_table,
28 NULL, NULL);
29}
30
31static void __init imx35_irq_init(void)
32{
33 imx_init_l2cache();
34 mx35_init_irq();
35}
36
37static const char *imx35_dt_board_compat[] __initconst = {
38 "fsl,imx35",
39 NULL
40};
41
42DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
43 .map_io = mx35_map_io,
44 .init_early = imx35_init_early,
45 .init_irq = imx35_irq_init,
46 .handle_irq = imx35_handle_irq,
47 .init_machine = imx35_dt_init,
48 .dt_compat = imx35_dt_board_compat,
49 .restart = mxc_restart,
50MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index bece8a65e6f0..0230d78d1413 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -29,7 +29,7 @@ static void __init imx51_dt_init(void)
29 platform_device_register_full(&devinfo); 29 platform_device_register_full(&devinfo);
30} 30}
31 31
32static const char *imx51_dt_board_compat[] __initdata = { 32static const char *imx51_dt_board_compat[] __initconst = {
33 "fsl,imx51", 33 "fsl,imx51",
34 NULL 34 NULL
35}; 35};
diff --git a/arch/arm/mach-imx/irq-common.h b/arch/arm/mach-imx/irq-common.h
index 5b2dabba330f..6e3175dc0c0a 100644
--- a/arch/arm/mach-imx/irq-common.h
+++ b/arch/arm/mach-imx/irq-common.h
@@ -24,7 +24,6 @@
24 24
25struct mxc_extra_irq 25struct mxc_extra_irq
26{ 26{
27 int (*set_priority)(unsigned char irq, unsigned char prio);
28 int (*set_irq_fiq)(unsigned int irq, unsigned int type); 27 int (*set_irq_fiq)(unsigned int irq, unsigned int type);
29}; 28};
30 29
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
new file mode 100644
index 000000000000..77b77a92bb5d
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
3 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2011 Linaro Ltd.
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include <linux/of_platform.h>
15#include <asm/mach/arch.h>
16
17#include "common.h"
18
19static void __init imx50_dt_init(void)
20{
21 mxc_arch_reset_init_dt();
22
23 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
24}
25
26static const char *imx50_dt_board_compat[] __initconst = {
27 "fsl,imx50",
28 NULL
29};
30
31DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
32 .map_io = mx53_map_io,
33 .init_irq = mx53_init_irq,
34 .handle_irq = imx50_handle_irq,
35 .init_machine = imx50_dt_init,
36 .dt_compat = imx50_dt_board_compat,
37 .restart = mxc_restart,
38MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index c9c4d8d96931..65850908a4b4 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -31,7 +31,7 @@ static void __init imx53_dt_init(void)
31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
32} 32}
33 33
34static const char *imx53_dt_board_compat[] __initdata = { 34static const char *imx53_dt_board_compat[] __initconst = {
35 "fsl,imx53", 35 "fsl,imx53",
36 NULL 36 NULL
37}; 37};
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d0cfb225ec9a..d2ea6e60ea7b 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -13,6 +13,7 @@
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/clkdev.h> 14#include <linux/clkdev.h>
15#include <linux/cpu.h> 15#include <linux/cpu.h>
16#include <linux/delay.h>
16#include <linux/export.h> 17#include <linux/export.h>
17#include <linux/init.h> 18#include <linux/init.h>
18#include <linux/io.h> 19#include <linux/io.h>
@@ -23,6 +24,7 @@
23#include <linux/of_irq.h> 24#include <linux/of_irq.h>
24#include <linux/of_platform.h> 25#include <linux/of_platform.h>
25#include <linux/pm_opp.h> 26#include <linux/pm_opp.h>
27#include <linux/pci.h>
26#include <linux/phy.h> 28#include <linux/phy.h>
27#include <linux/reboot.h> 29#include <linux/reboot.h>
28#include <linux/regmap.h> 30#include <linux/regmap.h>
@@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev)
78 return 0; 80 return 0;
79} 81}
80 82
83/*
84 * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
85 * as they are used for slots1-7 PERST#
86 */
87static void ventana_pciesw_early_fixup(struct pci_dev *dev)
88{
89 u32 dw;
90
91 if (!of_machine_is_compatible("gw,ventana"))
92 return;
93
94 if (dev->devfn != 0)
95 return;
96
97 pci_read_config_dword(dev, 0x62c, &dw);
98 dw |= 0xaaa8; // GPIO1-7 outputs
99 pci_write_config_dword(dev, 0x62c, dw);
100
101 pci_read_config_dword(dev, 0x644, &dw);
102 dw |= 0xfe; // GPIO1-7 output high
103 pci_write_config_dword(dev, 0x644, dw);
104
105 msleep(100);
106}
107DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
108DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
109DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
110
81static int ar8031_phy_fixup(struct phy_device *dev) 111static int ar8031_phy_fixup(struct phy_device *dev)
82{ 112{
83 u16 val; 113 u16 val;
@@ -243,7 +273,7 @@ static void __init imx6q_init_irq(void)
243 irqchip_init(); 273 irqchip_init();
244} 274}
245 275
246static const char *imx6q_dt_compat[] __initdata = { 276static const char *imx6q_dt_compat[] __initconst = {
247 "fsl,imx6dl", 277 "fsl,imx6dl",
248 "fsl,imx6q", 278 "fsl,imx6q",
249 NULL, 279 NULL,
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 2f952e3fcf89..0f4fd4c0ab8e 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -34,6 +34,13 @@ static void __init imx6sl_fec_init(void)
34 } 34 }
35} 35}
36 36
37static void __init imx6sl_init_late(void)
38{
39 /* imx6sl reuses imx6q cpufreq driver */
40 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
41 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
42}
43
37static void __init imx6sl_init_machine(void) 44static void __init imx6sl_init_machine(void)
38{ 45{
39 struct device *parent; 46 struct device *parent;
@@ -61,7 +68,7 @@ static void __init imx6sl_init_irq(void)
61 irqchip_init(); 68 irqchip_init();
62} 69}
63 70
64static const char *imx6sl_dt_compat[] __initdata = { 71static const char *imx6sl_dt_compat[] __initconst = {
65 "fsl,imx6sl", 72 "fsl,imx6sl",
66 NULL, 73 NULL,
67}; 74};
@@ -70,6 +77,7 @@ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
70 .map_io = debug_ll_io_init, 77 .map_io = debug_ll_io_init,
71 .init_irq = imx6sl_init_irq, 78 .init_irq = imx6sl_init_irq,
72 .init_machine = imx6sl_init_machine, 79 .init_machine = imx6sl_init_machine,
80 .init_late = imx6sl_init_late,
73 .dt_compat = imx6sl_dt_compat, 81 .dt_compat = imx6sl_dt_compat,
74 .restart = mxc_restart, 82 .restart = mxc_restart,
75MACHINE_END 83MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index af0cb8a9dc48..2d8aef5a6efa 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -26,7 +26,7 @@ static void __init vf610_init_irq(void)
26 irqchip_init(); 26 irqchip_init();
27} 27}
28 28
29static const char *vf610_dt_compat[] __initdata = { 29static const char *vf610_dt_compat[] __initconst = {
30 "fsl,vf610", 30 "fsl,vf610",
31 NULL, 31 NULL,
32}; 32};
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index d1d52600f458..4c112021aa4e 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -89,15 +89,7 @@ void __init imx51_init_early(void)
89 89
90void __init imx53_init_early(void) 90void __init imx53_init_early(void)
91{ 91{
92 struct device_node *np;
93 void __iomem *base;
94
95 mxc_set_cpu_type(MXC_CPU_MX53); 92 mxc_set_cpu_type(MXC_CPU_MX53);
96
97 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc");
98 base = of_iomap(np, 0);
99 WARN_ON(!base);
100 mxc_iomux_v3_init(base);
101 imx_src_init(); 93 imx_src_init();
102} 94}
103 95
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index aecd9f8037e0..9d47adc078aa 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -156,10 +156,16 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
156 } 156 }
157 157
158 /* 158 /*
159 * Unmask the always pending IOMUXC interrupt #32 as wakeup source to 159 * ERR007265: CCM: When improper low-power sequence is used,
160 * deassert dsm_request signal, so that we can ensure dsm_request 160 * the SoC enters low power mode before the ARM core executes WFI.
161 * is not asserted when we're going to write CLPCR register to set LPM. 161 *
162 * After setting up LPM bits, we need to mask this wakeup source. 162 * Software workaround:
163 * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
164 * by setting IOMUX_GPR1_GINT.
165 * 2) Software should then unmask IRQ #32 in GPC before setting CCM
166 * Low-Power mode.
167 * 3) Software should mask IRQ #32 right after CCM Low-Power mode
168 * is set (set bits 0-1 of CCM_CLPCR).
163 */ 169 */
164 iomuxc_irq_desc = irq_to_desc(32); 170 iomuxc_irq_desc = irq_to_desc(32);
165 imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data); 171 imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
@@ -219,6 +225,8 @@ void __init imx6q_pm_init(void)
219 WARN_ON(!ccm_base); 225 WARN_ON(!ccm_base);
220 226
221 /* 227 /*
228 * This is for SW workaround step #1 of ERR007265, see comments
229 * in imx6q_set_lpm for details of this errata.
222 * Force IOMUXC irq pending, so that the interrupt to GPC can be 230 * Force IOMUXC irq pending, so that the interrupt to GPC can be
223 * used to deassert dsm_request signal when the signal gets 231 * used to deassert dsm_request signal when the signal gets
224 * asserted unexpectedly. 232 * asserted unexpectedly.
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
new file mode 100644
index 000000000000..5f2667ecd98e
--- /dev/null
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -0,0 +1,203 @@
1/*
2 * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX5_H
11#define __DT_BINDINGS_CLOCK_IMX5_H
12
13#define IMX5_CLK_DUMMY 0
14#define IMX5_CLK_CKIL 1
15#define IMX5_CLK_OSC 2
16#define IMX5_CLK_CKIH1 3
17#define IMX5_CLK_CKIH2 4
18#define IMX5_CLK_AHB 5
19#define IMX5_CLK_IPG 6
20#define IMX5_CLK_AXI_A 7
21#define IMX5_CLK_AXI_B 8
22#define IMX5_CLK_UART_PRED 9
23#define IMX5_CLK_UART_ROOT 10
24#define IMX5_CLK_ESDHC_A_PRED 11
25#define IMX5_CLK_ESDHC_B_PRED 12
26#define IMX5_CLK_ESDHC_C_SEL 13
27#define IMX5_CLK_ESDHC_D_SEL 14
28#define IMX5_CLK_EMI_SEL 15
29#define IMX5_CLK_EMI_SLOW_PODF 16
30#define IMX5_CLK_NFC_PODF 17
31#define IMX5_CLK_ECSPI_PRED 18
32#define IMX5_CLK_ECSPI_PODF 19
33#define IMX5_CLK_USBOH3_PRED 20
34#define IMX5_CLK_USBOH3_PODF 21
35#define IMX5_CLK_USB_PHY_PRED 22
36#define IMX5_CLK_USB_PHY_PODF 23
37#define IMX5_CLK_CPU_PODF 24
38#define IMX5_CLK_DI_PRED 25
39#define IMX5_CLK_TVE_SEL 27
40#define IMX5_CLK_UART1_IPG_GATE 28
41#define IMX5_CLK_UART1_PER_GATE 29
42#define IMX5_CLK_UART2_IPG_GATE 30
43#define IMX5_CLK_UART2_PER_GATE 31
44#define IMX5_CLK_UART3_IPG_GATE 32
45#define IMX5_CLK_UART3_PER_GATE 33
46#define IMX5_CLK_I2C1_GATE 34
47#define IMX5_CLK_I2C2_GATE 35
48#define IMX5_CLK_GPT_IPG_GATE 36
49#define IMX5_CLK_PWM1_IPG_GATE 37
50#define IMX5_CLK_PWM1_HF_GATE 38
51#define IMX5_CLK_PWM2_IPG_GATE 39
52#define IMX5_CLK_PWM2_HF_GATE 40
53#define IMX5_CLK_GPT_HF_GATE 41
54#define IMX5_CLK_FEC_GATE 42
55#define IMX5_CLK_USBOH3_PER_GATE 43
56#define IMX5_CLK_ESDHC1_IPG_GATE 44
57#define IMX5_CLK_ESDHC2_IPG_GATE 45
58#define IMX5_CLK_ESDHC3_IPG_GATE 46
59#define IMX5_CLK_ESDHC4_IPG_GATE 47
60#define IMX5_CLK_SSI1_IPG_GATE 48
61#define IMX5_CLK_SSI2_IPG_GATE 49
62#define IMX5_CLK_SSI3_IPG_GATE 50
63#define IMX5_CLK_ECSPI1_IPG_GATE 51
64#define IMX5_CLK_ECSPI1_PER_GATE 52
65#define IMX5_CLK_ECSPI2_IPG_GATE 53
66#define IMX5_CLK_ECSPI2_PER_GATE 54
67#define IMX5_CLK_CSPI_IPG_GATE 55
68#define IMX5_CLK_SDMA_GATE 56
69#define IMX5_CLK_EMI_SLOW_GATE 57
70#define IMX5_CLK_IPU_SEL 58
71#define IMX5_CLK_IPU_GATE 59
72#define IMX5_CLK_NFC_GATE 60
73#define IMX5_CLK_IPU_DI1_GATE 61
74#define IMX5_CLK_VPU_SEL 62
75#define IMX5_CLK_VPU_GATE 63
76#define IMX5_CLK_VPU_REFERENCE_GATE 64
77#define IMX5_CLK_UART4_IPG_GATE 65
78#define IMX5_CLK_UART4_PER_GATE 66
79#define IMX5_CLK_UART5_IPG_GATE 67
80#define IMX5_CLK_UART5_PER_GATE 68
81#define IMX5_CLK_TVE_GATE 69
82#define IMX5_CLK_TVE_PRED 70
83#define IMX5_CLK_ESDHC1_PER_GATE 71
84#define IMX5_CLK_ESDHC2_PER_GATE 72
85#define IMX5_CLK_ESDHC3_PER_GATE 73
86#define IMX5_CLK_ESDHC4_PER_GATE 74
87#define IMX5_CLK_USB_PHY_GATE 75
88#define IMX5_CLK_HSI2C_GATE 76
89#define IMX5_CLK_MIPI_HSC1_GATE 77
90#define IMX5_CLK_MIPI_HSC2_GATE 78
91#define IMX5_CLK_MIPI_ESC_GATE 79
92#define IMX5_CLK_MIPI_HSP_GATE 80
93#define IMX5_CLK_LDB_DI1_DIV_3_5 81
94#define IMX5_CLK_LDB_DI1_DIV 82
95#define IMX5_CLK_LDB_DI0_DIV_3_5 83
96#define IMX5_CLK_LDB_DI0_DIV 84
97#define IMX5_CLK_LDB_DI1_GATE 85
98#define IMX5_CLK_CAN2_SERIAL_GATE 86
99#define IMX5_CLK_CAN2_IPG_GATE 87
100#define IMX5_CLK_I2C3_GATE 88
101#define IMX5_CLK_LP_APM 89
102#define IMX5_CLK_PERIPH_APM 90
103#define IMX5_CLK_MAIN_BUS 91
104#define IMX5_CLK_AHB_MAX 92
105#define IMX5_CLK_AIPS_TZ1 93
106#define IMX5_CLK_AIPS_TZ2 94
107#define IMX5_CLK_TMAX1 95
108#define IMX5_CLK_TMAX2 96
109#define IMX5_CLK_TMAX3 97
110#define IMX5_CLK_SPBA 98
111#define IMX5_CLK_UART_SEL 99
112#define IMX5_CLK_ESDHC_A_SEL 100
113#define IMX5_CLK_ESDHC_B_SEL 101
114#define IMX5_CLK_ESDHC_A_PODF 102
115#define IMX5_CLK_ESDHC_B_PODF 103
116#define IMX5_CLK_ECSPI_SEL 104
117#define IMX5_CLK_USBOH3_SEL 105
118#define IMX5_CLK_USB_PHY_SEL 106
119#define IMX5_CLK_IIM_GATE 107
120#define IMX5_CLK_USBOH3_GATE 108
121#define IMX5_CLK_EMI_FAST_GATE 109
122#define IMX5_CLK_IPU_DI0_GATE 110
123#define IMX5_CLK_GPC_DVFS 111
124#define IMX5_CLK_PLL1_SW 112
125#define IMX5_CLK_PLL2_SW 113
126#define IMX5_CLK_PLL3_SW 114
127#define IMX5_CLK_IPU_DI0_SEL 115
128#define IMX5_CLK_IPU_DI1_SEL 116
129#define IMX5_CLK_TVE_EXT_SEL 117
130#define IMX5_CLK_MX51_MIPI 118
131#define IMX5_CLK_PLL4_SW 119
132#define IMX5_CLK_LDB_DI1_SEL 120
133#define IMX5_CLK_DI_PLL4_PODF 121
134#define IMX5_CLK_LDB_DI0_SEL 122
135#define IMX5_CLK_LDB_DI0_GATE 123
136#define IMX5_CLK_USB_PHY1_GATE 124
137#define IMX5_CLK_USB_PHY2_GATE 125
138#define IMX5_CLK_PER_LP_APM 126
139#define IMX5_CLK_PER_PRED1 127
140#define IMX5_CLK_PER_PRED2 128
141#define IMX5_CLK_PER_PODF 129
142#define IMX5_CLK_PER_ROOT 130
143#define IMX5_CLK_SSI_APM 131
144#define IMX5_CLK_SSI1_ROOT_SEL 132
145#define IMX5_CLK_SSI2_ROOT_SEL 133
146#define IMX5_CLK_SSI3_ROOT_SEL 134
147#define IMX5_CLK_SSI_EXT1_SEL 135
148#define IMX5_CLK_SSI_EXT2_SEL 136
149#define IMX5_CLK_SSI_EXT1_COM_SEL 137
150#define IMX5_CLK_SSI_EXT2_COM_SEL 138
151#define IMX5_CLK_SSI1_ROOT_PRED 139
152#define IMX5_CLK_SSI1_ROOT_PODF 140
153#define IMX5_CLK_SSI2_ROOT_PRED 141
154#define IMX5_CLK_SSI2_ROOT_PODF 142
155#define IMX5_CLK_SSI_EXT1_PRED 143
156#define IMX5_CLK_SSI_EXT1_PODF 144
157#define IMX5_CLK_SSI_EXT2_PRED 145
158#define IMX5_CLK_SSI_EXT2_PODF 146
159#define IMX5_CLK_SSI1_ROOT_GATE 147
160#define IMX5_CLK_SSI2_ROOT_GATE 148
161#define IMX5_CLK_SSI3_ROOT_GATE 149
162#define IMX5_CLK_SSI_EXT1_GATE 150
163#define IMX5_CLK_SSI_EXT2_GATE 151
164#define IMX5_CLK_EPIT1_IPG_GATE 152
165#define IMX5_CLK_EPIT1_HF_GATE 153
166#define IMX5_CLK_EPIT2_IPG_GATE 154
167#define IMX5_CLK_EPIT2_HF_GATE 155
168#define IMX5_CLK_CAN_SEL 156
169#define IMX5_CLK_CAN1_SERIAL_GATE 157
170#define IMX5_CLK_CAN1_IPG_GATE 158
171#define IMX5_CLK_OWIRE_GATE 159
172#define IMX5_CLK_GPU3D_SEL 160
173#define IMX5_CLK_GPU2D_SEL 161
174#define IMX5_CLK_GPU3D_GATE 162
175#define IMX5_CLK_GPU2D_GATE 163
176#define IMX5_CLK_GARB_GATE 164
177#define IMX5_CLK_CKO1_SEL 165
178#define IMX5_CLK_CKO1_PODF 166
179#define IMX5_CLK_CKO1 167
180#define IMX5_CLK_CKO2_SEL 168
181#define IMX5_CLK_CKO2_PODF 169
182#define IMX5_CLK_CKO2 170
183#define IMX5_CLK_SRTC_GATE 171
184#define IMX5_CLK_PATA_GATE 172
185#define IMX5_CLK_SATA_GATE 173
186#define IMX5_CLK_SPDIF_XTAL_SEL 174
187#define IMX5_CLK_SPDIF0_SEL 175
188#define IMX5_CLK_SPDIF1_SEL 176
189#define IMX5_CLK_SPDIF0_PRED 177
190#define IMX5_CLK_SPDIF0_PODF 178
191#define IMX5_CLK_SPDIF1_PRED 179
192#define IMX5_CLK_SPDIF1_PODF 180
193#define IMX5_CLK_SPDIF0_COM_SEL 181
194#define IMX5_CLK_SPDIF1_COM_SEL 182
195#define IMX5_CLK_SPDIF0_GATE 183
196#define IMX5_CLK_SPDIF1_GATE 184
197#define IMX5_CLK_SPDIF_IPG_GATE 185
198#define IMX5_CLK_OCRAM 186
199#define IMX5_CLK_SAHARA_IPG_GATE 187
200#define IMX5_CLK_SATA_REF 188
201#define IMX5_CLK_END 189
202
203#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index 7fcdf90879f2..7cf5c9969336 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -143,6 +143,8 @@
143#define IMX6SL_CLK_USDHC2 130 143#define IMX6SL_CLK_USDHC2 130
144#define IMX6SL_CLK_USDHC3 131 144#define IMX6SL_CLK_USDHC3 131
145#define IMX6SL_CLK_USDHC4 132 145#define IMX6SL_CLK_USDHC4 132
146#define IMX6SL_CLK_CLK_END 133 146#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
147#define IMX6SL_CLK_SPBA 134
148#define IMX6SL_CLK_END 135
147 149
148#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ 150#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 4aa2b48cd151..a91602951d3d 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -160,6 +160,10 @@
160#define VF610_CLK_GPU2D 147 160#define VF610_CLK_GPU2D 147
161#define VF610_CLK_ENET0 148 161#define VF610_CLK_ENET0 148
162#define VF610_CLK_ENET1 149 162#define VF610_CLK_ENET1 149
163#define VF610_CLK_END 150 163#define VF610_CLK_DMAMUX0 150
164#define VF610_CLK_DMAMUX1 151
165#define VF610_CLK_DMAMUX2 152
166#define VF610_CLK_DMAMUX3 153
167#define VF610_CLK_END 154
164 168
165#endif /* __DT_BINDINGS_CLOCK_VF610_H */ 169#endif /* __DT_BINDINGS_CLOCK_VF610_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 23:26:20 -0400