diff options
author | Alexey Brodkin <abrodkin@synopsys.com> | 2015-04-01 09:21:00 -0400 |
---|---|---|
committer | Vineet Gupta <vgupta@synopsys.com> | 2015-06-24 20:30:20 -0400 |
commit | e0183f523025f96e2053200616a6d602ea2b3451 (patch) | |
tree | 8d9571f884cab9025c3503bfa913c6094267e639 | |
parent | a12ebe16a5cea66c17a621ece3a557b8afda2361 (diff) |
ARC: [axs101] Prepare for AXS103
To avoid duplicating the MB DTS file, move the MB intc entry into cpu
card specific file
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
-rw-r--r-- | arch/arc/boot/dts/axc001.dtsi | 21 | ||||
-rw-r--r-- | arch/arc/boot/dts/axs10x_mb.dtsi | 17 |
2 files changed, 21 insertions, 17 deletions
diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi index 6990ca45fc7b..a5e2726a067e 100644 --- a/arch/arc/boot/dts/axc001.dtsi +++ b/arch/arc/boot/dts/axc001.dtsi | |||
@@ -69,6 +69,27 @@ | |||
69 | }; | 69 | }; |
70 | }; | 70 | }; |
71 | 71 | ||
72 | /* | ||
73 | * This INTC is actually connected to DW APB GPIO | ||
74 | * which acts as a wire between MB INTC and CPU INTC. | ||
75 | * GPIO INTC is configured in platform init code | ||
76 | * and here we mimic direct connection from MB INTC to | ||
77 | * CPU INTC, thus we set "interrupts = <7>" instead of | ||
78 | * "interrupts = <12>" | ||
79 | * | ||
80 | * This intc actually resides on MB, but we move it here to | ||
81 | * avoid duplicating the MB dtsi file given that IRQ from | ||
82 | * this intc to cpu intc are different for axs101 and axs103 | ||
83 | */ | ||
84 | mb_intc: dw-apb-ictl@0xe0012000 { | ||
85 | #interrupt-cells = <1>; | ||
86 | compatible = "snps,dw-apb-ictl"; | ||
87 | reg = < 0xe0012000 0x200 >; | ||
88 | interrupt-controller; | ||
89 | interrupt-parent = <&cpu_intc>; | ||
90 | interrupts = < 7 >; | ||
91 | }; | ||
92 | |||
72 | memory { | 93 | memory { |
73 | #address-cells = <1>; | 94 | #address-cells = <1>; |
74 | #size-cells = <1>; | 95 | #size-cells = <1>; |
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi index 5d06f1fb4266..f3db32154973 100644 --- a/arch/arc/boot/dts/axs10x_mb.dtsi +++ b/arch/arc/boot/dts/axs10x_mb.dtsi | |||
@@ -36,23 +36,6 @@ | |||
36 | }; | 36 | }; |
37 | }; | 37 | }; |
38 | 38 | ||
39 | /* | ||
40 | * This INTC is actually connected to DW APB GPIO | ||
41 | * which acts as a wire between MB INTC and CPU INTC. | ||
42 | * GPIO INTC is configured in platform init code | ||
43 | * and here we mimic direct connection from MB INTC to | ||
44 | * CPU INTC, thus we set "interrupts = <7>" instead of | ||
45 | * "interrupts = <12>" | ||
46 | */ | ||
47 | mb_intc: dw-apb-ictl@0x12000 { | ||
48 | #interrupt-cells = <1>; | ||
49 | compatible = "snps,dw-apb-ictl"; | ||
50 | reg = < 0x12000 0x200 >; | ||
51 | interrupt-controller; | ||
52 | interrupt-parent = <&cpu_intc>; | ||
53 | interrupts = < 7 >; | ||
54 | }; | ||
55 | |||
56 | ethernet@0x18000 { | 39 | ethernet@0x18000 { |
57 | #interrupt-cells = <1>; | 40 | #interrupt-cells = <1>; |
58 | compatible = "snps,dwmac"; | 41 | compatible = "snps,dwmac"; |