diff options
author | Niklas Cassel <niklas.cassel@axis.com> | 2017-12-19 18:29:34 -0500 |
---|---|---|
committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2017-12-21 06:10:33 -0500 |
commit | dff9cba6f8ef2fe26dadbaebacc7cbf7ed50a327 (patch) | |
tree | 8b7020b017bc4f0073894fca008fb48b071b8347 | |
parent | 87c9a730fe3161984848afc78c53eeb98ba40b4f (diff) |
bindings: PCI: artpec: Add support for endpoint mode
The PCIe controller integrated in ARTPEC-6 SoCs is capable of operating in
endpoint mode. Add endpoint mode support to the artpec6 driver.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
-rw-r--r-- | Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 4e4aee4439ea..33eef7ae5a23 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | |||
@@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP | |||
4 | and thus inherits all the common properties defined in designware-pcie.txt. | 4 | and thus inherits all the common properties defined in designware-pcie.txt. |
5 | 5 | ||
6 | Required properties: | 6 | Required properties: |
7 | - compatible: "axis,artpec6-pcie", "snps,dw-pcie" | 7 | - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; |
8 | "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; | ||
8 | - reg: base addresses and lengths of the PCIe controller (DBI), | 9 | - reg: base addresses and lengths of the PCIe controller (DBI), |
9 | the PHY controller, and configuration address space. | 10 | the PHY controller, and configuration address space. |
10 | - reg-names: Must include the following entries: | 11 | - reg-names: Must include the following entries: |