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authorDouglas Anderson <dianders@chromium.org>2019-04-09 16:47:06 -0400
committerHeiko Stuebner <heiko@sntech.de>2019-04-11 15:25:43 -0400
commitdfe7fb21cd9e730230d55a79bc72cf2ece67cdd5 (patch)
treec5fe1b331c0586476294b4e5a4780eda982d4512
parentfb903392131a324a243c7731389277db1cd9f8df (diff)
clk: rockchip: Make rkpwm a critical clock on rk3288
Most rk3288-based boards are derived from the EVB and thus use a PWM regulator for the logic rail. However, most rk3288-based boards don't specify the PWM regulator in their device tree. We'll deal with that by making it critical. NOTE: it's important to make it critical and not just IGNORE_UNUSED because all PWMs in the system share the same clock. We don't want another PWM user to turn the clock on and off and kill the logic rail. This change is in preparation for actually having the PWMs in the rk3288 device tree actually point to the proper PWM clock. Up until now they've all pointed to the clock for the old IP block and they've all worked due to the fact that rkpwm was IGNORE_UNUSED and that the clock rates for both clocks were the same. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 5a67b7869960..f47d514cba36 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -697,7 +697,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
697 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), 697 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
698 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), 698 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
699 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS), 699 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
700 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS), 700 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
701 701
702 /* ddrctrl [DDR Controller PHY clock] gates */ 702 /* ddrctrl [DDR Controller PHY clock] gates */
703 GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS), 703 GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
@@ -843,6 +843,8 @@ static const char *const rk3288_critical_clocks[] __initconst = {
843 "pclk_ddrupctl1", 843 "pclk_ddrupctl1",
844 "pclk_publ1", 844 "pclk_publ1",
845 "pmu_hclk_otg0", 845 "pmu_hclk_otg0",
846 /* pwm-regulators on some boards, so handoff-critical later */
847 "pclk_rkpwm",
846}; 848};
847 849
848static void __iomem *rk3288_cru_base; 850static void __iomem *rk3288_cru_base;