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authorAlexandre Demers <alexandre.f.demers@gmail.com>2016-08-21 20:38:41 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-08-22 13:47:25 -0400
commitdfaf2291ab6073e33068eabaa3f3d6b8632bc81c (patch)
tree74a4078a718b66dcc09a6bb5fb8cbbd9ad4d6ead
parent99e124f402d6d649498e2aa3cbcf4563a37fea0e (diff)
drm/amdgpu: Use correct mask in dce_v8_0_afmt_setmode() and fix comment typos.
We were using the same mask twice. Looking at radeon, it seems we should be using HDMI_AVI_INFO_CONT instead as the second mask. Being there, fix typos in comments and improved readability. I haven't looked at other DCEs, the mask may also be wrong for them. Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index efca1b972813..86a5fa0cccd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1739,6 +1739,7 @@ static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1739 /* Silent, r600_hdmi_enable will raise WARN for us */ 1739 /* Silent, r600_hdmi_enable will raise WARN for us */
1740 if (!dig->afmt->enabled) 1740 if (!dig->afmt->enabled)
1741 return; 1741 return;
1742
1742 offset = dig->afmt->offset; 1743 offset = dig->afmt->offset;
1743 1744
1744 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1745 /* hdmi deep color mode general control packets setup, if bpc > 8 */
@@ -1863,7 +1864,7 @@ static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1863 1864
1864 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, 1865 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1865 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */ 1866 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1866 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */ 1867 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */
1867 1868
1868 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, 1869 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1869 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */ 1870 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
@@ -1872,13 +1873,12 @@ static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1872 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1873 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1873 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */ 1874 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1874 1875
1875 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1876 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 1876 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1877 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 1877 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1878 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); 1878 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1879 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); 1879 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1880 1880
1881 /* enable audio after to setting up hw */ 1881 /* enable audio after setting up hw */
1882 dce_v8_0_audio_enable(adev, dig->afmt->pin, true); 1882 dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1883} 1883}
1884 1884