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authorBard Liao <bardliao@realtek.com>2016-09-08 22:33:10 -0400
committerMark Brown <broonie@kernel.org>2016-09-14 11:22:14 -0400
commitdf7c52168ee15b3951b50078c0c3960598eb0109 (patch)
tree166972bb263f933dbec89ff6b5abff927c3ab640
parent29b4817d4018df78086157ea3a55c1d9424a7cfc (diff)
ASoC: add rt5663 codec driver
This is the initial codec driver for both rt5663 rt5668 codec. Signed-off-by: John Lin <john.lin@realtek.com> Signed-off-by: Jack Yu <jack.yu@realtek.com> Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/sound/rt5663.txt30
-rw-r--r--sound/soc/codecs/Kconfig7
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/rt5663.c3216
-rw-r--r--sound/soc/codecs/rt5663.h1121
5 files changed, 4376 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt
new file mode 100644
index 000000000000..7d3c974c6e2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5663.txt
@@ -0,0 +1,30 @@
1RT5663/RT5668 audio CODEC
2
3This device supports I2C only.
4
5Required properties:
6
7- compatible : One of "realtek,rt5663" or "realtek,rt5668".
8
9- reg : The I2C address of the device.
10
11- interrupts : The CODEC's interrupt output.
12
13Optional properties:
14
15Pins on the device (for linking into audio routes) for RT5663/RT5668:
16
17 * IN1P
18 * IN1N
19 * IN2P
20 * IN2N
21 * HPOL
22 * HPOR
23
24Example:
25
26codec: rt5663@12 {
27 compatible = "realtek,rt5663";
28 reg = <0x12>;
29 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
30};
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 1cd6ab344d67..302860610b72 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -112,6 +112,7 @@ config SND_SOC_ALL_CODECS
112 select SND_SOC_RT5645 if I2C 112 select SND_SOC_RT5645 if I2C
113 select SND_SOC_RT5651 if I2C 113 select SND_SOC_RT5651 if I2C
114 select SND_SOC_RT5659 if I2C 114 select SND_SOC_RT5659 if I2C
115 select SND_SOC_RT5663 if I2C
115 select SND_SOC_RT5670 if I2C 116 select SND_SOC_RT5670 if I2C
116 select SND_SOC_RT5677 if I2C && SPI_MASTER 117 select SND_SOC_RT5677 if I2C && SPI_MASTER
117 select SND_SOC_SGTL5000 if I2C 118 select SND_SOC_SGTL5000 if I2C
@@ -645,6 +646,7 @@ config SND_SOC_RL6231
645 default y if SND_SOC_RT5645=y 646 default y if SND_SOC_RT5645=y
646 default y if SND_SOC_RT5651=y 647 default y if SND_SOC_RT5651=y
647 default y if SND_SOC_RT5659=y 648 default y if SND_SOC_RT5659=y
649 default y if SND_SOC_RT5663=y
648 default y if SND_SOC_RT5670=y 650 default y if SND_SOC_RT5670=y
649 default y if SND_SOC_RT5677=y 651 default y if SND_SOC_RT5677=y
650 default m if SND_SOC_RT5514=m 652 default m if SND_SOC_RT5514=m
@@ -653,6 +655,7 @@ config SND_SOC_RL6231
653 default m if SND_SOC_RT5645=m 655 default m if SND_SOC_RT5645=m
654 default m if SND_SOC_RT5651=m 656 default m if SND_SOC_RT5651=m
655 default m if SND_SOC_RT5659=m 657 default m if SND_SOC_RT5659=m
658 default m if SND_SOC_RT5663=m
656 default m if SND_SOC_RT5670=m 659 default m if SND_SOC_RT5670=m
657 default m if SND_SOC_RT5677=m 660 default m if SND_SOC_RT5677=m
658 661
@@ -665,6 +668,7 @@ config SND_SOC_RL6347A
665 668
666config SND_SOC_RT286 669config SND_SOC_RT286
667 tristate 670 tristate
671 select SND_SOC_RT5663
668 depends on I2C 672 depends on I2C
669 673
670config SND_SOC_RT298 674config SND_SOC_RT298
@@ -697,6 +701,9 @@ config SND_SOC_RT5651
697config SND_SOC_RT5659 701config SND_SOC_RT5659
698 tristate 702 tristate
699 703
704config SND_SOC_RT5663
705 tristate
706
700config SND_SOC_RT5670 707config SND_SOC_RT5670
701 tristate 708 tristate
702 709
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 58036af2c7d9..dca8d9ca59fc 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -112,6 +112,7 @@ snd-soc-rt5640-objs := rt5640.o
112snd-soc-rt5645-objs := rt5645.o 112snd-soc-rt5645-objs := rt5645.o
113snd-soc-rt5651-objs := rt5651.o 113snd-soc-rt5651-objs := rt5651.o
114snd-soc-rt5659-objs := rt5659.o 114snd-soc-rt5659-objs := rt5659.o
115snd-soc-rt5663-objs := rt5663.o
115snd-soc-rt5670-objs := rt5670.o 116snd-soc-rt5670-objs := rt5670.o
116snd-soc-rt5677-objs := rt5677.o 117snd-soc-rt5677-objs := rt5677.o
117snd-soc-rt5677-spi-objs := rt5677-spi.o 118snd-soc-rt5677-spi-objs := rt5677-spi.o
@@ -333,6 +334,7 @@ obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
333obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o 334obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
334obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o 335obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
335obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o 336obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o
337obj-$(CONFIG_SND_SOC_RT5663) += snd-soc-rt5663.o
336obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o 338obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
337obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o 339obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
338obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o 340obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o
diff --git a/sound/soc/codecs/rt5663.c b/sound/soc/codecs/rt5663.c
new file mode 100644
index 000000000000..7963a2736a91
--- /dev/null
+++ b/sound/soc/codecs/rt5663.c
@@ -0,0 +1,3216 @@
1/*
2 * rt5663.c -- RT5668/RT5663 ALSA SoC audio codec driver
3 *
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/i2c.h>
17#include <linux/platform_device.h>
18#include <linux/spi/spi.h>
19#include <linux/acpi.h>
20#include <linux/workqueue.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5663.h"
31#include "rl6231.h"
32
33#define RT5668_DEVICE_ID 0x6451
34#define RT5663_DEVICE_ID 0x6406
35
36enum {
37 CODEC_TYPE_RT5668,
38 CODEC_TYPE_RT5663,
39};
40
41struct rt5663_priv {
42 struct snd_soc_codec *codec;
43 struct regmap *regmap;
44 struct delayed_work jack_detect_work;
45 struct snd_soc_jack *hs_jack;
46 struct timer_list btn_check_timer;
47
48 int codec_type;
49 int sysclk;
50 int sysclk_src;
51 int lrck;
52
53 int pll_src;
54 int pll_in;
55 int pll_out;
56
57 int jack_type;
58};
59
60static const struct reg_default rt5668_reg[] = {
61 { 0x0000, 0x0000 },
62 { 0x0001, 0xc8c8 },
63 { 0x0002, 0x8080 },
64 { 0x0003, 0x8000 },
65 { 0x0004, 0xc80a },
66 { 0x0005, 0x0000 },
67 { 0x0006, 0x0000 },
68 { 0x0007, 0x0000 },
69 { 0x000a, 0x0000 },
70 { 0x000b, 0x0000 },
71 { 0x000c, 0x0000 },
72 { 0x000d, 0x0000 },
73 { 0x000f, 0x0808 },
74 { 0x0010, 0x4000 },
75 { 0x0011, 0x0000 },
76 { 0x0012, 0x1404 },
77 { 0x0013, 0x1000 },
78 { 0x0014, 0xa00a },
79 { 0x0015, 0x0404 },
80 { 0x0016, 0x0404 },
81 { 0x0017, 0x0011 },
82 { 0x0018, 0xafaf },
83 { 0x0019, 0xafaf },
84 { 0x001a, 0xafaf },
85 { 0x001b, 0x0011 },
86 { 0x001c, 0x2f2f },
87 { 0x001d, 0x2f2f },
88 { 0x001e, 0x2f2f },
89 { 0x001f, 0x0000 },
90 { 0x0020, 0x0000 },
91 { 0x0021, 0x0000 },
92 { 0x0022, 0x5757 },
93 { 0x0023, 0x0039 },
94 { 0x0024, 0x000b },
95 { 0x0026, 0xc0c0 },
96 { 0x0027, 0xc0c0 },
97 { 0x0028, 0xc0c0 },
98 { 0x0029, 0x8080 },
99 { 0x002a, 0xaaaa },
100 { 0x002b, 0xaaaa },
101 { 0x002c, 0xaba8 },
102 { 0x002d, 0x0000 },
103 { 0x002e, 0x0000 },
104 { 0x002f, 0x0000 },
105 { 0x0030, 0x0000 },
106 { 0x0031, 0x5000 },
107 { 0x0032, 0x0000 },
108 { 0x0033, 0x0000 },
109 { 0x0034, 0x0000 },
110 { 0x0035, 0x0000 },
111 { 0x003a, 0x0000 },
112 { 0x003b, 0x0000 },
113 { 0x003c, 0x00ff },
114 { 0x003d, 0x0000 },
115 { 0x003e, 0x00ff },
116 { 0x003f, 0x0000 },
117 { 0x0040, 0x0000 },
118 { 0x0041, 0x00ff },
119 { 0x0042, 0x0000 },
120 { 0x0043, 0x00ff },
121 { 0x0044, 0x0c0c },
122 { 0x0049, 0xc00b },
123 { 0x004a, 0x0000 },
124 { 0x004b, 0x031f },
125 { 0x004d, 0x0000 },
126 { 0x004e, 0x001f },
127 { 0x004f, 0x0000 },
128 { 0x0050, 0x001f },
129 { 0x0052, 0xf000 },
130 { 0x0061, 0x0000 },
131 { 0x0062, 0x0000 },
132 { 0x0063, 0x003e },
133 { 0x0064, 0x0000 },
134 { 0x0065, 0x0000 },
135 { 0x0066, 0x003f },
136 { 0x0067, 0x0000 },
137 { 0x006b, 0x0000 },
138 { 0x006d, 0xff00 },
139 { 0x006e, 0x2808 },
140 { 0x006f, 0x000a },
141 { 0x0070, 0x8000 },
142 { 0x0071, 0x8000 },
143 { 0x0072, 0x8000 },
144 { 0x0073, 0x7000 },
145 { 0x0074, 0x7770 },
146 { 0x0075, 0x0002 },
147 { 0x0076, 0x0001 },
148 { 0x0078, 0x00f0 },
149 { 0x0079, 0x0000 },
150 { 0x007a, 0x0000 },
151 { 0x007b, 0x0000 },
152 { 0x007c, 0x0000 },
153 { 0x007d, 0x0123 },
154 { 0x007e, 0x4500 },
155 { 0x007f, 0x8003 },
156 { 0x0080, 0x0000 },
157 { 0x0081, 0x0000 },
158 { 0x0082, 0x0000 },
159 { 0x0083, 0x0000 },
160 { 0x0084, 0x0000 },
161 { 0x0085, 0x0000 },
162 { 0x0086, 0x0008 },
163 { 0x0087, 0x0000 },
164 { 0x0088, 0x0000 },
165 { 0x0089, 0x0000 },
166 { 0x008a, 0x0000 },
167 { 0x008b, 0x0000 },
168 { 0x008c, 0x0003 },
169 { 0x008e, 0x0060 },
170 { 0x008f, 0x1000 },
171 { 0x0091, 0x0c26 },
172 { 0x0092, 0x0073 },
173 { 0x0093, 0x0000 },
174 { 0x0094, 0x0080 },
175 { 0x0098, 0x0000 },
176 { 0x0099, 0x0000 },
177 { 0x009a, 0x0007 },
178 { 0x009f, 0x0000 },
179 { 0x00a0, 0x0000 },
180 { 0x00a1, 0x0002 },
181 { 0x00a2, 0x0001 },
182 { 0x00a3, 0x0002 },
183 { 0x00a4, 0x0001 },
184 { 0x00ae, 0x2040 },
185 { 0x00af, 0x0000 },
186 { 0x00b6, 0x0000 },
187 { 0x00b7, 0x0000 },
188 { 0x00b8, 0x0000 },
189 { 0x00b9, 0x0000 },
190 { 0x00ba, 0x0002 },
191 { 0x00bb, 0x0000 },
192 { 0x00be, 0x0000 },
193 { 0x00c0, 0x0000 },
194 { 0x00c1, 0x0aaa },
195 { 0x00c2, 0xaa80 },
196 { 0x00c3, 0x0003 },
197 { 0x00c4, 0x0000 },
198 { 0x00d0, 0x0000 },
199 { 0x00d1, 0x2244 },
200 { 0x00d2, 0x0000 },
201 { 0x00d3, 0x3300 },
202 { 0x00d4, 0x2200 },
203 { 0x00d9, 0x0809 },
204 { 0x00da, 0x0000 },
205 { 0x00db, 0x0008 },
206 { 0x00dc, 0x00c0 },
207 { 0x00dd, 0x6724 },
208 { 0x00de, 0x3131 },
209 { 0x00df, 0x0008 },
210 { 0x00e0, 0x4000 },
211 { 0x00e1, 0x3131 },
212 { 0x00e2, 0x600c },
213 { 0x00ea, 0xb320 },
214 { 0x00eb, 0x0000 },
215 { 0x00ec, 0xb300 },
216 { 0x00ed, 0x0000 },
217 { 0x00ee, 0xb320 },
218 { 0x00ef, 0x0000 },
219 { 0x00f0, 0x0201 },
220 { 0x00f1, 0x0ddd },
221 { 0x00f2, 0x0ddd },
222 { 0x00f6, 0x0000 },
223 { 0x00f7, 0x0000 },
224 { 0x00f8, 0x0000 },
225 { 0x00fa, 0x0000 },
226 { 0x00fb, 0x0000 },
227 { 0x00fc, 0x0000 },
228 { 0x00fd, 0x0000 },
229 { 0x00fe, 0x10ec },
230 { 0x00ff, 0x6451 },
231 { 0x0100, 0xaaaa },
232 { 0x0101, 0x000a },
233 { 0x010a, 0xaaaa },
234 { 0x010b, 0xa0a0 },
235 { 0x010c, 0xaeae },
236 { 0x010d, 0xaaaa },
237 { 0x010e, 0xaaaa },
238 { 0x010f, 0xaaaa },
239 { 0x0110, 0xe002 },
240 { 0x0111, 0xa602 },
241 { 0x0112, 0xaaaa },
242 { 0x0113, 0x2000 },
243 { 0x0117, 0x0f00 },
244 { 0x0125, 0x0420 },
245 { 0x0132, 0x0000 },
246 { 0x0133, 0x0000 },
247 { 0x0136, 0x5555 },
248 { 0x0137, 0x5540 },
249 { 0x0138, 0x3700 },
250 { 0x0139, 0x79a1 },
251 { 0x013a, 0x2020 },
252 { 0x013b, 0x2020 },
253 { 0x013c, 0x2005 },
254 { 0x013f, 0x0000 },
255 { 0x0145, 0x0002 },
256 { 0x0146, 0x0000 },
257 { 0x0147, 0x0000 },
258 { 0x0148, 0x0000 },
259 { 0x0160, 0x4ec0 },
260 { 0x0161, 0x0080 },
261 { 0x0162, 0x0200 },
262 { 0x0163, 0x0800 },
263 { 0x0164, 0x0000 },
264 { 0x0165, 0x0000 },
265 { 0x0166, 0x0000 },
266 { 0x0167, 0x000f },
267 { 0x0168, 0x000f },
268 { 0x0170, 0x4e80 },
269 { 0x0171, 0x0080 },
270 { 0x0172, 0x0200 },
271 { 0x0173, 0x0800 },
272 { 0x0174, 0x00ff },
273 { 0x0175, 0x0000 },
274 { 0x0190, 0x4131 },
275 { 0x0191, 0x4131 },
276 { 0x0192, 0x4131 },
277 { 0x0193, 0x4131 },
278 { 0x0194, 0x0000 },
279 { 0x0195, 0x0000 },
280 { 0x0196, 0x0000 },
281 { 0x0197, 0x0000 },
282 { 0x0198, 0x0000 },
283 { 0x0199, 0x0000 },
284 { 0x01a0, 0x1e64 },
285 { 0x01a1, 0x06a3 },
286 { 0x01a2, 0x0000 },
287 { 0x01a3, 0x0000 },
288 { 0x01a4, 0x0000 },
289 { 0x01a5, 0x0000 },
290 { 0x01a6, 0x0000 },
291 { 0x01a7, 0x0000 },
292 { 0x01a8, 0x0000 },
293 { 0x01a9, 0x0000 },
294 { 0x01aa, 0x0000 },
295 { 0x01ab, 0x0000 },
296 { 0x01b5, 0x0000 },
297 { 0x01b6, 0x01c3 },
298 { 0x01b7, 0x02a0 },
299 { 0x01b8, 0x03e9 },
300 { 0x01b9, 0x1389 },
301 { 0x01ba, 0xc351 },
302 { 0x01bb, 0x0009 },
303 { 0x01bc, 0x0018 },
304 { 0x01bd, 0x002a },
305 { 0x01be, 0x004c },
306 { 0x01bf, 0x0097 },
307 { 0x01c0, 0x433d },
308 { 0x01c1, 0x0000 },
309 { 0x01c2, 0x0000 },
310 { 0x01c3, 0x0000 },
311 { 0x01c4, 0x0000 },
312 { 0x01c5, 0x0000 },
313 { 0x01c6, 0x0000 },
314 { 0x01c7, 0x0000 },
315 { 0x01c8, 0x40af },
316 { 0x01c9, 0x0702 },
317 { 0x01ca, 0x0000 },
318 { 0x01cb, 0x0000 },
319 { 0x01cc, 0x5757 },
320 { 0x01cd, 0x5757 },
321 { 0x01ce, 0x5757 },
322 { 0x01cf, 0x5757 },
323 { 0x01d0, 0x5757 },
324 { 0x01d1, 0x5757 },
325 { 0x01d2, 0x5757 },
326 { 0x01d3, 0x5757 },
327 { 0x01d4, 0x5757 },
328 { 0x01d5, 0x5757 },
329 { 0x01d6, 0x003c },
330 { 0x01da, 0x0000 },
331 { 0x01db, 0x0000 },
332 { 0x01dc, 0x0000 },
333 { 0x01de, 0x7c00 },
334 { 0x01df, 0x0320 },
335 { 0x01e0, 0x06a1 },
336 { 0x01e1, 0x0000 },
337 { 0x01e2, 0x0000 },
338 { 0x01e3, 0x0000 },
339 { 0x01e4, 0x0000 },
340 { 0x01e5, 0x0000 },
341 { 0x01e6, 0x0001 },
342 { 0x01e7, 0x0000 },
343 { 0x01e8, 0x0000 },
344 { 0x01ea, 0x0000 },
345 { 0x01eb, 0x0000 },
346 { 0x01ec, 0x0000 },
347 { 0x01ed, 0x0000 },
348 { 0x01ee, 0x0000 },
349 { 0x01ef, 0x0000 },
350 { 0x01f0, 0x0000 },
351 { 0x01f1, 0x0000 },
352 { 0x01f2, 0x0000 },
353 { 0x01f3, 0x0000 },
354 { 0x01f4, 0x0000 },
355 { 0x0200, 0x0000 },
356 { 0x0201, 0x0000 },
357 { 0x0202, 0x0000 },
358 { 0x0203, 0x0000 },
359 { 0x0204, 0x0000 },
360 { 0x0205, 0x0000 },
361 { 0x0206, 0x0000 },
362 { 0x0207, 0x0000 },
363 { 0x0208, 0x0000 },
364 { 0x0210, 0x60b1 },
365 { 0x0211, 0xa000 },
366 { 0x0212, 0x024c },
367 { 0x0213, 0xf7ff },
368 { 0x0214, 0x024c },
369 { 0x0215, 0x0102 },
370 { 0x0216, 0x00a3 },
371 { 0x0217, 0x0048 },
372 { 0x0218, 0x92c0 },
373 { 0x0219, 0x0000 },
374 { 0x021a, 0x00c8 },
375 { 0x021b, 0x0020 },
376 { 0x02fa, 0x0000 },
377 { 0x02fb, 0x0000 },
378 { 0x02fc, 0x0000 },
379 { 0x02ff, 0x0110 },
380 { 0x0300, 0x001f },
381 { 0x0301, 0x032c },
382 { 0x0302, 0x5f21 },
383 { 0x0303, 0x4000 },
384 { 0x0304, 0x4000 },
385 { 0x0305, 0x06d5 },
386 { 0x0306, 0x8000 },
387 { 0x0307, 0x0700 },
388 { 0x0310, 0x4560 },
389 { 0x0311, 0xa4a8 },
390 { 0x0312, 0x7418 },
391 { 0x0313, 0x0000 },
392 { 0x0314, 0x0006 },
393 { 0x0315, 0xffff },
394 { 0x0316, 0xc400 },
395 { 0x0317, 0x0000 },
396 { 0x0330, 0x00a6 },
397 { 0x0331, 0x04c3 },
398 { 0x0332, 0x27c8 },
399 { 0x0333, 0xbf50 },
400 { 0x0334, 0x0045 },
401 { 0x0335, 0x0007 },
402 { 0x0336, 0x7418 },
403 { 0x0337, 0x0501 },
404 { 0x0338, 0x0000 },
405 { 0x0339, 0x0010 },
406 { 0x033a, 0x1010 },
407 { 0x03c0, 0x7e00 },
408 { 0x03c1, 0x8000 },
409 { 0x03c2, 0x8000 },
410 { 0x03c3, 0x8000 },
411 { 0x03c4, 0x8000 },
412 { 0x03c5, 0x8000 },
413 { 0x03c6, 0x8000 },
414 { 0x03c7, 0x8000 },
415 { 0x03c8, 0x8000 },
416 { 0x03c9, 0x8000 },
417 { 0x03ca, 0x8000 },
418 { 0x03cb, 0x8000 },
419 { 0x03cc, 0x8000 },
420 { 0x03d0, 0x0000 },
421 { 0x03d1, 0x0000 },
422 { 0x03d2, 0x0000 },
423 { 0x03d3, 0x0000 },
424 { 0x03d4, 0x2000 },
425 { 0x03d5, 0x2000 },
426 { 0x03d6, 0x0000 },
427 { 0x03d7, 0x0000 },
428 { 0x03d8, 0x2000 },
429 { 0x03d9, 0x2000 },
430 { 0x03da, 0x2000 },
431 { 0x03db, 0x2000 },
432 { 0x03dc, 0x0000 },
433 { 0x03dd, 0x0000 },
434 { 0x03de, 0x0000 },
435 { 0x03df, 0x2000 },
436 { 0x03e0, 0x0000 },
437 { 0x03e1, 0x0000 },
438 { 0x03e2, 0x0000 },
439 { 0x03e3, 0x0000 },
440 { 0x03e4, 0x0000 },
441 { 0x03e5, 0x0000 },
442 { 0x03e6, 0x0000 },
443 { 0x03e7, 0x0000 },
444 { 0x03e8, 0x0000 },
445 { 0x03e9, 0x0000 },
446 { 0x03ea, 0x0000 },
447 { 0x03eb, 0x0000 },
448 { 0x03ec, 0x0000 },
449 { 0x03ed, 0x0000 },
450 { 0x03ee, 0x0000 },
451 { 0x03ef, 0x0000 },
452 { 0x03f0, 0x0800 },
453 { 0x03f1, 0x0800 },
454 { 0x03f2, 0x0800 },
455 { 0x03f3, 0x0800 },
456 { 0x03fe, 0x0000 },
457 { 0x03ff, 0x0000 },
458 { 0x07f0, 0x0000 },
459 { 0x07fa, 0x0000 },
460};
461
462static const struct reg_default rt5663_reg[] = {
463 { 0x0000, 0x0000 },
464 { 0x0002, 0x0008 },
465 { 0x0005, 0x1000 },
466 { 0x0006, 0x1000 },
467 { 0x000a, 0x0000 },
468 { 0x0010, 0x000f },
469 { 0x0015, 0x42c1 },
470 { 0x0016, 0x0000 },
471 { 0x0018, 0x000b },
472 { 0x0019, 0xafaf },
473 { 0x001c, 0x2f2f },
474 { 0x001f, 0x0000 },
475 { 0x0022, 0x5757 },
476 { 0x0023, 0x0039 },
477 { 0x0026, 0xc0c0 },
478 { 0x0029, 0x8080 },
479 { 0x002a, 0xa0a0 },
480 { 0x002c, 0x000c },
481 { 0x002d, 0x0000 },
482 { 0x0040, 0x0808 },
483 { 0x0061, 0x0000 },
484 { 0x0062, 0x0000 },
485 { 0x0063, 0x003e },
486 { 0x0064, 0x0000 },
487 { 0x0065, 0x0000 },
488 { 0x0066, 0x0000 },
489 { 0x006b, 0x0000 },
490 { 0x006e, 0x0000 },
491 { 0x006f, 0x0000 },
492 { 0x0070, 0x8020 },
493 { 0x0073, 0x1000 },
494 { 0x0074, 0xe400 },
495 { 0x0075, 0x0002 },
496 { 0x0076, 0x0001 },
497 { 0x0077, 0x00f0 },
498 { 0x0078, 0x0000 },
499 { 0x0079, 0x0000 },
500 { 0x007a, 0x0123 },
501 { 0x007b, 0x8003 },
502 { 0x0080, 0x0000 },
503 { 0x0081, 0x0000 },
504 { 0x0082, 0x0000 },
505 { 0x0083, 0x0000 },
506 { 0x0084, 0x0000 },
507 { 0x0086, 0x0008 },
508 { 0x0087, 0x0000 },
509 { 0x008a, 0x0000 },
510 { 0x008b, 0x0000 },
511 { 0x008c, 0x0003 },
512 { 0x008e, 0x0004 },
513 { 0x008f, 0x1000 },
514 { 0x0090, 0x0646 },
515 { 0x0091, 0x0e3e },
516 { 0x0092, 0x1071 },
517 { 0x0093, 0x0000 },
518 { 0x0094, 0x0080 },
519 { 0x0097, 0x0000 },
520 { 0x0098, 0x0000 },
521 { 0x009a, 0x0000 },
522 { 0x009f, 0x0000 },
523 { 0x00ae, 0x2000 },
524 { 0x00af, 0x0000 },
525 { 0x00b6, 0x0000 },
526 { 0x00b7, 0x0000 },
527 { 0x00b8, 0x0000 },
528 { 0x00ba, 0x0000 },
529 { 0x00bb, 0x0000 },
530 { 0x00be, 0x0000 },
531 { 0x00bf, 0x0000 },
532 { 0x00c0, 0x0000 },
533 { 0x00c1, 0x0000 },
534 { 0x00c5, 0x0000 },
535 { 0x00cb, 0xa02f },
536 { 0x00cc, 0x0000 },
537 { 0x00cd, 0x0e02 },
538 { 0x00d9, 0x08f9 },
539 { 0x00db, 0x0008 },
540 { 0x00dc, 0x00c0 },
541 { 0x00dd, 0x6724 },
542 { 0x00de, 0x3131 },
543 { 0x00df, 0x0008 },
544 { 0x00e0, 0x4000 },
545 { 0x00e1, 0x3131 },
546 { 0x00e2, 0x0043 },
547 { 0x00e4, 0x400b },
548 { 0x00e5, 0x8031 },
549 { 0x00e6, 0x3080 },
550 { 0x00e7, 0x4100 },
551 { 0x00e8, 0x1400 },
552 { 0x00e9, 0xe00a },
553 { 0x00ea, 0x0404 },
554 { 0x00eb, 0x0404 },
555 { 0x00ec, 0xb320 },
556 { 0x00ed, 0x0000 },
557 { 0x00f4, 0x0000 },
558 { 0x00f6, 0x0000 },
559 { 0x00f8, 0x0000 },
560 { 0x00fa, 0x8000 },
561 { 0x00fd, 0x0001 },
562 { 0x00fe, 0x10ec },
563 { 0x00ff, 0x6406 },
564 { 0x0100, 0xa0a0 },
565 { 0x0108, 0x4444 },
566 { 0x0109, 0x4444 },
567 { 0x010a, 0xaaaa },
568 { 0x010b, 0x00a0 },
569 { 0x010c, 0x8aaa },
570 { 0x010d, 0xaaaa },
571 { 0x010e, 0x2aaa },
572 { 0x010f, 0x002a },
573 { 0x0110, 0xa0a4 },
574 { 0x0111, 0x4602 },
575 { 0x0112, 0x0101 },
576 { 0x0113, 0x2000 },
577 { 0x0114, 0x0000 },
578 { 0x0116, 0x0000 },
579 { 0x0117, 0x0f00 },
580 { 0x0118, 0x0006 },
581 { 0x0125, 0x2224 },
582 { 0x0126, 0x5550 },
583 { 0x0127, 0x0400 },
584 { 0x0128, 0x7711 },
585 { 0x0132, 0x0004 },
586 { 0x0137, 0x5441 },
587 { 0x0139, 0x79a1 },
588 { 0x013a, 0x30c0 },
589 { 0x013b, 0x2000 },
590 { 0x013c, 0x2005 },
591 { 0x013d, 0x30c0 },
592 { 0x013e, 0x0000 },
593 { 0x0140, 0x3700 },
594 { 0x0141, 0x1f00 },
595 { 0x0144, 0x0000 },
596 { 0x0145, 0x0002 },
597 { 0x0146, 0x0000 },
598 { 0x0160, 0x0e80 },
599 { 0x0161, 0x0020 },
600 { 0x0162, 0x0080 },
601 { 0x0163, 0x0800 },
602 { 0x0164, 0x0000 },
603 { 0x0165, 0x0000 },
604 { 0x0166, 0x0000 },
605 { 0x0167, 0x1417 },
606 { 0x0168, 0x0017 },
607 { 0x0169, 0x0017 },
608 { 0x0180, 0x2000 },
609 { 0x0181, 0x0000 },
610 { 0x0182, 0x0000 },
611 { 0x0183, 0x2000 },
612 { 0x0184, 0x0000 },
613 { 0x0185, 0x0000 },
614 { 0x01b0, 0x4b30 },
615 { 0x01b1, 0x0000 },
616 { 0x01b2, 0xd870 },
617 { 0x01b3, 0x0000 },
618 { 0x01b4, 0x0030 },
619 { 0x01b5, 0x5757 },
620 { 0x01b6, 0x5757 },
621 { 0x01b7, 0x5757 },
622 { 0x01b8, 0x5757 },
623 { 0x01c0, 0x433d },
624 { 0x01c1, 0x0540 },
625 { 0x01c2, 0x0000 },
626 { 0x01c3, 0x0000 },
627 { 0x01c4, 0x0000 },
628 { 0x01c5, 0x0009 },
629 { 0x01c6, 0x0018 },
630 { 0x01c7, 0x002a },
631 { 0x01c8, 0x004c },
632 { 0x01c9, 0x0097 },
633 { 0x01ca, 0x01c3 },
634 { 0x01cb, 0x03e9 },
635 { 0x01cc, 0x1389 },
636 { 0x01cd, 0xc351 },
637 { 0x01ce, 0x0000 },
638 { 0x01cf, 0x0000 },
639 { 0x01d0, 0x0000 },
640 { 0x01d1, 0x0000 },
641 { 0x01d2, 0x0000 },
642 { 0x01d3, 0x003c },
643 { 0x01d4, 0x5757 },
644 { 0x01d5, 0x5757 },
645 { 0x01d6, 0x5757 },
646 { 0x01d7, 0x5757 },
647 { 0x01d8, 0x5757 },
648 { 0x01d9, 0x5757 },
649 { 0x01da, 0x0000 },
650 { 0x01db, 0x0000 },
651 { 0x01dd, 0x0009 },
652 { 0x01de, 0x7f00 },
653 { 0x01df, 0x00c8 },
654 { 0x01e0, 0x0691 },
655 { 0x01e1, 0x0000 },
656 { 0x01e2, 0x0000 },
657 { 0x01e3, 0x0000 },
658 { 0x01e4, 0x0000 },
659 { 0x01e5, 0x0040 },
660 { 0x01e6, 0x0000 },
661 { 0x01e7, 0x0000 },
662 { 0x01e8, 0x0000 },
663 { 0x01ea, 0x0000 },
664 { 0x01eb, 0x0000 },
665 { 0x01ec, 0x0000 },
666 { 0x01ed, 0x0000 },
667 { 0x01ee, 0x0000 },
668 { 0x01ef, 0x0000 },
669 { 0x01f0, 0x0000 },
670 { 0x01f1, 0x0000 },
671 { 0x01f2, 0x0000 },
672 { 0x0200, 0x0000 },
673 { 0x0201, 0x2244 },
674 { 0x0202, 0xaaaa },
675 { 0x0250, 0x8010 },
676 { 0x0251, 0x0000 },
677 { 0x0252, 0x028a },
678 { 0x02fa, 0x0000 },
679 { 0x02fb, 0x0000 },
680 { 0x02fc, 0x0000 },
681 { 0x0300, 0x0000 },
682 { 0x03d0, 0x0000 },
683 { 0x03d1, 0x0000 },
684 { 0x03d2, 0x0000 },
685 { 0x03d3, 0x0000 },
686 { 0x03d4, 0x2000 },
687 { 0x03d5, 0x2000 },
688 { 0x03d6, 0x0000 },
689 { 0x03d7, 0x0000 },
690 { 0x03d8, 0x2000 },
691 { 0x03d9, 0x2000 },
692 { 0x03da, 0x2000 },
693 { 0x03db, 0x2000 },
694 { 0x03dc, 0x0000 },
695 { 0x03dd, 0x0000 },
696 { 0x03de, 0x0000 },
697 { 0x03df, 0x2000 },
698 { 0x03e0, 0x0000 },
699 { 0x03e1, 0x0000 },
700 { 0x03e2, 0x0000 },
701 { 0x03e3, 0x0000 },
702 { 0x03e4, 0x0000 },
703 { 0x03e5, 0x0000 },
704 { 0x03e6, 0x0000 },
705 { 0x03e7, 0x0000 },
706 { 0x03e8, 0x0000 },
707 { 0x03e9, 0x0000 },
708 { 0x03ea, 0x0000 },
709 { 0x03eb, 0x0000 },
710 { 0x03ec, 0x0000 },
711 { 0x03ed, 0x0000 },
712 { 0x03ee, 0x0000 },
713 { 0x03ef, 0x0000 },
714 { 0x03f0, 0x0800 },
715 { 0x03f1, 0x0800 },
716 { 0x03f2, 0x0800 },
717 { 0x03f3, 0x0800 },
718};
719
720static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
721{
722 switch (reg) {
723 case RT5663_RESET:
724 case RT5663_SIL_DET_CTL:
725 case RT5663_HP_IMP_GAIN_2:
726 case RT5663_AD_DA_MIXER:
727 case RT5663_FRAC_DIV_2:
728 case RT5663_MICBIAS_1:
729 case RT5663_ASRC_11_2:
730 case RT5663_ADC_EQ_1:
731 case RT5663_INT_ST_1:
732 case RT5663_INT_ST_2:
733 case RT5663_GPIO_STA:
734 case RT5663_SIN_GEN_1:
735 case RT5663_IL_CMD_1:
736 case RT5663_IL_CMD_5:
737 case RT5663_IL_CMD_PWRSAV1:
738 case RT5663_EM_JACK_TYPE_1:
739 case RT5663_EM_JACK_TYPE_2:
740 case RT5663_EM_JACK_TYPE_3:
741 case RT5663_JD_CTRL2:
742 case RT5663_VENDOR_ID:
743 case RT5663_VENDOR_ID_1:
744 case RT5663_VENDOR_ID_2:
745 case RT5663_PLL_INT_REG:
746 case RT5663_SOFT_RAMP:
747 case RT5663_STO_DRE_1:
748 case RT5663_STO_DRE_5:
749 case RT5663_STO_DRE_6:
750 case RT5663_STO_DRE_7:
751 case RT5663_MIC_DECRO_1:
752 case RT5663_MIC_DECRO_4:
753 case RT5663_HP_IMP_SEN_1:
754 case RT5663_HP_IMP_SEN_3:
755 case RT5663_HP_IMP_SEN_4:
756 case RT5663_HP_IMP_SEN_5:
757 case RT5663_HP_CALIB_1_1:
758 case RT5663_HP_CALIB_9:
759 case RT5663_HP_CALIB_ST1:
760 case RT5663_HP_CALIB_ST2:
761 case RT5663_HP_CALIB_ST3:
762 case RT5663_HP_CALIB_ST4:
763 case RT5663_HP_CALIB_ST5:
764 case RT5663_HP_CALIB_ST6:
765 case RT5663_HP_CALIB_ST7:
766 case RT5663_HP_CALIB_ST8:
767 case RT5663_HP_CALIB_ST9:
768 case RT5663_ANA_JD:
769 return true;
770 default:
771 return false;
772 }
773}
774
775static bool rt5663_readable_register(struct device *dev, unsigned int reg)
776{
777 switch (reg) {
778 case RT5663_RESET:
779 case RT5663_HP_OUT_EN:
780 case RT5663_HP_LCH_DRE:
781 case RT5663_HP_RCH_DRE:
782 case RT5663_CALIB_BST:
783 case RT5663_RECMIX:
784 case RT5663_SIL_DET_CTL:
785 case RT5663_PWR_SAV_SILDET:
786 case RT5663_SIDETONE_CTL:
787 case RT5663_STO1_DAC_DIG_VOL:
788 case RT5663_STO1_ADC_DIG_VOL:
789 case RT5663_STO1_BOOST:
790 case RT5663_HP_IMP_GAIN_1:
791 case RT5663_HP_IMP_GAIN_2:
792 case RT5663_STO1_ADC_MIXER:
793 case RT5663_AD_DA_MIXER:
794 case RT5663_STO_DAC_MIXER:
795 case RT5663_DIG_SIDE_MIXER:
796 case RT5663_BYPASS_STO_DAC:
797 case RT5663_CALIB_REC_MIX:
798 case RT5663_PWR_DIG_1:
799 case RT5663_PWR_DIG_2:
800 case RT5663_PWR_ANLG_1:
801 case RT5663_PWR_ANLG_2:
802 case RT5663_PWR_ANLG_3:
803 case RT5663_PWR_MIXER:
804 case RT5663_SIG_CLK_DET:
805 case RT5663_PRE_DIV_GATING_1:
806 case RT5663_PRE_DIV_GATING_2:
807 case RT5663_I2S1_SDP:
808 case RT5663_ADDA_CLK_1:
809 case RT5663_ADDA_RST:
810 case RT5663_FRAC_DIV_1:
811 case RT5663_FRAC_DIV_2:
812 case RT5663_TDM_1:
813 case RT5663_TDM_2:
814 case RT5663_TDM_3:
815 case RT5663_TDM_4:
816 case RT5663_TDM_5:
817 case RT5663_GLB_CLK:
818 case RT5663_PLL_1:
819 case RT5663_PLL_2:
820 case RT5663_ASRC_1:
821 case RT5663_ASRC_2:
822 case RT5663_ASRC_4:
823 case RT5663_DUMMY_REG:
824 case RT5663_ASRC_8:
825 case RT5663_ASRC_9:
826 case RT5663_ASRC_11:
827 case RT5663_DEPOP_1:
828 case RT5663_DEPOP_2:
829 case RT5663_DEPOP_3:
830 case RT5663_HP_CHARGE_PUMP_1:
831 case RT5663_HP_CHARGE_PUMP_2:
832 case RT5663_MICBIAS_1:
833 case RT5663_RC_CLK:
834 case RT5663_ASRC_11_2:
835 case RT5663_DUMMY_REG_2:
836 case RT5663_REC_PATH_GAIN:
837 case RT5663_AUTO_1MRC_CLK:
838 case RT5663_ADC_EQ_1:
839 case RT5663_ADC_EQ_2:
840 case RT5663_IRQ_1:
841 case RT5663_IRQ_2:
842 case RT5663_IRQ_3:
843 case RT5663_IRQ_4:
844 case RT5663_IRQ_5:
845 case RT5663_INT_ST_1:
846 case RT5663_INT_ST_2:
847 case RT5663_GPIO_1:
848 case RT5663_GPIO_2:
849 case RT5663_GPIO_STA:
850 case RT5663_SIN_GEN_1:
851 case RT5663_SIN_GEN_2:
852 case RT5663_SIN_GEN_3:
853 case RT5663_SOF_VOL_ZC1:
854 case RT5663_IL_CMD_1:
855 case RT5663_IL_CMD_2:
856 case RT5663_IL_CMD_3:
857 case RT5663_IL_CMD_4:
858 case RT5663_IL_CMD_5:
859 case RT5663_IL_CMD_6:
860 case RT5663_IL_CMD_7:
861 case RT5663_IL_CMD_8:
862 case RT5663_IL_CMD_PWRSAV1:
863 case RT5663_IL_CMD_PWRSAV2:
864 case RT5663_EM_JACK_TYPE_1:
865 case RT5663_EM_JACK_TYPE_2:
866 case RT5663_EM_JACK_TYPE_3:
867 case RT5663_EM_JACK_TYPE_4:
868 case RT5663_EM_JACK_TYPE_5:
869 case RT5663_EM_JACK_TYPE_6:
870 case RT5663_STO1_HPF_ADJ1:
871 case RT5663_STO1_HPF_ADJ2:
872 case RT5663_FAST_OFF_MICBIAS:
873 case RT5663_JD_CTRL1:
874 case RT5663_JD_CTRL2:
875 case RT5663_DIG_MISC:
876 case RT5663_VENDOR_ID:
877 case RT5663_VENDOR_ID_1:
878 case RT5663_VENDOR_ID_2:
879 case RT5663_DIG_VOL_ZCD:
880 case RT5663_ANA_BIAS_CUR_1:
881 case RT5663_ANA_BIAS_CUR_2:
882 case RT5663_ANA_BIAS_CUR_3:
883 case RT5663_ANA_BIAS_CUR_4:
884 case RT5663_ANA_BIAS_CUR_5:
885 case RT5663_ANA_BIAS_CUR_6:
886 case RT5663_BIAS_CUR_5:
887 case RT5663_BIAS_CUR_6:
888 case RT5663_BIAS_CUR_7:
889 case RT5663_BIAS_CUR_8:
890 case RT5663_DACREF_LDO:
891 case RT5663_DUMMY_REG_3:
892 case RT5663_BIAS_CUR_9:
893 case RT5663_DUMMY_REG_4:
894 case RT5663_VREFADJ_OP:
895 case RT5663_VREF_RECMIX:
896 case RT5663_CHARGE_PUMP_1:
897 case RT5663_CHARGE_PUMP_1_2:
898 case RT5663_CHARGE_PUMP_1_3:
899 case RT5663_CHARGE_PUMP_2:
900 case RT5663_DIG_IN_PIN1:
901 case RT5663_PAD_DRV_CTL:
902 case RT5663_PLL_INT_REG:
903 case RT5663_CHOP_DAC_L:
904 case RT5663_CHOP_ADC:
905 case RT5663_CALIB_ADC:
906 case RT5663_CHOP_DAC_R:
907 case RT5663_DUMMY_CTL_DACLR:
908 case RT5663_DUMMY_REG_5:
909 case RT5663_SOFT_RAMP:
910 case RT5663_TEST_MODE_1:
911 case RT5663_TEST_MODE_2:
912 case RT5663_TEST_MODE_3:
913 case RT5663_STO_DRE_1:
914 case RT5663_STO_DRE_2:
915 case RT5663_STO_DRE_3:
916 case RT5663_STO_DRE_4:
917 case RT5663_STO_DRE_5:
918 case RT5663_STO_DRE_6:
919 case RT5663_STO_DRE_7:
920 case RT5663_STO_DRE_8:
921 case RT5663_STO_DRE_9:
922 case RT5663_STO_DRE_10:
923 case RT5663_MIC_DECRO_1:
924 case RT5663_MIC_DECRO_2:
925 case RT5663_MIC_DECRO_3:
926 case RT5663_MIC_DECRO_4:
927 case RT5663_MIC_DECRO_5:
928 case RT5663_MIC_DECRO_6:
929 case RT5663_HP_DECRO_1:
930 case RT5663_HP_DECRO_2:
931 case RT5663_HP_DECRO_3:
932 case RT5663_HP_DECRO_4:
933 case RT5663_HP_DECOUP:
934 case RT5663_HP_IMP_SEN_MAP8:
935 case RT5663_HP_IMP_SEN_MAP9:
936 case RT5663_HP_IMP_SEN_MAP10:
937 case RT5663_HP_IMP_SEN_MAP11:
938 case RT5663_HP_IMP_SEN_1:
939 case RT5663_HP_IMP_SEN_2:
940 case RT5663_HP_IMP_SEN_3:
941 case RT5663_HP_IMP_SEN_4:
942 case RT5663_HP_IMP_SEN_5:
943 case RT5663_HP_IMP_SEN_6:
944 case RT5663_HP_IMP_SEN_7:
945 case RT5663_HP_IMP_SEN_8:
946 case RT5663_HP_IMP_SEN_9:
947 case RT5663_HP_IMP_SEN_10:
948 case RT5663_HP_IMP_SEN_11:
949 case RT5663_HP_IMP_SEN_12:
950 case RT5663_HP_IMP_SEN_13:
951 case RT5663_HP_IMP_SEN_14:
952 case RT5663_HP_IMP_SEN_15:
953 case RT5663_HP_IMP_SEN_16:
954 case RT5663_HP_IMP_SEN_17:
955 case RT5663_HP_IMP_SEN_18:
956 case RT5663_HP_IMP_SEN_19:
957 case RT5663_HP_IMPSEN_DIG5:
958 case RT5663_HP_IMPSEN_MAP1:
959 case RT5663_HP_IMPSEN_MAP2:
960 case RT5663_HP_IMPSEN_MAP3:
961 case RT5663_HP_IMPSEN_MAP4:
962 case RT5663_HP_IMPSEN_MAP5:
963 case RT5663_HP_IMPSEN_MAP7:
964 case RT5663_HP_LOGIC_1:
965 case RT5663_HP_LOGIC_2:
966 case RT5663_HP_CALIB_1:
967 case RT5663_HP_CALIB_1_1:
968 case RT5663_HP_CALIB_2:
969 case RT5663_HP_CALIB_3:
970 case RT5663_HP_CALIB_4:
971 case RT5663_HP_CALIB_5:
972 case RT5663_HP_CALIB_5_1:
973 case RT5663_HP_CALIB_6:
974 case RT5663_HP_CALIB_7:
975 case RT5663_HP_CALIB_9:
976 case RT5663_HP_CALIB_10:
977 case RT5663_HP_CALIB_11:
978 case RT5663_HP_CALIB_ST1:
979 case RT5663_HP_CALIB_ST2:
980 case RT5663_HP_CALIB_ST3:
981 case RT5663_HP_CALIB_ST4:
982 case RT5663_HP_CALIB_ST5:
983 case RT5663_HP_CALIB_ST6:
984 case RT5663_HP_CALIB_ST7:
985 case RT5663_HP_CALIB_ST8:
986 case RT5663_HP_CALIB_ST9:
987 case RT5663_HP_AMP_DET:
988 case RT5663_DUMMY_REG_6:
989 case RT5663_HP_BIAS:
990 case RT5663_CBJ_1:
991 case RT5663_CBJ_2:
992 case RT5663_CBJ_3:
993 case RT5663_DUMMY_1:
994 case RT5663_DUMMY_2:
995 case RT5663_DUMMY_3:
996 case RT5663_ANA_JD:
997 case RT5663_ADC_LCH_LPF1_A1:
998 case RT5663_ADC_RCH_LPF1_A1:
999 case RT5663_ADC_LCH_LPF1_H0:
1000 case RT5663_ADC_RCH_LPF1_H0:
1001 case RT5663_ADC_LCH_BPF1_A1:
1002 case RT5663_ADC_RCH_BPF1_A1:
1003 case RT5663_ADC_LCH_BPF1_A2:
1004 case RT5663_ADC_RCH_BPF1_A2:
1005 case RT5663_ADC_LCH_BPF1_H0:
1006 case RT5663_ADC_RCH_BPF1_H0:
1007 case RT5663_ADC_LCH_BPF2_A1:
1008 case RT5663_ADC_RCH_BPF2_A1:
1009 case RT5663_ADC_LCH_BPF2_A2:
1010 case RT5663_ADC_RCH_BPF2_A2:
1011 case RT5663_ADC_LCH_BPF2_H0:
1012 case RT5663_ADC_RCH_BPF2_H0:
1013 case RT5663_ADC_LCH_BPF3_A1:
1014 case RT5663_ADC_RCH_BPF3_A1:
1015 case RT5663_ADC_LCH_BPF3_A2:
1016 case RT5663_ADC_RCH_BPF3_A2:
1017 case RT5663_ADC_LCH_BPF3_H0:
1018 case RT5663_ADC_RCH_BPF3_H0:
1019 case RT5663_ADC_LCH_BPF4_A1:
1020 case RT5663_ADC_RCH_BPF4_A1:
1021 case RT5663_ADC_LCH_BPF4_A2:
1022 case RT5663_ADC_RCH_BPF4_A2:
1023 case RT5663_ADC_LCH_BPF4_H0:
1024 case RT5663_ADC_RCH_BPF4_H0:
1025 case RT5663_ADC_LCH_HPF1_A1:
1026 case RT5663_ADC_RCH_HPF1_A1:
1027 case RT5663_ADC_LCH_HPF1_H0:
1028 case RT5663_ADC_RCH_HPF1_H0:
1029 case RT5663_ADC_EQ_PRE_VOL_L:
1030 case RT5663_ADC_EQ_PRE_VOL_R:
1031 case RT5663_ADC_EQ_POST_VOL_L:
1032 case RT5663_ADC_EQ_POST_VOL_R:
1033 return true;
1034 default:
1035 return false;
1036 }
1037}
1038
1039static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
1040{
1041 switch (reg) {
1042 case RT5663_RESET:
1043 case RT5668_CBJ_TYPE_2:
1044 case RT5668_PDM_OUT_CTL:
1045 case RT5668_PDM_I2C_DATA_CTL1:
1046 case RT5668_PDM_I2C_DATA_CTL4:
1047 case RT5668_ALC_BK_GAIN:
1048 case RT5663_PLL_2:
1049 case RT5663_MICBIAS_1:
1050 case RT5663_ADC_EQ_1:
1051 case RT5663_INT_ST_1:
1052 case RT5668_GPIO_STA:
1053 case RT5663_IL_CMD_1:
1054 case RT5663_IL_CMD_5:
1055 case RT5668_A_JD_CTRL:
1056 case RT5663_JD_CTRL2:
1057 case RT5663_VENDOR_ID:
1058 case RT5663_VENDOR_ID_1:
1059 case RT5663_VENDOR_ID_2:
1060 case RT5663_STO_DRE_1:
1061 case RT5663_STO_DRE_5:
1062 case RT5663_STO_DRE_6:
1063 case RT5663_STO_DRE_7:
1064 case RT5668_MONO_DYNA_6:
1065 case RT5668_STO1_SIL_DET:
1066 case RT5668_MONOL_SIL_DET:
1067 case RT5668_MONOR_SIL_DET:
1068 case RT5668_STO2_DAC_SIL:
1069 case RT5668_MONO_AMP_CAL_ST1:
1070 case RT5668_MONO_AMP_CAL_ST2:
1071 case RT5668_MONO_AMP_CAL_ST3:
1072 case RT5668_MONO_AMP_CAL_ST4:
1073 case RT5663_HP_IMP_SEN_2:
1074 case RT5663_HP_IMP_SEN_3:
1075 case RT5663_HP_IMP_SEN_4:
1076 case RT5663_HP_IMP_SEN_10:
1077 case RT5663_HP_CALIB_1:
1078 case RT5663_HP_CALIB_10:
1079 case RT5663_HP_CALIB_ST1:
1080 case RT5663_HP_CALIB_ST4:
1081 case RT5663_HP_CALIB_ST5:
1082 case RT5663_HP_CALIB_ST6:
1083 case RT5663_HP_CALIB_ST7:
1084 case RT5663_HP_CALIB_ST8:
1085 case RT5663_HP_CALIB_ST9:
1086 case RT5668_HP_CALIB_ST10:
1087 case RT5668_HP_CALIB_ST11:
1088 return true;
1089 default:
1090 return false;
1091 }
1092}
1093
1094static bool rt5668_readable_register(struct device *dev, unsigned int reg)
1095{
1096 switch (reg) {
1097 case RT5668_LOUT_CTRL:
1098 case RT5668_HP_AMP_2:
1099 case RT5668_MONO_OUT:
1100 case RT5668_MONO_GAIN:
1101 case RT5668_AEC_BST:
1102 case RT5668_IN1_IN2:
1103 case RT5668_IN3_IN4:
1104 case RT5668_INL1_INR1:
1105 case RT5668_CBJ_TYPE_2:
1106 case RT5668_CBJ_TYPE_3:
1107 case RT5668_CBJ_TYPE_4:
1108 case RT5668_CBJ_TYPE_5:
1109 case RT5668_CBJ_TYPE_8:
1110 case RT5668_DAC3_DIG_VOL:
1111 case RT5668_DAC3_CTRL:
1112 case RT5668_MONO_ADC_DIG_VOL:
1113 case RT5668_STO2_ADC_DIG_VOL:
1114 case RT5668_MONO_ADC_BST_GAIN:
1115 case RT5668_STO2_ADC_BST_GAIN:
1116 case RT5668_SIDETONE_CTRL:
1117 case RT5668_MONO1_ADC_MIXER:
1118 case RT5668_STO2_ADC_MIXER:
1119 case RT5668_MONO_DAC_MIXER:
1120 case RT5668_DAC2_SRC_CTRL:
1121 case RT5668_IF_3_4_DATA_CTL:
1122 case RT5668_IF_5_DATA_CTL:
1123 case RT5668_PDM_OUT_CTL:
1124 case RT5668_PDM_I2C_DATA_CTL1:
1125 case RT5668_PDM_I2C_DATA_CTL2:
1126 case RT5668_PDM_I2C_DATA_CTL3:
1127 case RT5668_PDM_I2C_DATA_CTL4:
1128 case RT5668_RECMIX1_NEW:
1129 case RT5668_RECMIX1L_0:
1130 case RT5668_RECMIX1L:
1131 case RT5668_RECMIX1R_0:
1132 case RT5668_RECMIX1R:
1133 case RT5668_RECMIX2_NEW:
1134 case RT5668_RECMIX2_L_2:
1135 case RT5668_RECMIX2_R:
1136 case RT5668_RECMIX2_R_2:
1137 case RT5668_CALIB_REC_LR:
1138 case RT5668_ALC_BK_GAIN:
1139 case RT5668_MONOMIX_GAIN:
1140 case RT5668_MONOMIX_IN_GAIN:
1141 case RT5668_OUT_MIXL_GAIN:
1142 case RT5668_OUT_LMIX_IN_GAIN:
1143 case RT5668_OUT_RMIX_IN_GAIN:
1144 case RT5668_OUT_RMIX_IN_GAIN1:
1145 case RT5668_LOUT_MIXER_CTRL:
1146 case RT5668_PWR_VOL:
1147 case RT5668_ADCDAC_RST:
1148 case RT5668_I2S34_SDP:
1149 case RT5668_I2S5_SDP:
1150 case RT5668_TDM_5:
1151 case RT5668_TDM_6:
1152 case RT5668_TDM_7:
1153 case RT5668_TDM_8:
1154 case RT5668_ASRC_3:
1155 case RT5668_ASRC_6:
1156 case RT5668_ASRC_7:
1157 case RT5668_PLL_TRK_13:
1158 case RT5668_I2S_M_CLK_CTL:
1159 case RT5668_FDIV_I2S34_M_CLK:
1160 case RT5668_FDIV_I2S34_M_CLK2:
1161 case RT5668_FDIV_I2S5_M_CLK:
1162 case RT5668_FDIV_I2S5_M_CLK2:
1163 case RT5668_IRQ_4:
1164 case RT5668_GPIO_3:
1165 case RT5668_GPIO_4:
1166 case RT5668_GPIO_STA:
1167 case RT5668_HP_AMP_DET1:
1168 case RT5668_HP_AMP_DET2:
1169 case RT5668_HP_AMP_DET3:
1170 case RT5668_MID_BD_HP_AMP:
1171 case RT5668_LOW_BD_HP_AMP:
1172 case RT5668_SOF_VOL_ZC2:
1173 case RT5668_ADC_STO2_ADJ1:
1174 case RT5668_ADC_STO2_ADJ2:
1175 case RT5668_A_JD_CTRL:
1176 case RT5668_JD1_TRES_CTRL:
1177 case RT5668_JD2_TRES_CTRL:
1178 case RT5668_JD_CTRL2:
1179 case RT5668_DUM_REG_2:
1180 case RT5668_DUM_REG_3:
1181 case RT5663_VENDOR_ID:
1182 case RT5663_VENDOR_ID_1:
1183 case RT5663_VENDOR_ID_2:
1184 case RT5668_DACADC_DIG_VOL2:
1185 case RT5668_DIG_IN_PIN2:
1186 case RT5668_PAD_DRV_CTL1:
1187 case RT5668_SOF_RAM_DEPOP:
1188 case RT5668_VOL_TEST:
1189 case RT5668_TEST_MODE_3:
1190 case RT5668_TEST_MODE_4:
1191 case RT5663_STO_DRE_9:
1192 case RT5668_MONO_DYNA_1:
1193 case RT5668_MONO_DYNA_2:
1194 case RT5668_MONO_DYNA_3:
1195 case RT5668_MONO_DYNA_4:
1196 case RT5668_MONO_DYNA_5:
1197 case RT5668_MONO_DYNA_6:
1198 case RT5668_STO1_SIL_DET:
1199 case RT5668_MONOL_SIL_DET:
1200 case RT5668_MONOR_SIL_DET:
1201 case RT5668_STO2_DAC_SIL:
1202 case RT5668_PWR_SAV_CTL1:
1203 case RT5668_PWR_SAV_CTL2:
1204 case RT5668_PWR_SAV_CTL3:
1205 case RT5668_PWR_SAV_CTL4:
1206 case RT5668_PWR_SAV_CTL5:
1207 case RT5668_PWR_SAV_CTL6:
1208 case RT5668_MONO_AMP_CAL1:
1209 case RT5668_MONO_AMP_CAL2:
1210 case RT5668_MONO_AMP_CAL3:
1211 case RT5668_MONO_AMP_CAL4:
1212 case RT5668_MONO_AMP_CAL5:
1213 case RT5668_MONO_AMP_CAL6:
1214 case RT5668_MONO_AMP_CAL7:
1215 case RT5668_MONO_AMP_CAL_ST1:
1216 case RT5668_MONO_AMP_CAL_ST2:
1217 case RT5668_MONO_AMP_CAL_ST3:
1218 case RT5668_MONO_AMP_CAL_ST4:
1219 case RT5668_MONO_AMP_CAL_ST5:
1220 case RT5668_HP_IMP_SEN_13:
1221 case RT5668_HP_IMP_SEN_14:
1222 case RT5668_HP_IMP_SEN_6:
1223 case RT5668_HP_IMP_SEN_7:
1224 case RT5668_HP_IMP_SEN_8:
1225 case RT5668_HP_IMP_SEN_9:
1226 case RT5668_HP_IMP_SEN_10:
1227 case RT5668_HP_LOGIC_3:
1228 case RT5668_HP_CALIB_ST10:
1229 case RT5668_HP_CALIB_ST11:
1230 case RT5668_PRO_REG_TBL_4:
1231 case RT5668_PRO_REG_TBL_5:
1232 case RT5668_PRO_REG_TBL_6:
1233 case RT5668_PRO_REG_TBL_7:
1234 case RT5668_PRO_REG_TBL_8:
1235 case RT5668_PRO_REG_TBL_9:
1236 case RT5668_SAR_ADC_INL_1:
1237 case RT5668_SAR_ADC_INL_2:
1238 case RT5668_SAR_ADC_INL_3:
1239 case RT5668_SAR_ADC_INL_4:
1240 case RT5668_SAR_ADC_INL_5:
1241 case RT5668_SAR_ADC_INL_6:
1242 case RT5668_SAR_ADC_INL_7:
1243 case RT5668_SAR_ADC_INL_8:
1244 case RT5668_SAR_ADC_INL_9:
1245 case RT5668_SAR_ADC_INL_10:
1246 case RT5668_SAR_ADC_INL_11:
1247 case RT5668_SAR_ADC_INL_12:
1248 case RT5668_DRC_CTRL_1:
1249 case RT5668_DRC1_CTRL_2:
1250 case RT5668_DRC1_CTRL_3:
1251 case RT5668_DRC1_CTRL_4:
1252 case RT5668_DRC1_CTRL_5:
1253 case RT5668_DRC1_CTRL_6:
1254 case RT5668_DRC1_HD_CTRL_1:
1255 case RT5668_DRC1_HD_CTRL_2:
1256 case RT5668_DRC1_PRI_REG_1:
1257 case RT5668_DRC1_PRI_REG_2:
1258 case RT5668_DRC1_PRI_REG_3:
1259 case RT5668_DRC1_PRI_REG_4:
1260 case RT5668_DRC1_PRI_REG_5:
1261 case RT5668_DRC1_PRI_REG_6:
1262 case RT5668_DRC1_PRI_REG_7:
1263 case RT5668_DRC1_PRI_REG_8:
1264 case RT5668_ALC_PGA_CTL_1:
1265 case RT5668_ALC_PGA_CTL_2:
1266 case RT5668_ALC_PGA_CTL_3:
1267 case RT5668_ALC_PGA_CTL_4:
1268 case RT5668_ALC_PGA_CTL_5:
1269 case RT5668_ALC_PGA_CTL_6:
1270 case RT5668_ALC_PGA_CTL_7:
1271 case RT5668_ALC_PGA_CTL_8:
1272 case RT5668_ALC_PGA_REG_1:
1273 case RT5668_ALC_PGA_REG_2:
1274 case RT5668_ALC_PGA_REG_3:
1275 case RT5668_ADC_EQ_RECOV_1:
1276 case RT5668_ADC_EQ_RECOV_2:
1277 case RT5668_ADC_EQ_RECOV_3:
1278 case RT5668_ADC_EQ_RECOV_4:
1279 case RT5668_ADC_EQ_RECOV_5:
1280 case RT5668_ADC_EQ_RECOV_6:
1281 case RT5668_ADC_EQ_RECOV_7:
1282 case RT5668_ADC_EQ_RECOV_8:
1283 case RT5668_ADC_EQ_RECOV_9:
1284 case RT5668_ADC_EQ_RECOV_10:
1285 case RT5668_ADC_EQ_RECOV_11:
1286 case RT5668_ADC_EQ_RECOV_12:
1287 case RT5668_ADC_EQ_RECOV_13:
1288 case RT5668_VID_HIDDEN:
1289 case RT5668_VID_CUSTOMER:
1290 case RT5668_SCAN_MODE:
1291 case RT5668_I2C_BYPA:
1292 return true;
1293 case RT5663_TDM_1:
1294 case RT5663_DEPOP_3:
1295 case RT5663_ASRC_11_2:
1296 case RT5663_INT_ST_2:
1297 case RT5663_GPIO_STA:
1298 case RT5663_SIN_GEN_1:
1299 case RT5663_SIN_GEN_2:
1300 case RT5663_SIN_GEN_3:
1301 case RT5663_IL_CMD_PWRSAV1:
1302 case RT5663_IL_CMD_PWRSAV2:
1303 case RT5663_EM_JACK_TYPE_1:
1304 case RT5663_EM_JACK_TYPE_2:
1305 case RT5663_EM_JACK_TYPE_3:
1306 case RT5663_EM_JACK_TYPE_4:
1307 case RT5663_FAST_OFF_MICBIAS:
1308 case RT5663_ANA_BIAS_CUR_1:
1309 case RT5663_ANA_BIAS_CUR_2:
1310 case RT5663_BIAS_CUR_9:
1311 case RT5663_DUMMY_REG_4:
1312 case RT5663_VREF_RECMIX:
1313 case RT5663_CHARGE_PUMP_1_2:
1314 case RT5663_CHARGE_PUMP_1_3:
1315 case RT5663_CHARGE_PUMP_2:
1316 case RT5663_CHOP_DAC_R:
1317 case RT5663_DUMMY_CTL_DACLR:
1318 case RT5663_DUMMY_REG_5:
1319 case RT5663_SOFT_RAMP:
1320 case RT5663_TEST_MODE_1:
1321 case RT5663_STO_DRE_10:
1322 case RT5663_MIC_DECRO_1:
1323 case RT5663_MIC_DECRO_2:
1324 case RT5663_MIC_DECRO_3:
1325 case RT5663_MIC_DECRO_4:
1326 case RT5663_MIC_DECRO_5:
1327 case RT5663_MIC_DECRO_6:
1328 case RT5663_HP_DECRO_1:
1329 case RT5663_HP_DECRO_2:
1330 case RT5663_HP_DECRO_3:
1331 case RT5663_HP_DECRO_4:
1332 case RT5663_HP_DECOUP:
1333 case RT5663_HP_IMPSEN_MAP4:
1334 case RT5663_HP_IMPSEN_MAP5:
1335 case RT5663_HP_IMPSEN_MAP7:
1336 case RT5663_HP_CALIB_1:
1337 case RT5663_CBJ_1:
1338 case RT5663_CBJ_2:
1339 case RT5663_CBJ_3:
1340 return false;
1341 default:
1342 return rt5663_readable_register(dev, reg);
1343 }
1344}
1345
1346static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1347static const DECLARE_TLV_DB_SCALE(rt5668_hp_vol_tlv, -2250, 150, 0);
1348static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1349static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1350
1351/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1352static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1353 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1354 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1355 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1356 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1357 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1358 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1359 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1360);
1361
1362/* Interface data select */
1363static const char * const rt5663_if1_adc_data_select[] = {
1364 "L/R", "R/L", "L/L", "R/R"
1365};
1366
1367static const SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1368 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1369
1370static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1371 bool enable)
1372{
1373 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1374
1375 if (enable) {
1376 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1377 RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_EN);
1378 /* reset in-line command */
1379 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1380 RT5668_RESET_4BTN_INL_MASK,
1381 RT5668_RESET_4BTN_INL_RESET);
1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1383 RT5668_RESET_4BTN_INL_MASK,
1384 RT5668_RESET_4BTN_INL_NOR);
1385 switch (rt5663->codec_type) {
1386 case CODEC_TYPE_RT5668:
1387 snd_soc_update_bits(codec, RT5663_IRQ_3,
1388 RT5668_EN_IRQ_INLINE_MASK,
1389 RT5668_EN_IRQ_INLINE_NOR);
1390 break;
1391 case CODEC_TYPE_RT5663:
1392 snd_soc_update_bits(codec, RT5663_IRQ_2,
1393 RT5663_EN_IRQ_INLINE_MASK,
1394 RT5663_EN_IRQ_INLINE_NOR);
1395 break;
1396 default:
1397 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1398 }
1399 } else {
1400 switch (rt5663->codec_type) {
1401 case CODEC_TYPE_RT5668:
1402 snd_soc_update_bits(codec, RT5663_IRQ_3,
1403 RT5668_EN_IRQ_INLINE_MASK,
1404 RT5668_EN_IRQ_INLINE_BYP);
1405 break;
1406 case CODEC_TYPE_RT5663:
1407 snd_soc_update_bits(codec, RT5663_IRQ_2,
1408 RT5663_EN_IRQ_INLINE_MASK,
1409 RT5663_EN_IRQ_INLINE_BYP);
1410 break;
1411 default:
1412 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1413 }
1414 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1415 RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_DIS);
1416 /* reset in-line command */
1417 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1418 RT5668_RESET_4BTN_INL_MASK,
1419 RT5668_RESET_4BTN_INL_RESET);
1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1421 RT5668_RESET_4BTN_INL_MASK,
1422 RT5668_RESET_4BTN_INL_NOR);
1423 }
1424}
1425
1426/**
1427 * rt5668_jack_detect - Detect headset.
1428 * @codec: SoC audio codec device.
1429 * @jack_insert: Jack insert or not.
1430 *
1431 * Detect whether is headset or not when jack inserted.
1432 *
1433 * Returns detect status.
1434 */
1435
1436static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1437{
1438 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1439 struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
1440 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1441
1442 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1443 if (jack_insert) {
1444 snd_soc_write(codec, RT5668_CBJ_TYPE_2, 0x8040);
1445 snd_soc_write(codec, RT5668_CBJ_TYPE_3, 0x1484);
1446
1447 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1448 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1449 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1450 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1451 snd_soc_dapm_sync(dapm);
1452 snd_soc_update_bits(codec, RT5663_RC_CLK,
1453 RT5668_DIG_1M_CLK_MASK, RT5668_DIG_1M_CLK_EN);
1454 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1455
1456 while (i < 5) {
1457 msleep(sleep_time[i]);
1458 val = snd_soc_read(codec, RT5668_CBJ_TYPE_2) & 0x0003;
1459 if (val == 0x1 || val == 0x2 || val == 0x3)
1460 break;
1461 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1462 __func__, val, sleep_time[i]);
1463 i++;
1464 }
1465 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1466 switch (val) {
1467 case 1:
1468 case 2:
1469 rt5668->jack_type = SND_JACK_HEADSET;
1470 rt5663_enable_push_button_irq(codec, true);
1471 break;
1472 default:
1473 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1474 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1475 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1476 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1477 snd_soc_dapm_sync(dapm);
1478 rt5668->jack_type = SND_JACK_HEADPHONE;
1479 break;
1480 }
1481 } else {
1482 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1483
1484 if (rt5668->jack_type == SND_JACK_HEADSET) {
1485 rt5663_enable_push_button_irq(codec, false);
1486 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1487 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1488 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1489 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1490 snd_soc_dapm_sync(dapm);
1491 }
1492 rt5668->jack_type = 0;
1493 }
1494
1495 dev_dbg(codec->dev, "jack_type = %d\n", rt5668->jack_type);
1496 return rt5668->jack_type;
1497}
1498
1499/**
1500 * rt5663_jack_detect - Detect headset.
1501 * @codec: SoC audio codec device.
1502 * @jack_insert: Jack insert or not.
1503 *
1504 * Detect whether is headset or not when jack inserted.
1505 *
1506 * Returns detect status.
1507 */
1508static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1509{
1510 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1511 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1512
1513 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1514
1515 if (jack_insert) {
1516 snd_soc_update_bits(codec, RT5663_DIG_MISC,
1517 RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN);
1518 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1519 RT5663_SI_HP_MASK | RT5668_OSW_HP_L_MASK |
1520 RT5668_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1521 RT5668_OSW_HP_L_DIS | RT5668_OSW_HP_R_DIS);
1522 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1523 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1524 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1525 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1526 snd_soc_update_bits(codec, RT5663_CBJ_1,
1527 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1528 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1529 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1530 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1531 /* BST1 power on for JD */
1532 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1533 RT5668_PWR_BST1_MASK, RT5668_PWR_BST1_ON);
1534 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1535 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1536 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1537 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1539 RT5668_PWR_MB_MASK | RT5668_LDO1_DVO_MASK |
1540 RT5668_AMP_HP_MASK, RT5668_PWR_MB |
1541 RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
1542 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
1543 RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN);
1544 snd_soc_update_bits(codec, RT5663_IRQ_1,
1545 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1546 while (i < 5) {
1547 msleep(sleep_time[i]);
1548 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) &
1549 0x0003;
1550 i++;
1551 if (val == 0x1 || val == 0x2 || val == 0x3)
1552 break;
1553 dev_dbg(codec->dev, "%s: MX-00e7 val=%x sleep %d\n",
1554 __func__, val, sleep_time[i]);
1555 }
1556 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1557 switch (val) {
1558 case 1:
1559 case 2:
1560 rt5663->jack_type = SND_JACK_HEADSET;
1561 rt5663_enable_push_button_irq(codec, true);
1562 break;
1563 default:
1564 rt5663->jack_type = SND_JACK_HEADPHONE;
1565 break;
1566 }
1567 } else {
1568 if (rt5663->jack_type == SND_JACK_HEADSET)
1569 rt5663_enable_push_button_irq(codec, false);
1570 rt5663->jack_type = 0;
1571 }
1572
1573 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1574 return rt5663->jack_type;
1575}
1576
1577int rt5663_button_detect(struct snd_soc_codec *codec)
1578{
1579 int btn_type, val;
1580
1581 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1582 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1583 btn_type = val & 0xfff0;
1584 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1585
1586 return btn_type;
1587}
1588
1589static irqreturn_t rt5663_irq(int irq, void *data)
1590{
1591 struct rt5663_priv *rt5663 = data;
1592
1593 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__);
1594
1595 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1596 msecs_to_jiffies(250));
1597
1598 return IRQ_HANDLED;
1599}
1600
1601int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1602 struct snd_soc_jack *hs_jack)
1603{
1604 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1605
1606 rt5663->hs_jack = hs_jack;
1607
1608 rt5663_irq(0, rt5663);
1609
1610 return 0;
1611}
1612EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1613
1614static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1615{
1616 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1617 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1618
1619 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1620
1621 /* JD1 */
1622 switch (rt5663->codec_type) {
1623 case CODEC_TYPE_RT5668:
1624 return !(val & 0x2000);
1625 case CODEC_TYPE_RT5663:
1626 return !(val & 0x1000);
1627 default:
1628 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1629 }
1630
1631 return false;
1632}
1633
1634static void rt5663_jack_detect_work(struct work_struct *work)
1635{
1636 struct rt5663_priv *rt5663 =
1637 container_of(work, struct rt5663_priv, jack_detect_work.work);
1638 struct snd_soc_codec *codec = rt5663->codec;
1639 int btn_type, report = 0;
1640
1641 if (!codec)
1642 return;
1643
1644 if (rt5663_check_jd_status(codec)) {
1645 /* jack in */
1646 if (rt5663->jack_type == 0) {
1647 /* jack was out, report jack type */
1648 switch (rt5663->codec_type) {
1649 case CODEC_TYPE_RT5668:
1650 report = rt5668_jack_detect(rt5663->codec, 1);
1651 break;
1652 case CODEC_TYPE_RT5663:
1653 report = rt5663_jack_detect(rt5663->codec, 1);
1654 break;
1655 default:
1656 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1657 }
1658 } else {
1659 /* jack is already in, report button event */
1660 report = SND_JACK_HEADSET;
1661 btn_type = rt5663_button_detect(rt5663->codec);
1662 /**
1663 * rt5663 can report three kinds of button behavior,
1664 * one click, double click and hold. However,
1665 * currently we will report button pressed/released
1666 * event. So all the three button behaviors are
1667 * treated as button pressed.
1668 */
1669 switch (btn_type) {
1670 case 0x8000:
1671 case 0x4000:
1672 case 0x2000:
1673 report |= SND_JACK_BTN_0;
1674 break;
1675 case 0x1000:
1676 case 0x0800:
1677 case 0x0400:
1678 report |= SND_JACK_BTN_1;
1679 break;
1680 case 0x0200:
1681 case 0x0100:
1682 case 0x0080:
1683 report |= SND_JACK_BTN_2;
1684 break;
1685 case 0x0040:
1686 case 0x0020:
1687 case 0x0010:
1688 report |= SND_JACK_BTN_3;
1689 break;
1690 case 0x0000: /* unpressed */
1691 break;
1692 default:
1693 btn_type = 0;
1694 dev_err(rt5663->codec->dev,
1695 "Unexpected button code 0x%04x\n",
1696 btn_type);
1697 break;
1698 }
1699 /* button release or spurious interrput*/
1700 if (btn_type == 0)
1701 report = rt5663->jack_type;
1702 }
1703 } else {
1704 /* jack out */
1705 switch (rt5663->codec_type) {
1706 case CODEC_TYPE_RT5668:
1707 report = rt5668_jack_detect(rt5663->codec, 0);
1708 break;
1709 case CODEC_TYPE_RT5663:
1710 report = rt5663_jack_detect(rt5663->codec, 0);
1711 break;
1712 default:
1713 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1714 }
1715 }
1716 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1717 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1718 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1719 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1720}
1721
1722static const struct snd_kcontrol_new rt5663_snd_controls[] = {
1723 /* DAC Digital Volume */
1724 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
1725 RT5668_DAC_L1_VOL_SHIFT + 1, RT5668_DAC_R1_VOL_SHIFT + 1,
1726 87, 0, dac_vol_tlv),
1727 /* ADC Digital Volume Control */
1728 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
1729 RT5668_ADC_L_MUTE_SHIFT, RT5668_ADC_R_MUTE_SHIFT, 1, 1),
1730 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
1731 RT5668_ADC_L_VOL_SHIFT + 1, RT5668_ADC_R_VOL_SHIFT + 1,
1732 63, 0, adc_vol_tlv),
1733};
1734
1735static const struct snd_kcontrol_new rt5668_specific_controls[] = {
1736 /* Headphone Output Volume */
1737 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
1738 RT5663_HP_RCH_DRE, RT5668_GAIN_HP_SHIFT, 15, 1,
1739 rt5668_hp_vol_tlv),
1740 /* Mic Boost Volume */
1741 SOC_SINGLE_TLV("IN1 Capture Volume", RT5668_AEC_BST,
1742 RT5668_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
1743};
1744
1745static const struct snd_kcontrol_new rt5663_specific_controls[] = {
1746 /* Headphone Output Volume */
1747 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
1748 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
1749 rt5663_hp_vol_tlv),
1750 /* Mic Boost Volume*/
1751 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
1752 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
1753 /* Data Swap for Slot0/1 in ADCDAT1 */
1754 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
1755};
1756
1757static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1758 struct snd_soc_dapm_widget *sink)
1759{
1760 unsigned int val;
1761 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1762
1763 val = snd_soc_read(codec, RT5663_GLB_CLK);
1764 val &= RT5663_SCLK_SRC_MASK;
1765 if (val == RT5663_SCLK_SRC_PLL1)
1766 return 1;
1767 else
1768 return 0;
1769}
1770
1771static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
1772 struct snd_soc_dapm_widget *sink)
1773{
1774 unsigned int reg, shift, val;
1775 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1776 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1777
1778 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
1779 switch (w->shift) {
1780 case RT5668_ADC_STO1_ASRC_SHIFT:
1781 reg = RT5668_ASRC_3;
1782 shift = RT5668_AD_STO1_TRACK_SHIFT;
1783 break;
1784 case RT5668_DAC_STO1_ASRC_SHIFT:
1785 reg = RT5663_ASRC_2;
1786 shift = RT5668_DA_STO1_TRACK_SHIFT;
1787 break;
1788 default:
1789 return 0;
1790 }
1791 } else {
1792 switch (w->shift) {
1793 case RT5663_ADC_STO1_ASRC_SHIFT:
1794 reg = RT5663_ASRC_2;
1795 shift = RT5663_AD_STO1_TRACK_SHIFT;
1796 break;
1797 case RT5663_DAC_STO1_ASRC_SHIFT:
1798 reg = RT5663_ASRC_2;
1799 shift = RT5663_DA_STO1_TRACK_SHIFT;
1800 break;
1801 default:
1802 return 0;
1803 }
1804 }
1805
1806 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
1807
1808 if (val)
1809 return 1;
1810
1811 return 0;
1812}
1813
1814static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1815 struct snd_soc_dapm_widget *sink)
1816{
1817 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1818 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1819 int da_asrc_en, ad_asrc_en;
1820
1821 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1822 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
1823 switch (rt5663->codec_type) {
1824 case CODEC_TYPE_RT5668:
1825 ad_asrc_en = (snd_soc_read(codec, RT5668_ASRC_3) &
1826 RT5668_AD_STO1_TRACK_MASK) ? 1 : 0;
1827 break;
1828 case CODEC_TYPE_RT5663:
1829 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1830 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
1831 break;
1832 default:
1833 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1834 }
1835
1836 if (da_asrc_en || ad_asrc_en)
1837 if (rt5663->sysclk > rt5663->lrck * 384)
1838 return 1;
1839
1840 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
1841
1842 return 0;
1843}
1844
1845/**
1846 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
1847 * @codec: SoC audio codec device.
1848 * @filter_mask: mask of filters.
1849 * @clk_src: clock source
1850 *
1851 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
1852 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1853 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1854 * ASRC function will track i2s clock and generate a corresponding system clock
1855 * for codec. This function provides an API to select the clock source for a
1856 * set of filters specified by the mask. And the codec driver will turn on ASRC
1857 * for these filters if ASRC is selected as their clock source.
1858 */
1859int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1860 unsigned int filter_mask, unsigned int clk_src)
1861{
1862 struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
1863 unsigned int asrc2_mask = 0;
1864 unsigned int asrc2_value = 0;
1865 unsigned int asrc3_mask = 0;
1866 unsigned int asrc3_value = 0;
1867
1868 switch (clk_src) {
1869 case RT5663_CLK_SEL_SYS:
1870 case RT5663_CLK_SEL_I2S1_ASRC:
1871 break;
1872
1873 default:
1874 return -EINVAL;
1875 }
1876
1877 if (filter_mask & RT5663_DA_STEREO_FILTER) {
1878 asrc2_mask |= RT5668_DA_STO1_TRACK_MASK;
1879 asrc2_value |= clk_src << RT5668_DA_STO1_TRACK_SHIFT;
1880 }
1881
1882 if (filter_mask & RT5663_AD_STEREO_FILTER) {
1883 switch (rt5668->codec_type) {
1884 case CODEC_TYPE_RT5668:
1885 asrc3_mask |= RT5668_AD_STO1_TRACK_MASK;
1886 asrc3_value |= clk_src << RT5668_AD_STO1_TRACK_SHIFT;
1887 break;
1888 case CODEC_TYPE_RT5663:
1889 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
1890 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
1891 break;
1892 default:
1893 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1894 }
1895 }
1896
1897 if (asrc2_mask)
1898 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
1899 asrc2_value);
1900
1901 if (asrc3_mask)
1902 snd_soc_update_bits(codec, RT5668_ASRC_3, asrc3_mask,
1903 asrc3_value);
1904
1905 return 0;
1906}
1907EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
1908
1909/* Analog Mixer */
1910static const struct snd_kcontrol_new rt5668_recmix1l[] = {
1911 SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1L,
1912 RT5668_RECMIX1L_BST2_SHIFT, 1, 1),
1913 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5668_RECMIX1L,
1914 RT5668_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
1915};
1916
1917static const struct snd_kcontrol_new rt5668_recmix1r[] = {
1918 SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1R,
1919 RT5668_RECMIX1R_BST2_SHIFT, 1, 1),
1920};
1921
1922/* Digital Mixer */
1923static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
1924 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1925 RT5668_M_STO1_ADC_L1_SHIFT, 1, 1),
1926 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1927 RT5668_M_STO1_ADC_L2_SHIFT, 1, 1),
1928};
1929
1930static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
1931 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1932 RT5668_M_STO1_ADC_R1_SHIFT, 1, 1),
1933 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1934 RT5668_M_STO1_ADC_R2_SHIFT, 1, 1),
1935};
1936
1937static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
1938 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
1939 RT5668_M_ADCMIX_L_SHIFT, 1, 1),
1940 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
1941 RT5668_M_DAC1_L_SHIFT, 1, 1),
1942};
1943
1944static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
1945 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
1946 RT5668_M_ADCMIX_R_SHIFT, 1, 1),
1947 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
1948 RT5668_M_DAC1_R_SHIFT, 1, 1),
1949};
1950
1951static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
1952 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
1953 RT5668_M_DAC_L1_STO_L_SHIFT, 1, 1),
1954 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
1955 RT5668_M_DAC_R1_STO_L_SHIFT, 1, 1),
1956};
1957
1958static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
1959 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
1960 RT5668_M_DAC_L1_STO_R_SHIFT, 1, 1),
1961 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
1962 RT5668_M_DAC_R1_STO_R_SHIFT, 1, 1),
1963};
1964
1965/* Out Switch */
1966static const struct snd_kcontrol_new rt5668_hpo_switch =
1967 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_AMP_2,
1968 RT5668_EN_DAC_HPO_SHIFT, 1, 0);
1969
1970/* Stereo ADC source */
1971static const char * const rt5668_sto1_adc_src[] = {
1972 "ADC L", "ADC R"
1973};
1974
1975static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
1976 RT5668_STO1_ADC_L_SRC_SHIFT, rt5668_sto1_adc_src);
1977
1978static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
1979 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5668_sto1_adcl_enum);
1980
1981static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
1982 RT5668_STO1_ADC_R_SRC_SHIFT, rt5668_sto1_adc_src);
1983
1984static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
1985 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5668_sto1_adcr_enum);
1986
1987/* RT5663: Analog DACL1 input source */
1988static const char * const rt5663_alg_dacl_src[] = {
1989 "DAC L", "STO DAC MIXL"
1990};
1991
1992static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
1993 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
1994
1995static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
1996 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
1997
1998/* RT5663: Analog DACR1 input source */
1999static const char * const rt5663_alg_dacr_src[] = {
2000 "DAC R", "STO DAC MIXR"
2001};
2002
2003static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2004 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2005
2006static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2007 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2008
2009static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2010 struct snd_kcontrol *kcontrol, int event)
2011{
2012 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2013 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2014
2015 switch (event) {
2016 case SND_SOC_DAPM_POST_PMU:
2017 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2018 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2019 RT5668_SEL_PM_HP_SHIFT, RT5668_SEL_PM_HP_HIGH);
2020 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2021 RT5668_HP_SIG_SRC1_MASK,
2022 RT5668_HP_SIG_SRC1_SILENCE);
2023 } else {
2024 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
2025 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
2026 0x000b);
2027 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
2028 0x0030);
2029 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2030 RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_DIS);
2031 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2032 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2033 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2034 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2035 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2036 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
2037 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2038 0x3000);
2039 }
2040 break;
2041
2042 case SND_SOC_DAPM_PRE_PMD:
2043 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2044 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2045 RT5668_HP_SIG_SRC1_MASK,
2046 RT5668_HP_SIG_SRC1_REG);
2047 } else {
2048 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2049 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2050 RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_EN);
2051 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
2052 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
2053 0x000b);
2054 }
2055 break;
2056
2057 default:
2058 return 0;
2059 }
2060
2061 return 0;
2062}
2063
2064static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
2065 struct snd_kcontrol *kcontrol, int event)
2066{
2067 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2068
2069 switch (event) {
2070 case SND_SOC_DAPM_POST_PMU:
2071 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2072 RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK,
2073 RT5668_PWR_BST2 | RT5668_PWR_BST2_OP);
2074 break;
2075
2076 case SND_SOC_DAPM_PRE_PMD:
2077 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2078 RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK, 0);
2079 break;
2080
2081 default:
2082 return 0;
2083 }
2084
2085 return 0;
2086}
2087
2088static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2089 struct snd_kcontrol *kcontrol, int event)
2090{
2091 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2092
2093 switch (event) {
2094 case SND_SOC_DAPM_POST_PMU:
2095 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2096 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2097 break;
2098
2099 case SND_SOC_DAPM_PRE_PMD:
2100 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2101 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2102 break;
2103
2104 default:
2105 return 0;
2106 }
2107
2108 return 0;
2109}
2110
2111static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2112 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5668_PWR_PLL_SHIFT, 0,
2113 NULL, 0),
2114
2115 /* micbias */
2116 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2117 RT5668_PWR_MB1_SHIFT, 0),
2118 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2119 RT5668_PWR_MB2_SHIFT, 0),
2120
2121 /* Input Lines */
2122 SND_SOC_DAPM_INPUT("IN1P"),
2123 SND_SOC_DAPM_INPUT("IN1N"),
2124
2125 /* REC Mixer Power */
2126 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2127 RT5668_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2128
2129 /* ADCs */
2130 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2131 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2132 RT5668_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2133 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2134 RT5668_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2135
2136 /* ADC Mixer */
2137 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2138 0, 0, rt5663_sto1_adc_l_mix,
2139 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2140
2141 /* ADC Filter Power */
2142 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2143 RT5668_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2144
2145 /* Digital Interface */
2146 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5668_PWR_I2S1_SHIFT, 0,
2147 NULL, 0),
2148 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2149 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2150 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2151 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2152 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2153
2154 /* Audio Interface */
2155 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2156 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2157
2158 /* DAC mixer before sound effect */
2159 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2160 ARRAY_SIZE(rt5663_adda_l_mix)),
2161 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2162 ARRAY_SIZE(rt5663_adda_r_mix)),
2163 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2164 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2165
2166 /* DAC Mixer */
2167 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2168 RT5668_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2169 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2170 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2171 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2172 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2173
2174 /* DACs */
2175 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2176 RT5668_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2177 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2178 RT5668_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2179 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2180 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2181
2182 /* Headphone*/
2183 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2184 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2185
2186 /* Output Lines */
2187 SND_SOC_DAPM_OUTPUT("HPOL"),
2188 SND_SOC_DAPM_OUTPUT("HPOR"),
2189};
2190
2191static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
2192 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2193 RT5668_PWR_LDO2_SHIFT, 0, NULL, 0),
2194 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5668_PWR_VOL,
2195 RT5668_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2196 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2197 RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2198
2199 /* ASRC */
2200 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2201 RT5668_I2S1_ASRC_SHIFT, 0, NULL, 0),
2202 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2203 RT5668_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2204 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2205 RT5668_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2206
2207 /* Input Lines */
2208 SND_SOC_DAPM_INPUT("IN2P"),
2209 SND_SOC_DAPM_INPUT("IN2N"),
2210
2211 /* Boost */
2212 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2213 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2214 RT5668_PWR_CBJ_SHIFT, 0, NULL, 0),
2215 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2216 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2217 rt5668_bst2_power, SND_SOC_DAPM_PRE_PMD |
2218 SND_SOC_DAPM_POST_PMU),
2219
2220 /* REC Mixer */
2221 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_recmix1l,
2222 ARRAY_SIZE(rt5668_recmix1l)),
2223 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5668_recmix1r,
2224 ARRAY_SIZE(rt5668_recmix1r)),
2225 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2226 RT5668_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2227
2228 /* ADC */
2229 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2230 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2231 RT5668_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2232
2233 /* ADC Mux */
2234 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2235 RT5668_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2236 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2237 RT5668_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2238 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2239 RT5668_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2240 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2241 RT5668_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2242
2243 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2244 &rt5668_sto1_adcl_mux),
2245 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2246 &rt5668_sto1_adcr_mux),
2247
2248 /* ADC Mix */
2249 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2250 rt5668_sto1_adc_r_mix, ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
2251
2252 /* Analog DAC Clock */
2253 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2254 RT5668_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2255
2256 /* Headphone out */
2257 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2258 &rt5668_hpo_switch),
2259};
2260
2261static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2262 /* System Clock Pre Divider Gating */
2263 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2264 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2265 SND_SOC_DAPM_PRE_PMD),
2266
2267 /* LDO */
2268 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2269 RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2270
2271 /* ASRC */
2272 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2273 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2274 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2275 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2276 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2277 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2278
2279 /* Boost */
2280 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2281
2282 /* STO ADC */
2283 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2284 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2285
2286 /* Analog DAC source */
2287 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2288 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2289};
2290
2291static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2292 /* PLL */
2293 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2294
2295 /* ASRC */
2296 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2297 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2298 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2299
2300 { "ADC L", NULL, "ADC L Power" },
2301 { "ADC L", NULL, "ADC Clock" },
2302
2303 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2304
2305 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2306 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2307 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2308
2309 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2310 { "IF ADC", NULL, "IF1 ADC1" },
2311 { "AIFTX", NULL, "IF ADC" },
2312 { "AIFTX", NULL, "I2S" },
2313
2314 { "AIFRX", NULL, "I2S" },
2315 { "IF DAC", NULL, "AIFRX" },
2316 { "IF1 DAC1 L", NULL, "IF DAC" },
2317 { "IF1 DAC1 R", NULL, "IF DAC" },
2318
2319 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2320 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2321 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2322 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2323 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2324 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2325 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2326
2327 { "DAC L1", NULL, "ADDA MIXL" },
2328 { "DAC R1", NULL, "ADDA MIXR" },
2329
2330 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2331 { "STO1 DAC MIXL", "DAC R Switch", "DAC R1" },
2332 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2333 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2334 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2335 { "STO1 DAC MIXR", "DAC L Switch", "DAC L1" },
2336 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2337 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2338
2339 { "HP Amp", NULL, "DAC L" },
2340 { "HP Amp", NULL, "DAC R" },
2341};
2342
2343static const struct snd_soc_dapm_route rt5668_specific_dapm_routes[] = {
2344 { "MICBIAS1", NULL, "LDO2" },
2345 { "MICBIAS2", NULL, "LDO2" },
2346
2347 { "BST1 CBJ", NULL, "IN1P" },
2348 { "BST1 CBJ", NULL, "IN1N" },
2349 { "BST1 CBJ", NULL, "CBJ Power" },
2350
2351 { "BST2", NULL, "IN2P" },
2352 { "BST2", NULL, "IN2N" },
2353 { "BST2", NULL, "BST2 Power" },
2354
2355 { "RECMIX1L", "BST2 Switch", "BST2" },
2356 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2357 { "RECMIX1L", NULL, "RECMIX1L Power" },
2358 { "RECMIX1R", "BST2 Switch", "BST2" },
2359 { "RECMIX1R", NULL, "RECMIX1R Power" },
2360
2361 { "ADC L", NULL, "RECMIX1L" },
2362 { "ADC R", NULL, "RECMIX1R" },
2363 { "ADC R", NULL, "ADC R Power" },
2364 { "ADC R", NULL, "ADC Clock" },
2365
2366 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2367 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2368 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2369
2370 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2371 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2372 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2373 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2374
2375 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2376 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2377 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2378
2379 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2380
2381 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2382
2383 { "DAC L", NULL, "STO1 DAC MIXL" },
2384 { "DAC L", NULL, "LDO DAC" },
2385 { "DAC L", NULL, "DAC Clock" },
2386 { "DAC R", NULL, "STO1 DAC MIXR" },
2387 { "DAC R", NULL, "LDO DAC" },
2388 { "DAC R", NULL, "DAC Clock" },
2389
2390 { "HPO Playback", "Switch", "HP Amp" },
2391 { "HPOL", NULL, "HPO Playback" },
2392 { "HPOR", NULL, "HPO Playback" },
2393};
2394
2395static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2396 { "I2S", NULL, "Pre Div Power" },
2397
2398 { "BST1", NULL, "IN1P" },
2399 { "BST1", NULL, "IN1N" },
2400 { "BST1", NULL, "RECMIX1L Power" },
2401
2402 { "ADC L", NULL, "BST1" },
2403
2404 { "STO1 ADC L1", NULL, "ADC L" },
2405
2406 { "DAC L Mux", "DAC L", "DAC L1" },
2407 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2408 { "DAC R Mux", "DAC R", "DAC R1"},
2409 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2410
2411 { "DAC L", NULL, "DAC L Mux" },
2412 { "DAC R", NULL, "DAC R Mux" },
2413
2414 { "HPOL", NULL, "HP Amp" },
2415 { "HPOR", NULL, "HP Amp" },
2416};
2417
2418static int rt5663_hw_params(struct snd_pcm_substream *substream,
2419 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2420{
2421 struct snd_soc_codec *codec = dai->codec;
2422 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2423 unsigned int val_len = 0;
2424 int pre_div;
2425
2426 rt5663->lrck = params_rate(params);
2427
2428 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2429 rt5663->lrck, rt5663->sysclk);
2430
2431 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2432 if (pre_div < 0) {
2433 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2434 rt5663->lrck, dai->id);
2435 return -EINVAL;
2436 }
2437
2438 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2439
2440 switch (params_width(params)) {
2441 case 8:
2442 val_len = RT5668_I2S_DL_8;
2443 break;
2444 case 16:
2445 val_len = RT5668_I2S_DL_16;
2446 break;
2447 case 20:
2448 val_len = RT5668_I2S_DL_20;
2449 break;
2450 case 24:
2451 val_len = RT5668_I2S_DL_24;
2452 break;
2453 default:
2454 return -EINVAL;
2455 }
2456
2457 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
2458 RT5668_I2S_DL_MASK, val_len);
2459
2460 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
2461 RT5668_I2S_PD1_MASK, pre_div << RT5668_I2S_PD1_SHIFT);
2462
2463 return 0;
2464}
2465
2466static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2467{
2468 struct snd_soc_codec *codec = dai->codec;
2469 unsigned int reg_val = 0;
2470
2471 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2472 case SND_SOC_DAIFMT_CBM_CFM:
2473 break;
2474 case SND_SOC_DAIFMT_CBS_CFS:
2475 reg_val |= RT5668_I2S_MS_S;
2476 break;
2477 default:
2478 return -EINVAL;
2479 }
2480
2481 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2482 case SND_SOC_DAIFMT_NB_NF:
2483 break;
2484 case SND_SOC_DAIFMT_IB_NF:
2485 reg_val |= RT5668_I2S_BP_INV;
2486 break;
2487 default:
2488 return -EINVAL;
2489 }
2490
2491 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2492 case SND_SOC_DAIFMT_I2S:
2493 break;
2494 case SND_SOC_DAIFMT_LEFT_J:
2495 reg_val |= RT5668_I2S_DF_LEFT;
2496 break;
2497 case SND_SOC_DAIFMT_DSP_A:
2498 reg_val |= RT5668_I2S_DF_PCM_A;
2499 break;
2500 case SND_SOC_DAIFMT_DSP_B:
2501 reg_val |= RT5668_I2S_DF_PCM_B;
2502 break;
2503 default:
2504 return -EINVAL;
2505 }
2506
2507 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5668_I2S_MS_MASK |
2508 RT5668_I2S_BP_MASK | RT5668_I2S_DF_MASK, reg_val);
2509
2510 return 0;
2511}
2512
2513static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2514 unsigned int freq, int dir)
2515{
2516 struct snd_soc_codec *codec = dai->codec;
2517 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2518 unsigned int reg_val = 0;
2519
2520 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2521 return 0;
2522
2523 switch (clk_id) {
2524 case RT5663_SCLK_S_MCLK:
2525 reg_val |= RT5663_SCLK_SRC_MCLK;
2526 break;
2527 case RT5663_SCLK_S_PLL1:
2528 reg_val |= RT5663_SCLK_SRC_PLL1;
2529 break;
2530 case RT5663_SCLK_S_RCCLK:
2531 reg_val |= RT5663_SCLK_SRC_RCCLK;
2532 break;
2533 default:
2534 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2535 return -EINVAL;
2536 }
2537 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5668_SCLK_SRC_MASK,
2538 reg_val);
2539 rt5663->sysclk = freq;
2540 rt5663->sysclk_src = clk_id;
2541
2542 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2543 freq, clk_id);
2544
2545 return 0;
2546}
2547
2548static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2549 unsigned int freq_in, unsigned int freq_out)
2550{
2551 struct snd_soc_codec *codec = dai->codec;
2552 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2553 struct rl6231_pll_code pll_code;
2554 int ret;
2555 int mask, shift, val;
2556
2557 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2558 freq_out == rt5663->pll_out)
2559 return 0;
2560
2561 if (!freq_in || !freq_out) {
2562 dev_dbg(codec->dev, "PLL disabled\n");
2563
2564 rt5663->pll_in = 0;
2565 rt5663->pll_out = 0;
2566 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2567 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2568 return 0;
2569 }
2570
2571 switch (rt5663->codec_type) {
2572 case CODEC_TYPE_RT5668:
2573 mask = RT5668_PLL1_SRC_MASK;
2574 shift = RT5668_PLL1_SRC_SHIFT;
2575 break;
2576 case CODEC_TYPE_RT5663:
2577 mask = RT5663_PLL1_SRC_MASK;
2578 shift = RT5663_PLL1_SRC_SHIFT;
2579 break;
2580 default:
2581 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
2582 }
2583
2584 switch (source) {
2585 case RT5663_PLL1_S_MCLK:
2586 val = 0x0;
2587 break;
2588 case RT5663_PLL1_S_BCLK1:
2589 val = 0x1;
2590 break;
2591 default:
2592 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2593 return -EINVAL;
2594 }
2595 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2596
2597 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2598 if (ret < 0) {
2599 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2600 return ret;
2601 }
2602
2603 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2604 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2605 pll_code.k_code);
2606
2607 snd_soc_write(codec, RT5663_PLL_1,
2608 pll_code.n_code << RT5668_PLL_N_SHIFT | pll_code.k_code);
2609 snd_soc_write(codec, RT5663_PLL_2,
2610 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SHIFT |
2611 pll_code.m_bp << RT5668_PLL_M_BP_SHIFT);
2612
2613 rt5663->pll_in = freq_in;
2614 rt5663->pll_out = freq_out;
2615 rt5663->pll_src = source;
2616
2617 return 0;
2618}
2619
2620static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2621 unsigned int rx_mask, int slots, int slot_width)
2622{
2623 struct snd_soc_codec *codec = dai->codec;
2624 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2625 unsigned int val = 0, reg;
2626
2627 if (rx_mask || tx_mask)
2628 val |= RT5668_TDM_MODE_TDM;
2629
2630 switch (slots) {
2631 case 4:
2632 val |= RT5668_TDM_IN_CH_4;
2633 val |= RT5668_TDM_OUT_CH_4;
2634 break;
2635 case 6:
2636 val |= RT5668_TDM_IN_CH_6;
2637 val |= RT5668_TDM_OUT_CH_6;
2638 break;
2639 case 8:
2640 val |= RT5668_TDM_IN_CH_8;
2641 val |= RT5668_TDM_OUT_CH_8;
2642 break;
2643 case 2:
2644 break;
2645 default:
2646 return -EINVAL;
2647 }
2648
2649 switch (slot_width) {
2650 case 20:
2651 val |= RT5668_TDM_IN_LEN_20;
2652 val |= RT5668_TDM_OUT_LEN_20;
2653 break;
2654 case 24:
2655 val |= RT5668_TDM_IN_LEN_24;
2656 val |= RT5668_TDM_OUT_LEN_24;
2657 break;
2658 case 32:
2659 val |= RT5668_TDM_IN_LEN_32;
2660 val |= RT5668_TDM_OUT_LEN_32;
2661 break;
2662 case 16:
2663 break;
2664 default:
2665 return -EINVAL;
2666 }
2667
2668 switch (rt5663->codec_type) {
2669 case CODEC_TYPE_RT5668:
2670 reg = RT5663_TDM_2;
2671 break;
2672 case CODEC_TYPE_RT5663:
2673 reg = RT5663_TDM_1;
2674 break;
2675 default:
2676 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
2677 }
2678
2679 snd_soc_update_bits(codec, reg, RT5668_TDM_MODE_MASK |
2680 RT5668_TDM_IN_CH_MASK | RT5668_TDM_OUT_CH_MASK |
2681 RT5668_TDM_IN_LEN_MASK | RT5668_TDM_OUT_LEN_MASK, val);
2682
2683 return 0;
2684}
2685
2686static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2687{
2688 struct snd_soc_codec *codec = dai->codec;
2689 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2690 unsigned int reg;
2691
2692 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
2693
2694 if (rt5663->codec_type == CODEC_TYPE_RT5668)
2695 reg = RT5668_TDM_8;
2696 else
2697 reg = RT5663_TDM_5;
2698
2699 switch (ratio) {
2700 case 32:
2701 snd_soc_update_bits(codec, reg,
2702 RT5663_TDM_LENGTN_MASK,
2703 RT5663_TDM_LENGTN_16);
2704 break;
2705 case 40:
2706 snd_soc_update_bits(codec, reg,
2707 RT5663_TDM_LENGTN_MASK,
2708 RT5663_TDM_LENGTN_20);
2709 break;
2710 case 48:
2711 snd_soc_update_bits(codec, reg,
2712 RT5663_TDM_LENGTN_MASK,
2713 RT5663_TDM_LENGTN_24);
2714 break;
2715 case 64:
2716 snd_soc_update_bits(codec, reg,
2717 RT5663_TDM_LENGTN_MASK,
2718 RT5663_TDM_LENGTN_32);
2719 break;
2720 default:
2721 dev_err(codec->dev, "Invalid ratio!\n");
2722 return -EINVAL;
2723 }
2724
2725 return 0;
2726}
2727
2728static int rt5663_set_bias_level(struct snd_soc_codec *codec,
2729 enum snd_soc_bias_level level)
2730{
2731 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2732
2733 switch (level) {
2734 case SND_SOC_BIAS_ON:
2735 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2736 RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK,
2737 RT5668_PWR_FV1 | RT5668_PWR_FV2);
2738 break;
2739
2740 case SND_SOC_BIAS_PREPARE:
2741 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2742 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2743 RT5668_DIG_GATE_CTRL_MASK,
2744 RT5668_DIG_GATE_CTRL_EN);
2745 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2746 RT5668_EN_ANA_CLK_DET_MASK |
2747 RT5668_PWR_CLK_DET_MASK,
2748 RT5668_EN_ANA_CLK_DET_AUTO |
2749 RT5668_PWR_CLK_DET_EN);
2750 }
2751 break;
2752
2753 case SND_SOC_BIAS_STANDBY:
2754 if (rt5663->codec_type == CODEC_TYPE_RT5668)
2755 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2756 RT5668_DIG_GATE_CTRL_MASK,
2757 RT5668_DIG_GATE_CTRL_DIS);
2758 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2759 RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
2760 RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK |
2761 RT5668_PWR_MB_MASK, RT5668_PWR_VREF1 |
2762 RT5668_PWR_VREF2 | RT5668_PWR_MB);
2763 usleep_range(10000, 10005);
2764 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2765 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2766 RT5668_EN_ANA_CLK_DET_MASK |
2767 RT5668_PWR_CLK_DET_MASK,
2768 RT5668_EN_ANA_CLK_DET_DIS |
2769 RT5668_PWR_CLK_DET_DIS);
2770 }
2771 break;
2772
2773 case SND_SOC_BIAS_OFF:
2774 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2775 RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
2776 RT5668_PWR_FV1 | RT5668_PWR_FV2, 0x0);
2777 break;
2778
2779 default:
2780 break;
2781 }
2782
2783 return 0;
2784}
2785
2786static int rt5663_probe(struct snd_soc_codec *codec)
2787{
2788 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2789 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2790
2791 rt5663->codec = codec;
2792
2793 switch (rt5663->codec_type) {
2794 case CODEC_TYPE_RT5668:
2795 snd_soc_dapm_new_controls(dapm,
2796 rt5668_specific_dapm_widgets,
2797 ARRAY_SIZE(rt5668_specific_dapm_widgets));
2798 snd_soc_dapm_add_routes(dapm,
2799 rt5668_specific_dapm_routes,
2800 ARRAY_SIZE(rt5668_specific_dapm_routes));
2801 snd_soc_add_codec_controls(codec, rt5668_specific_controls,
2802 ARRAY_SIZE(rt5668_specific_controls));
2803 break;
2804 case CODEC_TYPE_RT5663:
2805 snd_soc_dapm_new_controls(dapm,
2806 rt5663_specific_dapm_widgets,
2807 ARRAY_SIZE(rt5663_specific_dapm_widgets));
2808 snd_soc_dapm_add_routes(dapm,
2809 rt5663_specific_dapm_routes,
2810 ARRAY_SIZE(rt5663_specific_dapm_routes));
2811 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
2812 ARRAY_SIZE(rt5663_specific_controls));
2813 break;
2814 }
2815
2816 return 0;
2817}
2818
2819static int rt5663_remove(struct snd_soc_codec *codec)
2820{
2821 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2822
2823 regmap_write(rt5663->regmap, RT5663_RESET, 0);
2824
2825 return 0;
2826}
2827
2828#ifdef CONFIG_PM
2829static int rt5663_suspend(struct snd_soc_codec *codec)
2830{
2831 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2832
2833 regcache_cache_only(rt5663->regmap, true);
2834 regcache_mark_dirty(rt5663->regmap);
2835
2836 return 0;
2837}
2838
2839static int rt5663_resume(struct snd_soc_codec *codec)
2840{
2841 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2842
2843 regcache_cache_only(rt5663->regmap, false);
2844 regcache_sync(rt5663->regmap);
2845
2846 return 0;
2847}
2848#else
2849#define rt5663_suspend NULL
2850#define rt5663_resume NULL
2851#endif
2852
2853#define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2854#define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2855 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2856
2857struct snd_soc_dai_ops rt5663_aif_dai_ops = {
2858 .hw_params = rt5663_hw_params,
2859 .set_fmt = rt5663_set_dai_fmt,
2860 .set_sysclk = rt5663_set_dai_sysclk,
2861 .set_pll = rt5663_set_dai_pll,
2862 .set_tdm_slot = rt5663_set_tdm_slot,
2863 .set_bclk_ratio = rt5663_set_bclk_ratio,
2864};
2865
2866struct snd_soc_dai_driver rt5663_dai[] = {
2867 {
2868 .name = "rt5663-aif",
2869 .id = RT5663_AIF,
2870 .playback = {
2871 .stream_name = "AIF Playback",
2872 .channels_min = 1,
2873 .channels_max = 2,
2874 .rates = RT5663_STEREO_RATES,
2875 .formats = RT5663_FORMATS,
2876 },
2877 .capture = {
2878 .stream_name = "AIF Capture",
2879 .channels_min = 1,
2880 .channels_max = 2,
2881 .rates = RT5663_STEREO_RATES,
2882 .formats = RT5663_FORMATS,
2883 },
2884 .ops = &rt5663_aif_dai_ops,
2885 },
2886};
2887
2888static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
2889 .probe = rt5663_probe,
2890 .remove = rt5663_remove,
2891 .suspend = rt5663_suspend,
2892 .resume = rt5663_resume,
2893 .set_bias_level = rt5663_set_bias_level,
2894 .idle_bias_off = true,
2895 .component_driver = {
2896 .controls = rt5663_snd_controls,
2897 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
2898 .dapm_widgets = rt5663_dapm_widgets,
2899 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
2900 .dapm_routes = rt5663_dapm_routes,
2901 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
2902 }
2903};
2904
2905static const struct regmap_config rt5668_regmap = {
2906 .reg_bits = 16,
2907 .val_bits = 16,
2908 .use_single_rw = true,
2909 .max_register = 0x07fa,
2910 .volatile_reg = rt5668_volatile_register,
2911 .readable_reg = rt5668_readable_register,
2912 .cache_type = REGCACHE_RBTREE,
2913 .reg_defaults = rt5668_reg,
2914 .num_reg_defaults = ARRAY_SIZE(rt5668_reg),
2915};
2916
2917static const struct regmap_config rt5663_regmap = {
2918 .reg_bits = 16,
2919 .val_bits = 16,
2920 .use_single_rw = true,
2921 .max_register = 0x03f3,
2922 .volatile_reg = rt5663_volatile_register,
2923 .readable_reg = rt5663_readable_register,
2924 .cache_type = REGCACHE_RBTREE,
2925 .reg_defaults = rt5663_reg,
2926 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
2927};
2928
2929static const struct regmap_config temp_regmap = {
2930 .name = "nocache",
2931 .reg_bits = 16,
2932 .val_bits = 16,
2933 .use_single_rw = true,
2934 .max_register = 0x03f3,
2935 .cache_type = REGCACHE_NONE,
2936};
2937
2938static const struct i2c_device_id rt5663_i2c_id[] = {
2939 { "rt5668", 0 },
2940 { "rt5663", 0 },
2941 {}
2942};
2943MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
2944
2945#if defined(CONFIG_OF)
2946static const struct of_device_id rt5663_of_match[] = {
2947 { .compatible = "realtek,rt5668", },
2948 { .compatible = "realtek,rt5663", },
2949 {},
2950};
2951MODULE_DEVICE_TABLE(of, rt5663_of_match);
2952#endif
2953
2954#ifdef CONFIG_ACPI
2955static struct acpi_device_id rt5663_acpi_match[] = {
2956 { "10EC5668", 0},
2957 { "10EC5663", 0},
2958 {},
2959};
2960MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
2961#endif
2962
2963static void rt5668_calibrate(struct rt5663_priv *rt5668)
2964{
2965 regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0xa402);
2966 regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x0100);
2967 regmap_write(rt5668->regmap, RT5663_RECMIX, 0x4040);
2968 regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x0001);
2969 regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0380);
2970 regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
2971 regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1000);
2972 regmap_write(rt5668->regmap, RT5663_CHOP_DAC_L, 0x3030);
2973 regmap_write(rt5668->regmap, RT5663_CALIB_ADC, 0x3c05);
2974 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa23e);
2975 msleep(40);
2976 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf23e);
2977 regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x0321);
2978 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0xfc00);
2979 msleep(500);
2980}
2981
2982static void rt5663_calibrate(struct rt5663_priv *rt5668)
2983{
2984 int value, count;
2985
2986 regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0280);
2987 regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
2988 regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x8001);
2989 regmap_write(rt5668->regmap, RT5663_VREF_RECMIX, 0x0032);
2990 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa2be);
2991 msleep(20);
2992 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf2be);
2993 regmap_write(rt5668->regmap, RT5663_PWR_DIG_2, 0x8400);
2994 regmap_write(rt5668->regmap, RT5663_CHOP_ADC, 0x3000);
2995 regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
2996 regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x8df8);
2997 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_2, 0x0003);
2998 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_3, 0x018c);
2999 regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1111);
3000 regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3001 regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3002 regmap_write(rt5668->regmap, RT5663_DEPOP_2, 0x3003);
3003 regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
3004 regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3005 regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
3006 regmap_write(rt5668->regmap, RT5663_DACREF_LDO, 0x3b0b);
3007 regmap_write(rt5668->regmap, RT5663_STO_DAC_MIXER, 0x2080);
3008 regmap_write(rt5668->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3009 regmap_write(rt5668->regmap, RT5663_HP_BIAS, 0xabba);
3010 regmap_write(rt5668->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3011 regmap_write(rt5668->regmap, RT5663_HP_OUT_EN, 0x8088);
3012 regmap_write(rt5668->regmap, RT5663_STO_DRE_9, 0x0017);
3013 regmap_write(rt5668->regmap, RT5663_STO_DRE_10, 0x0017);
3014 regmap_write(rt5668->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3015 regmap_write(rt5668->regmap, RT5663_RECMIX, 0x0005);
3016 regmap_write(rt5668->regmap, RT5663_ADDA_RST, 0xc000);
3017 regmap_write(rt5668->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3018 regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x00c9);
3019 regmap_write(rt5668->regmap, RT5663_DUMMY_1, 0x004c);
3020 regmap_write(rt5668->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
3021 regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0x4702);
3022 msleep(200);
3023 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0x0069);
3024 regmap_write(rt5668->regmap, RT5663_HP_CALIB_3, 0x06c2);
3025 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
3026 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
3027 count = 0;
3028 while (true) {
3029 regmap_read(rt5668->regmap, RT5663_HP_CALIB_1_1, &value);
3030 if (value & 0x8000)
3031 usleep_range(10000, 10005);
3032 else
3033 break;
3034
3035 if (count > 200)
3036 return;
3037 count++;
3038 }
3039}
3040
3041static int rt5663_i2c_probe(struct i2c_client *i2c,
3042 const struct i2c_device_id *id)
3043{
3044 struct rt5663_priv *rt5663;
3045 int ret;
3046 unsigned int val;
3047 struct regmap *regmap;
3048
3049 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3050 GFP_KERNEL);
3051
3052 if (rt5663 == NULL)
3053 return -ENOMEM;
3054
3055 i2c_set_clientdata(i2c, rt5663);
3056
3057 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3058 if (IS_ERR(regmap)) {
3059 ret = PTR_ERR(regmap);
3060 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3061 ret);
3062 return ret;
3063 }
3064 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3065 switch (val) {
3066 case RT5668_DEVICE_ID:
3067 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
3068 rt5663->codec_type = CODEC_TYPE_RT5668;
3069 break;
3070 case RT5663_DEVICE_ID:
3071 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3072 rt5663->codec_type = CODEC_TYPE_RT5663;
3073 break;
3074 default:
3075 dev_err(&i2c->dev,
3076 "Device with ID register %#x is not rt5663 or rt5668\n",
3077 val);
3078 return -ENODEV;
3079 }
3080
3081 if (IS_ERR(rt5663->regmap)) {
3082 ret = PTR_ERR(rt5663->regmap);
3083 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3084 ret);
3085 return ret;
3086 }
3087
3088 /* reset and calibrate */
3089 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3090 regcache_cache_bypass(rt5663->regmap, true);
3091 switch (rt5663->codec_type) {
3092 case CODEC_TYPE_RT5668:
3093 rt5668_calibrate(rt5663);
3094 break;
3095 case CODEC_TYPE_RT5663:
3096 rt5663_calibrate(rt5663);
3097 break;
3098 default:
3099 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3100 }
3101 regcache_cache_bypass(rt5663->regmap, false);
3102 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3103 dev_dbg(&i2c->dev, "calibrate done\n");
3104
3105 /* GPIO1 as IRQ */
3106 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5668_GP1_PIN_MASK,
3107 RT5668_GP1_PIN_IRQ);
3108 /* 4btn inline command debounce */
3109 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3110 RT5668_4BTN_CLK_DEB_MASK, RT5668_4BTN_CLK_DEB_65MS);
3111
3112 switch (rt5663->codec_type) {
3113 case CODEC_TYPE_RT5668:
3114 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3115 /* JD1 */
3116 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3117 RT5668_IRQ_POW_SAV_MASK | RT5668_IRQ_POW_SAV_JD1_MASK,
3118 RT5668_IRQ_POW_SAV_EN | RT5668_IRQ_POW_SAV_JD1_EN);
3119 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3120 RT5668_PWR_JD1_MASK, RT5668_PWR_JD1);
3121 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3122 RT5668_EN_CB_JD_MASK, RT5668_EN_CB_JD_EN);
3123
3124 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3125 RT5668_HP_SIG_SRC1_MASK, RT5668_HP_SIG_SRC1_REG);
3126 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3127 RT5668_VREF_BIAS_MASK | RT5668_CBJ_DET_MASK |
3128 RT5668_DET_TYPE_MASK, RT5668_VREF_BIAS_REG |
3129 RT5668_CBJ_DET_EN | RT5668_DET_TYPE_QFN);
3130 /* Set GPIO4 and GPIO8 as input for combo jack */
3131 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3132 RT5668_GP4_PIN_CONF_MASK, RT5668_GP4_PIN_CONF_INPUT);
3133 regmap_update_bits(rt5663->regmap, RT5668_GPIO_3,
3134 RT5668_GP8_PIN_CONF_MASK, RT5668_GP8_PIN_CONF_INPUT);
3135 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3136 RT5668_LDO1_DVO_MASK | RT5668_AMP_HP_MASK,
3137 RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
3138 break;
3139 case CODEC_TYPE_RT5663:
3140 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3141 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3142 msleep(20);
3143 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3144 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3145 RT5663_GP1_PIN_CONF_MASK, RT5663_GP1_PIN_CONF_OUTPUT);
3146 /* DACREF LDO control */
3147 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3148 0x3a0a);
3149 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3150 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3151 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3152 RT5663_DATA_SWAP_ADCDAT1_MASK,
3153 RT5663_DATA_SWAP_ADCDAT1_LL);
3154 break;
3155 default:
3156 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3157 }
3158
3159 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3160
3161 if (i2c->irq) {
3162 ret = request_irq(i2c->irq, rt5663_irq,
3163 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3164 | IRQF_ONESHOT, "rt5663", rt5663);
3165 if (ret)
3166 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3167 __func__, ret);
3168 }
3169
3170 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3171 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3172
3173 if (ret) {
3174 if (i2c->irq)
3175 free_irq(i2c->irq, rt5663);
3176 }
3177
3178 return ret;
3179}
3180
3181static int rt5663_i2c_remove(struct i2c_client *i2c)
3182{
3183 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3184
3185 if (i2c->irq)
3186 free_irq(i2c->irq, rt5663);
3187
3188 snd_soc_unregister_codec(&i2c->dev);
3189
3190 return 0;
3191}
3192
3193void rt5663_i2c_shutdown(struct i2c_client *client)
3194{
3195 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3196
3197 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3198}
3199
3200struct i2c_driver rt5663_i2c_driver = {
3201 .driver = {
3202 .name = "rt5663",
3203 .owner = THIS_MODULE,
3204 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3205 .of_match_table = of_match_ptr(rt5663_of_match),
3206 },
3207 .probe = rt5663_i2c_probe,
3208 .remove = rt5663_i2c_remove,
3209 .shutdown = rt5663_i2c_shutdown,
3210 .id_table = rt5663_i2c_id,
3211};
3212module_i2c_driver(rt5663_i2c_driver);
3213
3214MODULE_DESCRIPTION("ASoC RT5663 driver");
3215MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3216MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5663.h b/sound/soc/codecs/rt5663.h
new file mode 100644
index 000000000000..2cc8f28080f6
--- /dev/null
+++ b/sound/soc/codecs/rt5663.h
@@ -0,0 +1,1121 @@
1/*
2 * rt5663.h -- RT5663 ALSA SoC audio driver
3 *
4 * Copyright 2016 Realtek Microelectronics
5 * Author: Jack Yu <jack.yu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5663_H__
13#define __RT5663_H__
14
15/* Info */
16#define RT5663_RESET 0x0000
17#define RT5663_VENDOR_ID 0x00fd
18#define RT5663_VENDOR_ID_1 0x00fe
19#define RT5663_VENDOR_ID_2 0x00ff
20
21#define RT5668_LOUT_CTRL 0x0001
22#define RT5668_HP_AMP_2 0x0003
23#define RT5668_MONO_OUT 0x0004
24#define RT5668_MONO_GAIN 0x0007
25
26#define RT5668_AEC_BST 0x000b
27#define RT5668_IN1_IN2 0x000c
28#define RT5668_IN3_IN4 0x000d
29#define RT5668_INL1_INR1 0x000f
30#define RT5668_CBJ_TYPE_2 0x0011
31#define RT5668_CBJ_TYPE_3 0x0012
32#define RT5668_CBJ_TYPE_4 0x0013
33#define RT5668_CBJ_TYPE_5 0x0014
34#define RT5668_CBJ_TYPE_8 0x0017
35
36/* I/O - ADC/DAC/DMIC */
37#define RT5668_DAC3_DIG_VOL 0x001a
38#define RT5668_DAC3_CTRL 0x001b
39#define RT5668_MONO_ADC_DIG_VOL 0x001d
40#define RT5668_STO2_ADC_DIG_VOL 0x001e
41#define RT5668_MONO_ADC_BST_GAIN 0x0020
42#define RT5668_STO2_ADC_BST_GAIN 0x0021
43#define RT5668_SIDETONE_CTRL 0x0024
44/* Mixer - D-D */
45#define RT5668_MONO1_ADC_MIXER 0x0027
46#define RT5668_STO2_ADC_MIXER 0x0028
47#define RT5668_MONO_DAC_MIXER 0x002b
48#define RT5668_DAC2_SRC_CTRL 0x002e
49#define RT5668_IF_3_4_DATA_CTL 0x002f
50#define RT5668_IF_5_DATA_CTL 0x0030
51#define RT5668_PDM_OUT_CTL 0x0031
52#define RT5668_PDM_I2C_DATA_CTL1 0x0032
53#define RT5668_PDM_I2C_DATA_CTL2 0x0033
54#define RT5668_PDM_I2C_DATA_CTL3 0x0034
55#define RT5668_PDM_I2C_DATA_CTL4 0x0035
56
57/*Mixer - Analog*/
58#define RT5668_RECMIX1_NEW 0x003a
59#define RT5668_RECMIX1L_0 0x003b
60#define RT5668_RECMIX1L 0x003c
61#define RT5668_RECMIX1R_0 0x003d
62#define RT5668_RECMIX1R 0x003e
63#define RT5668_RECMIX2_NEW 0x003f
64#define RT5668_RECMIX2_L_2 0x0041
65#define RT5668_RECMIX2_R 0x0042
66#define RT5668_RECMIX2_R_2 0x0043
67#define RT5668_CALIB_REC_LR 0x0044
68#define RT5668_ALC_BK_GAIN 0x0049
69#define RT5668_MONOMIX_GAIN 0x004a
70#define RT5668_MONOMIX_IN_GAIN 0x004b
71#define RT5668_OUT_MIXL_GAIN 0x004d
72#define RT5668_OUT_LMIX_IN_GAIN 0x004e
73#define RT5668_OUT_RMIX_IN_GAIN 0x004f
74#define RT5668_OUT_RMIX_IN_GAIN1 0x0050
75#define RT5668_LOUT_MIXER_CTRL 0x0052
76/* Power */
77#define RT5668_PWR_VOL 0x0067
78
79#define RT5668_ADCDAC_RST 0x006d
80/* Format - ADC/DAC */
81#define RT5668_I2S34_SDP 0x0071
82#define RT5668_I2S5_SDP 0x0072
83/* Format - TDM Control */
84#define RT5668_TDM_5 0x007c
85#define RT5668_TDM_6 0x007d
86#define RT5668_TDM_7 0x007e
87#define RT5668_TDM_8 0x007f
88
89/* Function - Analog */
90#define RT5668_ASRC_3 0x0085
91#define RT5668_ASRC_6 0x0088
92#define RT5668_ASRC_7 0x0089
93#define RT5668_PLL_TRK_13 0x0099
94#define RT5668_I2S_M_CLK_CTL 0x00a0
95#define RT5668_FDIV_I2S34_M_CLK 0x00a1
96#define RT5668_FDIV_I2S34_M_CLK2 0x00a2
97#define RT5668_FDIV_I2S5_M_CLK 0x00a3
98#define RT5668_FDIV_I2S5_M_CLK2 0x00a4
99
100/* Function - Digital */
101#define RT5668_IRQ_4 0x00b9
102#define RT5668_GPIO_3 0x00c2
103#define RT5668_GPIO_4 0x00c3
104#define RT5668_GPIO_STA 0x00c4
105#define RT5668_HP_AMP_DET1 0x00d0
106#define RT5668_HP_AMP_DET2 0x00d1
107#define RT5668_HP_AMP_DET3 0x00d2
108#define RT5668_MID_BD_HP_AMP 0x00d3
109#define RT5668_LOW_BD_HP_AMP 0x00d4
110#define RT5668_SOF_VOL_ZC2 0x00da
111#define RT5668_ADC_STO2_ADJ1 0x00ee
112#define RT5668_ADC_STO2_ADJ2 0x00ef
113/* General Control */
114#define RT5668_A_JD_CTRL 0x00f0
115#define RT5668_JD1_TRES_CTRL 0x00f1
116#define RT5668_JD2_TRES_CTRL 0x00f2
117#define RT5668_JD_CTRL2 0x00f7
118#define RT5668_DUM_REG_2 0x00fb
119#define RT5668_DUM_REG_3 0x00fc
120
121
122#define RT5668_DACADC_DIG_VOL2 0x0101
123#define RT5668_DIG_IN_PIN2 0x0133
124#define RT5668_PAD_DRV_CTL1 0x0136
125#define RT5668_SOF_RAM_DEPOP 0x0138
126#define RT5668_VOL_TEST 0x013f
127#define RT5668_TEST_MODE_3 0x0147
128#define RT5668_TEST_MODE_4 0x0148
129#define RT5668_MONO_DYNA_1 0x0170
130#define RT5668_MONO_DYNA_2 0x0171
131#define RT5668_MONO_DYNA_3 0x0172
132#define RT5668_MONO_DYNA_4 0x0173
133#define RT5668_MONO_DYNA_5 0x0174
134#define RT5668_MONO_DYNA_6 0x0175
135#define RT5668_STO1_SIL_DET 0x0190
136#define RT5668_MONOL_SIL_DET 0x0191
137#define RT5668_MONOR_SIL_DET 0x0192
138#define RT5668_STO2_DAC_SIL 0x0193
139#define RT5668_PWR_SAV_CTL1 0x0194
140#define RT5668_PWR_SAV_CTL2 0x0195
141#define RT5668_PWR_SAV_CTL3 0x0196
142#define RT5668_PWR_SAV_CTL4 0x0197
143#define RT5668_PWR_SAV_CTL5 0x0198
144#define RT5668_PWR_SAV_CTL6 0x0199
145#define RT5668_MONO_AMP_CAL1 0x01a0
146#define RT5668_MONO_AMP_CAL2 0x01a1
147#define RT5668_MONO_AMP_CAL3 0x01a2
148#define RT5668_MONO_AMP_CAL4 0x01a3
149#define RT5668_MONO_AMP_CAL5 0x01a4
150#define RT5668_MONO_AMP_CAL6 0x01a5
151#define RT5668_MONO_AMP_CAL7 0x01a6
152#define RT5668_MONO_AMP_CAL_ST1 0x01a7
153#define RT5668_MONO_AMP_CAL_ST2 0x01a8
154#define RT5668_MONO_AMP_CAL_ST3 0x01a9
155#define RT5668_MONO_AMP_CAL_ST4 0x01aa
156#define RT5668_MONO_AMP_CAL_ST5 0x01ab
157#define RT5668_HP_IMP_SEN_13 0x01b9
158#define RT5668_HP_IMP_SEN_14 0x01ba
159#define RT5668_HP_IMP_SEN_6 0x01bb
160#define RT5668_HP_IMP_SEN_7 0x01bc
161#define RT5668_HP_IMP_SEN_8 0x01bd
162#define RT5668_HP_IMP_SEN_9 0x01be
163#define RT5668_HP_IMP_SEN_10 0x01bf
164#define RT5668_HP_LOGIC_3 0x01dc
165#define RT5668_HP_CALIB_ST10 0x01f3
166#define RT5668_HP_CALIB_ST11 0x01f4
167#define RT5668_PRO_REG_TBL_4 0x0203
168#define RT5668_PRO_REG_TBL_5 0x0204
169#define RT5668_PRO_REG_TBL_6 0x0205
170#define RT5668_PRO_REG_TBL_7 0x0206
171#define RT5668_PRO_REG_TBL_8 0x0207
172#define RT5668_PRO_REG_TBL_9 0x0208
173#define RT5668_SAR_ADC_INL_1 0x0210
174#define RT5668_SAR_ADC_INL_2 0x0211
175#define RT5668_SAR_ADC_INL_3 0x0212
176#define RT5668_SAR_ADC_INL_4 0x0213
177#define RT5668_SAR_ADC_INL_5 0x0214
178#define RT5668_SAR_ADC_INL_6 0x0215
179#define RT5668_SAR_ADC_INL_7 0x0216
180#define RT5668_SAR_ADC_INL_8 0x0217
181#define RT5668_SAR_ADC_INL_9 0x0218
182#define RT5668_SAR_ADC_INL_10 0x0219
183#define RT5668_SAR_ADC_INL_11 0x021a
184#define RT5668_SAR_ADC_INL_12 0x021b
185#define RT5668_DRC_CTRL_1 0x02ff
186#define RT5668_DRC1_CTRL_2 0x0301
187#define RT5668_DRC1_CTRL_3 0x0302
188#define RT5668_DRC1_CTRL_4 0x0303
189#define RT5668_DRC1_CTRL_5 0x0304
190#define RT5668_DRC1_CTRL_6 0x0305
191#define RT5668_DRC1_HD_CTRL_1 0x0306
192#define RT5668_DRC1_HD_CTRL_2 0x0307
193#define RT5668_DRC1_PRI_REG_1 0x0310
194#define RT5668_DRC1_PRI_REG_2 0x0311
195#define RT5668_DRC1_PRI_REG_3 0x0312
196#define RT5668_DRC1_PRI_REG_4 0x0313
197#define RT5668_DRC1_PRI_REG_5 0x0314
198#define RT5668_DRC1_PRI_REG_6 0x0315
199#define RT5668_DRC1_PRI_REG_7 0x0316
200#define RT5668_DRC1_PRI_REG_8 0x0317
201#define RT5668_ALC_PGA_CTL_1 0x0330
202#define RT5668_ALC_PGA_CTL_2 0x0331
203#define RT5668_ALC_PGA_CTL_3 0x0332
204#define RT5668_ALC_PGA_CTL_4 0x0333
205#define RT5668_ALC_PGA_CTL_5 0x0334
206#define RT5668_ALC_PGA_CTL_6 0x0335
207#define RT5668_ALC_PGA_CTL_7 0x0336
208#define RT5668_ALC_PGA_CTL_8 0x0337
209#define RT5668_ALC_PGA_REG_1 0x0338
210#define RT5668_ALC_PGA_REG_2 0x0339
211#define RT5668_ALC_PGA_REG_3 0x033a
212#define RT5668_ADC_EQ_RECOV_1 0x03c0
213#define RT5668_ADC_EQ_RECOV_2 0x03c1
214#define RT5668_ADC_EQ_RECOV_3 0x03c2
215#define RT5668_ADC_EQ_RECOV_4 0x03c3
216#define RT5668_ADC_EQ_RECOV_5 0x03c4
217#define RT5668_ADC_EQ_RECOV_6 0x03c5
218#define RT5668_ADC_EQ_RECOV_7 0x03c6
219#define RT5668_ADC_EQ_RECOV_8 0x03c7
220#define RT5668_ADC_EQ_RECOV_9 0x03c8
221#define RT5668_ADC_EQ_RECOV_10 0x03c9
222#define RT5668_ADC_EQ_RECOV_11 0x03ca
223#define RT5668_ADC_EQ_RECOV_12 0x03cb
224#define RT5668_ADC_EQ_RECOV_13 0x03cc
225#define RT5668_VID_HIDDEN 0x03fe
226#define RT5668_VID_CUSTOMER 0x03ff
227#define RT5668_SCAN_MODE 0x07f0
228#define RT5668_I2C_BYPA 0x07fa
229
230/* Headphone Amp Control 2 (0x0003) */
231#define RT5668_EN_DAC_HPO_MASK (0x1 << 14)
232#define RT5668_EN_DAC_HPO_SHIFT 14
233#define RT5668_EN_DAC_HPO_DIS (0x0 << 14)
234#define RT5668_EN_DAC_HPO_EN (0x1 << 14)
235
236/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
237#define RT5668_GAIN_HP (0x1f << 8)
238#define RT5668_GAIN_HP_SHIFT 8
239
240/* AEC BST Control (0x000b) */
241#define RT5668_GAIN_CBJ_MASK (0xf << 8)
242#define RT5668_GAIN_CBJ_SHIFT 8
243
244/* IN1 Control / MIC GND REF (0x000c) */
245#define RT5668_IN1_DF_MASK (0x1 << 15)
246#define RT5668_IN1_DF_SHIFT 15
247
248/* Combo Jack and Type Detection Control 1 (0x0010) */
249#define RT5668_CBJ_DET_MASK (0x1 << 15)
250#define RT5668_CBJ_DET_SHIFT 15
251#define RT5668_CBJ_DET_DIS (0x0 << 15)
252#define RT5668_CBJ_DET_EN (0x1 << 15)
253#define RT5668_DET_TYPE_MASK (0x1 << 12)
254#define RT5668_DET_TYPE_SHIFT 12
255#define RT5668_DET_TYPE_WLCSP (0x0 << 12)
256#define RT5668_DET_TYPE_QFN (0x1 << 12)
257#define RT5668_VREF_BIAS_MASK (0x1 << 6)
258#define RT5668_VREF_BIAS_SHIFT 6
259#define RT5668_VREF_BIAS_FSM (0x0 << 6)
260#define RT5668_VREF_BIAS_REG (0x1 << 6)
261
262/* REC Left Mixer Control 2 (0x003c) */
263#define RT5668_RECMIX1L_BST1_CBJ (0x1 << 7)
264#define RT5668_RECMIX1L_BST1_CBJ_SHIFT 7
265#define RT5668_RECMIX1L_BST2 (0x1 << 4)
266#define RT5668_RECMIX1L_BST2_SHIFT 4
267
268/* REC Right Mixer Control 2 (0x003e) */
269#define RT5668_RECMIX1R_BST2 (0x1 << 4)
270#define RT5668_RECMIX1R_BST2_SHIFT 4
271
272/* DAC1 Digital Volume (0x0019) */
273#define RT5668_DAC_L1_VOL_MASK (0xff << 8)
274#define RT5668_DAC_L1_VOL_SHIFT 8
275#define RT5668_DAC_R1_VOL_MASK (0xff)
276#define RT5668_DAC_R1_VOL_SHIFT 0
277
278/* ADC Digital Volume Control (0x001c) */
279#define RT5668_ADC_L_MUTE_MASK (0x1 << 15)
280#define RT5668_ADC_L_MUTE_SHIFT 15
281#define RT5668_ADC_L_VOL_MASK (0x7f << 8)
282#define RT5668_ADC_L_VOL_SHIFT 8
283#define RT5668_ADC_R_MUTE_MASK (0x1 << 7)
284#define RT5668_ADC_R_MUTE_SHIFT 7
285#define RT5668_ADC_R_VOL_MASK (0x7f)
286#define RT5668_ADC_R_VOL_SHIFT 0
287
288/* Stereo ADC Mixer Control (0x0026) */
289#define RT5668_M_STO1_ADC_L1 (0x1 << 15)
290#define RT5668_M_STO1_ADC_L1_SHIFT 15
291#define RT5668_M_STO1_ADC_L2 (0x1 << 14)
292#define RT5668_M_STO1_ADC_L2_SHIFT 14
293#define RT5668_STO1_ADC_L1_SRC (0x1 << 13)
294#define RT5668_STO1_ADC_L1_SRC_SHIFT 13
295#define RT5668_STO1_ADC_L2_SRC (0x1 << 12)
296#define RT5668_STO1_ADC_L2_SRC_SHIFT 12
297#define RT5668_STO1_ADC_L_SRC (0x3 << 10)
298#define RT5668_STO1_ADC_L_SRC_SHIFT 10
299#define RT5668_M_STO1_ADC_R1 (0x1 << 7)
300#define RT5668_M_STO1_ADC_R1_SHIFT 7
301#define RT5668_M_STO1_ADC_R2 (0x1 << 6)
302#define RT5668_M_STO1_ADC_R2_SHIFT 6
303#define RT5668_STO1_ADC_R1_SRC (0x1 << 5)
304#define RT5668_STO1_ADC_R1_SRC_SHIFT 5
305#define RT5668_STO1_ADC_R2_SRC (0x1 << 4)
306#define RT5668_STO1_ADC_R2_SRC_SHIFT 4
307#define RT5668_STO1_ADC_R_SRC (0x3 << 2)
308#define RT5668_STO1_ADC_R_SRC_SHIFT 2
309
310/* ADC Mixer to DAC Mixer Control (0x0029) */
311#define RT5668_M_ADCMIX_L (0x1 << 15)
312#define RT5668_M_ADCMIX_L_SHIFT 15
313#define RT5668_M_DAC1_L (0x1 << 14)
314#define RT5668_M_DAC1_L_SHIFT 14
315#define RT5668_M_ADCMIX_R (0x1 << 7)
316#define RT5668_M_ADCMIX_R_SHIFT 7
317#define RT5668_M_DAC1_R (0x1 << 6)
318#define RT5668_M_DAC1_R_SHIFT 6
319
320/* Stereo DAC Mixer Control (0x002a) */
321#define RT5668_M_DAC_L1_STO_L (0x1 << 15)
322#define RT5668_M_DAC_L1_STO_L_SHIFT 15
323#define RT5668_M_DAC_R1_STO_L (0x1 << 13)
324#define RT5668_M_DAC_R1_STO_L_SHIFT 13
325#define RT5668_M_DAC_L1_STO_R (0x1 << 7)
326#define RT5668_M_DAC_L1_STO_R_SHIFT 7
327#define RT5668_M_DAC_R1_STO_R (0x1 << 5)
328#define RT5668_M_DAC_R1_STO_R_SHIFT 5
329
330/* Power Management for Digital 1 (0x0061) */
331#define RT5668_PWR_I2S1 (0x1 << 15)
332#define RT5668_PWR_I2S1_SHIFT 15
333#define RT5668_PWR_DAC_L1 (0x1 << 11)
334#define RT5668_PWR_DAC_L1_SHIFT 11
335#define RT5668_PWR_DAC_R1 (0x1 << 10)
336#define RT5668_PWR_DAC_R1_SHIFT 10
337#define RT5668_PWR_LDO_DACREF_MASK (0x1 << 8)
338#define RT5668_PWR_LDO_DACREF_SHIFT 8
339#define RT5668_PWR_LDO_DACREF_ON (0x1 << 8)
340#define RT5668_PWR_LDO_DACREF_DOWN (0x0 << 8)
341#define RT5668_PWR_LDO_SHIFT 8
342#define RT5668_PWR_ADC_L1 (0x1 << 4)
343#define RT5668_PWR_ADC_L1_SHIFT 4
344#define RT5668_PWR_ADC_R1 (0x1 << 3)
345#define RT5668_PWR_ADC_R1_SHIFT 3
346
347/* Power Management for Digital 2 (0x0062) */
348#define RT5668_PWR_ADC_S1F (0x1 << 15)
349#define RT5668_PWR_ADC_S1F_SHIFT 15
350#define RT5668_PWR_DAC_S1F (0x1 << 10)
351#define RT5668_PWR_DAC_S1F_SHIFT 10
352
353/* Power Management for Analog 1 (0x0063) */
354#define RT5668_PWR_VREF1 (0x1 << 15)
355#define RT5668_PWR_VREF1_MASK (0x1 << 15)
356#define RT5668_PWR_VREF1_SHIFT 15
357#define RT5668_PWR_FV1 (0x1 << 14)
358#define RT5668_PWR_FV1_MASK (0x1 << 14)
359#define RT5668_PWR_FV1_SHIFT 14
360#define RT5668_PWR_VREF2 (0x1 << 13)
361#define RT5668_PWR_VREF2_MASK (0x1 << 13)
362#define RT5668_PWR_VREF2_SHIFT 13
363#define RT5668_PWR_FV2 (0x1 << 12)
364#define RT5668_PWR_FV2_MASK (0x1 << 12)
365#define RT5668_PWR_FV2_SHIFT 12
366#define RT5668_PWR_MB (0x1 << 9)
367#define RT5668_PWR_MB_MASK (0x1 << 9)
368#define RT5668_PWR_MB_SHIFT 9
369#define RT5668_AMP_HP_MASK (0x3 << 2)
370#define RT5668_AMP_HP_SHIFT 2
371#define RT5668_AMP_HP_1X (0x0 << 2)
372#define RT5668_AMP_HP_3X (0x1 << 2)
373#define RT5668_AMP_HP_5X (0x3 << 2)
374#define RT5668_LDO1_DVO_MASK (0x3)
375#define RT5668_LDO1_DVO_SHIFT 0
376#define RT5668_LDO1_DVO_0_9V (0x0)
377#define RT5668_LDO1_DVO_1_0V (0x1)
378#define RT5668_LDO1_DVO_1_2V (0x2)
379#define RT5668_LDO1_DVO_1_4V (0x3)
380
381/* Power Management for Analog 2 (0x0064) */
382#define RT5668_PWR_BST1 (0x1 << 15)
383#define RT5668_PWR_BST1_MASK (0x1 << 15)
384#define RT5668_PWR_BST1_SHIFT 15
385#define RT5668_PWR_BST1_OFF (0x0 << 15)
386#define RT5668_PWR_BST1_ON (0x1 << 15)
387#define RT5668_PWR_BST2 (0x1 << 14)
388#define RT5668_PWR_BST2_MASK (0x1 << 14)
389#define RT5668_PWR_BST2_SHIFT 14
390#define RT5668_PWR_MB1 (0x1 << 11)
391#define RT5668_PWR_MB1_SHIFT 11
392#define RT5668_PWR_MB2 (0x1 << 10)
393#define RT5668_PWR_MB2_SHIFT 10
394#define RT5668_PWR_BST2_OP (0x1 << 6)
395#define RT5668_PWR_BST2_OP_MASK (0x1 << 6)
396#define RT5668_PWR_BST2_OP_SHIFT 6
397#define RT5668_PWR_JD1 (0x1 << 3)
398#define RT5668_PWR_JD1_MASK (0x1 << 3)
399#define RT5668_PWR_JD1_SHIFT 3
400#define RT5668_PWR_JD2 (0x1 << 2)
401#define RT5668_PWR_JD2_MASK (0x1 << 2)
402#define RT5668_PWR_JD2_SHIFT 2
403#define RT5668_PWR_RECMIX1 (0x1 << 1)
404#define RT5668_PWR_RECMIX1_SHIFT 1
405#define RT5668_PWR_RECMIX2 (0x1)
406#define RT5668_PWR_RECMIX2_SHIFT 0
407
408/* Power Management for Analog 3 (0x0065) */
409#define RT5668_PWR_CBJ_MASK (0x1 << 9)
410#define RT5668_PWR_CBJ_SHIFT 9
411#define RT5668_PWR_CBJ_OFF (0x0 << 9)
412#define RT5668_PWR_CBJ_ON (0x1 << 9)
413#define RT5668_PWR_PLL (0x1 << 6)
414#define RT5668_PWR_PLL_SHIFT 6
415#define RT5668_PWR_LDO2 (0x1 << 2)
416#define RT5668_PWR_LDO2_SHIFT 2
417
418/* Power Management for Volume (0x0067) */
419#define RT5668_PWR_MIC_DET (0x1 << 5)
420#define RT5668_PWR_MIC_DET_SHIFT 5
421
422/* MCLK and System Clock Detection Control (0x006b) */
423#define RT5668_EN_ANA_CLK_DET_MASK (0x1 << 15)
424#define RT5668_EN_ANA_CLK_DET_SHIFT 15
425#define RT5668_EN_ANA_CLK_DET_DIS (0x0 << 15)
426#define RT5668_EN_ANA_CLK_DET_AUTO (0x1 << 15)
427#define RT5668_PWR_CLK_DET_MASK (0x1)
428#define RT5668_PWR_CLK_DET_SHIFT 0
429#define RT5668_PWR_CLK_DET_DIS (0x0)
430#define RT5668_PWR_CLK_DET_EN (0x1)
431
432/* I2S1 Audio Serial Data Port Control (0x0070) */
433#define RT5668_I2S_MS_MASK (0x1 << 15)
434#define RT5668_I2S_MS_SHIFT 15
435#define RT5668_I2S_MS_M (0x0 << 15)
436#define RT5668_I2S_MS_S (0x1 << 15)
437#define RT5668_I2S_BP_MASK (0x1 << 8)
438#define RT5668_I2S_BP_SHIFT 8
439#define RT5668_I2S_BP_NOR (0x0 << 8)
440#define RT5668_I2S_BP_INV (0x1 << 8)
441#define RT5668_I2S_DL_MASK (0x3 << 4)
442#define RT5668_I2S_DL_SHIFT 4
443#define RT5668_I2S_DL_16 (0x0 << 4)
444#define RT5668_I2S_DL_20 (0x1 << 4)
445#define RT5668_I2S_DL_24 (0x2 << 4)
446#define RT5668_I2S_DL_8 (0x3 << 4)
447#define RT5668_I2S_DF_MASK (0x7)
448#define RT5668_I2S_DF_SHIFT 0
449#define RT5668_I2S_DF_I2S (0x0)
450#define RT5668_I2S_DF_LEFT (0x1)
451#define RT5668_I2S_DF_PCM_A (0x2)
452#define RT5668_I2S_DF_PCM_B (0x3)
453#define RT5668_I2S_DF_PCM_A_N (0x6)
454#define RT5668_I2S_DF_PCM_B_N (0x7)
455
456/* ADC/DAC Clock Control 1 (0x0073) */
457#define RT5668_I2S_PD1_MASK (0x7 << 12)
458#define RT5668_I2S_PD1_SHIFT 12
459#define RT5668_M_I2S_DIV_MASK (0x7 << 8)
460#define RT5668_M_I2S_DIV_SHIFT 8
461#define RT5668_CLK_SRC_MASK (0x3 << 4)
462#define RT5668_CLK_SRC_MCLK (0x0 << 4)
463#define RT5668_CLK_SRC_PLL_OUT (0x1 << 4)
464#define RT5668_CLK_SRC_DIV (0x2 << 4)
465#define RT5668_CLK_SRC_RC (0x3 << 4)
466#define RT5668_DAC_OSR_MASK (0x3 << 2)
467#define RT5668_DAC_OSR_SHIFT 2
468#define RT5668_DAC_OSR_128 (0x0 << 2)
469#define RT5668_DAC_OSR_64 (0x1 << 2)
470#define RT5668_DAC_OSR_32 (0x2 << 2)
471#define RT5668_ADC_OSR_MASK (0x3)
472#define RT5668_ADC_OSR_SHIFT 0
473#define RT5668_ADC_OSR_128 (0x0)
474#define RT5668_ADC_OSR_64 (0x1)
475#define RT5668_ADC_OSR_32 (0x2)
476
477/* TDM1 control 1 (0x0078) */
478#define RT5668_TDM_MODE_MASK (0x1 << 15)
479#define RT5668_TDM_MODE_SHIFT 15
480#define RT5668_TDM_MODE_I2S (0x0 << 15)
481#define RT5668_TDM_MODE_TDM (0x1 << 15)
482#define RT5668_TDM_IN_CH_MASK (0x3 << 10)
483#define RT5668_TDM_IN_CH_SHIFT 10
484#define RT5668_TDM_IN_CH_2 (0x0 << 10)
485#define RT5668_TDM_IN_CH_4 (0x1 << 10)
486#define RT5668_TDM_IN_CH_6 (0x2 << 10)
487#define RT5668_TDM_IN_CH_8 (0x3 << 10)
488#define RT5668_TDM_OUT_CH_MASK (0x3 << 8)
489#define RT5668_TDM_OUT_CH_SHIFT 8
490#define RT5668_TDM_OUT_CH_2 (0x0 << 8)
491#define RT5668_TDM_OUT_CH_4 (0x1 << 8)
492#define RT5668_TDM_OUT_CH_6 (0x2 << 8)
493#define RT5668_TDM_OUT_CH_8 (0x3 << 8)
494#define RT5668_TDM_IN_LEN_MASK (0x3 << 6)
495#define RT5668_TDM_IN_LEN_SHIFT 6
496#define RT5668_TDM_IN_LEN_16 (0x0 << 6)
497#define RT5668_TDM_IN_LEN_20 (0x1 << 6)
498#define RT5668_TDM_IN_LEN_24 (0x2 << 6)
499#define RT5668_TDM_IN_LEN_32 (0x3 << 6)
500#define RT5668_TDM_OUT_LEN_MASK (0x3 << 4)
501#define RT5668_TDM_OUT_LEN_SHIFT 4
502#define RT5668_TDM_OUT_LEN_16 (0x0 << 4)
503#define RT5668_TDM_OUT_LEN_20 (0x1 << 4)
504#define RT5668_TDM_OUT_LEN_24 (0x2 << 4)
505#define RT5668_TDM_OUT_LEN_32 (0x3 << 4)
506
507/* Global Clock Control (0x0080) */
508#define RT5668_SCLK_SRC_MASK (0x3 << 14)
509#define RT5668_SCLK_SRC_SHIFT 14
510#define RT5668_SCLK_SRC_MCLK (0x0 << 14)
511#define RT5668_SCLK_SRC_PLL1 (0x1 << 14)
512#define RT5668_SCLK_SRC_RCCLK (0x2 << 14)
513#define RT5668_PLL1_SRC_MASK (0x7 << 8)
514#define RT5668_PLL1_SRC_SHIFT 8
515#define RT5668_PLL1_SRC_MCLK (0x0 << 8)
516#define RT5668_PLL1_SRC_BCLK1 (0x1 << 8)
517#define RT5668_PLL1_PD_MASK (0x1 << 4)
518#define RT5668_PLL1_PD_SHIFT 4
519
520#define RT5668_PLL_INP_MAX 40000000
521#define RT5668_PLL_INP_MIN 256000
522/* PLL M/N/K Code Control 1 (0x0081) */
523#define RT5668_PLL_N_MAX 0x001ff
524#define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7)
525#define RT5668_PLL_N_SHIFT 7
526#define RT5668_PLL_K_MAX 0x001f
527#define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX)
528#define RT5668_PLL_K_SHIFT 0
529
530/* PLL M/N/K Code Control 2 (0x0082) */
531#define RT5668_PLL_M_MAX 0x00f
532#define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)
533#define RT5668_PLL_M_SHIFT 12
534#define RT5668_PLL_M_BP (0x1 << 11)
535#define RT5668_PLL_M_BP_SHIFT 11
536
537/* PLL tracking mode 1 (0x0083) */
538#define RT5668_I2S1_ASRC_MASK (0x1 << 13)
539#define RT5668_I2S1_ASRC_SHIFT 13
540#define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
541#define RT5668_DAC_STO1_ASRC_SHIFT 12
542#define RT5668_ADC_STO1_ASRC_MASK (0x1 << 4)
543#define RT5668_ADC_STO1_ASRC_SHIFT 4
544
545/* PLL tracking mode 2 (0x0084)*/
546#define RT5668_DA_STO1_TRACK_MASK (0x7 << 12)
547#define RT5668_DA_STO1_TRACK_SHIFT 12
548#define RT5668_DA_STO1_TRACK_SYSCLK (0x0 << 12)
549#define RT5668_DA_STO1_TRACK_I2S1 (0x1 << 12)
550
551/* PLL tracking mode 3 (0x0085)*/
552#define RT5668_AD_STO1_TRACK_MASK (0x7 << 12)
553#define RT5668_AD_STO1_TRACK_SHIFT 12
554#define RT5668_AD_STO1_TRACK_SYSCLK (0x0 << 12)
555#define RT5668_AD_STO1_TRACK_I2S1 (0x1 << 12)
556
557/* HPOUT Charge pump control 1 (0x0091) */
558#define RT5668_OSW_HP_L_MASK (0x1 << 11)
559#define RT5668_OSW_HP_L_SHIFT 11
560#define RT5668_OSW_HP_L_EN (0x1 << 11)
561#define RT5668_OSW_HP_L_DIS (0x0 << 11)
562#define RT5668_OSW_HP_R_MASK (0x1 << 10)
563#define RT5668_OSW_HP_R_SHIFT 10
564#define RT5668_OSW_HP_R_EN (0x1 << 10)
565#define RT5668_OSW_HP_R_DIS (0x0 << 10)
566#define RT5668_SEL_PM_HP_MASK (0x3 << 8)
567#define RT5668_SEL_PM_HP_SHIFT 8
568#define RT5668_SEL_PM_HP_0_6 (0x0 << 8)
569#define RT5668_SEL_PM_HP_0_9 (0x1 << 8)
570#define RT5668_SEL_PM_HP_1_8 (0x2 << 8)
571#define RT5668_SEL_PM_HP_HIGH (0x3 << 8)
572#define RT5668_OVCD_HP_MASK (0x1 << 2)
573#define RT5668_OVCD_HP_SHIFT 2
574#define RT5668_OVCD_HP_EN (0x1 << 2)
575#define RT5668_OVCD_HP_DIS (0x0 << 2)
576
577/* RC Clock Control (0x0094) */
578#define RT5668_DIG_25M_CLK_MASK (0x1 << 9)
579#define RT5668_DIG_25M_CLK_SHIFT 9
580#define RT5668_DIG_25M_CLK_DIS (0x0 << 9)
581#define RT5668_DIG_25M_CLK_EN (0x1 << 9)
582#define RT5668_DIG_1M_CLK_MASK (0x1 << 8)
583#define RT5668_DIG_1M_CLK_SHIFT 8
584#define RT5668_DIG_1M_CLK_DIS (0x0 << 8)
585#define RT5668_DIG_1M_CLK_EN (0x1 << 8)
586
587/* Auto Turn On 1M RC CLK (0x009f) */
588#define RT5668_IRQ_POW_SAV_MASK (0x1 << 15)
589#define RT5668_IRQ_POW_SAV_SHIFT 15
590#define RT5668_IRQ_POW_SAV_DIS (0x0 << 15)
591#define RT5668_IRQ_POW_SAV_EN (0x1 << 15)
592#define RT5668_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
593#define RT5668_IRQ_POW_SAV_JD1_SHIFT 14
594#define RT5668_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
595#define RT5668_IRQ_POW_SAV_JD1_EN (0x1 << 14)
596
597/* IRQ Control 1 (0x00b6) */
598#define RT5668_EN_CB_JD_MASK (0x1 << 3)
599#define RT5668_EN_CB_JD_SHIFT 3
600#define RT5668_EN_CB_JD_EN (0x1 << 3)
601#define RT5668_EN_CB_JD_DIS (0x0 << 3)
602
603/* IRQ Control 3 (0x00b8) */
604#define RT5668_EN_IRQ_INLINE_MASK (0x1 << 6)
605#define RT5668_EN_IRQ_INLINE_SHIFT 6
606#define RT5668_EN_IRQ_INLINE_BYP (0x0 << 6)
607#define RT5668_EN_IRQ_INLINE_NOR (0x1 << 6)
608
609/* GPIO Control 1 (0x00c0) */
610#define RT5668_GP1_PIN_MASK (0x1 << 15)
611#define RT5668_GP1_PIN_SHIFT 15
612#define RT5668_GP1_PIN_GPIO1 (0x0 << 15)
613#define RT5668_GP1_PIN_IRQ (0x1 << 15)
614
615/* GPIO Control 2 (0x00c1) */
616#define RT5668_GP4_PIN_CONF_MASK (0x1 << 5)
617#define RT5668_GP4_PIN_CONF_SHIFT 5
618#define RT5668_GP4_PIN_CONF_INPUT (0x0 << 5)
619#define RT5668_GP4_PIN_CONF_OUTPUT (0x1 << 5)
620
621/* GPIO Control 2 (0x00c2) */
622#define RT5668_GP8_PIN_CONF_MASK (0x1 << 13)
623#define RT5668_GP8_PIN_CONF_SHIFT 13
624#define RT5668_GP8_PIN_CONF_INPUT (0x0 << 13)
625#define RT5668_GP8_PIN_CONF_OUTPUT (0x1 << 13)
626
627/* 4 Buttons Inline Command Function 1 (0x00df) */
628#define RT5668_4BTN_CLK_DEB_MASK (0x3 << 2)
629#define RT5668_4BTN_CLK_DEB_SHIFT 2
630#define RT5668_4BTN_CLK_DEB_8MS (0x0 << 2)
631#define RT5668_4BTN_CLK_DEB_16MS (0x1 << 2)
632#define RT5668_4BTN_CLK_DEB_32MS (0x2 << 2)
633#define RT5668_4BTN_CLK_DEB_65MS (0x3 << 2)
634
635/* Inline Command Function 6 (0x00e0) */
636#define RT5668_EN_4BTN_INL_MASK (0x1 << 15)
637#define RT5668_EN_4BTN_INL_SHIFT 15
638#define RT5668_EN_4BTN_INL_DIS (0x0 << 15)
639#define RT5668_EN_4BTN_INL_EN (0x1 << 15)
640#define RT5668_RESET_4BTN_INL_MASK (0x1 << 14)
641#define RT5668_RESET_4BTN_INL_SHIFT 14
642#define RT5668_RESET_4BTN_INL_RESET (0x0 << 14)
643#define RT5668_RESET_4BTN_INL_NOR (0x1 << 14)
644
645/* Digital Misc Control (0x00fa) */
646#define RT5668_DIG_GATE_CTRL_MASK 0x1
647#define RT5668_DIG_GATE_CTRL_SHIFT (0)
648#define RT5668_DIG_GATE_CTRL_DIS 0x0
649#define RT5668_DIG_GATE_CTRL_EN 0x1
650
651/* Chopper and Clock control for DAC L (0x013a)*/
652#define RT5668_CKXEN_DAC1_MASK (0x1 << 13)
653#define RT5668_CKXEN_DAC1_SHIFT 13
654#define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
655#define RT5668_CKGEN_DAC1_SHIFT 12
656
657/* Chopper and Clock control for ADC (0x013b)*/
658#define RT5668_CKXEN_ADCC_MASK (0x1 << 13)
659#define RT5668_CKXEN_ADCC_SHIFT 13
660#define RT5668_CKGEN_ADCC_MASK (0x1 << 12)
661#define RT5668_CKGEN_ADCC_SHIFT 12
662
663/* HP Behavior Logic Control 2 (0x01db) */
664#define RT5668_HP_SIG_SRC1_MASK (0x3)
665#define RT5668_HP_SIG_SRC1_SHIFT 0
666#define RT5668_HP_SIG_SRC1_HP_DC (0x0)
667#define RT5668_HP_SIG_SRC1_HP_CALIB (0x1)
668#define RT5668_HP_SIG_SRC1_REG (0x2)
669#define RT5668_HP_SIG_SRC1_SILENCE (0x3)
670
671/* RT5663 specific register */
672#define RT5663_HP_OUT_EN 0x0002
673#define RT5663_HP_LCH_DRE 0x0005
674#define RT5663_HP_RCH_DRE 0x0006
675#define RT5663_CALIB_BST 0x000a
676#define RT5663_RECMIX 0x0010
677#define RT5663_SIL_DET_CTL 0x0015
678#define RT5663_PWR_SAV_SILDET 0x0016
679#define RT5663_SIDETONE_CTL 0x0018
680#define RT5663_STO1_DAC_DIG_VOL 0x0019
681#define RT5663_STO1_ADC_DIG_VOL 0x001c
682#define RT5663_STO1_BOOST 0x001f
683#define RT5663_HP_IMP_GAIN_1 0x0022
684#define RT5663_HP_IMP_GAIN_2 0x0023
685#define RT5663_STO1_ADC_MIXER 0x0026
686#define RT5663_AD_DA_MIXER 0x0029
687#define RT5663_STO_DAC_MIXER 0x002a
688#define RT5663_DIG_SIDE_MIXER 0x002c
689#define RT5663_BYPASS_STO_DAC 0x002d
690#define RT5663_CALIB_REC_MIX 0x0040
691#define RT5663_PWR_DIG_1 0x0061
692#define RT5663_PWR_DIG_2 0x0062
693#define RT5663_PWR_ANLG_1 0x0063
694#define RT5663_PWR_ANLG_2 0x0064
695#define RT5663_PWR_ANLG_3 0x0065
696#define RT5663_PWR_MIXER 0x0066
697#define RT5663_SIG_CLK_DET 0x006b
698#define RT5663_PRE_DIV_GATING_1 0x006e
699#define RT5663_PRE_DIV_GATING_2 0x006f
700#define RT5663_I2S1_SDP 0x0070
701#define RT5663_ADDA_CLK_1 0x0073
702#define RT5663_ADDA_RST 0x0074
703#define RT5663_FRAC_DIV_1 0x0075
704#define RT5663_FRAC_DIV_2 0x0076
705#define RT5663_TDM_1 0x0077
706#define RT5663_TDM_2 0x0078
707#define RT5663_TDM_3 0x0079
708#define RT5663_TDM_4 0x007a
709#define RT5663_TDM_5 0x007b
710#define RT5663_GLB_CLK 0x0080
711#define RT5663_PLL_1 0x0081
712#define RT5663_PLL_2 0x0082
713#define RT5663_ASRC_1 0x0083
714#define RT5663_ASRC_2 0x0084
715#define RT5663_ASRC_4 0x0086
716#define RT5663_DUMMY_REG 0x0087
717#define RT5663_ASRC_8 0x008a
718#define RT5663_ASRC_9 0x008b
719#define RT5663_ASRC_11 0x008c
720#define RT5663_DEPOP_1 0x008e
721#define RT5663_DEPOP_2 0x008f
722#define RT5663_DEPOP_3 0x0090
723#define RT5663_HP_CHARGE_PUMP_1 0x0091
724#define RT5663_HP_CHARGE_PUMP_2 0x0092
725#define RT5663_MICBIAS_1 0x0093
726#define RT5663_RC_CLK 0x0094
727#define RT5663_ASRC_11_2 0x0097
728#define RT5663_DUMMY_REG_2 0x0098
729#define RT5663_REC_PATH_GAIN 0x009a
730#define RT5663_AUTO_1MRC_CLK 0x009f
731#define RT5663_ADC_EQ_1 0x00ae
732#define RT5663_ADC_EQ_2 0x00af
733#define RT5663_IRQ_1 0x00b6
734#define RT5663_IRQ_2 0x00b7
735#define RT5663_IRQ_3 0x00b8
736#define RT5663_IRQ_4 0x00ba
737#define RT5663_IRQ_5 0x00bb
738#define RT5663_INT_ST_1 0x00be
739#define RT5663_INT_ST_2 0x00bf
740#define RT5663_GPIO_1 0x00c0
741#define RT5663_GPIO_2 0x00c1
742#define RT5663_GPIO_STA 0x00c5
743#define RT5663_SIN_GEN_1 0x00cb
744#define RT5663_SIN_GEN_2 0x00cc
745#define RT5663_SIN_GEN_3 0x00cd
746#define RT5663_SOF_VOL_ZC1 0x00d9
747#define RT5663_IL_CMD_1 0x00db
748#define RT5663_IL_CMD_2 0x00dc
749#define RT5663_IL_CMD_3 0x00dd
750#define RT5663_IL_CMD_4 0x00de
751#define RT5663_IL_CMD_5 0x00df
752#define RT5663_IL_CMD_6 0x00e0
753#define RT5663_IL_CMD_7 0x00e1
754#define RT5663_IL_CMD_8 0x00e2
755#define RT5663_IL_CMD_PWRSAV1 0x00e4
756#define RT5663_IL_CMD_PWRSAV2 0x00e5
757#define RT5663_EM_JACK_TYPE_1 0x00e6
758#define RT5663_EM_JACK_TYPE_2 0x00e7
759#define RT5663_EM_JACK_TYPE_3 0x00e8
760#define RT5663_EM_JACK_TYPE_4 0x00e9
761#define RT5663_EM_JACK_TYPE_5 0x00ea
762#define RT5663_EM_JACK_TYPE_6 0x00eb
763#define RT5663_STO1_HPF_ADJ1 0x00ec
764#define RT5663_STO1_HPF_ADJ2 0x00ed
765#define RT5663_FAST_OFF_MICBIAS 0x00f4
766#define RT5663_JD_CTRL1 0x00f6
767#define RT5663_JD_CTRL2 0x00f8
768#define RT5663_DIG_MISC 0x00fa
769#define RT5663_DIG_VOL_ZCD 0x0100
770#define RT5663_ANA_BIAS_CUR_1 0x0108
771#define RT5663_ANA_BIAS_CUR_2 0x0109
772#define RT5663_ANA_BIAS_CUR_3 0x010a
773#define RT5663_ANA_BIAS_CUR_4 0x010b
774#define RT5663_ANA_BIAS_CUR_5 0x010c
775#define RT5663_ANA_BIAS_CUR_6 0x010d
776#define RT5663_BIAS_CUR_5 0x010e
777#define RT5663_BIAS_CUR_6 0x010f
778#define RT5663_BIAS_CUR_7 0x0110
779#define RT5663_BIAS_CUR_8 0x0111
780#define RT5663_DACREF_LDO 0x0112
781#define RT5663_DUMMY_REG_3 0x0113
782#define RT5663_BIAS_CUR_9 0x0114
783#define RT5663_DUMMY_REG_4 0x0116
784#define RT5663_VREFADJ_OP 0x0117
785#define RT5663_VREF_RECMIX 0x0118
786#define RT5663_CHARGE_PUMP_1 0x0125
787#define RT5663_CHARGE_PUMP_1_2 0x0126
788#define RT5663_CHARGE_PUMP_1_3 0x0127
789#define RT5663_CHARGE_PUMP_2 0x0128
790#define RT5663_DIG_IN_PIN1 0x0132
791#define RT5663_PAD_DRV_CTL 0x0137
792#define RT5663_PLL_INT_REG 0x0139
793#define RT5663_CHOP_DAC_L 0x013a
794#define RT5663_CHOP_ADC 0x013b
795#define RT5663_CALIB_ADC 0x013c
796#define RT5663_CHOP_DAC_R 0x013d
797#define RT5663_DUMMY_CTL_DACLR 0x013e
798#define RT5663_DUMMY_REG_5 0x0140
799#define RT5663_SOFT_RAMP 0x0141
800#define RT5663_TEST_MODE_1 0x0144
801#define RT5663_TEST_MODE_2 0x0145
802#define RT5663_TEST_MODE_3 0x0146
803#define RT5663_STO_DRE_1 0x0160
804#define RT5663_STO_DRE_2 0x0161
805#define RT5663_STO_DRE_3 0x0162
806#define RT5663_STO_DRE_4 0x0163
807#define RT5663_STO_DRE_5 0x0164
808#define RT5663_STO_DRE_6 0x0165
809#define RT5663_STO_DRE_7 0x0166
810#define RT5663_STO_DRE_8 0x0167
811#define RT5663_STO_DRE_9 0x0168
812#define RT5663_STO_DRE_10 0x0169
813#define RT5663_MIC_DECRO_1 0x0180
814#define RT5663_MIC_DECRO_2 0x0181
815#define RT5663_MIC_DECRO_3 0x0182
816#define RT5663_MIC_DECRO_4 0x0183
817#define RT5663_MIC_DECRO_5 0x0184
818#define RT5663_MIC_DECRO_6 0x0185
819#define RT5663_HP_DECRO_1 0x01b0
820#define RT5663_HP_DECRO_2 0x01b1
821#define RT5663_HP_DECRO_3 0x01b2
822#define RT5663_HP_DECRO_4 0x01b3
823#define RT5663_HP_DECOUP 0x01b4
824#define RT5663_HP_IMP_SEN_MAP8 0x01b5
825#define RT5663_HP_IMP_SEN_MAP9 0x01b6
826#define RT5663_HP_IMP_SEN_MAP10 0x01b7
827#define RT5663_HP_IMP_SEN_MAP11 0x01b8
828#define RT5663_HP_IMP_SEN_1 0x01c0
829#define RT5663_HP_IMP_SEN_2 0x01c1
830#define RT5663_HP_IMP_SEN_3 0x01c2
831#define RT5663_HP_IMP_SEN_4 0x01c3
832#define RT5663_HP_IMP_SEN_5 0x01c4
833#define RT5663_HP_IMP_SEN_6 0x01c5
834#define RT5663_HP_IMP_SEN_7 0x01c6
835#define RT5663_HP_IMP_SEN_8 0x01c7
836#define RT5663_HP_IMP_SEN_9 0x01c8
837#define RT5663_HP_IMP_SEN_10 0x01c9
838#define RT5663_HP_IMP_SEN_11 0x01ca
839#define RT5663_HP_IMP_SEN_12 0x01cb
840#define RT5663_HP_IMP_SEN_13 0x01cc
841#define RT5663_HP_IMP_SEN_14 0x01cd
842#define RT5663_HP_IMP_SEN_15 0x01ce
843#define RT5663_HP_IMP_SEN_16 0x01cf
844#define RT5663_HP_IMP_SEN_17 0x01d0
845#define RT5663_HP_IMP_SEN_18 0x01d1
846#define RT5663_HP_IMP_SEN_19 0x01d2
847#define RT5663_HP_IMPSEN_DIG5 0x01d3
848#define RT5663_HP_IMPSEN_MAP1 0x01d4
849#define RT5663_HP_IMPSEN_MAP2 0x01d5
850#define RT5663_HP_IMPSEN_MAP3 0x01d6
851#define RT5663_HP_IMPSEN_MAP4 0x01d7
852#define RT5663_HP_IMPSEN_MAP5 0x01d8
853#define RT5663_HP_IMPSEN_MAP7 0x01d9
854#define RT5663_HP_LOGIC_1 0x01da
855#define RT5663_HP_LOGIC_2 0x01db
856#define RT5663_HP_CALIB_1 0x01dd
857#define RT5663_HP_CALIB_1_1 0x01de
858#define RT5663_HP_CALIB_2 0x01df
859#define RT5663_HP_CALIB_3 0x01e0
860#define RT5663_HP_CALIB_4 0x01e1
861#define RT5663_HP_CALIB_5 0x01e2
862#define RT5663_HP_CALIB_5_1 0x01e3
863#define RT5663_HP_CALIB_6 0x01e4
864#define RT5663_HP_CALIB_7 0x01e5
865#define RT5663_HP_CALIB_9 0x01e6
866#define RT5663_HP_CALIB_10 0x01e7
867#define RT5663_HP_CALIB_11 0x01e8
868#define RT5663_HP_CALIB_ST1 0x01ea
869#define RT5663_HP_CALIB_ST2 0x01eb
870#define RT5663_HP_CALIB_ST3 0x01ec
871#define RT5663_HP_CALIB_ST4 0x01ed
872#define RT5663_HP_CALIB_ST5 0x01ee
873#define RT5663_HP_CALIB_ST6 0x01ef
874#define RT5663_HP_CALIB_ST7 0x01f0
875#define RT5663_HP_CALIB_ST8 0x01f1
876#define RT5663_HP_CALIB_ST9 0x01f2
877#define RT5663_HP_AMP_DET 0x0200
878#define RT5663_DUMMY_REG_6 0x0201
879#define RT5663_HP_BIAS 0x0202
880#define RT5663_CBJ_1 0x0250
881#define RT5663_CBJ_2 0x0251
882#define RT5663_CBJ_3 0x0252
883#define RT5663_DUMMY_1 0x02fa
884#define RT5663_DUMMY_2 0x02fb
885#define RT5663_DUMMY_3 0x02fc
886#define RT5663_ANA_JD 0x0300
887#define RT5663_ADC_LCH_LPF1_A1 0x03d0
888#define RT5663_ADC_RCH_LPF1_A1 0x03d1
889#define RT5663_ADC_LCH_LPF1_H0 0x03d2
890#define RT5663_ADC_RCH_LPF1_H0 0x03d3
891#define RT5663_ADC_LCH_BPF1_A1 0x03d4
892#define RT5663_ADC_RCH_BPF1_A1 0x03d5
893#define RT5663_ADC_LCH_BPF1_A2 0x03d6
894#define RT5663_ADC_RCH_BPF1_A2 0x03d7
895#define RT5663_ADC_LCH_BPF1_H0 0x03d8
896#define RT5663_ADC_RCH_BPF1_H0 0x03d9
897#define RT5663_ADC_LCH_BPF2_A1 0x03da
898#define RT5663_ADC_RCH_BPF2_A1 0x03db
899#define RT5663_ADC_LCH_BPF2_A2 0x03dc
900#define RT5663_ADC_RCH_BPF2_A2 0x03dd
901#define RT5663_ADC_LCH_BPF2_H0 0x03de
902#define RT5663_ADC_RCH_BPF2_H0 0x03df
903#define RT5663_ADC_LCH_BPF3_A1 0x03e0
904#define RT5663_ADC_RCH_BPF3_A1 0x03e1
905#define RT5663_ADC_LCH_BPF3_A2 0x03e2
906#define RT5663_ADC_RCH_BPF3_A2 0x03e3
907#define RT5663_ADC_LCH_BPF3_H0 0x03e4
908#define RT5663_ADC_RCH_BPF3_H0 0x03e5
909#define RT5663_ADC_LCH_BPF4_A1 0x03e6
910#define RT5663_ADC_RCH_BPF4_A1 0x03e7
911#define RT5663_ADC_LCH_BPF4_A2 0x03e8
912#define RT5663_ADC_RCH_BPF4_A2 0x03e9
913#define RT5663_ADC_LCH_BPF4_H0 0x03ea
914#define RT5663_ADC_RCH_BPF4_H0 0x03eb
915#define RT5663_ADC_LCH_HPF1_A1 0x03ec
916#define RT5663_ADC_RCH_HPF1_A1 0x03ed
917#define RT5663_ADC_LCH_HPF1_H0 0x03ee
918#define RT5663_ADC_RCH_HPF1_H0 0x03ef
919#define RT5663_ADC_EQ_PRE_VOL_L 0x03f0
920#define RT5663_ADC_EQ_PRE_VOL_R 0x03f1
921#define RT5663_ADC_EQ_POST_VOL_L 0x03f2
922#define RT5663_ADC_EQ_POST_VOL_R 0x03f3
923
924/* RT5663: RECMIX Control (0x0010) */
925#define RT5663_RECMIX1_BST1_MASK (0x1)
926#define RT5663_RECMIX1_BST1_SHIFT 0
927#define RT5663_RECMIX1_BST1_ON (0x0)
928#define RT5663_RECMIX1_BST1_OFF (0x1)
929
930/* RT5663: Bypass Stereo1 DAC Mixer Control (0x002d) */
931#define RT5663_DACL1_SRC_MASK (0x1 << 3)
932#define RT5663_DACL1_SRC_SHIFT 3
933#define RT5663_DACR1_SRC_MASK (0x1 << 2)
934#define RT5663_DACR1_SRC_SHIFT 2
935
936/* RT5663: TDM control 2 (0x0078) */
937#define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14)
938#define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14
939#define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14)
940#define RT5663_DATA_SWAP_ADCDAT1_RL (0x1 << 14)
941#define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14)
942#define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14)
943
944/* RT5663: TDM control 5 (0x007b) */
945#define RT5663_TDM_LENGTN_MASK (0x3)
946#define RT5663_TDM_LENGTN_SHIFT 0
947#define RT5663_TDM_LENGTN_16 (0x0)
948#define RT5663_TDM_LENGTN_20 (0x1)
949#define RT5663_TDM_LENGTN_24 (0x2)
950#define RT5663_TDM_LENGTN_32 (0x3)
951
952/* RT5663: Global Clock Control (0x0080) */
953#define RT5663_SCLK_SRC_MASK (0x3 << 14)
954#define RT5663_SCLK_SRC_SHIFT 14
955#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
956#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
957#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
958#define RT5663_PLL1_SRC_MASK (0x7 << 11)
959#define RT5663_PLL1_SRC_SHIFT 11
960#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
961#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
962
963/* PLL tracking mode 1 (0x0083) */
964#define RT5663_I2S1_ASRC_MASK (0x1 << 11)
965#define RT5663_I2S1_ASRC_SHIFT 11
966#define RT5663_DAC_STO1_ASRC_MASK (0x1 << 10)
967#define RT5663_DAC_STO1_ASRC_SHIFT 10
968#define RT5663_ADC_STO1_ASRC_MASK (0x1 << 3)
969#define RT5663_ADC_STO1_ASRC_SHIFT 3
970
971/* PLL tracking mode 2 (0x0084)*/
972#define RT5663_DA_STO1_TRACK_MASK (0x7 << 12)
973#define RT5663_DA_STO1_TRACK_SHIFT 12
974#define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12)
975#define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12)
976#define RT5663_AD_STO1_TRACK_MASK (0x7)
977#define RT5663_AD_STO1_TRACK_SHIFT 0
978#define RT5663_AD_STO1_TRACK_SYSCLK (0x0)
979#define RT5663_AD_STO1_TRACK_I2S1 (0x1)
980
981/* RT5663: HPOUT Charge pump control 1 (0x0091) */
982#define RT5663_SI_HP_MASK (0x1 << 12)
983#define RT5663_SI_HP_SHIFT 12
984#define RT5663_SI_HP_EN (0x1 << 12)
985#define RT5663_SI_HP_DIS (0x0 << 12)
986
987/* RT5663: GPIO Control 2 (0x00b6) */
988#define RT5663_GP1_PIN_CONF_MASK (0x1 << 2)
989#define RT5663_GP1_PIN_CONF_SHIFT 2
990#define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2)
991#define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2)
992
993/* RT5663: GPIO Control 2 (0x00b7) */
994#define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3)
995#define RT5663_EN_IRQ_INLINE_SHIFT 3
996#define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3)
997#define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3)
998
999/* RT5663: IRQ Control 1 (0x00c1) */
1000#define RT5663_EN_IRQ_JD1_MASK (0x1 << 6)
1001#define RT5663_EN_IRQ_JD1_SHIFT 6
1002#define RT5663_EN_IRQ_JD1_EN (0x1 << 6)
1003#define RT5663_EN_IRQ_JD1_DIS (0x0 << 6)
1004
1005/* RT5663: Inline Command Function 2 (0x00dc) */
1006#define RT5663_PWR_MIC_DET_MASK (0x1)
1007#define RT5663_PWR_MIC_DET_SHIFT 0
1008#define RT5663_PWR_MIC_DET_ON (0x1)
1009#define RT5663_PWR_MIC_DET_OFF (0x0)
1010
1011/* RT5663: Embeeded Jack and Type Detection Control 1 (0x00e6)*/
1012#define RT5663_CBJ_DET_MASK (0x1 << 15)
1013#define RT5663_CBJ_DET_SHIFT 15
1014#define RT5663_CBJ_DET_DIS (0x0 << 15)
1015#define RT5663_CBJ_DET_EN (0x1 << 15)
1016#define RT5663_EXT_JD_MASK (0x1 << 11)
1017#define RT5663_EXT_JD_SHIFT 11
1018#define RT5663_EXT_JD_EN (0x1 << 11)
1019#define RT5663_EXT_JD_DIS (0x0 << 11)
1020#define RT5663_POL_EXT_JD_MASK (0x1 << 10)
1021#define RT5663_POL_EXT_JD_SHIFT 10
1022#define RT5663_POL_EXT_JD_EN (0x1 << 10)
1023#define RT5663_POL_EXT_JD_DIS (0x0 << 10)
1024
1025/* RT5663: DACREF LDO Control (0x0112)*/
1026#define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9)
1027#define RT5663_PWR_LDO_DACREFL_SHIFT 9
1028#define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1)
1029#define RT5663_PWR_LDO_DACREFR_SHIFT 1
1030
1031/* RT5663: Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
1032#define RT5663_DRE_GAIN_HP_MASK (0x1f)
1033#define RT5663_DRE_GAIN_HP_SHIFT 0
1034
1035/* RT5663: Combo Jack Control (0x0250) */
1036#define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11)
1037#define RT5663_INBUF_CBJ_BST1_SHIFT 11
1038#define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11)
1039#define RT5663_INBUF_CBJ_BST1_OFF (0x0 << 11)
1040#define RT5663_CBJ_SENSE_BST1_MASK (0x1 << 10)
1041#define RT5663_CBJ_SENSE_BST1_SHIFT 10
1042#define RT5663_CBJ_SENSE_BST1_L (0x1 << 10)
1043#define RT5663_CBJ_SENSE_BST1_R (0x0 << 10)
1044
1045/* RT5663: Combo Jack Control (0x0251) */
1046#define RT5663_GAIN_BST1_MASK (0xf)
1047#define RT5663_GAIN_BST1_SHIFT 0
1048
1049/* RT5663: Dummy register 1 (0x02fa) */
1050#define RT5663_EMB_CLK_MASK (0x1 << 9)
1051#define RT5663_EMB_CLK_SHIFT 9
1052#define RT5663_EMB_CLK_EN (0x1 << 9)
1053#define RT5663_EMB_CLK_DIS (0x0 << 9)
1054#define RT5663_HPA_CPL_BIAS_MASK (0x7 << 6)
1055#define RT5663_HPA_CPL_BIAS_SHIFT 6
1056#define RT5663_HPA_CPL_BIAS_0_5 (0x0 << 6)
1057#define RT5663_HPA_CPL_BIAS_1 (0x1 << 6)
1058#define RT5663_HPA_CPL_BIAS_2 (0x2 << 6)
1059#define RT5663_HPA_CPL_BIAS_3 (0x3 << 6)
1060#define RT5663_HPA_CPL_BIAS_4_1 (0x4 << 6)
1061#define RT5663_HPA_CPL_BIAS_4_2 (0x5 << 6)
1062#define RT5663_HPA_CPL_BIAS_6 (0x6 << 6)
1063#define RT5663_HPA_CPL_BIAS_8 (0x7 << 6)
1064#define RT5663_HPA_CPR_BIAS_MASK (0x7 << 3)
1065#define RT5663_HPA_CPR_BIAS_SHIFT 3
1066#define RT5663_HPA_CPR_BIAS_0_5 (0x0 << 3)
1067#define RT5663_HPA_CPR_BIAS_1 (0x1 << 3)
1068#define RT5663_HPA_CPR_BIAS_2 (0x2 << 3)
1069#define RT5663_HPA_CPR_BIAS_3 (0x3 << 3)
1070#define RT5663_HPA_CPR_BIAS_4_1 (0x4 << 3)
1071#define RT5663_HPA_CPR_BIAS_4_2 (0x5 << 3)
1072#define RT5663_HPA_CPR_BIAS_6 (0x6 << 3)
1073#define RT5663_HPA_CPR_BIAS_8 (0x7 << 3)
1074#define RT5663_DUMMY_BIAS_MASK (0x7)
1075#define RT5663_DUMMY_BIAS_SHIFT 0
1076#define RT5663_DUMMY_BIAS_0_5 (0x0)
1077#define RT5663_DUMMY_BIAS_1 (0x1)
1078#define RT5663_DUMMY_BIAS_2 (0x2)
1079#define RT5663_DUMMY_BIAS_3 (0x3)
1080#define RT5663_DUMMY_BIAS_4_1 (0x4)
1081#define RT5663_DUMMY_BIAS_4_2 (0x5)
1082#define RT5663_DUMMY_BIAS_6 (0x6)
1083#define RT5663_DUMMY_BIAS_8 (0x7)
1084
1085
1086/* System Clock Source */
1087enum {
1088 RT5663_SCLK_S_MCLK,
1089 RT5663_SCLK_S_PLL1,
1090 RT5663_SCLK_S_RCCLK,
1091};
1092
1093/* PLL1 Source */
1094enum {
1095 RT5663_PLL1_S_MCLK,
1096 RT5663_PLL1_S_BCLK1,
1097};
1098
1099enum {
1100 RT5663_AIF,
1101 RT5663_AIFS,
1102};
1103
1104/* asrc clock source */
1105enum {
1106 RT5663_CLK_SEL_SYS = 0x0,
1107 RT5663_CLK_SEL_I2S1_ASRC = 0x1,
1108};
1109
1110/* filter mask */
1111enum {
1112 RT5663_DA_STEREO_FILTER = 0x1,
1113 RT5663_AD_STEREO_FILTER = 0x2,
1114};
1115
1116int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1117 struct snd_soc_jack *hs_jack);
1118int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1119 unsigned int filter_mask, unsigned int clk_src);
1120
1121#endif /* __RT5663_H__ */
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