diff options
author | Leo Liu <leo.liu@amd.com> | 2018-05-17 13:54:21 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-05-18 17:08:32 -0400 |
commit | def139037bbf9195467fa83c0a299d666e6ed0bb (patch) | |
tree | 8a49d87a792934e0beca461abf8ff3bc53b9bb89 | |
parent | 0232e30623f3761ce9350328d4d96cea8372b114 (diff) |
drm/amdgpu: fix insert nop for UVD4.2 ring
NO_OP register should be writen to 0
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 5f22135de77f..6fed3d7797a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | |||
@@ -524,6 +524,18 @@ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, | |||
524 | amdgpu_ring_write(ring, ib->length_dw); | 524 | amdgpu_ring_write(ring, ib->length_dw); |
525 | } | 525 | } |
526 | 526 | ||
527 | static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) | ||
528 | { | ||
529 | int i; | ||
530 | |||
531 | WARN_ON(ring->wptr % 2 || count % 2); | ||
532 | |||
533 | for (i = 0; i < count / 2; i++) { | ||
534 | amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); | ||
535 | amdgpu_ring_write(ring, 0); | ||
536 | } | ||
537 | } | ||
538 | |||
527 | /** | 539 | /** |
528 | * uvd_v4_2_mc_resume - memory controller programming | 540 | * uvd_v4_2_mc_resume - memory controller programming |
529 | * | 541 | * |
@@ -733,7 +745,6 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { | |||
733 | static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { | 745 | static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { |
734 | .type = AMDGPU_RING_TYPE_UVD, | 746 | .type = AMDGPU_RING_TYPE_UVD, |
735 | .align_mask = 0xf, | 747 | .align_mask = 0xf, |
736 | .nop = PACKET0(mmUVD_NO_OP, 0), | ||
737 | .support_64bit_ptrs = false, | 748 | .support_64bit_ptrs = false, |
738 | .get_rptr = uvd_v4_2_ring_get_rptr, | 749 | .get_rptr = uvd_v4_2_ring_get_rptr, |
739 | .get_wptr = uvd_v4_2_ring_get_wptr, | 750 | .get_wptr = uvd_v4_2_ring_get_wptr, |
@@ -746,7 +757,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { | |||
746 | .emit_fence = uvd_v4_2_ring_emit_fence, | 757 | .emit_fence = uvd_v4_2_ring_emit_fence, |
747 | .test_ring = uvd_v4_2_ring_test_ring, | 758 | .test_ring = uvd_v4_2_ring_test_ring, |
748 | .test_ib = amdgpu_uvd_ring_test_ib, | 759 | .test_ib = amdgpu_uvd_ring_test_ib, |
749 | .insert_nop = amdgpu_ring_insert_nop, | 760 | .insert_nop = uvd_v4_2_ring_insert_nop, |
750 | .pad_ib = amdgpu_ring_generic_pad_ib, | 761 | .pad_ib = amdgpu_ring_generic_pad_ib, |
751 | .begin_use = amdgpu_uvd_ring_begin_use, | 762 | .begin_use = amdgpu_uvd_ring_begin_use, |
752 | .end_use = amdgpu_uvd_ring_end_use, | 763 | .end_use = amdgpu_uvd_ring_end_use, |