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authorSimon Horman <horms+renesas@verge.net.au>2015-02-23 18:22:10 -0500
committerSimon Horman <horms+renesas@verge.net.au>2015-02-23 18:22:10 -0500
commitded416ff3ae664c37ec4c270a3ab273b01218838 (patch)
tree13c5ca47249459ed5e0cbd4a7928b3f949d6b9c4
parent89d463ea106dba530786a2815fd174f9e6eab71f (diff)
parentb8e8ea127d00f1b0c18d8c1ae1b8388e190d5052 (diff)
Merge branch 'heads/dt-for-v4.1' into sh73a0-multiplatform-for-v4.1.base
Diffstat
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts13
-rw-r--r--arch/arm/boot/dts/emev2.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi79
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi102
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts11
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts50
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi122
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts13
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi157
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts42
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts2
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi82
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7790.c4
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7791.c2
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h3
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h3
-rw-r--r--include/dt-bindings/clock/sh73a0-clock.h3
17 files changed, 647 insertions, 51 deletions
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 667d323e80a3..19446273e4a7 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -94,3 +94,16 @@
94 vdd33a-supply = <&reg_3p3v>; 94 vdd33a-supply = <&reg_3p3v>;
95 }; 95 };
96}; 96};
97
98&pfc {
99 uart1_pins: uart@e1030000 {
100 renesas,groups = "uart1_ctrl", "uart1_data";
101 renesas,function = "uart1";
102 };
103};
104
105&uart1 {
106 pinctrl-0 = <&uart1_pins>;
107 pinctrl-names = "default";
108 status = "okay";
109};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index cc7bfe0ba40a..bb45694d91bc 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -169,12 +169,18 @@
169 clock-names = "sclk"; 169 clock-names = "sclk";
170 }; 170 };
171 171
172 pfc: pfc@e0140200 {
173 compatible = "renesas,pfc-emev2";
174 reg = <0xe0140200 0x100>;
175 };
176
172 gpio0: gpio@e0050000 { 177 gpio0: gpio@e0050000 {
173 compatible = "renesas,em-gio"; 178 compatible = "renesas,em-gio";
174 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; 179 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
175 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, 180 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
176 <0 68 IRQ_TYPE_LEVEL_HIGH>; 181 <0 68 IRQ_TYPE_LEVEL_HIGH>;
177 gpio-controller; 182 gpio-controller;
183 gpio-ranges = <&pfc 0 0 32>;
178 #gpio-cells = <2>; 184 #gpio-cells = <2>;
179 ngpios = <32>; 185 ngpios = <32>;
180 interrupt-controller; 186 interrupt-controller;
@@ -186,6 +192,7 @@
186 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, 192 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
187 <0 70 IRQ_TYPE_LEVEL_HIGH>; 193 <0 70 IRQ_TYPE_LEVEL_HIGH>;
188 gpio-controller; 194 gpio-controller;
195 gpio-ranges = <&pfc 0 32 32>;
189 #gpio-cells = <2>; 196 #gpio-cells = <2>;
190 ngpios = <32>; 197 ngpios = <32>;
191 interrupt-controller; 198 interrupt-controller;
@@ -197,6 +204,7 @@
197 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, 204 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
198 <0 72 IRQ_TYPE_LEVEL_HIGH>; 205 <0 72 IRQ_TYPE_LEVEL_HIGH>;
199 gpio-controller; 206 gpio-controller;
207 gpio-ranges = <&pfc 0 64 32>;
200 #gpio-cells = <2>; 208 #gpio-cells = <2>;
201 ngpios = <32>; 209 ngpios = <32>;
202 interrupt-controller; 210 interrupt-controller;
@@ -208,6 +216,7 @@
208 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, 216 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
209 <0 74 IRQ_TYPE_LEVEL_HIGH>; 217 <0 74 IRQ_TYPE_LEVEL_HIGH>;
210 gpio-controller; 218 gpio-controller;
219 gpio-ranges = <&pfc 0 96 32>;
211 #gpio-cells = <2>; 220 #gpio-cells = <2>;
212 ngpios = <32>; 221 ngpios = <32>;
213 interrupt-controller; 222 interrupt-controller;
@@ -219,6 +228,7 @@
219 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, 228 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
220 <0 76 IRQ_TYPE_LEVEL_HIGH>; 229 <0 76 IRQ_TYPE_LEVEL_HIGH>;
221 gpio-controller; 230 gpio-controller;
231 gpio-ranges = <&pfc 0 128 31>;
222 #gpio-cells = <2>; 232 #gpio-cells = <2>;
223 ngpios = <31>; 233 ngpios = <31>;
224 interrupt-controller; 234 interrupt-controller;
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 8a092605d641..83c1c3ca1b8f 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -431,6 +431,18 @@
431 clock-frequency = <27000000>; 431 clock-frequency = <27000000>;
432 clock-output-names = "dv"; 432 clock-output-names = "dv";
433 }; 433 };
434 fmsick_clk: fmsick_clk {
435 compatible = "fixed-clock";
436 #clock-cells = <0>;
437 clock-frequency = <0>;
438 clock-output-names = "fmsick";
439 };
440 fmsock_clk: fmsock_clk {
441 compatible = "fixed-clock";
442 #clock-cells = <0>;
443 clock-frequency = <0>;
444 clock-output-names = "fmsock";
445 };
434 fsiack_clk: fsiack_clk { 446 fsiack_clk: fsiack_clk {
435 compatible = "fixed-clock"; 447 compatible = "fixed-clock";
436 #clock-cells = <0>; 448 #clock-cells = <0>;
@@ -459,13 +471,78 @@
459 }; 471 };
460 472
461 /* Variable factor clocks (DIV6) */ 473 /* Variable factor clocks (DIV6) */
474 vclk1_clk: vclk1_clk@e6150008 {
475 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
476 reg = <0xe6150008 4>;
477 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
478 <&cpg_clocks R8A7740_CLK_USB24S>,
479 <&extal1_div2_clk>, <&extalr_clk>, <0>,
480 <0>;
481 #clock-cells = <0>;
482 clock-output-names = "vclk1";
483 };
484 vclk2_clk: vclk2_clk@e615000c {
485 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
486 reg = <0xe615000c 4>;
487 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
488 <&cpg_clocks R8A7740_CLK_USB24S>,
489 <&extal1_div2_clk>, <&extalr_clk>, <0>,
490 <0>;
491 #clock-cells = <0>;
492 clock-output-names = "vclk2";
493 };
494 fmsi_clk: fmsi_clk@e6150010 {
495 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
496 reg = <0xe6150010 4>;
497 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
498 #clock-cells = <0>;
499 clock-output-names = "fmsi";
500 };
501 fmso_clk: fmso_clk@e6150014 {
502 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
503 reg = <0xe6150014 4>;
504 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
505 #clock-cells = <0>;
506 clock-output-names = "fmso";
507 };
508 fsia_clk: fsia_clk@e6150018 {
509 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
510 reg = <0xe6150018 4>;
511 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
512 #clock-cells = <0>;
513 clock-output-names = "fsia";
514 };
462 sub_clk: sub_clk@e6150080 { 515 sub_clk: sub_clk@e6150080 {
463 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 516 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
464 reg = <0xe6150080 4>; 517 reg = <0xe6150080 4>;
465 clocks = <&pllc1_div2_clk>; 518 clocks = <&pllc1_div2_clk>,
519 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
466 #clock-cells = <0>; 520 #clock-cells = <0>;
467 clock-output-names = "sub"; 521 clock-output-names = "sub";
468 }; 522 };
523 spu_clk: spu_clk@e6150084 {
524 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
525 reg = <0xe6150084 4>;
526 clocks = <&pllc1_div2_clk>,
527 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
528 #clock-cells = <0>;
529 clock-output-names = "spu";
530 };
531 vou_clk: vou_clk@e6150088 {
532 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
533 reg = <0xe6150088 4>;
534 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
535 <0>;
536 #clock-cells = <0>;
537 clock-output-names = "vou";
538 };
539 stpro_clk: stpro_clk@e615009c {
540 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
541 reg = <0xe615009c 4>;
542 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
543 #clock-cells = <0>;
544 clock-output-names = "stpro";
545 };
469 546
470 /* Fixed factor clocks */ 547 /* Fixed factor clocks */
471 pllc1_div2_clk: pllc1_div2_clk { 548 pllc1_div2_clk: pllc1_div2_clk {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 4b38fc920114..c6c0a0c8f1be 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -792,6 +792,26 @@
792 }; 792 };
793 }; 793 };
794 794
795 can0: can@e6e80000 {
796 compatible = "renesas,can-r8a7790";
797 reg = <0 0xe6e80000 0 0x1000>;
798 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
800 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
801 clock-names = "clkp1", "clkp2", "can_clk";
802 status = "disabled";
803 };
804
805 can1: can@e6e88000 {
806 compatible = "renesas,can-r8a7790";
807 reg = <0 0xe6e88000 0 0x1000>;
808 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
810 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
811 clock-names = "clkp1", "clkp2", "can_clk";
812 status = "disabled";
813 };
814
795 clocks { 815 clocks {
796 #address-cells = <2>; 816 #address-cells = <2>;
797 #size-cells = <2>; 817 #size-cells = <2>;
@@ -838,16 +858,34 @@
838 clock-output-names = "audio_clk_c"; 858 clock-output-names = "audio_clk_c";
839 }; 859 };
840 860
861 /* External USB clock - can be overridden by the board */
862 usb_extal_clk: usb_extal_clk {
863 compatible = "fixed-clock";
864 #clock-cells = <0>;
865 clock-frequency = <48000000>;
866 clock-output-names = "usb_extal";
867 };
868
869 /* External CAN clock */
870 can_clk: can_clk {
871 compatible = "fixed-clock";
872 #clock-cells = <0>;
873 /* This value must be overridden by the board. */
874 clock-frequency = <0>;
875 clock-output-names = "can_clk";
876 status = "disabled";
877 };
878
841 /* Special CPG clocks */ 879 /* Special CPG clocks */
842 cpg_clocks: cpg_clocks@e6150000 { 880 cpg_clocks: cpg_clocks@e6150000 {
843 compatible = "renesas,r8a7790-cpg-clocks", 881 compatible = "renesas,r8a7790-cpg-clocks",
844 "renesas,rcar-gen2-cpg-clocks"; 882 "renesas,rcar-gen2-cpg-clocks";
845 reg = <0 0xe6150000 0 0x1000>; 883 reg = <0 0xe6150000 0 0x1000>;
846 clocks = <&extal_clk>; 884 clocks = <&extal_clk &usb_extal_clk>;
847 #clock-cells = <1>; 885 #clock-cells = <1>;
848 clock-output-names = "main", "pll0", "pll1", "pll3", 886 clock-output-names = "main", "pll0", "pll1", "pll3",
849 "lb", "qspi", "sdh", "sd0", "sd1", 887 "lb", "qspi", "sdh", "sd0", "sd1",
850 "z"; 888 "z", "rcan", "adsp";
851 }; 889 };
852 890
853 /* Variable factor clocks */ 891 /* Variable factor clocks */
@@ -1121,13 +1159,16 @@
1121 mstp5_clks: mstp5_clks@e6150144 { 1159 mstp5_clks: mstp5_clks@e6150144 {
1122 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1160 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1161 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1162 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1163 <&extal_clk>, <&p_clk>;
1125 #clock-cells = <1>; 1164 #clock-cells = <1>;
1126 clock-indices = < 1165 clock-indices = <
1127 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 1166 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1128 R8A7790_CLK_THERMAL R8A7790_CLK_PWM 1167 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1168 R8A7790_CLK_PWM
1129 >; 1169 >;
1130 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1170 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1171 "thermal", "pwm";
1131 }; 1172 };
1132 mstp7_clks: mstp7_clks@e615014c { 1173 mstp7_clks: mstp7_clks@e615014c {
1133 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1174 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1465,4 +1506,55 @@
1465 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; 1506 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1466 }; 1507 };
1467 }; 1508 };
1509
1510 ipmmu_sy0: mmu@e6280000 {
1511 compatible = "renesas,ipmmu-vmsa";
1512 reg = <0 0xe6280000 0 0x1000>;
1513 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1514 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1515 #iommu-cells = <1>;
1516 status = "disabled";
1517 };
1518
1519 ipmmu_sy1: mmu@e6290000 {
1520 compatible = "renesas,ipmmu-vmsa";
1521 reg = <0 0xe6290000 0 0x1000>;
1522 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1523 #iommu-cells = <1>;
1524 status = "disabled";
1525 };
1526
1527 ipmmu_ds: mmu@e6740000 {
1528 compatible = "renesas,ipmmu-vmsa";
1529 reg = <0 0xe6740000 0 0x1000>;
1530 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1531 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1532 #iommu-cells = <1>;
1533 status = "disabled";
1534 };
1535
1536 ipmmu_mp: mmu@ec680000 {
1537 compatible = "renesas,ipmmu-vmsa";
1538 reg = <0 0xec680000 0 0x1000>;
1539 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1540 #iommu-cells = <1>;
1541 status = "disabled";
1542 };
1543
1544 ipmmu_mx: mmu@fe951000 {
1545 compatible = "renesas,ipmmu-vmsa";
1546 reg = <0 0xfe951000 0 0x1000>;
1547 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1548 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1549 #iommu-cells = <1>;
1550 status = "disabled";
1551 };
1552
1553 ipmmu_rt: mmu@ffc80000 {
1554 compatible = "renesas,ipmmu-vmsa";
1555 reg = <0 0xffc80000 0 0x1000>;
1556 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1557 #iommu-cells = <1>;
1558 status = "disabled";
1559 };
1468}; 1560};
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index d2ebf11f9881..e33e4047b0b0 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -141,6 +141,11 @@
141 renesas,groups = "vin0_data8", "vin0_clk"; 141 renesas,groups = "vin0_data8", "vin0_clk";
142 renesas,function = "vin0"; 142 renesas,function = "vin0";
143 }; 143 };
144
145 can0_pins: can0 {
146 renesas,groups = "can0_data";
147 renesas,function = "can0";
148 };
144}; 149};
145 150
146&scif0 { 151&scif0 {
@@ -307,3 +312,9 @@
307 }; 312 };
308 }; 313 };
309}; 314};
315
316&can0 {
317 pinctrl-0 = <&can0_pins>;
318 pinctrl-names = "default";
319 status = "okay";
320};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index a3c27807f6c5..624bb2c30513 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -258,6 +258,17 @@
258 system-clock-frequency = <11289600>; 258 system-clock-frequency = <11289600>;
259 }; 259 };
260 }; 260 };
261
262 hdmi-out {
263 compatible = "hdmi-connector";
264 type = "a";
265
266 port {
267 hdmi_con: endpoint {
268 remote-endpoint = <&adv7511_out>;
269 };
270 };
271 };
261}; 272};
262 273
263&du { 274&du {
@@ -266,6 +277,11 @@
266 status = "okay"; 277 status = "okay";
267 278
268 ports { 279 ports {
280 port@0 {
281 endpoint {
282 remote-endpoint = <&adv7511_in>;
283 };
284 };
269 port@1 { 285 port@1 {
270 lvds_connector: endpoint { 286 lvds_connector: endpoint {
271 }; 287 };
@@ -284,7 +300,7 @@
284 }; 300 };
285 301
286 du_pins: du { 302 du_pins: du {
287 renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0"; 303 renesas,groups = "du_rgb666", "du_sync", "du_disp", "du_clk_out_0";
288 renesas,function = "du"; 304 renesas,function = "du";
289 }; 305 };
290 306
@@ -506,6 +522,38 @@
506 }; 522 };
507 }; 523 };
508 524
525 hdmi@39 {
526 compatible = "adi,adv7511w";
527 reg = <0x39>;
528 interrupt-parent = <&gpio3>;
529 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
530
531 adi,input-depth = <8>;
532 adi,input-colorspace = "rgb";
533 adi,input-clock = "1x";
534 adi,input-style = <1>;
535 adi,input-justification = "evenly";
536
537 ports {
538 #address-cells = <1>;
539 #size-cells = <0>;
540
541 port@0 {
542 reg = <0>;
543 adv7511_in: endpoint {
544 remote-endpoint = <&du_out_rgb>;
545 };
546 };
547
548 port@1 {
549 reg = <1>;
550 adv7511_out: endpoint {
551 remote-endpoint = <&hdmi_con>;
552 };
553 };
554 };
555 };
556
509 eeprom@50 { 557 eeprom@50 {
510 compatible = "renesas,24c02"; 558 compatible = "renesas,24c02";
511 reg = <0x50>; 559 reg = <0x50>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e35812a0d8d4..1e593a2b55fa 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -816,6 +816,26 @@
816 }; 816 };
817 }; 817 };
818 818
819 can0: can@e6e80000 {
820 compatible = "renesas,can-r8a7791";
821 reg = <0 0xe6e80000 0 0x1000>;
822 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
824 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
825 clock-names = "clkp1", "clkp2", "can_clk";
826 status = "disabled";
827 };
828
829 can1: can@e6e88000 {
830 compatible = "renesas,can-r8a7791";
831 reg = <0 0xe6e88000 0 0x1000>;
832 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
834 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
835 clock-names = "clkp1", "clkp2", "can_clk";
836 status = "disabled";
837 };
838
819 clocks { 839 clocks {
820 #address-cells = <2>; 840 #address-cells = <2>;
821 #size-cells = <2>; 841 #size-cells = <2>;
@@ -862,31 +882,50 @@
862 status = "disabled"; 882 status = "disabled";
863 }; 883 };
864 884
885 /* External USB clock - can be overridden by the board */
886 usb_extal_clk: usb_extal_clk {
887 compatible = "fixed-clock";
888 #clock-cells = <0>;
889 clock-frequency = <48000000>;
890 clock-output-names = "usb_extal";
891 };
892
893 /* External CAN clock */
894 can_clk: can_clk {
895 compatible = "fixed-clock";
896 #clock-cells = <0>;
897 /* This value must be overridden by the board. */
898 clock-frequency = <0>;
899 clock-output-names = "can_clk";
900 status = "disabled";
901 };
902
865 /* Special CPG clocks */ 903 /* Special CPG clocks */
866 cpg_clocks: cpg_clocks@e6150000 { 904 cpg_clocks: cpg_clocks@e6150000 {
867 compatible = "renesas,r8a7791-cpg-clocks", 905 compatible = "renesas,r8a7791-cpg-clocks",
868 "renesas,rcar-gen2-cpg-clocks"; 906 "renesas,rcar-gen2-cpg-clocks";
869 reg = <0 0xe6150000 0 0x1000>; 907 reg = <0 0xe6150000 0 0x1000>;
870 clocks = <&extal_clk>; 908 clocks = <&extal_clk &usb_extal_clk>;
871 #clock-cells = <1>; 909 #clock-cells = <1>;
872 clock-output-names = "main", "pll0", "pll1", "pll3", 910 clock-output-names = "main", "pll0", "pll1", "pll3",
873 "lb", "qspi", "sdh", "sd0", "z"; 911 "lb", "qspi", "sdh", "sd0", "z",
912 "rcan", "adsp";
874 }; 913 };
875 914
876 /* Variable factor clocks */ 915 /* Variable factor clocks */
877 sd1_clk: sd2_clk@e6150078 { 916 sd2_clk: sd2_clk@e6150078 {
878 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 917 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
879 reg = <0 0xe6150078 0 4>; 918 reg = <0 0xe6150078 0 4>;
880 clocks = <&pll1_div2_clk>; 919 clocks = <&pll1_div2_clk>;
881 #clock-cells = <0>; 920 #clock-cells = <0>;
882 clock-output-names = "sd1"; 921 clock-output-names = "sd2";
883 }; 922 };
884 sd2_clk: sd3_clk@e615026c { 923 sd3_clk: sd3_clk@e615026c {
885 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 924 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
886 reg = <0 0xe615026c 0 4>; 925 reg = <0 0xe615026c 0 4>;
887 clocks = <&pll1_div2_clk>; 926 clocks = <&pll1_div2_clk>;
888 #clock-cells = <0>; 927 #clock-cells = <0>;
889 clock-output-names = "sd2"; 928 clock-output-names = "sd3";
890 }; 929 };
891 mmc0_clk: mmc0_clk@e6150240 { 930 mmc0_clk: mmc0_clk@e6150240 {
892 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 931 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
@@ -1107,7 +1146,7 @@
1107 mstp3_clks: mstp3_clks@e615013c { 1146 mstp3_clks: mstp3_clks@e615013c {
1108 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1147 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1109 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1148 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1110 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, 1149 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1150 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1112 <&hp_clk>, <&hp_clk>; 1151 <&hp_clk>, <&hp_clk>;
1113 #clock-cells = <1>; 1152 #clock-cells = <1>;
@@ -1125,13 +1164,16 @@
1125 mstp5_clks: mstp5_clks@e6150144 { 1164 mstp5_clks: mstp5_clks@e6150144 {
1126 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1165 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1166 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1167 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1168 <&extal_clk>, <&p_clk>;
1129 #clock-cells = <1>; 1169 #clock-cells = <1>;
1130 clock-indices = < 1170 clock-indices = <
1131 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 1171 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1132 R8A7791_CLK_THERMAL R8A7791_CLK_PWM 1172 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1173 R8A7791_CLK_PWM
1133 >; 1174 >;
1134 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1175 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1176 "thermal", "pwm";
1135 }; 1177 };
1136 mstp7_clks: mstp7_clks@e615014c { 1178 mstp7_clks: mstp7_clks@e615014c {
1137 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1179 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1384,6 +1426,66 @@
1384 status = "disabled"; 1426 status = "disabled";
1385 }; 1427 };
1386 1428
1429 ipmmu_sy0: mmu@e6280000 {
1430 compatible = "renesas,ipmmu-vmsa";
1431 reg = <0 0xe6280000 0 0x1000>;
1432 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1433 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1434 #iommu-cells = <1>;
1435 status = "disabled";
1436 };
1437
1438 ipmmu_sy1: mmu@e6290000 {
1439 compatible = "renesas,ipmmu-vmsa";
1440 reg = <0 0xe6290000 0 0x1000>;
1441 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1442 #iommu-cells = <1>;
1443 status = "disabled";
1444 };
1445
1446 ipmmu_ds: mmu@e6740000 {
1447 compatible = "renesas,ipmmu-vmsa";
1448 reg = <0 0xe6740000 0 0x1000>;
1449 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1450 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1451 #iommu-cells = <1>;
1452 status = "disabled";
1453 };
1454
1455 ipmmu_mp: mmu@ec680000 {
1456 compatible = "renesas,ipmmu-vmsa";
1457 reg = <0 0xec680000 0 0x1000>;
1458 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1459 #iommu-cells = <1>;
1460 status = "disabled";
1461 };
1462
1463 ipmmu_mx: mmu@fe951000 {
1464 compatible = "renesas,ipmmu-vmsa";
1465 reg = <0 0xfe951000 0 0x1000>;
1466 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1467 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1468 #iommu-cells = <1>;
1469 status = "disabled";
1470 };
1471
1472 ipmmu_rt: mmu@ffc80000 {
1473 compatible = "renesas,ipmmu-vmsa";
1474 reg = <0 0xffc80000 0 0x1000>;
1475 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1476 #iommu-cells = <1>;
1477 status = "disabled";
1478 };
1479
1480 ipmmu_gp: mmu@e62a0000 {
1481 compatible = "renesas,ipmmu-vmsa";
1482 reg = <0 0xe62a0000 0 0x1000>;
1483 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1484 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1485 #iommu-cells = <1>;
1486 status = "disabled";
1487 };
1488
1387 rcar_sound: rcar_sound@ec500000 { 1489 rcar_sound: rcar_sound@ec500000 {
1388 /* 1490 /*
1389 * #sound-dai-cells is required 1491 * #sound-dai-cells is required
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 0d848e605071..25bf434433b1 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -43,6 +43,19 @@
43 status = "okay"; 43 status = "okay";
44}; 44};
45 45
46&ether {
47 phy-handle = <&phy1>;
48 renesas,ether-link-active-low;
49 status = "okay";
50
51 phy1: ethernet-phy@1 {
52 reg = <1>;
53 interrupt-parent = <&irqc0>;
54 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
55 micrel,led-mode = <1>;
56 };
57};
58
46&scif2 { 59&scif2 {
47 status = "okay"; 60 status = "okay";
48}; 61};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 8f78da5ef10b..7a3ffa51a8bf 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -107,6 +107,66 @@
107 <0 17 IRQ_TYPE_LEVEL_HIGH>; 107 <0 17 IRQ_TYPE_LEVEL_HIGH>;
108 }; 108 };
109 109
110 dmac0: dma-controller@e6700000 {
111 compatible = "renesas,rcar-dmac";
112 reg = <0 0xe6700000 0 0x20000>;
113 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
114 0 200 IRQ_TYPE_LEVEL_HIGH
115 0 201 IRQ_TYPE_LEVEL_HIGH
116 0 202 IRQ_TYPE_LEVEL_HIGH
117 0 203 IRQ_TYPE_LEVEL_HIGH
118 0 204 IRQ_TYPE_LEVEL_HIGH
119 0 205 IRQ_TYPE_LEVEL_HIGH
120 0 206 IRQ_TYPE_LEVEL_HIGH
121 0 207 IRQ_TYPE_LEVEL_HIGH
122 0 208 IRQ_TYPE_LEVEL_HIGH
123 0 209 IRQ_TYPE_LEVEL_HIGH
124 0 210 IRQ_TYPE_LEVEL_HIGH
125 0 211 IRQ_TYPE_LEVEL_HIGH
126 0 212 IRQ_TYPE_LEVEL_HIGH
127 0 213 IRQ_TYPE_LEVEL_HIGH
128 0 214 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-names = "error",
130 "ch0", "ch1", "ch2", "ch3",
131 "ch4", "ch5", "ch6", "ch7",
132 "ch8", "ch9", "ch10", "ch11",
133 "ch12", "ch13", "ch14";
134 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
135 clock-names = "fck";
136 #dma-cells = <1>;
137 dma-channels = <15>;
138 };
139
140 dmac1: dma-controller@e6720000 {
141 compatible = "renesas,rcar-dmac";
142 reg = <0 0xe6720000 0 0x20000>;
143 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
144 0 216 IRQ_TYPE_LEVEL_HIGH
145 0 217 IRQ_TYPE_LEVEL_HIGH
146 0 218 IRQ_TYPE_LEVEL_HIGH
147 0 219 IRQ_TYPE_LEVEL_HIGH
148 0 308 IRQ_TYPE_LEVEL_HIGH
149 0 309 IRQ_TYPE_LEVEL_HIGH
150 0 310 IRQ_TYPE_LEVEL_HIGH
151 0 311 IRQ_TYPE_LEVEL_HIGH
152 0 312 IRQ_TYPE_LEVEL_HIGH
153 0 313 IRQ_TYPE_LEVEL_HIGH
154 0 314 IRQ_TYPE_LEVEL_HIGH
155 0 315 IRQ_TYPE_LEVEL_HIGH
156 0 316 IRQ_TYPE_LEVEL_HIGH
157 0 317 IRQ_TYPE_LEVEL_HIGH
158 0 318 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-names = "error",
160 "ch0", "ch1", "ch2", "ch3",
161 "ch4", "ch5", "ch6", "ch7",
162 "ch8", "ch9", "ch10", "ch11",
163 "ch12", "ch13", "ch14";
164 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
165 clock-names = "fck";
166 #dma-cells = <1>;
167 dma-channels = <15>;
168 };
169
110 scifa0: serial@e6c40000 { 170 scifa0: serial@e6c40000 {
111 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 171 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
112 reg = <0 0xe6c40000 0 64>; 172 reg = <0 0xe6c40000 0 64>;
@@ -269,6 +329,41 @@
269 status = "disabled"; 329 status = "disabled";
270 }; 330 };
271 331
332 ether: ethernet@ee700000 {
333 compatible = "renesas,ether-r8a7794";
334 reg = <0 0xee700000 0 0x400>;
335 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
337 phy-mode = "rmii";
338 #address-cells = <1>;
339 #size-cells = <0>;
340 status = "disabled";
341 };
342
343 sdhi0: sd@ee100000 {
344 compatible = "renesas,sdhi-r8a7794";
345 reg = <0 0xee100000 0 0x200>;
346 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
348 status = "disabled";
349 };
350
351 sdhi1: sd@ee140000 {
352 compatible = "renesas,sdhi-r8a7794";
353 reg = <0 0xee140000 0 0x100>;
354 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
356 status = "disabled";
357 };
358
359 sdhi2: sd@ee160000 {
360 compatible = "renesas,sdhi-r8a7794";
361 reg = <0 0xee160000 0 0x100>;
362 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
364 status = "disabled";
365 };
366
272 clocks { 367 clocks {
273 #address-cells = <2>; 368 #address-cells = <2>;
274 #size-cells = <2>; 369 #size-cells = <2>;
@@ -294,19 +389,19 @@
294 "lb", "qspi", "sdh", "sd0", "z"; 389 "lb", "qspi", "sdh", "sd0", "z";
295 }; 390 };
296 /* Variable factor clocks */ 391 /* Variable factor clocks */
297 sd1_clk: sd2_clk@e6150078 { 392 sd2_clk: sd2_clk@e6150078 {
298 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 393 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
299 reg = <0 0xe6150078 0 4>; 394 reg = <0 0xe6150078 0 4>;
300 clocks = <&pll1_div2_clk>; 395 clocks = <&pll1_div2_clk>;
301 #clock-cells = <0>; 396 #clock-cells = <0>;
302 clock-output-names = "sd1"; 397 clock-output-names = "sd2";
303 }; 398 };
304 sd2_clk: sd3_clk@e615007c { 399 sd3_clk: sd3_clk@e615026c {
305 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 400 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
306 reg = <0 0xe615007c 0 4>; 401 reg = <0 0xe615026c 0 4>;
307 clocks = <&pll1_div2_clk>; 402 clocks = <&pll1_div2_clk>;
308 #clock-cells = <0>; 403 #clock-cells = <0>;
309 clock-output-names = "sd2"; 404 clock-output-names = "sd3";
310 }; 405 };
311 mmc0_clk: mmc0_clk@e6150240 { 406 mmc0_clk: mmc0_clk@e6150240 {
312 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 407 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
@@ -518,7 +613,7 @@
518 mstp3_clks: mstp3_clks@e615013c { 613 mstp3_clks: mstp3_clks@e615013c {
519 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 614 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
520 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 615 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
521 clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>, 616 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
522 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; 617 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
523 #clock-cells = <1>; 618 #clock-cells = <1>;
524 clock-indices = < 619 clock-indices = <
@@ -585,4 +680,54 @@
585 clock-output-names = "scifa3", "scifa4", "scifa5"; 680 clock-output-names = "scifa3", "scifa4", "scifa5";
586 }; 681 };
587 }; 682 };
683
684 ipmmu_sy0: mmu@e6280000 {
685 compatible = "renesas,ipmmu-vmsa";
686 reg = <0 0xe6280000 0 0x1000>;
687 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
688 <0 224 IRQ_TYPE_LEVEL_HIGH>;
689 #iommu-cells = <1>;
690 status = "disabled";
691 };
692
693 ipmmu_sy1: mmu@e6290000 {
694 compatible = "renesas,ipmmu-vmsa";
695 reg = <0 0xe6290000 0 0x1000>;
696 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
697 #iommu-cells = <1>;
698 status = "disabled";
699 };
700
701 ipmmu_ds: mmu@e6740000 {
702 compatible = "renesas,ipmmu-vmsa";
703 reg = <0 0xe6740000 0 0x1000>;
704 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
705 <0 199 IRQ_TYPE_LEVEL_HIGH>;
706 #iommu-cells = <1>;
707 };
708
709 ipmmu_mp: mmu@ec680000 {
710 compatible = "renesas,ipmmu-vmsa";
711 reg = <0 0xec680000 0 0x1000>;
712 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
713 #iommu-cells = <1>;
714 status = "disabled";
715 };
716
717 ipmmu_mx: mmu@fe951000 {
718 compatible = "renesas,ipmmu-vmsa";
719 reg = <0 0xfe951000 0 0x1000>;
720 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
721 <0 221 IRQ_TYPE_LEVEL_HIGH>;
722 #iommu-cells = <1>;
723 };
724
725 ipmmu_gp: mmu@e62a0000 {
726 compatible = "renesas,ipmmu-vmsa";
727 reg = <0 0xe62a0000 0 0x1000>;
728 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
729 <0 261 IRQ_TYPE_LEVEL_HIGH>;
730 #iommu-cells = <1>;
731 status = "disabled";
732 };
588}; 733};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 6d32c87632d4..bf365f7fef47 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -45,7 +45,7 @@
45 45
46 memory { 46 memory {
47 device_type = "memory"; 47 device_type = "memory";
48 reg = <0x41000000 0x1e800000>; 48 reg = <0x40000000 0x20000000>;
49 }; 49 };
50 50
51 reg_1p8v: regulator@0 { 51 reg_1p8v: regulator@0 {
@@ -188,6 +188,33 @@
188 188
189&i2c0 { 189&i2c0 {
190 status = "okay"; 190 status = "okay";
191
192 compass@c {
193 compatible = "asahi-kasei,ak8975";
194 reg = <0x0c>;
195 interrupt-parent = <&irqpin3>;
196 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
197 };
198
199 ak4648: codec@12 {
200 compatible = "asahi-kasei,ak4648";
201 reg = <0x12>;
202 #sound-dai-cells = <0>;
203 };
204
205 accelerometer@1d {
206 compatible = "adi,adxl34x";
207 reg = <0x1d>;
208 interrupt-parent = <&irqpin3>;
209 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
210 <3 IRQ_TYPE_LEVEL_HIGH>;
211 };
212
213 rtc@32 {
214 compatible = "ricoh,r2025sd";
215 reg = <0x32>;
216 };
217
191 as3711@40 { 218 as3711@40 {
192 compatible = "ams,as3711"; 219 compatible = "ams,as3711";
193 reg = <0x40>; 220 reg = <0x40>;
@@ -258,11 +285,16 @@
258 }; 285 };
259 }; 286 };
260 }; 287 };
288};
261 289
262 ak4648: ak4648@12 { 290&i2c1 {
263 #sound-dai-cells = <0>; 291 status = "okay";
264 compatible = "asahi-kasei,ak4648"; 292
265 reg = <0x12>; 293 touchscreen@55 {
294 compatible = "sitronix,st1232";
295 reg = <0x55>;
296 interrupt-parent = <&irqpin1>;
297 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
266 }; 298 };
267}; 299};
268 300
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 27c5f426d172..e7dae01933a5 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -21,6 +21,6 @@
21 21
22 memory { 22 memory {
23 device_type = "memory"; 23 device_type = "memory";
24 reg = <0x41000000 0x1e800000>; 24 reg = <0x40000000 0x20000000>;
25 }; 25 };
26}; 26};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 2dfd5b44255d..ab319b73e282 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -94,6 +94,8 @@
94 0 6 IRQ_TYPE_LEVEL_HIGH 94 0 6 IRQ_TYPE_LEVEL_HIGH
95 0 7 IRQ_TYPE_LEVEL_HIGH 95 0 7 IRQ_TYPE_LEVEL_HIGH
96 0 8 IRQ_TYPE_LEVEL_HIGH>; 96 0 8 IRQ_TYPE_LEVEL_HIGH>;
97 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
98 control-parent;
97 }; 99 };
98 100
99 irqpin1: irqpin@e6900004 { 101 irqpin1: irqpin@e6900004 {
@@ -113,6 +115,7 @@
113 0 14 IRQ_TYPE_LEVEL_HIGH 115 0 14 IRQ_TYPE_LEVEL_HIGH
114 0 15 IRQ_TYPE_LEVEL_HIGH 116 0 15 IRQ_TYPE_LEVEL_HIGH
115 0 16 IRQ_TYPE_LEVEL_HIGH>; 117 0 16 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
116 control-parent; 119 control-parent;
117 }; 120 };
118 121
@@ -133,6 +136,8 @@
133 0 22 IRQ_TYPE_LEVEL_HIGH 136 0 22 IRQ_TYPE_LEVEL_HIGH
134 0 23 IRQ_TYPE_LEVEL_HIGH 137 0 23 IRQ_TYPE_LEVEL_HIGH
135 0 24 IRQ_TYPE_LEVEL_HIGH>; 138 0 24 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
140 control-parent;
136 }; 141 };
137 142
138 irqpin3: irqpin@e690000c { 143 irqpin3: irqpin@e690000c {
@@ -152,6 +157,8 @@
152 0 30 IRQ_TYPE_LEVEL_HIGH 157 0 30 IRQ_TYPE_LEVEL_HIGH
153 0 31 IRQ_TYPE_LEVEL_HIGH 158 0 31 IRQ_TYPE_LEVEL_HIGH
154 0 32 IRQ_TYPE_LEVEL_HIGH>; 159 0 32 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
161 control-parent;
155 }; 162 };
156 163
157 i2c0: i2c@e6820000 { 164 i2c0: i2c@e6820000 {
@@ -426,133 +433,159 @@
426 vclk1_clk: vclk1_clk@e6150008 { 433 vclk1_clk: vclk1_clk@e6150008 {
427 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 434 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
428 reg = <0xe6150008 4>; 435 reg = <0xe6150008 4>;
429 clocks = <&pll1_div2_clk>; 436 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
437 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
438 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
439 <0>;
430 #clock-cells = <0>; 440 #clock-cells = <0>;
431 clock-output-names = "vclk1"; 441 clock-output-names = "vclk1";
432 }; 442 };
433 vclk2_clk: vclk2_clk@e615000c { 443 vclk2_clk: vclk2_clk@e615000c {
434 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 444 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
435 reg = <0xe615000c 4>; 445 reg = <0xe615000c 4>;
436 clocks = <&pll1_div2_clk>; 446 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
447 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
448 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
449 <0>;
437 #clock-cells = <0>; 450 #clock-cells = <0>;
438 clock-output-names = "vclk2"; 451 clock-output-names = "vclk2";
439 }; 452 };
440 vclk3_clk: vclk3_clk@e615001c { 453 vclk3_clk: vclk3_clk@e615001c {
441 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 454 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
442 reg = <0xe615001c 4>; 455 reg = <0xe615001c 4>;
443 clocks = <&pll1_div2_clk>; 456 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
457 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
458 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
459 <0>;
444 #clock-cells = <0>; 460 #clock-cells = <0>;
445 clock-output-names = "vclk3"; 461 clock-output-names = "vclk3";
446 }; 462 };
447 zb_clk: zb_clk@e6150010 { 463 zb_clk: zb_clk@e6150010 {
448 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 464 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
449 reg = <0xe6150010 4>; 465 reg = <0xe6150010 4>;
450 clocks = <&pll1_div2_clk>; 466 clocks = <&pll1_div2_clk>, <0>,
467 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
451 #clock-cells = <0>; 468 #clock-cells = <0>;
452 clock-output-names = "zb"; 469 clock-output-names = "zb";
453 }; 470 };
454 flctl_clk: flctl_clk@e6150014 { 471 flctl_clk: flctl_clk@e6150014 {
455 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 472 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
456 reg = <0xe6150014 4>; 473 reg = <0xe6150014 4>;
457 clocks = <&pll1_div2_clk>; 474 clocks = <&pll1_div2_clk>, <0>,
475 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
458 #clock-cells = <0>; 476 #clock-cells = <0>;
459 clock-output-names = "flctlck"; 477 clock-output-names = "flctlck";
460 }; 478 };
461 sdhi0_clk: sdhi0_clk@e6150074 { 479 sdhi0_clk: sdhi0_clk@e6150074 {
462 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 480 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
463 reg = <0xe6150074 4>; 481 reg = <0xe6150074 4>;
464 clocks = <&pll1_div2_clk>; 482 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
483 <&pll1_div13_clk>, <0>;
465 #clock-cells = <0>; 484 #clock-cells = <0>;
466 clock-output-names = "sdhi0ck"; 485 clock-output-names = "sdhi0ck";
467 }; 486 };
468 sdhi1_clk: sdhi1_clk@e6150078 { 487 sdhi1_clk: sdhi1_clk@e6150078 {
469 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 488 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
470 reg = <0xe6150078 4>; 489 reg = <0xe6150078 4>;
471 clocks = <&pll1_div2_clk>; 490 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
491 <&pll1_div13_clk>, <0>;
472 #clock-cells = <0>; 492 #clock-cells = <0>;
473 clock-output-names = "sdhi1ck"; 493 clock-output-names = "sdhi1ck";
474 }; 494 };
475 sdhi2_clk: sdhi2_clk@e615007c { 495 sdhi2_clk: sdhi2_clk@e615007c {
476 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 496 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
477 reg = <0xe615007c 4>; 497 reg = <0xe615007c 4>;
478 clocks = <&pll1_div2_clk>; 498 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
499 <&pll1_div13_clk>, <0>;
479 #clock-cells = <0>; 500 #clock-cells = <0>;
480 clock-output-names = "sdhi2ck"; 501 clock-output-names = "sdhi2ck";
481 }; 502 };
482 fsia_clk: fsia_clk@e6150018 { 503 fsia_clk: fsia_clk@e6150018 {
483 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 504 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
484 reg = <0xe6150018 4>; 505 reg = <0xe6150018 4>;
485 clocks = <&pll1_div2_clk>; 506 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
507 <&fsiack_clk>, <&fsiack_clk>;
486 #clock-cells = <0>; 508 #clock-cells = <0>;
487 clock-output-names = "fsia"; 509 clock-output-names = "fsia";
488 }; 510 };
489 fsib_clk: fsib_clk@e6150090 { 511 fsib_clk: fsib_clk@e6150090 {
490 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 512 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
491 reg = <0xe6150090 4>; 513 reg = <0xe6150090 4>;
492 clocks = <&pll1_div2_clk>; 514 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
515 <&fsibck_clk>, <&fsibck_clk>;
493 #clock-cells = <0>; 516 #clock-cells = <0>;
494 clock-output-names = "fsib"; 517 clock-output-names = "fsib";
495 }; 518 };
496 sub_clk: sub_clk@e6150080 { 519 sub_clk: sub_clk@e6150080 {
497 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 520 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
498 reg = <0xe6150080 4>; 521 reg = <0xe6150080 4>;
499 clocks = <&extal2_clk>; 522 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
523 <&extal2_clk>, <&extal2_clk>;
500 #clock-cells = <0>; 524 #clock-cells = <0>;
501 clock-output-names = "sub"; 525 clock-output-names = "sub";
502 }; 526 };
503 spua_clk: spua_clk@e6150084 { 527 spua_clk: spua_clk@e6150084 {
504 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 528 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
505 reg = <0xe6150084 4>; 529 reg = <0xe6150084 4>;
506 clocks = <&pll1_div2_clk>; 530 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
531 <&extal2_clk>, <&extal2_clk>;
507 #clock-cells = <0>; 532 #clock-cells = <0>;
508 clock-output-names = "spua"; 533 clock-output-names = "spua";
509 }; 534 };
510 spuv_clk: spuv_clk@e6150094 { 535 spuv_clk: spuv_clk@e6150094 {
511 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 536 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
512 reg = <0xe6150094 4>; 537 reg = <0xe6150094 4>;
513 clocks = <&pll1_div2_clk>; 538 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
539 <&extal2_clk>, <&extal2_clk>;
514 #clock-cells = <0>; 540 #clock-cells = <0>;
515 clock-output-names = "spuv"; 541 clock-output-names = "spuv";
516 }; 542 };
517 msu_clk: msu_clk@e6150088 { 543 msu_clk: msu_clk@e6150088 {
518 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 544 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
519 reg = <0xe6150088 4>; 545 reg = <0xe6150088 4>;
520 clocks = <&pll1_div2_clk>; 546 clocks = <&pll1_div2_clk>, <0>,
547 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
521 #clock-cells = <0>; 548 #clock-cells = <0>;
522 clock-output-names = "msu"; 549 clock-output-names = "msu";
523 }; 550 };
524 hsi_clk: hsi_clk@e615008c { 551 hsi_clk: hsi_clk@e615008c {
525 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 552 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
526 reg = <0xe615008c 4>; 553 reg = <0xe615008c 4>;
527 clocks = <&pll1_div2_clk>; 554 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
555 <&pll1_div7_clk>, <0>;
528 #clock-cells = <0>; 556 #clock-cells = <0>;
529 clock-output-names = "hsi"; 557 clock-output-names = "hsi";
530 }; 558 };
531 mfg1_clk: mfg1_clk@e6150098 { 559 mfg1_clk: mfg1_clk@e6150098 {
532 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 560 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
533 reg = <0xe6150098 4>; 561 reg = <0xe6150098 4>;
534 clocks = <&pll1_div2_clk>; 562 clocks = <&pll1_div2_clk>, <0>,
563 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
535 #clock-cells = <0>; 564 #clock-cells = <0>;
536 clock-output-names = "mfg1"; 565 clock-output-names = "mfg1";
537 }; 566 };
538 mfg2_clk: mfg2_clk@e615009c { 567 mfg2_clk: mfg2_clk@e615009c {
539 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 568 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
540 reg = <0xe615009c 4>; 569 reg = <0xe615009c 4>;
541 clocks = <&pll1_div2_clk>; 570 clocks = <&pll1_div2_clk>, <0>,
571 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
542 #clock-cells = <0>; 572 #clock-cells = <0>;
543 clock-output-names = "mfg2"; 573 clock-output-names = "mfg2";
544 }; 574 };
545 dsit_clk: dsit_clk@e6150060 { 575 dsit_clk: dsit_clk@e6150060 {
546 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 576 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
547 reg = <0xe6150060 4>; 577 reg = <0xe6150060 4>;
548 clocks = <&pll1_div2_clk>; 578 clocks = <&pll1_div2_clk>, <0>,
579 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
549 #clock-cells = <0>; 580 #clock-cells = <0>;
550 clock-output-names = "dsit"; 581 clock-output-names = "dsit";
551 }; 582 };
552 dsi0p_clk: dsi0p_clk@e6150064 { 583 dsi0p_clk: dsi0p_clk@e6150064 {
553 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 584 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
554 reg = <0xe6150064 4>; 585 reg = <0xe6150064 4>;
555 clocks = <&pll1_div2_clk>; 586 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
587 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
588 <&extcki_clk>, <0>, <0>, <0>;
556 #clock-cells = <0>; 589 #clock-cells = <0>;
557 clock-output-names = "dsi0pck"; 590 clock-output-names = "dsi0pck";
558 }; 591 };
@@ -695,5 +728,16 @@
695 clock-output-names = 728 clock-output-names =
696 "iic3", "iic4", "keysc"; 729 "iic3", "iic4", "keysc";
697 }; 730 };
731 mstp5_clks: mstp5_clks@e6150144 {
732 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
733 reg = <0xe6150144 4>, <0xe615003c 4>;
734 clocks = <&cpg_clocks SH73A0_CLK_HP>;
735 #clock-cells = <1>;
736 clock-indices = <
737 SH73A0_CLK_INTCA0
738 >;
739 clock-output-names =
740 "intca0";
741 };
698 }; 742 };
699}; 743};
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 9c3da1345b8b..a5bef873d37e 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -37,11 +37,11 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
37 37
38static struct rcar_apmu_config r8a7790_apmu_config[] = { 38static struct rcar_apmu_config r8a7790_apmu_config[] = {
39 { 39 {
40 .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), 40 .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
41 .cpus = { 0, 1, 2, 3 }, 41 .cpus = { 0, 1, 2, 3 },
42 }, 42 },
43 { 43 {
44 .iomem = DEFINE_RES_MEM(0xe6151000, 0x88), 44 .iomem = DEFINE_RES_MEM(0xe6151000, 0x188),
45 .cpus = { 0x100, 0x0101, 0x102, 0x103 }, 45 .cpus = { 0x100, 0x0101, 0x102, 0x103 },
46 } 46 }
47}; 47};
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index 7e49e0a52e32..de1d92dc1323 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -27,7 +27,7 @@
27 27
28static struct rcar_apmu_config r8a7791_apmu_config[] = { 28static struct rcar_apmu_config r8a7791_apmu_config[] = {
29 { 29 {
30 .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), 30 .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
31 .cpus = { 0, 1 }, 31 .cpus = { 0, 1 },
32 } 32 }
33}; 33};
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 91940271cf83..3f2c6b198d4a 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -21,6 +21,8 @@
21#define R8A7790_CLK_SD0 7 21#define R8A7790_CLK_SD0 7
22#define R8A7790_CLK_SD1 8 22#define R8A7790_CLK_SD1 8
23#define R8A7790_CLK_Z 9 23#define R8A7790_CLK_Z 9
24#define R8A7790_CLK_RCAN 10
25#define R8A7790_CLK_ADSP 11
24 26
25/* MSTP0 */ 27/* MSTP0 */
26#define R8A7790_CLK_MSIOF0 0 28#define R8A7790_CLK_MSIOF0 0
@@ -80,6 +82,7 @@
80/* MSTP5 */ 82/* MSTP5 */
81#define R8A7790_CLK_AUDIO_DMAC1 1 83#define R8A7790_CLK_AUDIO_DMAC1 1
82#define R8A7790_CLK_AUDIO_DMAC0 2 84#define R8A7790_CLK_AUDIO_DMAC0 2
85#define R8A7790_CLK_ADSP_MOD 6
83#define R8A7790_CLK_THERMAL 22 86#define R8A7790_CLK_THERMAL 22
84#define R8A7790_CLK_PWM 23 87#define R8A7790_CLK_PWM 23
85 88
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index f096f3f6c16a..8fc5dc8faeea 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -20,6 +20,8 @@
20#define R8A7791_CLK_SDH 6 20#define R8A7791_CLK_SDH 6
21#define R8A7791_CLK_SD0 7 21#define R8A7791_CLK_SD0 7
22#define R8A7791_CLK_Z 8 22#define R8A7791_CLK_Z 8
23#define R8A7791_CLK_RCAN 9
24#define R8A7791_CLK_ADSP 10
23 25
24/* MSTP0 */ 26/* MSTP0 */
25#define R8A7791_CLK_MSIOF0 0 27#define R8A7791_CLK_MSIOF0 0
@@ -71,6 +73,7 @@
71/* MSTP5 */ 73/* MSTP5 */
72#define R8A7791_CLK_AUDIO_DMAC1 1 74#define R8A7791_CLK_AUDIO_DMAC1 1
73#define R8A7791_CLK_AUDIO_DMAC0 2 75#define R8A7791_CLK_AUDIO_DMAC0 2
76#define R8A7791_CLK_ADSP_MOD 6
74#define R8A7791_CLK_THERMAL 22 77#define R8A7791_CLK_THERMAL 22
75#define R8A7791_CLK_PWM 23 78#define R8A7791_CLK_PWM 23
76 79
diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h
index 1dd3eb2b7d90..53369568c24c 100644
--- a/include/dt-bindings/clock/sh73a0-clock.h
+++ b/include/dt-bindings/clock/sh73a0-clock.h
@@ -76,4 +76,7 @@
76#define SH73A0_CLK_IIC4 10 76#define SH73A0_CLK_IIC4 10
77#define SH73A0_CLK_KEYSC 3 77#define SH73A0_CLK_KEYSC 3
78 78
79/* MSTP5 */
80#define SH73A0_CLK_INTCA0 8
81
79#endif 82#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 08:33:08 -0400