aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Walleij <linus.walleij@linaro.org>2017-08-22 09:32:28 -0400
committerLinus Walleij <linus.walleij@linaro.org>2017-08-22 09:32:28 -0400
commitdddd9663d16512ca42c11cd3d0410008a7d258f6 (patch)
tree55d0074563956be7572b6290a08c7586a6abdeb0
parent1865af212dfa0819ca21c7e5c18c2a75202c1827 (diff)
parent56d57391ab6720c4b7bbc0a0cbc079c7b7d653fb (diff)
Merge tag 'sh-pfc-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v4.14 - Propagate errors on group config, now r8a7740-armadillo800eva.dts is fixed, - Add MSIOF and USB2.0 pin groups on R-Car H3 ES2.0, - Add USB2.0 and USB3.0 pin groups on R-Car M3-W, - Add a missing MMC pin group on R-Car M2-W and RZ/G1M, - Add initial support for R-Car D3, - Small fixes and cleanups.
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt1
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c6
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c15
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c1082
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c146
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77995.c1812
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c9
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h23
10 files changed, 2978 insertions, 122 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 645082f03259..f4d127df980d 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -24,6 +24,7 @@ Required Properties:
24 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. 24 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
25 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. 25 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
26 - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. 26 - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
27 - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
27 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. 28 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
28 29
29 - reg: Base address and length of each memory resource used by the pin 30 - reg: Base address and length of each memory resource used by the pin
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 24f76a05a5a9..5d5312eb7102 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
89 depends on ARCH_R8A7796 89 depends on ARCH_R8A7796
90 select PINCTRL_SH_PFC 90 select PINCTRL_SH_PFC
91 91
92config PINCTRL_PFC_R8A77995
93 def_bool y
94 depends on ARCH_R8A77995
95 select PINCTRL_SH_PFC
96
92config PINCTRL_PFC_SH7203 97config PINCTRL_PFC_SH7203
93 def_bool y 98 def_bool y
94 depends on CPU_SUBTYPE_SH7203 99 depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 33d28eed9ba3..1d4f05a96bd4 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
15obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o 15obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
16obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o 16obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
17obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o 17obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
18obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
18obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 19obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
19obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 20obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
20obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 21obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index e72391d5e57d..0c5e952461fd 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -551,6 +551,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
551 .data = &r8a7796_pinmux_info, 551 .data = &r8a7796_pinmux_info,
552 }, 552 },
553#endif 553#endif
554#ifdef CONFIG_PINCTRL_PFC_R8A77995
555 {
556 .compatible = "renesas,pfc-r8a77995",
557 .data = &r8a77995_pinmux_info,
558 },
559#endif
554#ifdef CONFIG_PINCTRL_PFC_SH73A0 560#ifdef CONFIG_PINCTRL_PFC_SH73A0
555 { 561 {
556 .compatible = "renesas,pfc-sh73a0", 562 .compatible = "renesas,pfc-sh73a0",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 4c5ffbd75be7..10bd35f8c894 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -2589,6 +2589,17 @@ static const unsigned int mmc_data8_mux[] = {
2589 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, 2589 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2590 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, 2590 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2591}; 2591};
2592static const unsigned int mmc_data8_b_pins[] = {
2593 /* D[0:7] */
2594 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2595 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2596 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2597 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2598};
2599static const unsigned int mmc_data8_b_mux[] = {
2600 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2601 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2602};
2592static const unsigned int mmc_ctrl_pins[] = { 2603static const unsigned int mmc_ctrl_pins[] = {
2593 /* CLK, CMD */ 2604 /* CLK, CMD */
2594 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), 2605 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
@@ -4420,7 +4431,7 @@ static const unsigned int vin2_clk_mux[] = {
4420}; 4431};
4421 4432
4422static const struct { 4433static const struct {
4423 struct sh_pfc_pin_group common[341]; 4434 struct sh_pfc_pin_group common[342];
4424 struct sh_pfc_pin_group r8a779x[9]; 4435 struct sh_pfc_pin_group r8a779x[9];
4425} pinmux_groups = { 4436} pinmux_groups = {
4426 .common = { 4437 .common = {
@@ -4523,6 +4534,7 @@ static const struct {
4523 SH_PFC_PIN_GROUP(mmc_data1), 4534 SH_PFC_PIN_GROUP(mmc_data1),
4524 SH_PFC_PIN_GROUP(mmc_data4), 4535 SH_PFC_PIN_GROUP(mmc_data4),
4525 SH_PFC_PIN_GROUP(mmc_data8), 4536 SH_PFC_PIN_GROUP(mmc_data8),
4537 SH_PFC_PIN_GROUP(mmc_data8_b),
4526 SH_PFC_PIN_GROUP(mmc_ctrl), 4538 SH_PFC_PIN_GROUP(mmc_ctrl),
4527 SH_PFC_PIN_GROUP(msiof0_clk), 4539 SH_PFC_PIN_GROUP(msiof0_clk),
4528 SH_PFC_PIN_GROUP(msiof0_sync), 4540 SH_PFC_PIN_GROUP(msiof0_sync),
@@ -4955,6 +4967,7 @@ static const char * const mmc_groups[] = {
4955 "mmc_data1", 4967 "mmc_data1",
4956 "mmc_data4", 4968 "mmc_data4",
4957 "mmc_data8", 4969 "mmc_data8",
4970 "mmc_data8_b",
4958 "mmc_ctrl", 4971 "mmc_ctrl",
4959}; 4972};
4960 4973
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 1656295af2b0..8b35772cda98 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -61,7 +61,7 @@
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28) 61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24) 62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20) 63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) 64#define GPSR1_21 F_(CS1_N, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12) 65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8) 66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4) 67#define GPSR1_18 F_(A18, IP4_7_4)
@@ -168,8 +168,8 @@
168#define GPSR5_0 F_(SCK0, IP11_27_24) 168#define GPSR5_0 F_(SCK0, IP11_27_24)
169 169
170/* GPSR6 */ 170/* GPSR6 */
171#define GPSR6_31 F_(USB3_OVC, IP18_7_4) 171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB3_PWEN, IP18_3_0) 172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
173#define GPSR6_29 F_(USB30_OVC, IP17_31_28) 173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24) 174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20) 175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
@@ -215,8 +215,8 @@
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -247,7 +247,7 @@
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -270,7 +270,6 @@
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 274
276/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@@ -285,24 +284,24 @@
285#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 306
308/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@@ -361,8 +360,8 @@
361#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP18_3_0 FM(USB3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) 363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
365#define IP18_7_4 FM(USB3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) 364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
366 365
367#define PINMUX_GPSR \ 366#define PINMUX_GPSR \
368\ 367\
@@ -413,7 +412,7 @@ FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_3
413FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
417FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
@@ -469,7 +468,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
469/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0) 470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) 471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
473#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3) 472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0) 473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1) 474#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
@@ -480,7 +479,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
480#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
483#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) 482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
484#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
@@ -497,7 +496,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
497#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) 496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) 497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
501#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) 499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
502#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
503#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) 501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
@@ -514,7 +512,7 @@ MOD_SEL0_28_27 MOD_SEL2_28_27 \
514MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \ 512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
515 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \ 513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
516MOD_SEL0_23 MOD_SEL1_23_22_21 \ 514MOD_SEL0_23 MOD_SEL1_23_22_21 \
517MOD_SEL0_22 MOD_SEL2_22 \ 515MOD_SEL0_22 \
518MOD_SEL0_21 MOD_SEL2_21 \ 516MOD_SEL0_21 MOD_SEL2_21 \
519MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \ 517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
520MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \ 518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
@@ -833,7 +831,7 @@ static const u16 pinmux_data[] = {
833 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
834 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
835 833
836 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), 834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
837 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
838 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
839 837
@@ -986,8 +984,6 @@ static const u16 pinmux_data[] = {
986 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
987 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
988 986
989 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
990
991 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
992 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
@@ -1023,35 +1019,35 @@ static const u16 pinmux_data[] = {
1023 1019
1024 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), 1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1025 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), 1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), 1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1027 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), 1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1028 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), 1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1029 1025
1030 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), 1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1031 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), 1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1032 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), 1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), 1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1034 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), 1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), 1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1036 1032
1037 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), 1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1038 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), 1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1039 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), 1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), 1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1041 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), 1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), 1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1043 1039
1044 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), 1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1045 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), 1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1046 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), 1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), 1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1048 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), 1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), 1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1050 1046
1051 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), 1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1052 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), 1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1053 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), 1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1054 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), 1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1055 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), 1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1056 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), 1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1057 1053
@@ -1201,7 +1197,7 @@ static const u16 pinmux_data[] = {
1201 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1202 1198
1203 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1), 1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1205 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1206 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
@@ -1271,12 +1267,12 @@ static const u16 pinmux_data[] = {
1271 /* IPSR14 */ 1267 /* IPSR14 */
1272 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), 1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1273 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), 1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), 1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1275 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), 1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1276 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0), 1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1277 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), 1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1278 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), 1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1279 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1), 1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1280 1276
1281 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), 1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1282 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), 1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
@@ -1392,7 +1388,7 @@ static const u16 pinmux_data[] = {
1392 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0), 1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1396 1392
1397 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1398 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
@@ -1409,17 +1405,17 @@ static const u16 pinmux_data[] = {
1409 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), 1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1410 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1411 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1412 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A), 1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1413 1409
1414 /* IPSR17 */ 1410 /* IPSR17 */
1415 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), 1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1416 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), 1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1417 1413
1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), 1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0), 1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1422 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1423 1419
1424 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN), 1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1425 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2), 1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
@@ -1460,10 +1456,10 @@ static const u16 pinmux_data[] = {
1460 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1461 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), 1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1463 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1465 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1466 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1), 1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1467 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1468 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1469 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
@@ -1479,7 +1475,7 @@ static const u16 pinmux_data[] = {
1479 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1480 1476
1481 /* IPSR18 */ 1477 /* IPSR18 */
1482 PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN), 1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1483 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B), 1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1484 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1), 1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1485 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4), 1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
@@ -1489,7 +1485,7 @@ static const u16 pinmux_data[] = {
1489 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1491 1487
1492 PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC), 1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1493 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B), 1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1494 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1), 1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1495 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4), 1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
@@ -1744,6 +1740,704 @@ static const unsigned int du_disp_mux[] = {
1744 DU_DISP_MARK, 1740 DU_DISP_MARK,
1745}; 1741};
1746 1742
1743/* - MSIOF0 ----------------------------------------------------------------- */
1744static const unsigned int msiof0_clk_pins[] = {
1745 /* SCK */
1746 RCAR_GP_PIN(5, 17),
1747};
1748static const unsigned int msiof0_clk_mux[] = {
1749 MSIOF0_SCK_MARK,
1750};
1751static const unsigned int msiof0_sync_pins[] = {
1752 /* SYNC */
1753 RCAR_GP_PIN(5, 18),
1754};
1755static const unsigned int msiof0_sync_mux[] = {
1756 MSIOF0_SYNC_MARK,
1757};
1758static const unsigned int msiof0_ss1_pins[] = {
1759 /* SS1 */
1760 RCAR_GP_PIN(5, 19),
1761};
1762static const unsigned int msiof0_ss1_mux[] = {
1763 MSIOF0_SS1_MARK,
1764};
1765static const unsigned int msiof0_ss2_pins[] = {
1766 /* SS2 */
1767 RCAR_GP_PIN(5, 21),
1768};
1769static const unsigned int msiof0_ss2_mux[] = {
1770 MSIOF0_SS2_MARK,
1771};
1772static const unsigned int msiof0_txd_pins[] = {
1773 /* TXD */
1774 RCAR_GP_PIN(5, 20),
1775};
1776static const unsigned int msiof0_txd_mux[] = {
1777 MSIOF0_TXD_MARK,
1778};
1779static const unsigned int msiof0_rxd_pins[] = {
1780 /* RXD */
1781 RCAR_GP_PIN(5, 22),
1782};
1783static const unsigned int msiof0_rxd_mux[] = {
1784 MSIOF0_RXD_MARK,
1785};
1786/* - MSIOF1 ----------------------------------------------------------------- */
1787static const unsigned int msiof1_clk_a_pins[] = {
1788 /* SCK */
1789 RCAR_GP_PIN(6, 8),
1790};
1791static const unsigned int msiof1_clk_a_mux[] = {
1792 MSIOF1_SCK_A_MARK,
1793};
1794static const unsigned int msiof1_sync_a_pins[] = {
1795 /* SYNC */
1796 RCAR_GP_PIN(6, 9),
1797};
1798static const unsigned int msiof1_sync_a_mux[] = {
1799 MSIOF1_SYNC_A_MARK,
1800};
1801static const unsigned int msiof1_ss1_a_pins[] = {
1802 /* SS1 */
1803 RCAR_GP_PIN(6, 5),
1804};
1805static const unsigned int msiof1_ss1_a_mux[] = {
1806 MSIOF1_SS1_A_MARK,
1807};
1808static const unsigned int msiof1_ss2_a_pins[] = {
1809 /* SS2 */
1810 RCAR_GP_PIN(6, 6),
1811};
1812static const unsigned int msiof1_ss2_a_mux[] = {
1813 MSIOF1_SS2_A_MARK,
1814};
1815static const unsigned int msiof1_txd_a_pins[] = {
1816 /* TXD */
1817 RCAR_GP_PIN(6, 7),
1818};
1819static const unsigned int msiof1_txd_a_mux[] = {
1820 MSIOF1_TXD_A_MARK,
1821};
1822static const unsigned int msiof1_rxd_a_pins[] = {
1823 /* RXD */
1824 RCAR_GP_PIN(6, 10),
1825};
1826static const unsigned int msiof1_rxd_a_mux[] = {
1827 MSIOF1_RXD_A_MARK,
1828};
1829static const unsigned int msiof1_clk_b_pins[] = {
1830 /* SCK */
1831 RCAR_GP_PIN(5, 9),
1832};
1833static const unsigned int msiof1_clk_b_mux[] = {
1834 MSIOF1_SCK_B_MARK,
1835};
1836static const unsigned int msiof1_sync_b_pins[] = {
1837 /* SYNC */
1838 RCAR_GP_PIN(5, 3),
1839};
1840static const unsigned int msiof1_sync_b_mux[] = {
1841 MSIOF1_SYNC_B_MARK,
1842};
1843static const unsigned int msiof1_ss1_b_pins[] = {
1844 /* SS1 */
1845 RCAR_GP_PIN(5, 4),
1846};
1847static const unsigned int msiof1_ss1_b_mux[] = {
1848 MSIOF1_SS1_B_MARK,
1849};
1850static const unsigned int msiof1_ss2_b_pins[] = {
1851 /* SS2 */
1852 RCAR_GP_PIN(5, 0),
1853};
1854static const unsigned int msiof1_ss2_b_mux[] = {
1855 MSIOF1_SS2_B_MARK,
1856};
1857static const unsigned int msiof1_txd_b_pins[] = {
1858 /* TXD */
1859 RCAR_GP_PIN(5, 8),
1860};
1861static const unsigned int msiof1_txd_b_mux[] = {
1862 MSIOF1_TXD_B_MARK,
1863};
1864static const unsigned int msiof1_rxd_b_pins[] = {
1865 /* RXD */
1866 RCAR_GP_PIN(5, 7),
1867};
1868static const unsigned int msiof1_rxd_b_mux[] = {
1869 MSIOF1_RXD_B_MARK,
1870};
1871static const unsigned int msiof1_clk_c_pins[] = {
1872 /* SCK */
1873 RCAR_GP_PIN(6, 17),
1874};
1875static const unsigned int msiof1_clk_c_mux[] = {
1876 MSIOF1_SCK_C_MARK,
1877};
1878static const unsigned int msiof1_sync_c_pins[] = {
1879 /* SYNC */
1880 RCAR_GP_PIN(6, 18),
1881};
1882static const unsigned int msiof1_sync_c_mux[] = {
1883 MSIOF1_SYNC_C_MARK,
1884};
1885static const unsigned int msiof1_ss1_c_pins[] = {
1886 /* SS1 */
1887 RCAR_GP_PIN(6, 21),
1888};
1889static const unsigned int msiof1_ss1_c_mux[] = {
1890 MSIOF1_SS1_C_MARK,
1891};
1892static const unsigned int msiof1_ss2_c_pins[] = {
1893 /* SS2 */
1894 RCAR_GP_PIN(6, 27),
1895};
1896static const unsigned int msiof1_ss2_c_mux[] = {
1897 MSIOF1_SS2_C_MARK,
1898};
1899static const unsigned int msiof1_txd_c_pins[] = {
1900 /* TXD */
1901 RCAR_GP_PIN(6, 20),
1902};
1903static const unsigned int msiof1_txd_c_mux[] = {
1904 MSIOF1_TXD_C_MARK,
1905};
1906static const unsigned int msiof1_rxd_c_pins[] = {
1907 /* RXD */
1908 RCAR_GP_PIN(6, 19),
1909};
1910static const unsigned int msiof1_rxd_c_mux[] = {
1911 MSIOF1_RXD_C_MARK,
1912};
1913static const unsigned int msiof1_clk_d_pins[] = {
1914 /* SCK */
1915 RCAR_GP_PIN(5, 12),
1916};
1917static const unsigned int msiof1_clk_d_mux[] = {
1918 MSIOF1_SCK_D_MARK,
1919};
1920static const unsigned int msiof1_sync_d_pins[] = {
1921 /* SYNC */
1922 RCAR_GP_PIN(5, 15),
1923};
1924static const unsigned int msiof1_sync_d_mux[] = {
1925 MSIOF1_SYNC_D_MARK,
1926};
1927static const unsigned int msiof1_ss1_d_pins[] = {
1928 /* SS1 */
1929 RCAR_GP_PIN(5, 16),
1930};
1931static const unsigned int msiof1_ss1_d_mux[] = {
1932 MSIOF1_SS1_D_MARK,
1933};
1934static const unsigned int msiof1_ss2_d_pins[] = {
1935 /* SS2 */
1936 RCAR_GP_PIN(5, 21),
1937};
1938static const unsigned int msiof1_ss2_d_mux[] = {
1939 MSIOF1_SS2_D_MARK,
1940};
1941static const unsigned int msiof1_txd_d_pins[] = {
1942 /* TXD */
1943 RCAR_GP_PIN(5, 14),
1944};
1945static const unsigned int msiof1_txd_d_mux[] = {
1946 MSIOF1_TXD_D_MARK,
1947};
1948static const unsigned int msiof1_rxd_d_pins[] = {
1949 /* RXD */
1950 RCAR_GP_PIN(5, 13),
1951};
1952static const unsigned int msiof1_rxd_d_mux[] = {
1953 MSIOF1_RXD_D_MARK,
1954};
1955static const unsigned int msiof1_clk_e_pins[] = {
1956 /* SCK */
1957 RCAR_GP_PIN(3, 0),
1958};
1959static const unsigned int msiof1_clk_e_mux[] = {
1960 MSIOF1_SCK_E_MARK,
1961};
1962static const unsigned int msiof1_sync_e_pins[] = {
1963 /* SYNC */
1964 RCAR_GP_PIN(3, 1),
1965};
1966static const unsigned int msiof1_sync_e_mux[] = {
1967 MSIOF1_SYNC_E_MARK,
1968};
1969static const unsigned int msiof1_ss1_e_pins[] = {
1970 /* SS1 */
1971 RCAR_GP_PIN(3, 4),
1972};
1973static const unsigned int msiof1_ss1_e_mux[] = {
1974 MSIOF1_SS1_E_MARK,
1975};
1976static const unsigned int msiof1_ss2_e_pins[] = {
1977 /* SS2 */
1978 RCAR_GP_PIN(3, 5),
1979};
1980static const unsigned int msiof1_ss2_e_mux[] = {
1981 MSIOF1_SS2_E_MARK,
1982};
1983static const unsigned int msiof1_txd_e_pins[] = {
1984 /* TXD */
1985 RCAR_GP_PIN(3, 3),
1986};
1987static const unsigned int msiof1_txd_e_mux[] = {
1988 MSIOF1_TXD_E_MARK,
1989};
1990static const unsigned int msiof1_rxd_e_pins[] = {
1991 /* RXD */
1992 RCAR_GP_PIN(3, 2),
1993};
1994static const unsigned int msiof1_rxd_e_mux[] = {
1995 MSIOF1_RXD_E_MARK,
1996};
1997static const unsigned int msiof1_clk_f_pins[] = {
1998 /* SCK */
1999 RCAR_GP_PIN(5, 23),
2000};
2001static const unsigned int msiof1_clk_f_mux[] = {
2002 MSIOF1_SCK_F_MARK,
2003};
2004static const unsigned int msiof1_sync_f_pins[] = {
2005 /* SYNC */
2006 RCAR_GP_PIN(5, 24),
2007};
2008static const unsigned int msiof1_sync_f_mux[] = {
2009 MSIOF1_SYNC_F_MARK,
2010};
2011static const unsigned int msiof1_ss1_f_pins[] = {
2012 /* SS1 */
2013 RCAR_GP_PIN(6, 1),
2014};
2015static const unsigned int msiof1_ss1_f_mux[] = {
2016 MSIOF1_SS1_F_MARK,
2017};
2018static const unsigned int msiof1_ss2_f_pins[] = {
2019 /* SS2 */
2020 RCAR_GP_PIN(6, 2),
2021};
2022static const unsigned int msiof1_ss2_f_mux[] = {
2023 MSIOF1_SS2_F_MARK,
2024};
2025static const unsigned int msiof1_txd_f_pins[] = {
2026 /* TXD */
2027 RCAR_GP_PIN(6, 0),
2028};
2029static const unsigned int msiof1_txd_f_mux[] = {
2030 MSIOF1_TXD_F_MARK,
2031};
2032static const unsigned int msiof1_rxd_f_pins[] = {
2033 /* RXD */
2034 RCAR_GP_PIN(5, 25),
2035};
2036static const unsigned int msiof1_rxd_f_mux[] = {
2037 MSIOF1_RXD_F_MARK,
2038};
2039static const unsigned int msiof1_clk_g_pins[] = {
2040 /* SCK */
2041 RCAR_GP_PIN(3, 6),
2042};
2043static const unsigned int msiof1_clk_g_mux[] = {
2044 MSIOF1_SCK_G_MARK,
2045};
2046static const unsigned int msiof1_sync_g_pins[] = {
2047 /* SYNC */
2048 RCAR_GP_PIN(3, 7),
2049};
2050static const unsigned int msiof1_sync_g_mux[] = {
2051 MSIOF1_SYNC_G_MARK,
2052};
2053static const unsigned int msiof1_ss1_g_pins[] = {
2054 /* SS1 */
2055 RCAR_GP_PIN(3, 10),
2056};
2057static const unsigned int msiof1_ss1_g_mux[] = {
2058 MSIOF1_SS1_G_MARK,
2059};
2060static const unsigned int msiof1_ss2_g_pins[] = {
2061 /* SS2 */
2062 RCAR_GP_PIN(3, 11),
2063};
2064static const unsigned int msiof1_ss2_g_mux[] = {
2065 MSIOF1_SS2_G_MARK,
2066};
2067static const unsigned int msiof1_txd_g_pins[] = {
2068 /* TXD */
2069 RCAR_GP_PIN(3, 9),
2070};
2071static const unsigned int msiof1_txd_g_mux[] = {
2072 MSIOF1_TXD_G_MARK,
2073};
2074static const unsigned int msiof1_rxd_g_pins[] = {
2075 /* RXD */
2076 RCAR_GP_PIN(3, 8),
2077};
2078static const unsigned int msiof1_rxd_g_mux[] = {
2079 MSIOF1_RXD_G_MARK,
2080};
2081/* - MSIOF2 ----------------------------------------------------------------- */
2082static const unsigned int msiof2_clk_a_pins[] = {
2083 /* SCK */
2084 RCAR_GP_PIN(1, 9),
2085};
2086static const unsigned int msiof2_clk_a_mux[] = {
2087 MSIOF2_SCK_A_MARK,
2088};
2089static const unsigned int msiof2_sync_a_pins[] = {
2090 /* SYNC */
2091 RCAR_GP_PIN(1, 8),
2092};
2093static const unsigned int msiof2_sync_a_mux[] = {
2094 MSIOF2_SYNC_A_MARK,
2095};
2096static const unsigned int msiof2_ss1_a_pins[] = {
2097 /* SS1 */
2098 RCAR_GP_PIN(1, 6),
2099};
2100static const unsigned int msiof2_ss1_a_mux[] = {
2101 MSIOF2_SS1_A_MARK,
2102};
2103static const unsigned int msiof2_ss2_a_pins[] = {
2104 /* SS2 */
2105 RCAR_GP_PIN(1, 7),
2106};
2107static const unsigned int msiof2_ss2_a_mux[] = {
2108 MSIOF2_SS2_A_MARK,
2109};
2110static const unsigned int msiof2_txd_a_pins[] = {
2111 /* TXD */
2112 RCAR_GP_PIN(1, 11),
2113};
2114static const unsigned int msiof2_txd_a_mux[] = {
2115 MSIOF2_TXD_A_MARK,
2116};
2117static const unsigned int msiof2_rxd_a_pins[] = {
2118 /* RXD */
2119 RCAR_GP_PIN(1, 10),
2120};
2121static const unsigned int msiof2_rxd_a_mux[] = {
2122 MSIOF2_RXD_A_MARK,
2123};
2124static const unsigned int msiof2_clk_b_pins[] = {
2125 /* SCK */
2126 RCAR_GP_PIN(0, 4),
2127};
2128static const unsigned int msiof2_clk_b_mux[] = {
2129 MSIOF2_SCK_B_MARK,
2130};
2131static const unsigned int msiof2_sync_b_pins[] = {
2132 /* SYNC */
2133 RCAR_GP_PIN(0, 5),
2134};
2135static const unsigned int msiof2_sync_b_mux[] = {
2136 MSIOF2_SYNC_B_MARK,
2137};
2138static const unsigned int msiof2_ss1_b_pins[] = {
2139 /* SS1 */
2140 RCAR_GP_PIN(0, 0),
2141};
2142static const unsigned int msiof2_ss1_b_mux[] = {
2143 MSIOF2_SS1_B_MARK,
2144};
2145static const unsigned int msiof2_ss2_b_pins[] = {
2146 /* SS2 */
2147 RCAR_GP_PIN(0, 1),
2148};
2149static const unsigned int msiof2_ss2_b_mux[] = {
2150 MSIOF2_SS2_B_MARK,
2151};
2152static const unsigned int msiof2_txd_b_pins[] = {
2153 /* TXD */
2154 RCAR_GP_PIN(0, 7),
2155};
2156static const unsigned int msiof2_txd_b_mux[] = {
2157 MSIOF2_TXD_B_MARK,
2158};
2159static const unsigned int msiof2_rxd_b_pins[] = {
2160 /* RXD */
2161 RCAR_GP_PIN(0, 6),
2162};
2163static const unsigned int msiof2_rxd_b_mux[] = {
2164 MSIOF2_RXD_B_MARK,
2165};
2166static const unsigned int msiof2_clk_c_pins[] = {
2167 /* SCK */
2168 RCAR_GP_PIN(2, 12),
2169};
2170static const unsigned int msiof2_clk_c_mux[] = {
2171 MSIOF2_SCK_C_MARK,
2172};
2173static const unsigned int msiof2_sync_c_pins[] = {
2174 /* SYNC */
2175 RCAR_GP_PIN(2, 11),
2176};
2177static const unsigned int msiof2_sync_c_mux[] = {
2178 MSIOF2_SYNC_C_MARK,
2179};
2180static const unsigned int msiof2_ss1_c_pins[] = {
2181 /* SS1 */
2182 RCAR_GP_PIN(2, 10),
2183};
2184static const unsigned int msiof2_ss1_c_mux[] = {
2185 MSIOF2_SS1_C_MARK,
2186};
2187static const unsigned int msiof2_ss2_c_pins[] = {
2188 /* SS2 */
2189 RCAR_GP_PIN(2, 9),
2190};
2191static const unsigned int msiof2_ss2_c_mux[] = {
2192 MSIOF2_SS2_C_MARK,
2193};
2194static const unsigned int msiof2_txd_c_pins[] = {
2195 /* TXD */
2196 RCAR_GP_PIN(2, 14),
2197};
2198static const unsigned int msiof2_txd_c_mux[] = {
2199 MSIOF2_TXD_C_MARK,
2200};
2201static const unsigned int msiof2_rxd_c_pins[] = {
2202 /* RXD */
2203 RCAR_GP_PIN(2, 13),
2204};
2205static const unsigned int msiof2_rxd_c_mux[] = {
2206 MSIOF2_RXD_C_MARK,
2207};
2208static const unsigned int msiof2_clk_d_pins[] = {
2209 /* SCK */
2210 RCAR_GP_PIN(0, 8),
2211};
2212static const unsigned int msiof2_clk_d_mux[] = {
2213 MSIOF2_SCK_D_MARK,
2214};
2215static const unsigned int msiof2_sync_d_pins[] = {
2216 /* SYNC */
2217 RCAR_GP_PIN(0, 9),
2218};
2219static const unsigned int msiof2_sync_d_mux[] = {
2220 MSIOF2_SYNC_D_MARK,
2221};
2222static const unsigned int msiof2_ss1_d_pins[] = {
2223 /* SS1 */
2224 RCAR_GP_PIN(0, 12),
2225};
2226static const unsigned int msiof2_ss1_d_mux[] = {
2227 MSIOF2_SS1_D_MARK,
2228};
2229static const unsigned int msiof2_ss2_d_pins[] = {
2230 /* SS2 */
2231 RCAR_GP_PIN(0, 13),
2232};
2233static const unsigned int msiof2_ss2_d_mux[] = {
2234 MSIOF2_SS2_D_MARK,
2235};
2236static const unsigned int msiof2_txd_d_pins[] = {
2237 /* TXD */
2238 RCAR_GP_PIN(0, 11),
2239};
2240static const unsigned int msiof2_txd_d_mux[] = {
2241 MSIOF2_TXD_D_MARK,
2242};
2243static const unsigned int msiof2_rxd_d_pins[] = {
2244 /* RXD */
2245 RCAR_GP_PIN(0, 10),
2246};
2247static const unsigned int msiof2_rxd_d_mux[] = {
2248 MSIOF2_RXD_D_MARK,
2249};
2250/* - MSIOF3 ----------------------------------------------------------------- */
2251static const unsigned int msiof3_clk_a_pins[] = {
2252 /* SCK */
2253 RCAR_GP_PIN(0, 0),
2254};
2255static const unsigned int msiof3_clk_a_mux[] = {
2256 MSIOF3_SCK_A_MARK,
2257};
2258static const unsigned int msiof3_sync_a_pins[] = {
2259 /* SYNC */
2260 RCAR_GP_PIN(0, 1),
2261};
2262static const unsigned int msiof3_sync_a_mux[] = {
2263 MSIOF3_SYNC_A_MARK,
2264};
2265static const unsigned int msiof3_ss1_a_pins[] = {
2266 /* SS1 */
2267 RCAR_GP_PIN(0, 14),
2268};
2269static const unsigned int msiof3_ss1_a_mux[] = {
2270 MSIOF3_SS1_A_MARK,
2271};
2272static const unsigned int msiof3_ss2_a_pins[] = {
2273 /* SS2 */
2274 RCAR_GP_PIN(0, 15),
2275};
2276static const unsigned int msiof3_ss2_a_mux[] = {
2277 MSIOF3_SS2_A_MARK,
2278};
2279static const unsigned int msiof3_txd_a_pins[] = {
2280 /* TXD */
2281 RCAR_GP_PIN(0, 3),
2282};
2283static const unsigned int msiof3_txd_a_mux[] = {
2284 MSIOF3_TXD_A_MARK,
2285};
2286static const unsigned int msiof3_rxd_a_pins[] = {
2287 /* RXD */
2288 RCAR_GP_PIN(0, 2),
2289};
2290static const unsigned int msiof3_rxd_a_mux[] = {
2291 MSIOF3_RXD_A_MARK,
2292};
2293static const unsigned int msiof3_clk_b_pins[] = {
2294 /* SCK */
2295 RCAR_GP_PIN(1, 2),
2296};
2297static const unsigned int msiof3_clk_b_mux[] = {
2298 MSIOF3_SCK_B_MARK,
2299};
2300static const unsigned int msiof3_sync_b_pins[] = {
2301 /* SYNC */
2302 RCAR_GP_PIN(1, 0),
2303};
2304static const unsigned int msiof3_sync_b_mux[] = {
2305 MSIOF3_SYNC_B_MARK,
2306};
2307static const unsigned int msiof3_ss1_b_pins[] = {
2308 /* SS1 */
2309 RCAR_GP_PIN(1, 4),
2310};
2311static const unsigned int msiof3_ss1_b_mux[] = {
2312 MSIOF3_SS1_B_MARK,
2313};
2314static const unsigned int msiof3_ss2_b_pins[] = {
2315 /* SS2 */
2316 RCAR_GP_PIN(1, 5),
2317};
2318static const unsigned int msiof3_ss2_b_mux[] = {
2319 MSIOF3_SS2_B_MARK,
2320};
2321static const unsigned int msiof3_txd_b_pins[] = {
2322 /* TXD */
2323 RCAR_GP_PIN(1, 1),
2324};
2325static const unsigned int msiof3_txd_b_mux[] = {
2326 MSIOF3_TXD_B_MARK,
2327};
2328static const unsigned int msiof3_rxd_b_pins[] = {
2329 /* RXD */
2330 RCAR_GP_PIN(1, 3),
2331};
2332static const unsigned int msiof3_rxd_b_mux[] = {
2333 MSIOF3_RXD_B_MARK,
2334};
2335static const unsigned int msiof3_clk_c_pins[] = {
2336 /* SCK */
2337 RCAR_GP_PIN(1, 12),
2338};
2339static const unsigned int msiof3_clk_c_mux[] = {
2340 MSIOF3_SCK_C_MARK,
2341};
2342static const unsigned int msiof3_sync_c_pins[] = {
2343 /* SYNC */
2344 RCAR_GP_PIN(1, 13),
2345};
2346static const unsigned int msiof3_sync_c_mux[] = {
2347 MSIOF3_SYNC_C_MARK,
2348};
2349static const unsigned int msiof3_txd_c_pins[] = {
2350 /* TXD */
2351 RCAR_GP_PIN(1, 15),
2352};
2353static const unsigned int msiof3_txd_c_mux[] = {
2354 MSIOF3_TXD_C_MARK,
2355};
2356static const unsigned int msiof3_rxd_c_pins[] = {
2357 /* RXD */
2358 RCAR_GP_PIN(1, 14),
2359};
2360static const unsigned int msiof3_rxd_c_mux[] = {
2361 MSIOF3_RXD_C_MARK,
2362};
2363static const unsigned int msiof3_clk_d_pins[] = {
2364 /* SCK */
2365 RCAR_GP_PIN(1, 22),
2366};
2367static const unsigned int msiof3_clk_d_mux[] = {
2368 MSIOF3_SCK_D_MARK,
2369};
2370static const unsigned int msiof3_sync_d_pins[] = {
2371 /* SYNC */
2372 RCAR_GP_PIN(1, 23),
2373};
2374static const unsigned int msiof3_sync_d_mux[] = {
2375 MSIOF3_SYNC_D_MARK,
2376};
2377static const unsigned int msiof3_ss1_d_pins[] = {
2378 /* SS1 */
2379 RCAR_GP_PIN(1, 26),
2380};
2381static const unsigned int msiof3_ss1_d_mux[] = {
2382 MSIOF3_SS1_D_MARK,
2383};
2384static const unsigned int msiof3_txd_d_pins[] = {
2385 /* TXD */
2386 RCAR_GP_PIN(1, 25),
2387};
2388static const unsigned int msiof3_txd_d_mux[] = {
2389 MSIOF3_TXD_D_MARK,
2390};
2391static const unsigned int msiof3_rxd_d_pins[] = {
2392 /* RXD */
2393 RCAR_GP_PIN(1, 24),
2394};
2395static const unsigned int msiof3_rxd_d_mux[] = {
2396 MSIOF3_RXD_D_MARK,
2397};
2398static const unsigned int msiof3_clk_e_pins[] = {
2399 /* SCK */
2400 RCAR_GP_PIN(2, 3),
2401};
2402static const unsigned int msiof3_clk_e_mux[] = {
2403 MSIOF3_SCK_E_MARK,
2404};
2405static const unsigned int msiof3_sync_e_pins[] = {
2406 /* SYNC */
2407 RCAR_GP_PIN(2, 2),
2408};
2409static const unsigned int msiof3_sync_e_mux[] = {
2410 MSIOF3_SYNC_E_MARK,
2411};
2412static const unsigned int msiof3_ss1_e_pins[] = {
2413 /* SS1 */
2414 RCAR_GP_PIN(2, 1),
2415};
2416static const unsigned int msiof3_ss1_e_mux[] = {
2417 MSIOF3_SS1_E_MARK,
2418};
2419static const unsigned int msiof3_ss2_e_pins[] = {
2420 /* SS1 */
2421 RCAR_GP_PIN(2, 0),
2422};
2423static const unsigned int msiof3_ss2_e_mux[] = {
2424 MSIOF3_SS2_E_MARK,
2425};
2426static const unsigned int msiof3_txd_e_pins[] = {
2427 /* TXD */
2428 RCAR_GP_PIN(2, 5),
2429};
2430static const unsigned int msiof3_txd_e_mux[] = {
2431 MSIOF3_TXD_E_MARK,
2432};
2433static const unsigned int msiof3_rxd_e_pins[] = {
2434 /* RXD */
2435 RCAR_GP_PIN(2, 4),
2436};
2437static const unsigned int msiof3_rxd_e_mux[] = {
2438 MSIOF3_RXD_E_MARK,
2439};
2440
1747/* - PWM0 --------------------------------------------------------------------*/ 2441/* - PWM0 --------------------------------------------------------------------*/
1748static const unsigned int pwm0_pins[] = { 2442static const unsigned int pwm0_pins[] = {
1749 /* PWM */ 2443 /* PWM */
@@ -2056,6 +2750,39 @@ static const unsigned int scif_clk_b_mux[] = {
2056 SCIF_CLK_B_MARK, 2750 SCIF_CLK_B_MARK,
2057}; 2751};
2058 2752
2753/* - USB0 ------------------------------------------------------------------- */
2754static const unsigned int usb0_pins[] = {
2755 /* PWEN, OVC */
2756 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2757};
2758static const unsigned int usb0_mux[] = {
2759 USB0_PWEN_MARK, USB0_OVC_MARK,
2760};
2761/* - USB1 ------------------------------------------------------------------- */
2762static const unsigned int usb1_pins[] = {
2763 /* PWEN, OVC */
2764 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2765};
2766static const unsigned int usb1_mux[] = {
2767 USB1_PWEN_MARK, USB1_OVC_MARK,
2768};
2769/* - USB2 ------------------------------------------------------------------- */
2770static const unsigned int usb2_pins[] = {
2771 /* PWEN, OVC */
2772 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2773};
2774static const unsigned int usb2_mux[] = {
2775 USB2_PWEN_MARK, USB2_OVC_MARK,
2776};
2777/* - USB2_CH3 --------------------------------------------------------------- */
2778static const unsigned int usb2_ch3_pins[] = {
2779 /* PWEN, OVC */
2780 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
2781};
2782static const unsigned int usb2_ch3_mux[] = {
2783 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
2784};
2785
2059static const struct sh_pfc_pin_group pinmux_groups[] = { 2786static const struct sh_pfc_pin_group pinmux_groups[] = {
2060 SH_PFC_PIN_GROUP(avb_link), 2787 SH_PFC_PIN_GROUP(avb_link),
2061 SH_PFC_PIN_GROUP(avb_magic), 2788 SH_PFC_PIN_GROUP(avb_magic),
@@ -2075,6 +2802,105 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2075 SH_PFC_PIN_GROUP(du_oddf), 2802 SH_PFC_PIN_GROUP(du_oddf),
2076 SH_PFC_PIN_GROUP(du_cde), 2803 SH_PFC_PIN_GROUP(du_cde),
2077 SH_PFC_PIN_GROUP(du_disp), 2804 SH_PFC_PIN_GROUP(du_disp),
2805 SH_PFC_PIN_GROUP(msiof0_clk),
2806 SH_PFC_PIN_GROUP(msiof0_sync),
2807 SH_PFC_PIN_GROUP(msiof0_ss1),
2808 SH_PFC_PIN_GROUP(msiof0_ss2),
2809 SH_PFC_PIN_GROUP(msiof0_txd),
2810 SH_PFC_PIN_GROUP(msiof0_rxd),
2811 SH_PFC_PIN_GROUP(msiof1_clk_a),
2812 SH_PFC_PIN_GROUP(msiof1_sync_a),
2813 SH_PFC_PIN_GROUP(msiof1_ss1_a),
2814 SH_PFC_PIN_GROUP(msiof1_ss2_a),
2815 SH_PFC_PIN_GROUP(msiof1_txd_a),
2816 SH_PFC_PIN_GROUP(msiof1_rxd_a),
2817 SH_PFC_PIN_GROUP(msiof1_clk_b),
2818 SH_PFC_PIN_GROUP(msiof1_sync_b),
2819 SH_PFC_PIN_GROUP(msiof1_ss1_b),
2820 SH_PFC_PIN_GROUP(msiof1_ss2_b),
2821 SH_PFC_PIN_GROUP(msiof1_txd_b),
2822 SH_PFC_PIN_GROUP(msiof1_rxd_b),
2823 SH_PFC_PIN_GROUP(msiof1_clk_c),
2824 SH_PFC_PIN_GROUP(msiof1_sync_c),
2825 SH_PFC_PIN_GROUP(msiof1_ss1_c),
2826 SH_PFC_PIN_GROUP(msiof1_ss2_c),
2827 SH_PFC_PIN_GROUP(msiof1_txd_c),
2828 SH_PFC_PIN_GROUP(msiof1_rxd_c),
2829 SH_PFC_PIN_GROUP(msiof1_clk_d),
2830 SH_PFC_PIN_GROUP(msiof1_sync_d),
2831 SH_PFC_PIN_GROUP(msiof1_ss1_d),
2832 SH_PFC_PIN_GROUP(msiof1_ss2_d),
2833 SH_PFC_PIN_GROUP(msiof1_txd_d),
2834 SH_PFC_PIN_GROUP(msiof1_rxd_d),
2835 SH_PFC_PIN_GROUP(msiof1_clk_e),
2836 SH_PFC_PIN_GROUP(msiof1_sync_e),
2837 SH_PFC_PIN_GROUP(msiof1_ss1_e),
2838 SH_PFC_PIN_GROUP(msiof1_ss2_e),
2839 SH_PFC_PIN_GROUP(msiof1_txd_e),
2840 SH_PFC_PIN_GROUP(msiof1_rxd_e),
2841 SH_PFC_PIN_GROUP(msiof1_clk_f),
2842 SH_PFC_PIN_GROUP(msiof1_sync_f),
2843 SH_PFC_PIN_GROUP(msiof1_ss1_f),
2844 SH_PFC_PIN_GROUP(msiof1_ss2_f),
2845 SH_PFC_PIN_GROUP(msiof1_txd_f),
2846 SH_PFC_PIN_GROUP(msiof1_rxd_f),
2847 SH_PFC_PIN_GROUP(msiof1_clk_g),
2848 SH_PFC_PIN_GROUP(msiof1_sync_g),
2849 SH_PFC_PIN_GROUP(msiof1_ss1_g),
2850 SH_PFC_PIN_GROUP(msiof1_ss2_g),
2851 SH_PFC_PIN_GROUP(msiof1_txd_g),
2852 SH_PFC_PIN_GROUP(msiof1_rxd_g),
2853 SH_PFC_PIN_GROUP(msiof2_clk_a),
2854 SH_PFC_PIN_GROUP(msiof2_sync_a),
2855 SH_PFC_PIN_GROUP(msiof2_ss1_a),
2856 SH_PFC_PIN_GROUP(msiof2_ss2_a),
2857 SH_PFC_PIN_GROUP(msiof2_txd_a),
2858 SH_PFC_PIN_GROUP(msiof2_rxd_a),
2859 SH_PFC_PIN_GROUP(msiof2_clk_b),
2860 SH_PFC_PIN_GROUP(msiof2_sync_b),
2861 SH_PFC_PIN_GROUP(msiof2_ss1_b),
2862 SH_PFC_PIN_GROUP(msiof2_ss2_b),
2863 SH_PFC_PIN_GROUP(msiof2_txd_b),
2864 SH_PFC_PIN_GROUP(msiof2_rxd_b),
2865 SH_PFC_PIN_GROUP(msiof2_clk_c),
2866 SH_PFC_PIN_GROUP(msiof2_sync_c),
2867 SH_PFC_PIN_GROUP(msiof2_ss1_c),
2868 SH_PFC_PIN_GROUP(msiof2_ss2_c),
2869 SH_PFC_PIN_GROUP(msiof2_txd_c),
2870 SH_PFC_PIN_GROUP(msiof2_rxd_c),
2871 SH_PFC_PIN_GROUP(msiof2_clk_d),
2872 SH_PFC_PIN_GROUP(msiof2_sync_d),
2873 SH_PFC_PIN_GROUP(msiof2_ss1_d),
2874 SH_PFC_PIN_GROUP(msiof2_ss2_d),
2875 SH_PFC_PIN_GROUP(msiof2_txd_d),
2876 SH_PFC_PIN_GROUP(msiof2_rxd_d),
2877 SH_PFC_PIN_GROUP(msiof3_clk_a),
2878 SH_PFC_PIN_GROUP(msiof3_sync_a),
2879 SH_PFC_PIN_GROUP(msiof3_ss1_a),
2880 SH_PFC_PIN_GROUP(msiof3_ss2_a),
2881 SH_PFC_PIN_GROUP(msiof3_txd_a),
2882 SH_PFC_PIN_GROUP(msiof3_rxd_a),
2883 SH_PFC_PIN_GROUP(msiof3_clk_b),
2884 SH_PFC_PIN_GROUP(msiof3_sync_b),
2885 SH_PFC_PIN_GROUP(msiof3_ss1_b),
2886 SH_PFC_PIN_GROUP(msiof3_ss2_b),
2887 SH_PFC_PIN_GROUP(msiof3_txd_b),
2888 SH_PFC_PIN_GROUP(msiof3_rxd_b),
2889 SH_PFC_PIN_GROUP(msiof3_clk_c),
2890 SH_PFC_PIN_GROUP(msiof3_sync_c),
2891 SH_PFC_PIN_GROUP(msiof3_txd_c),
2892 SH_PFC_PIN_GROUP(msiof3_rxd_c),
2893 SH_PFC_PIN_GROUP(msiof3_clk_d),
2894 SH_PFC_PIN_GROUP(msiof3_sync_d),
2895 SH_PFC_PIN_GROUP(msiof3_ss1_d),
2896 SH_PFC_PIN_GROUP(msiof3_txd_d),
2897 SH_PFC_PIN_GROUP(msiof3_rxd_d),
2898 SH_PFC_PIN_GROUP(msiof3_clk_e),
2899 SH_PFC_PIN_GROUP(msiof3_sync_e),
2900 SH_PFC_PIN_GROUP(msiof3_ss1_e),
2901 SH_PFC_PIN_GROUP(msiof3_ss2_e),
2902 SH_PFC_PIN_GROUP(msiof3_txd_e),
2903 SH_PFC_PIN_GROUP(msiof3_rxd_e),
2078 SH_PFC_PIN_GROUP(pwm0), 2904 SH_PFC_PIN_GROUP(pwm0),
2079 SH_PFC_PIN_GROUP(pwm1_a), 2905 SH_PFC_PIN_GROUP(pwm1_a),
2080 SH_PFC_PIN_GROUP(pwm1_b), 2906 SH_PFC_PIN_GROUP(pwm1_b),
@@ -2117,6 +2943,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2117 SH_PFC_PIN_GROUP(scif5_clk_b), 2943 SH_PFC_PIN_GROUP(scif5_clk_b),
2118 SH_PFC_PIN_GROUP(scif_clk_a), 2944 SH_PFC_PIN_GROUP(scif_clk_a),
2119 SH_PFC_PIN_GROUP(scif_clk_b), 2945 SH_PFC_PIN_GROUP(scif_clk_b),
2946 SH_PFC_PIN_GROUP(usb0),
2947 SH_PFC_PIN_GROUP(usb1),
2948 SH_PFC_PIN_GROUP(usb2),
2949 SH_PFC_PIN_GROUP(usb2_ch3),
2120}; 2950};
2121 2951
2122static const char * const avb_groups[] = { 2952static const char * const avb_groups[] = {
@@ -2143,6 +2973,117 @@ static const char * const du_groups[] = {
2143 "du_disp", 2973 "du_disp",
2144}; 2974};
2145 2975
2976static const char * const msiof0_groups[] = {
2977 "msiof0_clk",
2978 "msiof0_sync",
2979 "msiof0_ss1",
2980 "msiof0_ss2",
2981 "msiof0_txd",
2982 "msiof0_rxd",
2983};
2984
2985static const char * const msiof1_groups[] = {
2986 "msiof1_clk_a",
2987 "msiof1_sync_a",
2988 "msiof1_ss1_a",
2989 "msiof1_ss2_a",
2990 "msiof1_txd_a",
2991 "msiof1_rxd_a",
2992 "msiof1_clk_b",
2993 "msiof1_sync_b",
2994 "msiof1_ss1_b",
2995 "msiof1_ss2_b",
2996 "msiof1_txd_b",
2997 "msiof1_rxd_b",
2998 "msiof1_clk_c",
2999 "msiof1_sync_c",
3000 "msiof1_ss1_c",
3001 "msiof1_ss2_c",
3002 "msiof1_txd_c",
3003 "msiof1_rxd_c",
3004 "msiof1_clk_d",
3005 "msiof1_sync_d",
3006 "msiof1_ss1_d",
3007 "msiof1_ss2_d",
3008 "msiof1_txd_d",
3009 "msiof1_rxd_d",
3010 "msiof1_clk_e",
3011 "msiof1_sync_e",
3012 "msiof1_ss1_e",
3013 "msiof1_ss2_e",
3014 "msiof1_txd_e",
3015 "msiof1_rxd_e",
3016 "msiof1_clk_f",
3017 "msiof1_sync_f",
3018 "msiof1_ss1_f",
3019 "msiof1_ss2_f",
3020 "msiof1_txd_f",
3021 "msiof1_rxd_f",
3022 "msiof1_clk_g",
3023 "msiof1_sync_g",
3024 "msiof1_ss1_g",
3025 "msiof1_ss2_g",
3026 "msiof1_txd_g",
3027 "msiof1_rxd_g",
3028};
3029
3030static const char * const msiof2_groups[] = {
3031 "msiof2_clk_a",
3032 "msiof2_sync_a",
3033 "msiof2_ss1_a",
3034 "msiof2_ss2_a",
3035 "msiof2_txd_a",
3036 "msiof2_rxd_a",
3037 "msiof2_clk_b",
3038 "msiof2_sync_b",
3039 "msiof2_ss1_b",
3040 "msiof2_ss2_b",
3041 "msiof2_txd_b",
3042 "msiof2_rxd_b",
3043 "msiof2_clk_c",
3044 "msiof2_sync_c",
3045 "msiof2_ss1_c",
3046 "msiof2_ss2_c",
3047 "msiof2_txd_c",
3048 "msiof2_rxd_c",
3049 "msiof2_clk_d",
3050 "msiof2_sync_d",
3051 "msiof2_ss1_d",
3052 "msiof2_ss2_d",
3053 "msiof2_txd_d",
3054 "msiof2_rxd_d",
3055};
3056
3057static const char * const msiof3_groups[] = {
3058 "msiof3_clk_a",
3059 "msiof3_sync_a",
3060 "msiof3_ss1_a",
3061 "msiof3_ss2_a",
3062 "msiof3_txd_a",
3063 "msiof3_rxd_a",
3064 "msiof3_clk_b",
3065 "msiof3_sync_b",
3066 "msiof3_ss1_b",
3067 "msiof3_ss2_b",
3068 "msiof3_txd_b",
3069 "msiof3_rxd_b",
3070 "msiof3_clk_c",
3071 "msiof3_sync_c",
3072 "msiof3_txd_c",
3073 "msiof3_rxd_c",
3074 "msiof3_clk_d",
3075 "msiof3_sync_d",
3076 "msiof3_ss1_d",
3077 "msiof3_txd_d",
3078 "msiof3_rxd_d",
3079 "msiof3_clk_e",
3080 "msiof3_sync_e",
3081 "msiof3_ss1_e",
3082 "msiof3_ss2_e",
3083 "msiof3_txd_e",
3084 "msiof3_rxd_e",
3085};
3086
2146static const char * const pwm0_groups[] = { 3087static const char * const pwm0_groups[] = {
2147 "pwm0", 3088 "pwm0",
2148}; 3089};
@@ -2227,9 +3168,29 @@ static const char * const scif_clk_groups[] = {
2227 "scif_clk_b", 3168 "scif_clk_b",
2228}; 3169};
2229 3170
3171static const char * const usb0_groups[] = {
3172 "usb0",
3173};
3174
3175static const char * const usb1_groups[] = {
3176 "usb1",
3177};
3178
3179static const char * const usb2_groups[] = {
3180 "usb2",
3181};
3182
3183static const char * const usb2_ch3_groups[] = {
3184 "usb2_ch3",
3185};
3186
2230static const struct sh_pfc_function pinmux_functions[] = { 3187static const struct sh_pfc_function pinmux_functions[] = {
2231 SH_PFC_FUNCTION(avb), 3188 SH_PFC_FUNCTION(avb),
2232 SH_PFC_FUNCTION(du), 3189 SH_PFC_FUNCTION(du),
3190 SH_PFC_FUNCTION(msiof0),
3191 SH_PFC_FUNCTION(msiof1),
3192 SH_PFC_FUNCTION(msiof2),
3193 SH_PFC_FUNCTION(msiof3),
2233 SH_PFC_FUNCTION(pwm0), 3194 SH_PFC_FUNCTION(pwm0),
2234 SH_PFC_FUNCTION(pwm1), 3195 SH_PFC_FUNCTION(pwm1),
2235 SH_PFC_FUNCTION(pwm2), 3196 SH_PFC_FUNCTION(pwm2),
@@ -2244,6 +3205,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
2244 SH_PFC_FUNCTION(scif4), 3205 SH_PFC_FUNCTION(scif4),
2245 SH_PFC_FUNCTION(scif5), 3206 SH_PFC_FUNCTION(scif5),
2246 SH_PFC_FUNCTION(scif_clk), 3207 SH_PFC_FUNCTION(scif_clk),
3208 SH_PFC_FUNCTION(usb0),
3209 SH_PFC_FUNCTION(usb1),
3210 SH_PFC_FUNCTION(usb2),
3211 SH_PFC_FUNCTION(usb2_ch3),
2247}; 3212};
2248 3213
2249static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3214static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -2601,7 +3566,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2601 IP7_27_24 3566 IP7_27_24
2602 IP7_23_20 3567 IP7_23_20
2603 IP7_19_16 3568 IP7_19_16
2604 IP7_15_12 3569 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2605 IP7_11_8 3570 IP7_11_8
2606 IP7_7_4 3571 IP7_7_4
2607 IP7_3_0 } 3572 IP7_3_0 }
@@ -2782,7 +3747,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2782 MOD_SEL2_28_27 3747 MOD_SEL2_28_27
2783 MOD_SEL2_26 3748 MOD_SEL2_26
2784 MOD_SEL2_25_24_23 3749 MOD_SEL2_25_24_23
2785 MOD_SEL2_22 3750 /* RESERVED 22 */
3751 0, 0,
2786 MOD_SEL2_21 3752 MOD_SEL2_21
2787 MOD_SEL2_20 3753 MOD_SEL2_20
2788 MOD_SEL2_19 3754 MOD_SEL2_19
@@ -3049,8 +4015,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3049 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ 4015 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
3050 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ 4016 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
3051 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ 4017 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
3052 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB3_PWEN */ 4018 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
3053 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB3_OVC */ 4019 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
3054 } }, 4020 } },
3055 { }, 4021 { },
3056}; 4022};
@@ -3177,7 +4143,7 @@ static const struct sh_pfc_bias_info bias_info[] = {
3177 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ 4143 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
3178 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ 4144 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
3179 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ 4145 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
3180 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ 4146 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
3181 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ 4147 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
3182 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ 4148 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
3183 4149
@@ -3280,8 +4246,8 @@ static const struct sh_pfc_bias_info bias_info[] = {
3280 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ 4246 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
3281 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ 4247 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
3282 4248
3283 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB3_OVC */ 4249 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */
3284 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB3_PWEN */ 4250 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */
3285 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ 4251 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
3286 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ 4252 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
3287 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ 4253 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 98bf5d0e078e..200e1f4f6db9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -67,7 +67,7 @@
67#define GPSR1_24 F_(RD_WR_N, IP4_31_28) 67#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68#define GPSR1_23 F_(RD_N, IP4_27_24) 68#define GPSR1_23 F_(RD_N, IP4_27_24)
69#define GPSR1_22 F_(BS_N, IP4_23_20) 69#define GPSR1_22 F_(BS_N, IP4_23_20)
70#define GPSR1_21 F_(CS1_N_A26, IP4_19_16) 70#define GPSR1_21 F_(CS1_N, IP4_19_16)
71#define GPSR1_20 F_(CS0_N, IP4_15_12) 71#define GPSR1_20 F_(CS0_N, IP4_15_12)
72#define GPSR1_19 F_(A19, IP4_11_8) 72#define GPSR1_19 F_(A19, IP4_11_8)
73#define GPSR1_18 F_(A18, IP4_7_4) 73#define GPSR1_18 F_(A18, IP4_7_4)
@@ -221,8 +221,8 @@
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -253,7 +253,7 @@
253#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 253#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 254#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 255#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 256#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 257#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -278,7 +278,6 @@
278#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 278#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 279#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 280#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 281#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 282#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 283#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -291,24 +290,24 @@
291#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 290#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 291#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 292#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 293#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 294#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 295#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 296#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 297#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 298#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 299#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 300#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 301#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 302#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 303#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 304#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 305#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 306#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 307#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 308#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 309#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 310#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 311#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 312
314/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ 313/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@@ -319,14 +318,14 @@
319#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 318#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 319#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 320#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 321#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 322#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 323#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 324#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 325#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 326#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 327#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 328#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 329#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 330#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 331#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -366,9 +365,9 @@
366#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0) 365#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
367#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0) 366#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0) 367#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
369#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 368#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) 369#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
371#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0) 370#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
372 371
373#define PINMUX_GPSR \ 372#define PINMUX_GPSR \
374\ 373\
@@ -419,7 +418,7 @@ FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_3
419FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ 418FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
420FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ 419FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
421FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ 420FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
422FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ 421FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
423FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ 422FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
424FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ 423FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
425FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ 424FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
@@ -463,7 +462,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
463#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) 462#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
464#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) 463#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
465#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 464#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
466#define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1)
467#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0) 465#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
468#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) 466#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
469#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 467#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
@@ -472,7 +470,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
472#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) 470#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
473#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) 471#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
474#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) 472#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
475#define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1)
476 473
477/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 474/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
478#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) 475#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -488,7 +485,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
488#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) 485#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
489#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 486#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
490#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) 487#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
491#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1) 488#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
492#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) 489#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
493#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1) 490#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
494#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 491#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
@@ -529,7 +526,7 @@ MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
529MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \ 526MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
530 MOD_SEL2_17 \ 527 MOD_SEL2_17 \
531MOD_SEL0_16 MOD_SEL1_16 \ 528MOD_SEL0_16 MOD_SEL1_16 \
532MOD_SEL0_15 MOD_SEL1_15_14 \ 529 MOD_SEL1_15_14 \
533MOD_SEL0_14_13 \ 530MOD_SEL0_14_13 \
534 MOD_SEL1_13 \ 531 MOD_SEL1_13 \
535MOD_SEL0_12 MOD_SEL1_12 \ 532MOD_SEL0_12 MOD_SEL1_12 \
@@ -541,7 +538,7 @@ MOD_SEL0_7_6 \
541MOD_SEL0_5 MOD_SEL1_5 \ 538MOD_SEL0_5 MOD_SEL1_5 \
542MOD_SEL0_4_3 MOD_SEL1_4 \ 539MOD_SEL0_4_3 MOD_SEL1_4 \
543 MOD_SEL1_3 \ 540 MOD_SEL1_3 \
544MOD_SEL0_2 MOD_SEL1_2 \ 541 MOD_SEL1_2 \
545 MOD_SEL1_1 \ 542 MOD_SEL1_1 \
546 MOD_SEL1_0 MOD_SEL2_0 543 MOD_SEL1_0 MOD_SEL2_0
547 544
@@ -645,7 +642,7 @@ static const u16 pinmux_data[] = {
645 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), 642 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
646 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), 643 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
647 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), 644 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
648 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4), 645 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
649 646
650 /* IPSR1 */ 647 /* IPSR1 */
651 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2), 648 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
@@ -837,7 +834,7 @@ static const u16 pinmux_data[] = {
837 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N), 834 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
838 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB), 835 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
839 836
840 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26), 837 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
841 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK), 838 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
842 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1), 839 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
843 840
@@ -990,8 +987,6 @@ static const u16 pinmux_data[] = {
990 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7), 987 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
991 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2), 988 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
992 989
993 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
994
995 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK), 990 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
996 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4), 991 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1), 992 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
@@ -1173,7 +1168,6 @@ static const u16 pinmux_data[] = {
1173 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), 1168 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1174 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), 1169 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1175 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), 1170 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1176 PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0),
1177 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1), 1171 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1178 1172
1179 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0), 1173 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
@@ -1205,7 +1199,7 @@ static const u16 pinmux_data[] = {
1205 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0), 1199 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1206 1200
1207 PINMUX_IPSR_GPSR(IP12_31_28, SCK2), 1201 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1), 1202 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1209 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1), 1203 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1210 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2), 1204 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1211 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2), 1205 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
@@ -1218,14 +1212,14 @@ static const u16 pinmux_data[] = {
1218 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0), 1212 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0), 1213 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2), 1214 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1), 1215 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1222 1216
1223 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0), 1217 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1224 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1), 1218 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1225 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0), 1219 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1226 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0), 1220 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1227 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2), 1221 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1228 PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1), 1222 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1229 1223
1230 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), 1224 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1231 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), 1225 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
@@ -1393,7 +1387,7 @@ static const u16 pinmux_data[] = {
1393 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0), 1387 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0), 1388 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0), 1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1396 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0), 1390 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1397 1391
1398 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8), 1392 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1399 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1), 1393 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
@@ -1410,14 +1404,14 @@ static const u16 pinmux_data[] = {
1410 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1), 1404 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1411 PINMUX_IPSR_GPSR(IP16_31_28, SCK1), 1405 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1412 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0), 1406 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1413 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A), 1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1414 1408
1415 /* IPSR17 */ 1409 /* IPSR17 */
1416 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), 1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1417 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), 1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1418 1412
1419 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), 1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1420 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0), 1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1421 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), 1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1422 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), 1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1423 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0), 1417 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
@@ -1461,10 +1455,10 @@ static const u16 pinmux_data[] = {
1461 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), 1455 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1462 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), 1456 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1463 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), 1457 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), 1458 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1465 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1466 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), 1460 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1467 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1), 1461 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1468 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0), 1462 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1469 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2), 1463 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1470 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2), 1464 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
@@ -1476,7 +1470,7 @@ static const u16 pinmux_data[] = {
1476 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3), 1470 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1477 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4), 1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1478 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1), 1472 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1479 PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1), 1473 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1480 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1), 1474 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1481 1475
1482 /* IPSR18 */ 1476 /* IPSR18 */
@@ -1487,7 +1481,6 @@ static const u16 pinmux_data[] = {
1487 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4), 1481 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1488 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1), 1482 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1489 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2), 1483 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0),
1491 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2), 1484 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1492 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3), 1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1493 1486
@@ -1498,7 +1491,6 @@ static const u16 pinmux_data[] = {
1498 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4), 1491 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1499 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1), 1492 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1500 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3), 1493 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1501 PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0),
1502 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), 1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1503 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), 1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1504 1496
@@ -3082,7 +3074,7 @@ static const unsigned int msiof3_ss2_e_pins[] = {
3082 RCAR_GP_PIN(2, 0), 3074 RCAR_GP_PIN(2, 0),
3083}; 3075};
3084static const unsigned int msiof3_ss2_e_mux[] = { 3076static const unsigned int msiof3_ss2_e_mux[] = {
3085 MSIOF3_SS1_E_MARK, 3077 MSIOF3_SS2_E_MARK,
3086}; 3078};
3087static const unsigned int msiof3_txd_e_pins[] = { 3079static const unsigned int msiof3_txd_e_pins[] = {
3088 /* TXD */ 3080 /* TXD */
@@ -3796,6 +3788,32 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
3796 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3788 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3797}; 3789};
3798 3790
3791/* - USB0 ------------------------------------------------------------------- */
3792static const unsigned int usb0_pins[] = {
3793 /* PWEN, OVC */
3794 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3795};
3796static const unsigned int usb0_mux[] = {
3797 USB0_PWEN_MARK, USB0_OVC_MARK,
3798};
3799/* - USB1 ------------------------------------------------------------------- */
3800static const unsigned int usb1_pins[] = {
3801 /* PWEN, OVC */
3802 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3803};
3804static const unsigned int usb1_mux[] = {
3805 USB1_PWEN_MARK, USB1_OVC_MARK,
3806};
3807
3808/* - USB30 ------------------------------------------------------------------ */
3809static const unsigned int usb30_pins[] = {
3810 /* PWEN, OVC */
3811 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3812};
3813static const unsigned int usb30_mux[] = {
3814 USB30_PWEN_MARK, USB30_OVC_MARK,
3815};
3816
3799static const struct sh_pfc_pin_group pinmux_groups[] = { 3817static const struct sh_pfc_pin_group pinmux_groups[] = {
3800 SH_PFC_PIN_GROUP(audio_clk_a_a), 3818 SH_PFC_PIN_GROUP(audio_clk_a_a),
3801 SH_PFC_PIN_GROUP(audio_clk_a_b), 3819 SH_PFC_PIN_GROUP(audio_clk_a_b),
@@ -4096,6 +4114,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
4096 SH_PFC_PIN_GROUP(ssi9_data_b), 4114 SH_PFC_PIN_GROUP(ssi9_data_b),
4097 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 4115 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4098 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 4116 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4117 SH_PFC_PIN_GROUP(usb0),
4118 SH_PFC_PIN_GROUP(usb1),
4119 SH_PFC_PIN_GROUP(usb30),
4099}; 4120};
4100 4121
4101static const char * const audio_clk_groups[] = { 4122static const char * const audio_clk_groups[] = {
@@ -4526,6 +4547,18 @@ static const char * const ssi_groups[] = {
4526 "ssi9_ctrl_b", 4547 "ssi9_ctrl_b",
4527}; 4548};
4528 4549
4550static const char * const usb0_groups[] = {
4551 "usb0",
4552};
4553
4554static const char * const usb1_groups[] = {
4555 "usb1",
4556};
4557
4558static const char * const usb30_groups[] = {
4559 "usb30",
4560};
4561
4529static const struct sh_pfc_function pinmux_functions[] = { 4562static const struct sh_pfc_function pinmux_functions[] = {
4530 SH_PFC_FUNCTION(audio_clk), 4563 SH_PFC_FUNCTION(audio_clk),
4531 SH_PFC_FUNCTION(avb), 4564 SH_PFC_FUNCTION(avb),
@@ -4570,6 +4603,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
4570 SH_PFC_FUNCTION(sdhi2), 4603 SH_PFC_FUNCTION(sdhi2),
4571 SH_PFC_FUNCTION(sdhi3), 4604 SH_PFC_FUNCTION(sdhi3),
4572 SH_PFC_FUNCTION(ssi), 4605 SH_PFC_FUNCTION(ssi),
4606 SH_PFC_FUNCTION(usb0),
4607 SH_PFC_FUNCTION(usb1),
4608 SH_PFC_FUNCTION(usb30),
4573}; 4609};
4574 4610
4575static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4611static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -4927,7 +4963,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4927 IP7_27_24 4963 IP7_27_24
4928 IP7_23_20 4964 IP7_23_20
4929 IP7_19_16 4965 IP7_19_16
4930 IP7_15_12 4966 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4931 IP7_11_8 4967 IP7_11_8
4932 IP7_7_4 4968 IP7_7_4
4933 IP7_3_0 } 4969 IP7_3_0 }
@@ -5060,7 +5096,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5060 MOD_SEL0_19 5096 MOD_SEL0_19
5061 MOD_SEL0_18_17 5097 MOD_SEL0_18_17
5062 MOD_SEL0_16 5098 MOD_SEL0_16
5063 MOD_SEL0_15 5099 0, 0, /* RESERVED 15 */
5064 MOD_SEL0_14_13 5100 MOD_SEL0_14_13
5065 MOD_SEL0_12 5101 MOD_SEL0_12
5066 MOD_SEL0_11 5102 MOD_SEL0_11
@@ -5502,7 +5538,7 @@ static const struct sh_pfc_bias_info bias_info[] = {
5502 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ 5538 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
5503 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ 5539 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
5504 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ 5540 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
5505 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ 5541 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
5506 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ 5542 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
5507 { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ 5543 { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */
5508 5544
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
new file mode 100644
index 000000000000..4f5ee1d7317d
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -0,0 +1,1812 @@
1/*
2 * R8A77995 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17#include <linux/kernel.h>
18
19#include "core.h"
20#include "sh_pfc.h"
21
22#define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_9(0, fn, sfx), \
24 PORT_GP_32(1, fn, sfx), \
25 PORT_GP_32(2, fn, sfx), \
26 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_32(4, fn, sfx), \
28 PORT_GP_21(5, fn, sfx), \
29 PORT_GP_14(6, fn, sfx)
30
31/*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36/* GPSR0 */
37#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
38#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
39#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
40#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
41#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
42#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
43#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
44#define GPSR0_1 FM(USB0_OVC)
45#define GPSR0_0 FM(USB0_PWEN)
46
47/* GPSR1 */
48#define GPSR1_31 F_(QPOLB, IP4_27_24)
49#define GPSR1_30 F_(QPOLA, IP4_23_20)
50#define GPSR1_29 F_(DU_CDE, IP4_19_16)
51#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
52#define GPSR1_27 F_(DU_DISP, IP4_11_8)
53#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
54#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
55#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
56#define GPSR1_23 F_(DU_DR7, IP3_27_24)
57#define GPSR1_22 F_(DU_DR6, IP3_23_20)
58#define GPSR1_21 F_(DU_DR5, IP3_19_16)
59#define GPSR1_20 F_(DU_DR4, IP3_15_12)
60#define GPSR1_19 F_(DU_DR3, IP3_11_8)
61#define GPSR1_18 F_(DU_DR2, IP3_7_4)
62#define GPSR1_17 F_(DU_DR1, IP3_3_0)
63#define GPSR1_16 F_(DU_DR0, IP2_31_28)
64#define GPSR1_15 F_(DU_DG7, IP2_27_24)
65#define GPSR1_14 F_(DU_DG6, IP2_23_20)
66#define GPSR1_13 F_(DU_DG5, IP2_19_16)
67#define GPSR1_12 F_(DU_DG4, IP2_15_12)
68#define GPSR1_11 F_(DU_DG3, IP2_11_8)
69#define GPSR1_10 F_(DU_DG2, IP2_7_4)
70#define GPSR1_9 F_(DU_DG1, IP2_3_0)
71#define GPSR1_8 F_(DU_DG0, IP1_31_28)
72#define GPSR1_7 F_(DU_DB7, IP1_27_24)
73#define GPSR1_6 F_(DU_DB6, IP1_23_20)
74#define GPSR1_5 F_(DU_DB5, IP1_19_16)
75#define GPSR1_4 F_(DU_DB4, IP1_15_12)
76#define GPSR1_3 F_(DU_DB3, IP1_11_8)
77#define GPSR1_2 F_(DU_DB2, IP1_7_4)
78#define GPSR1_1 F_(DU_DB1, IP1_3_0)
79#define GPSR1_0 F_(DU_DB0, IP0_31_28)
80
81/* GPSR2 */
82#define GPSR2_31 F_(NFCE_N, IP8_19_16)
83#define GPSR2_30 F_(NFCLE, IP8_15_12)
84#define GPSR2_29 F_(NFALE, IP8_11_8)
85#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
86#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
87#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
88#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
89#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
90#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
91#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
92#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
93#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
94#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
95#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
96#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
97#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
98#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
99#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
100#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
101#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
102#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
103#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
104#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
105#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
106#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
107#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
108#define GPSR2_5 FM(VI4_DATA4)
109#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
110#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
111#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
112#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
113#define GPSR2_0 FM(VI4_CLK)
114
115/* GPSR3 */
116#define GPSR3_9 F_(NFDATA7, IP9_31_28)
117#define GPSR3_8 F_(NFDATA6, IP9_27_24)
118#define GPSR3_7 F_(NFDATA5, IP9_23_20)
119#define GPSR3_6 F_(NFDATA4, IP9_19_16)
120#define GPSR3_5 F_(NFDATA3, IP9_15_12)
121#define GPSR3_4 F_(NFDATA2, IP9_11_8)
122#define GPSR3_3 F_(NFDATA1, IP9_7_4)
123#define GPSR3_2 F_(NFDATA0, IP9_3_0)
124#define GPSR3_1 F_(NFWE_N, IP8_31_28)
125#define GPSR3_0 F_(NFRE_N, IP8_27_24)
126
127/* GPSR4 */
128#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
129#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
130#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
131#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
132#define GPSR4_27 FM(TX2)
133#define GPSR4_26 FM(RX2)
134#define GPSR4_25 F_(SCK2, IP12_11_8)
135#define GPSR4_24 F_(TX1_A, IP12_7_4)
136#define GPSR4_23 F_(RX1_A, IP12_3_0)
137#define GPSR4_22 F_(SCK1_A, IP11_31_28)
138#define GPSR4_21 F_(TX0_A, IP11_27_24)
139#define GPSR4_20 F_(RX0_A, IP11_23_20)
140#define GPSR4_19 F_(SCK0_A, IP11_19_16)
141#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
142#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
143#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
144#define GPSR4_15 FM(MSIOF0_RXD)
145#define GPSR4_14 FM(MSIOF0_TXD)
146#define GPSR4_13 FM(MSIOF0_SYNC)
147#define GPSR4_12 FM(MSIOF0_SCK)
148#define GPSR4_11 F_(SDA1, IP11_3_0)
149#define GPSR4_10 F_(SCL1, IP10_31_28)
150#define GPSR4_9 FM(SDA0)
151#define GPSR4_8 FM(SCL0)
152#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
153#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
154#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
155#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
156#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
157#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
158#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
159#define GPSR4_0 F_(NFRB_N, IP8_23_20)
160
161/* GPSR5 */
162#define GPSR5_20 FM(AVB0_LINK)
163#define GPSR5_19 FM(AVB0_PHY_INT)
164#define GPSR5_18 FM(AVB0_MAGIC)
165#define GPSR5_17 FM(AVB0_MDC)
166#define GPSR5_16 FM(AVB0_MDIO)
167#define GPSR5_15 FM(AVB0_TXCREFCLK)
168#define GPSR5_14 FM(AVB0_TD3)
169#define GPSR5_13 FM(AVB0_TD2)
170#define GPSR5_12 FM(AVB0_TD1)
171#define GPSR5_11 FM(AVB0_TD0)
172#define GPSR5_10 FM(AVB0_TXC)
173#define GPSR5_9 FM(AVB0_TX_CTL)
174#define GPSR5_8 FM(AVB0_RD3)
175#define GPSR5_7 FM(AVB0_RD2)
176#define GPSR5_6 FM(AVB0_RD1)
177#define GPSR5_5 FM(AVB0_RD0)
178#define GPSR5_4 FM(AVB0_RXC)
179#define GPSR5_3 FM(AVB0_RX_CTL)
180#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
181#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
182#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
183
184/* GPSR6 */
185#define GPSR6_13 FM(RPC_INT_N)
186#define GPSR6_12 FM(RPC_RESET_N)
187#define GPSR6_11 FM(QSPI1_SSL)
188#define GPSR6_10 FM(QSPI1_IO3)
189#define GPSR6_9 FM(QSPI1_IO2)
190#define GPSR6_8 FM(QSPI1_MISO_IO1)
191#define GPSR6_7 FM(QSPI1_MOSI_IO0)
192#define GPSR6_6 FM(QSPI1_SPCLK)
193#define GPSR6_5 FM(QSPI0_SSL)
194#define GPSR6_4 FM(QSPI0_IO3)
195#define GPSR6_3 FM(QSPI0_IO2)
196#define GPSR6_2 FM(QSPI0_MISO_IO1)
197#define GPSR6_1 FM(QSPI0_MOSI_IO0)
198#define GPSR6_0 FM(QSPI0_SPCLK)
199
200/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
201#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233
234/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
235#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267
268/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
269#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301
302/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
303#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314#define PINMUX_GPSR \
315\
316 GPSR1_31 GPSR2_31 GPSR4_31 \
317 GPSR1_30 GPSR2_30 GPSR4_30 \
318 GPSR1_29 GPSR2_29 GPSR4_29 \
319 GPSR1_28 GPSR2_28 GPSR4_28 \
320 GPSR1_27 GPSR2_27 GPSR4_27 \
321 GPSR1_26 GPSR2_26 GPSR4_26 \
322 GPSR1_25 GPSR2_25 GPSR4_25 \
323 GPSR1_24 GPSR2_24 GPSR4_24 \
324 GPSR1_23 GPSR2_23 GPSR4_23 \
325 GPSR1_22 GPSR2_22 GPSR4_22 \
326 GPSR1_21 GPSR2_21 GPSR4_21 \
327 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
328 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
329 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
330 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
331 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
332 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
333 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
334 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
335 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
336 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
337 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
338 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
339GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
340GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
341GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
342GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
343GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
344GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
345GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
346GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
347GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
348
349#define PINMUX_IPSR \
350\
351FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
352FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
353FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
354FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
355FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
356FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
357FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
358FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
359\
360FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
361FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
362FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
363FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
364FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
365FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
366FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
367FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
368\
369FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
370FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
371FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
372FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
373FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
374FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
375FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
376FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
377\
378FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
379FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
380FM(IP12_11_8) IP12_11_8 \
381FM(IP12_15_12) IP12_15_12 \
382FM(IP12_19_16) IP12_19_16 \
383FM(IP12_23_20) IP12_23_20 \
384FM(IP12_27_24) IP12_27_24 \
385FM(IP12_31_28) IP12_31_28 \
386
387/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
388#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
389#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
390#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
391#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
392#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
393#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
394#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
395#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
396#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
397#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
398#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
399#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
400#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
401#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
402#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
403#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
404#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
405#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
406#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
407#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
408#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
409#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
410
411#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
412#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
413#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
414#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
415#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
416#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
417
418
419#define PINMUX_MOD_SELS \
420\
421 MOD_SEL1_31 \
422MOD_SEL0_30 MOD_SEL1_30 \
423MOD_SEL0_29 MOD_SEL1_29 \
424MOD_SEL0_28 MOD_SEL1_28 \
425MOD_SEL0_27 MOD_SEL1_27 \
426MOD_SEL0_26 MOD_SEL1_26 \
427MOD_SEL0_25 \
428MOD_SEL0_24_23 \
429MOD_SEL0_22_21 \
430MOD_SEL0_20_19 \
431MOD_SEL0_18_17 \
432MOD_SEL0_15 \
433MOD_SEL0_14 \
434MOD_SEL0_13 \
435MOD_SEL0_12 \
436MOD_SEL0_11 \
437MOD_SEL0_10 \
438MOD_SEL0_5 \
439MOD_SEL0_4 \
440MOD_SEL0_3 \
441MOD_SEL0_2 \
442MOD_SEL0_1 \
443MOD_SEL0_0
444
445enum {
446 PINMUX_RESERVED = 0,
447
448 PINMUX_DATA_BEGIN,
449 GP_ALL(DATA),
450 PINMUX_DATA_END,
451
452#define F_(x, y)
453#define FM(x) FN_##x,
454 PINMUX_FUNCTION_BEGIN,
455 GP_ALL(FN),
456 PINMUX_GPSR
457 PINMUX_IPSR
458 PINMUX_MOD_SELS
459 PINMUX_FUNCTION_END,
460#undef F_
461#undef FM
462
463#define F_(x, y)
464#define FM(x) x##_MARK,
465 PINMUX_MARK_BEGIN,
466 PINMUX_GPSR
467 PINMUX_IPSR
468 PINMUX_MOD_SELS
469 PINMUX_MARK_END,
470#undef F_
471#undef FM
472};
473
474#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
475 PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
476
477#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
478 PINMUX_DATA(fn##_MARK, FN_##msel)
479
480static const u16 pinmux_data[] = {
481 PINMUX_DATA_GP_ALL(),
482
483 PINMUX_SINGLE(USB0_OVC),
484 PINMUX_SINGLE(USB0_PWEN),
485 PINMUX_SINGLE(VI4_DATA4),
486 PINMUX_SINGLE(VI4_CLK),
487 PINMUX_SINGLE(TX2),
488 PINMUX_SINGLE(RX2),
489 PINMUX_SINGLE(AVB0_LINK),
490 PINMUX_SINGLE(AVB0_PHY_INT),
491 PINMUX_SINGLE(AVB0_MAGIC),
492 PINMUX_SINGLE(AVB0_MDC),
493 PINMUX_SINGLE(AVB0_MDIO),
494 PINMUX_SINGLE(AVB0_TXCREFCLK),
495 PINMUX_SINGLE(AVB0_TD3),
496 PINMUX_SINGLE(AVB0_TD2),
497 PINMUX_SINGLE(AVB0_TD1),
498 PINMUX_SINGLE(AVB0_TD0),
499 PINMUX_SINGLE(AVB0_TXC),
500 PINMUX_SINGLE(AVB0_TX_CTL),
501 PINMUX_SINGLE(AVB0_RD3),
502 PINMUX_SINGLE(AVB0_RD2),
503 PINMUX_SINGLE(AVB0_RD1),
504 PINMUX_SINGLE(AVB0_RD0),
505 PINMUX_SINGLE(AVB0_RXC),
506 PINMUX_SINGLE(AVB0_RX_CTL),
507 PINMUX_SINGLE(RPC_INT_N),
508 PINMUX_SINGLE(RPC_RESET_N),
509 PINMUX_SINGLE(QSPI1_SSL),
510 PINMUX_SINGLE(QSPI1_IO3),
511 PINMUX_SINGLE(QSPI1_IO2),
512 PINMUX_SINGLE(QSPI1_MISO_IO1),
513 PINMUX_SINGLE(QSPI1_MOSI_IO0),
514 PINMUX_SINGLE(QSPI1_SPCLK),
515 PINMUX_SINGLE(QSPI0_SSL),
516 PINMUX_SINGLE(QSPI0_IO3),
517 PINMUX_SINGLE(QSPI0_IO2),
518 PINMUX_SINGLE(QSPI0_MISO_IO1),
519 PINMUX_SINGLE(QSPI0_MOSI_IO0),
520 PINMUX_SINGLE(QSPI0_SPCLK),
521
522 /* IPSR0 */
523 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
524 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
525 PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN),
526
527 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
528 PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU),
529
530 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
531 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
532
533 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
534 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
535
536 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
537 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
538 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
539
540 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
541 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
542 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
543 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
544
545 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
546 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
547 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
548 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
549
550 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
551 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
552 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
553
554 /* IPSR1 */
555 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
556 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
557 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
558
559 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
560 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
561 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
562
563 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
564 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
565 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
566
567 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
568 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
569 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
570
571 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
572 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
573 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
574
575 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
576 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
577 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
578
579 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
580 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
581 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
582
583 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
584 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
585 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
586
587 /* IPSR2 */
588 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
589 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
590 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
591
592 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
593 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
594
595 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
596 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
597 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
598
599 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
600 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
601 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
602
603 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
604 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
605 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
606
607 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
608 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
609 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
610
611 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
612 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
613 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
614
615 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
616 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
617 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
618
619 /* IPSR3 */
620 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
621 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
622 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
623
624 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
625 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
626 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
627
628 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
629 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
630 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
631
632 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
633 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
634 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
635
636 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
637 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
638 PINMUX_IPSR_GPSR(IP3_19_16, NMI),
639
640 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
641 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
642 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
643
644 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
645 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
646 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
647
648 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
649 PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
650
651 /* IPSR4 */
652 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
653 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
654 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
655
656 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
657 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
658 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
659
660 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
661 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
662 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
663
664 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
665 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
666 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
667 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
668
669 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
670 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
671 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
672
673 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
674 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
675
676 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
677 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
678
679 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
680 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
681
682 /* IPSR5 */
683 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
684 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
685
686 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
687 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
688
689 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
690 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
691
692 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
693 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
694
695 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
696 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
697
698 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
699 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
700
701 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
702
703 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
704 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
705 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
706
707 /* IPSR6 */
708 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
709 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
710
711 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
712 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
713
714 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
715 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
716
717 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
718 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
719 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
720
721 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
722 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
723 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
724
725 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
726 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
727
728 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
729 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
730
731 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
732 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
733
734 /* IPSR7 */
735 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
736 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
737
738 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
739 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
740 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
741
742 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
743 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
744 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
745
746 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
747 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
748
749 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
750 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
751 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
752
753 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
754 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
755 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
756
757 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
758
759 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
760 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
761 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
762
763 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
764 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
765 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
766
767 /* IPSR8 */
768 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
769 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
770 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
771 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
772 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
773
774 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
775 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
776 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
777 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
778
779 PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
780 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
781 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
782 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
783
784 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
785 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
786 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
787 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
788
789 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
790 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
791 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
792
793 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
794 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
795 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
796
797 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
798 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
799
800 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
801 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
802
803 /* IPSR9 */
804 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
805 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
806
807 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
808 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
809
810 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
811 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
812
813 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
814 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
815
816 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
817 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
818
819 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
820 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
821
822 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
823 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
824
825 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
826 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
827
828 /* IPSR10 */
829 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
830 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
831
832 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
833 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
834
835 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
836 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
837
838 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
839 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
840
841 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
842 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
843 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
844 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
845 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
846
847 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
848 PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
849 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
850 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
851
852 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
853 PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
854 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
855 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
856
857 PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
858 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
859
860 /* IPSR11 */
861 PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
862 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
863
864 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
865 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
866
867 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
868 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
869
870 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
871 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
872
873 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
874 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
875 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
876
877 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
878 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
879 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
880
881 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
882 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
883 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
884
885 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
886 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
887 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
888 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
889 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
890
891 /* IPSR12 */
892 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
893 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
894 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
895
896 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
897 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
898 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
899
900 PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
901 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
902 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
903
904 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
905 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
906 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
907
908 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
909 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
910 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
911
912 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
913 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
914 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
915 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
916
917 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
918 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
919 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
920
921 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
922 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
923 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
924
925 /* IPSR13 */
926 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
927 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
928 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
929
930 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
931 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
932 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
933};
934
935static const struct sh_pfc_pin pinmux_pins[] = {
936 PINMUX_GPIO_GP_ALL(),
937};
938
939/* - I2C -------------------------------------------------------------------- */
940static const unsigned int i2c0_pins[] = {
941 /* SCL, SDA */
942 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
943};
944static const unsigned int i2c0_mux[] = {
945 SCL0_MARK, SDA0_MARK,
946};
947static const unsigned int i2c1_pins[] = {
948 /* SCL, SDA */
949 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
950};
951static const unsigned int i2c1_mux[] = {
952 SCL1_MARK, SDA1_MARK,
953};
954static const unsigned int i2c2_a_pins[] = {
955 /* SCL, SDA */
956 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
957};
958static const unsigned int i2c2_a_mux[] = {
959 SCL2_A_MARK, SDA2_A_MARK,
960};
961static const unsigned int i2c2_b_pins[] = {
962 /* SCL, SDA */
963 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
964};
965static const unsigned int i2c2_b_mux[] = {
966 SCL2_B_MARK, SDA2_B_MARK,
967};
968static const unsigned int i2c3_a_pins[] = {
969 /* SCL, SDA */
970 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
971};
972static const unsigned int i2c3_a_mux[] = {
973 SCL3_A_MARK, SDA3_A_MARK,
974};
975static const unsigned int i2c3_b_pins[] = {
976 /* SCL, SDA */
977 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
978};
979static const unsigned int i2c3_b_mux[] = {
980 SCL3_B_MARK, SDA3_B_MARK,
981};
982
983/* - MMC ------------------------------------------------------------------- */
984static const unsigned int mmc_data1_pins[] = {
985 /* D0 */
986 RCAR_GP_PIN(3, 2),
987};
988static const unsigned int mmc_data1_mux[] = {
989 MMC_D0_MARK,
990};
991static const unsigned int mmc_data4_pins[] = {
992 /* D[0:3] */
993 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
994 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
995};
996static const unsigned int mmc_data4_mux[] = {
997 MMC_D0_MARK, MMC_D1_MARK,
998 MMC_D2_MARK, MMC_D3_MARK,
999};
1000static const unsigned int mmc_data8_pins[] = {
1001 /* D[0:7] */
1002 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1003 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1004 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1005 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1006};
1007static const unsigned int mmc_data8_mux[] = {
1008 MMC_D0_MARK, MMC_D1_MARK,
1009 MMC_D2_MARK, MMC_D3_MARK,
1010 MMC_D4_MARK, MMC_D5_MARK,
1011 MMC_D6_MARK, MMC_D7_MARK,
1012};
1013static const unsigned int mmc_ctrl_pins[] = {
1014 /* CLK, CMD */
1015 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1016};
1017static const unsigned int mmc_ctrl_mux[] = {
1018 MMC_CLK_MARK, MMC_CMD_MARK,
1019};
1020
1021/* - SCIF0 ------------------------------------------------------------------ */
1022static const unsigned int scif0_data_a_pins[] = {
1023 /* RX, TX */
1024 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1025};
1026static const unsigned int scif0_data_a_mux[] = {
1027 RX0_A_MARK, TX0_A_MARK,
1028};
1029static const unsigned int scif0_clk_a_pins[] = {
1030 /* SCK */
1031 RCAR_GP_PIN(4, 19),
1032};
1033static const unsigned int scif0_clk_a_mux[] = {
1034 SCK0_A_MARK,
1035};
1036static const unsigned int scif0_data_b_pins[] = {
1037 /* RX, TX */
1038 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
1039};
1040static const unsigned int scif0_data_b_mux[] = {
1041 RX0_B_MARK, TX0_B_MARK,
1042};
1043static const unsigned int scif0_clk_b_pins[] = {
1044 /* SCK */
1045 RCAR_GP_PIN(5, 2),
1046};
1047static const unsigned int scif0_clk_b_mux[] = {
1048 SCK0_B_MARK,
1049};
1050static const unsigned int scif0_ctrl_pins[] = {
1051 /* RTS, CTS */
1052 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1053};
1054static const unsigned int scif0_ctrl_mux[] = {
1055 RTS0_N_TANS_MARK, CTS0_N_MARK,
1056};
1057/* - SCIF1 ------------------------------------------------------------------ */
1058static const unsigned int scif1_data_a_pins[] = {
1059 /* RX, TX */
1060 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
1061};
1062static const unsigned int scif1_data_a_mux[] = {
1063 RX1_A_MARK, TX1_A_MARK,
1064};
1065static const unsigned int scif1_clk_a_pins[] = {
1066 /* SCK */
1067 RCAR_GP_PIN(4, 22),
1068};
1069static const unsigned int scif1_clk_a_mux[] = {
1070 SCK1_A_MARK,
1071};
1072static const unsigned int scif1_data_b_pins[] = {
1073 /* RX, TX */
1074 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
1075};
1076static const unsigned int scif1_data_b_mux[] = {
1077 RX1_B_MARK, TX1_B_MARK,
1078};
1079static const unsigned int scif1_clk_b_pins[] = {
1080 /* SCK */
1081 RCAR_GP_PIN(2, 25),
1082};
1083static const unsigned int scif1_clk_b_mux[] = {
1084 SCK1_B_MARK,
1085};
1086static const unsigned int scif1_ctrl_pins[] = {
1087 /* RTS, CTS */
1088 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1089};
1090static const unsigned int scif1_ctrl_mux[] = {
1091 RTS1_N_TANS_MARK, CTS1_N_MARK,
1092};
1093
1094/* - SCIF2 ------------------------------------------------------------------ */
1095static const unsigned int scif2_data_pins[] = {
1096 /* RX, TX */
1097 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
1098};
1099static const unsigned int scif2_data_mux[] = {
1100 RX2_MARK, TX2_MARK,
1101};
1102static const unsigned int scif2_clk_pins[] = {
1103 /* SCK */
1104 RCAR_GP_PIN(4, 25),
1105};
1106static const unsigned int scif2_clk_mux[] = {
1107 SCK2_MARK,
1108};
1109/* - SCIF3 ------------------------------------------------------------------ */
1110static const unsigned int scif3_data_a_pins[] = {
1111 /* RX, TX */
1112 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
1113};
1114static const unsigned int scif3_data_a_mux[] = {
1115 RX3_A_MARK, TX3_A_MARK,
1116};
1117static const unsigned int scif3_clk_a_pins[] = {
1118 /* SCK */
1119 RCAR_GP_PIN(2, 30),
1120};
1121static const unsigned int scif3_clk_a_mux[] = {
1122 SCK3_A_MARK,
1123};
1124static const unsigned int scif3_data_b_pins[] = {
1125 /* RX, TX */
1126 RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
1127};
1128static const unsigned int scif3_data_b_mux[] = {
1129 RX3_B_MARK, TX3_B_MARK,
1130};
1131static const unsigned int scif3_clk_b_pins[] = {
1132 /* SCK */
1133 RCAR_GP_PIN(1, 29),
1134};
1135static const unsigned int scif3_clk_b_mux[] = {
1136 SCK3_B_MARK,
1137};
1138/* - SCIF4 ------------------------------------------------------------------ */
1139static const unsigned int scif4_data_a_pins[] = {
1140 /* RX, TX */
1141 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1142};
1143static const unsigned int scif4_data_a_mux[] = {
1144 RX4_A_MARK, TX4_A_MARK,
1145};
1146static const unsigned int scif4_clk_a_pins[] = {
1147 /* SCK */
1148 RCAR_GP_PIN(2, 6),
1149};
1150static const unsigned int scif4_clk_a_mux[] = {
1151 SCK4_A_MARK,
1152};
1153static const unsigned int scif4_data_b_pins[] = {
1154 /* RX, TX */
1155 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1156};
1157static const unsigned int scif4_data_b_mux[] = {
1158 RX4_B_MARK, TX4_B_MARK,
1159};
1160static const unsigned int scif4_clk_b_pins[] = {
1161 /* SCK */
1162 RCAR_GP_PIN(1, 15),
1163};
1164static const unsigned int scif4_clk_b_mux[] = {
1165 SCK4_B_MARK,
1166};
1167/* - SCIF5 ------------------------------------------------------------------ */
1168static const unsigned int scif5_data_a_pins[] = {
1169 /* RX, TX */
1170 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1171};
1172static const unsigned int scif5_data_a_mux[] = {
1173 RX5_A_MARK, TX5_A_MARK,
1174};
1175static const unsigned int scif5_clk_a_pins[] = {
1176 /* SCK */
1177 RCAR_GP_PIN(0, 6),
1178};
1179static const unsigned int scif5_clk_a_mux[] = {
1180 SCK5_A_MARK,
1181};
1182static const unsigned int scif5_data_b_pins[] = {
1183 /* RX, TX */
1184 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1185};
1186static const unsigned int scif5_data_b_mux[] = {
1187 RX5_B_MARK, TX5_B_MARK,
1188};
1189static const unsigned int scif5_clk_b_pins[] = {
1190 /* SCK */
1191 RCAR_GP_PIN(1, 3),
1192};
1193static const unsigned int scif5_clk_b_mux[] = {
1194 SCK5_B_MARK,
1195};
1196/* - SCIF Clock ------------------------------------------------------------- */
1197static const unsigned int scif_clk_pins[] = {
1198 /* SCIF_CLK */
1199 RCAR_GP_PIN(2, 27),
1200};
1201static const unsigned int scif_clk_mux[] = {
1202 SCIF_CLK_MARK,
1203};
1204
1205static const struct sh_pfc_pin_group pinmux_groups[] = {
1206 SH_PFC_PIN_GROUP(i2c0),
1207 SH_PFC_PIN_GROUP(i2c1),
1208 SH_PFC_PIN_GROUP(i2c2_a),
1209 SH_PFC_PIN_GROUP(i2c2_b),
1210 SH_PFC_PIN_GROUP(i2c3_a),
1211 SH_PFC_PIN_GROUP(i2c3_b),
1212 SH_PFC_PIN_GROUP(mmc_data1),
1213 SH_PFC_PIN_GROUP(mmc_data4),
1214 SH_PFC_PIN_GROUP(mmc_data8),
1215 SH_PFC_PIN_GROUP(mmc_ctrl),
1216 SH_PFC_PIN_GROUP(scif0_data_a),
1217 SH_PFC_PIN_GROUP(scif0_clk_a),
1218 SH_PFC_PIN_GROUP(scif0_data_b),
1219 SH_PFC_PIN_GROUP(scif0_clk_b),
1220 SH_PFC_PIN_GROUP(scif0_ctrl),
1221 SH_PFC_PIN_GROUP(scif1_data_a),
1222 SH_PFC_PIN_GROUP(scif1_clk_a),
1223 SH_PFC_PIN_GROUP(scif1_data_b),
1224 SH_PFC_PIN_GROUP(scif1_clk_b),
1225 SH_PFC_PIN_GROUP(scif1_ctrl),
1226 SH_PFC_PIN_GROUP(scif2_data),
1227 SH_PFC_PIN_GROUP(scif2_clk),
1228 SH_PFC_PIN_GROUP(scif3_data_a),
1229 SH_PFC_PIN_GROUP(scif3_clk_a),
1230 SH_PFC_PIN_GROUP(scif3_data_b),
1231 SH_PFC_PIN_GROUP(scif3_clk_b),
1232 SH_PFC_PIN_GROUP(scif4_data_a),
1233 SH_PFC_PIN_GROUP(scif4_clk_a),
1234 SH_PFC_PIN_GROUP(scif4_data_b),
1235 SH_PFC_PIN_GROUP(scif4_clk_b),
1236 SH_PFC_PIN_GROUP(scif5_data_a),
1237 SH_PFC_PIN_GROUP(scif5_clk_a),
1238 SH_PFC_PIN_GROUP(scif5_data_b),
1239 SH_PFC_PIN_GROUP(scif5_clk_b),
1240 SH_PFC_PIN_GROUP(scif_clk),
1241};
1242
1243static const char * const i2c0_groups[] = {
1244 "i2c0",
1245};
1246static const char * const i2c1_groups[] = {
1247 "i2c1",
1248};
1249
1250static const char * const i2c2_groups[] = {
1251 "i2c2_a",
1252 "i2c2_b",
1253};
1254
1255static const char * const i2c3_groups[] = {
1256 "i2c3_a",
1257 "i2c3_b",
1258};
1259
1260static const char * const mmc_groups[] = {
1261 "mmc_data1",
1262 "mmc_data4",
1263 "mmc_data8",
1264 "mmc_ctrl",
1265};
1266
1267static const char * const scif0_groups[] = {
1268 "scif0_data_a",
1269 "scif0_clk_a",
1270 "scif0_data_b",
1271 "scif0_clk_b",
1272 "scif0_ctrl",
1273};
1274
1275static const char * const scif1_groups[] = {
1276 "scif1_data_a",
1277 "scif1_clk_a",
1278 "scif1_data_b",
1279 "scif1_clk_b",
1280 "scif1_ctrl",
1281};
1282
1283static const char * const scif2_groups[] = {
1284 "scif2_data",
1285 "scif2_clk",
1286};
1287
1288static const char * const scif3_groups[] = {
1289 "scif3_data_a",
1290 "scif3_clk_a",
1291 "scif3_data_b",
1292 "scif3_clk_b",
1293};
1294
1295static const char * const scif4_groups[] = {
1296 "scif4_data_a",
1297 "scif4_clk_a",
1298 "scif4_data_b",
1299 "scif4_clk_b",
1300};
1301
1302static const char * const scif5_groups[] = {
1303 "scif5_data_a",
1304 "scif5_clk_a",
1305 "scif5_data_b",
1306 "scif5_clk_b",
1307};
1308
1309static const char * const scif_clk_groups[] = {
1310 "scif_clk",
1311};
1312
1313static const struct sh_pfc_function pinmux_functions[] = {
1314 SH_PFC_FUNCTION(i2c0),
1315 SH_PFC_FUNCTION(i2c1),
1316 SH_PFC_FUNCTION(i2c2),
1317 SH_PFC_FUNCTION(i2c3),
1318 SH_PFC_FUNCTION(mmc),
1319 SH_PFC_FUNCTION(scif0),
1320 SH_PFC_FUNCTION(scif1),
1321 SH_PFC_FUNCTION(scif2),
1322 SH_PFC_FUNCTION(scif3),
1323 SH_PFC_FUNCTION(scif4),
1324 SH_PFC_FUNCTION(scif5),
1325 SH_PFC_FUNCTION(scif_clk),
1326};
1327
1328static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1329#define F_(x, y) FN_##y
1330#define FM(x) FN_##x
1331 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
1332 0, 0,
1333 0, 0,
1334 0, 0,
1335 0, 0,
1336 0, 0,
1337 0, 0,
1338 0, 0,
1339 0, 0,
1340 0, 0,
1341 0, 0,
1342 0, 0,
1343 0, 0,
1344 0, 0,
1345 0, 0,
1346 0, 0,
1347 0, 0,
1348 0, 0,
1349 0, 0,
1350 0, 0,
1351 0, 0,
1352 0, 0,
1353 0, 0,
1354 0, 0,
1355 GP_0_8_FN, GPSR0_8,
1356 GP_0_7_FN, GPSR0_7,
1357 GP_0_6_FN, GPSR0_6,
1358 GP_0_5_FN, GPSR0_5,
1359 GP_0_4_FN, GPSR0_4,
1360 GP_0_3_FN, GPSR0_3,
1361 GP_0_2_FN, GPSR0_2,
1362 GP_0_1_FN, GPSR0_1,
1363 GP_0_0_FN, GPSR0_0, }
1364 },
1365 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
1366 GP_1_31_FN, GPSR1_31,
1367 GP_1_30_FN, GPSR1_30,
1368 GP_1_29_FN, GPSR1_29,
1369 GP_1_28_FN, GPSR1_28,
1370 GP_1_27_FN, GPSR1_27,
1371 GP_1_26_FN, GPSR1_26,
1372 GP_1_25_FN, GPSR1_25,
1373 GP_1_24_FN, GPSR1_24,
1374 GP_1_23_FN, GPSR1_23,
1375 GP_1_22_FN, GPSR1_22,
1376 GP_1_21_FN, GPSR1_21,
1377 GP_1_20_FN, GPSR1_20,
1378 GP_1_19_FN, GPSR1_19,
1379 GP_1_18_FN, GPSR1_18,
1380 GP_1_17_FN, GPSR1_17,
1381 GP_1_16_FN, GPSR1_16,
1382 GP_1_15_FN, GPSR1_15,
1383 GP_1_14_FN, GPSR1_14,
1384 GP_1_13_FN, GPSR1_13,
1385 GP_1_12_FN, GPSR1_12,
1386 GP_1_11_FN, GPSR1_11,
1387 GP_1_10_FN, GPSR1_10,
1388 GP_1_9_FN, GPSR1_9,
1389 GP_1_8_FN, GPSR1_8,
1390 GP_1_7_FN, GPSR1_7,
1391 GP_1_6_FN, GPSR1_6,
1392 GP_1_5_FN, GPSR1_5,
1393 GP_1_4_FN, GPSR1_4,
1394 GP_1_3_FN, GPSR1_3,
1395 GP_1_2_FN, GPSR1_2,
1396 GP_1_1_FN, GPSR1_1,
1397 GP_1_0_FN, GPSR1_0, }
1398 },
1399 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
1400 GP_2_31_FN, GPSR2_31,
1401 GP_2_30_FN, GPSR2_30,
1402 GP_2_29_FN, GPSR2_29,
1403 GP_2_28_FN, GPSR2_28,
1404 GP_2_27_FN, GPSR2_27,
1405 GP_2_26_FN, GPSR2_26,
1406 GP_2_25_FN, GPSR2_25,
1407 GP_2_24_FN, GPSR2_24,
1408 GP_2_23_FN, GPSR2_23,
1409 GP_2_22_FN, GPSR2_22,
1410 GP_2_21_FN, GPSR2_21,
1411 GP_2_20_FN, GPSR2_20,
1412 GP_2_19_FN, GPSR2_19,
1413 GP_2_18_FN, GPSR2_18,
1414 GP_2_17_FN, GPSR2_17,
1415 GP_2_16_FN, GPSR2_16,
1416 GP_2_15_FN, GPSR2_15,
1417 GP_2_14_FN, GPSR2_14,
1418 GP_2_13_FN, GPSR2_13,
1419 GP_2_12_FN, GPSR2_12,
1420 GP_2_11_FN, GPSR2_11,
1421 GP_2_10_FN, GPSR2_10,
1422 GP_2_9_FN, GPSR2_9,
1423 GP_2_8_FN, GPSR2_8,
1424 GP_2_7_FN, GPSR2_7,
1425 GP_2_6_FN, GPSR2_6,
1426 GP_2_5_FN, GPSR2_5,
1427 GP_2_4_FN, GPSR2_4,
1428 GP_2_3_FN, GPSR2_3,
1429 GP_2_2_FN, GPSR2_2,
1430 GP_2_1_FN, GPSR2_1,
1431 GP_2_0_FN, GPSR2_0, }
1432 },
1433 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
1434 0, 0,
1435 0, 0,
1436 0, 0,
1437 0, 0,
1438 0, 0,
1439 0, 0,
1440 0, 0,
1441 0, 0,
1442 0, 0,
1443 0, 0,
1444 0, 0,
1445 0, 0,
1446 0, 0,
1447 0, 0,
1448 0, 0,
1449 0, 0,
1450 0, 0,
1451 0, 0,
1452 0, 0,
1453 0, 0,
1454 0, 0,
1455 0, 0,
1456 GP_3_9_FN, GPSR3_9,
1457 GP_3_8_FN, GPSR3_8,
1458 GP_3_7_FN, GPSR3_7,
1459 GP_3_6_FN, GPSR3_6,
1460 GP_3_5_FN, GPSR3_5,
1461 GP_3_4_FN, GPSR3_4,
1462 GP_3_3_FN, GPSR3_3,
1463 GP_3_2_FN, GPSR3_2,
1464 GP_3_1_FN, GPSR3_1,
1465 GP_3_0_FN, GPSR3_0, }
1466 },
1467 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
1468 GP_4_31_FN, GPSR4_31,
1469 GP_4_30_FN, GPSR4_30,
1470 GP_4_29_FN, GPSR4_29,
1471 GP_4_28_FN, GPSR4_28,
1472 GP_4_27_FN, GPSR4_27,
1473 GP_4_26_FN, GPSR4_26,
1474 GP_4_25_FN, GPSR4_25,
1475 GP_4_24_FN, GPSR4_24,
1476 GP_4_23_FN, GPSR4_23,
1477 GP_4_22_FN, GPSR4_22,
1478 GP_4_21_FN, GPSR4_21,
1479 GP_4_20_FN, GPSR4_20,
1480 GP_4_19_FN, GPSR4_19,
1481 GP_4_18_FN, GPSR4_18,
1482 GP_4_17_FN, GPSR4_17,
1483 GP_4_16_FN, GPSR4_16,
1484 GP_4_15_FN, GPSR4_15,
1485 GP_4_14_FN, GPSR4_14,
1486 GP_4_13_FN, GPSR4_13,
1487 GP_4_12_FN, GPSR4_12,
1488 GP_4_11_FN, GPSR4_11,
1489 GP_4_10_FN, GPSR4_10,
1490 GP_4_9_FN, GPSR4_9,
1491 GP_4_8_FN, GPSR4_8,
1492 GP_4_7_FN, GPSR4_7,
1493 GP_4_6_FN, GPSR4_6,
1494 GP_4_5_FN, GPSR4_5,
1495 GP_4_4_FN, GPSR4_4,
1496 GP_4_3_FN, GPSR4_3,
1497 GP_4_2_FN, GPSR4_2,
1498 GP_4_1_FN, GPSR4_1,
1499 GP_4_0_FN, GPSR4_0, }
1500 },
1501 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
1502 0, 0,
1503 0, 0,
1504 0, 0,
1505 0, 0,
1506 0, 0,
1507 0, 0,
1508 0, 0,
1509 0, 0,
1510 0, 0,
1511 0, 0,
1512 0, 0,
1513 GP_5_20_FN, GPSR5_20,
1514 GP_5_19_FN, GPSR5_19,
1515 GP_5_18_FN, GPSR5_18,
1516 GP_5_17_FN, GPSR5_17,
1517 GP_5_16_FN, GPSR5_16,
1518 GP_5_15_FN, GPSR5_15,
1519 GP_5_14_FN, GPSR5_14,
1520 GP_5_13_FN, GPSR5_13,
1521 GP_5_12_FN, GPSR5_12,
1522 GP_5_11_FN, GPSR5_11,
1523 GP_5_10_FN, GPSR5_10,
1524 GP_5_9_FN, GPSR5_9,
1525 GP_5_8_FN, GPSR5_8,
1526 GP_5_7_FN, GPSR5_7,
1527 GP_5_6_FN, GPSR5_6,
1528 GP_5_5_FN, GPSR5_5,
1529 GP_5_4_FN, GPSR5_4,
1530 GP_5_3_FN, GPSR5_3,
1531 GP_5_2_FN, GPSR5_2,
1532 GP_5_1_FN, GPSR5_1,
1533 GP_5_0_FN, GPSR5_0, }
1534 },
1535 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
1536 0, 0,
1537 0, 0,
1538 0, 0,
1539 0, 0,
1540 0, 0,
1541 0, 0,
1542 0, 0,
1543 0, 0,
1544 0, 0,
1545 0, 0,
1546 0, 0,
1547 0, 0,
1548 0, 0,
1549 0, 0,
1550 0, 0,
1551 0, 0,
1552 0, 0,
1553 0, 0,
1554 GP_6_13_FN, GPSR6_13,
1555 GP_6_12_FN, GPSR6_12,
1556 GP_6_11_FN, GPSR6_11,
1557 GP_6_10_FN, GPSR6_10,
1558 GP_6_9_FN, GPSR6_9,
1559 GP_6_8_FN, GPSR6_8,
1560 GP_6_7_FN, GPSR6_7,
1561 GP_6_6_FN, GPSR6_6,
1562 GP_6_5_FN, GPSR6_5,
1563 GP_6_4_FN, GPSR6_4,
1564 GP_6_3_FN, GPSR6_3,
1565 GP_6_2_FN, GPSR6_2,
1566 GP_6_1_FN, GPSR6_1,
1567 GP_6_0_FN, GPSR6_0, }
1568 },
1569#undef F_
1570#undef FM
1571
1572#define F_(x, y) x,
1573#define FM(x) FN_##x,
1574 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
1575 IP0_31_28
1576 IP0_27_24
1577 IP0_23_20
1578 IP0_19_16
1579 IP0_15_12
1580 IP0_11_8
1581 IP0_7_4
1582 IP0_3_0 }
1583 },
1584 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
1585 IP1_31_28
1586 IP1_27_24
1587 IP1_23_20
1588 IP1_19_16
1589 IP1_15_12
1590 IP1_11_8
1591 IP1_7_4
1592 IP1_3_0 }
1593 },
1594 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
1595 IP2_31_28
1596 IP2_27_24
1597 IP2_23_20
1598 IP2_19_16
1599 IP2_15_12
1600 IP2_11_8
1601 IP2_7_4
1602 IP2_3_0 }
1603 },
1604 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
1605 IP3_31_28
1606 IP3_27_24
1607 IP3_23_20
1608 IP3_19_16
1609 IP3_15_12
1610 IP3_11_8
1611 IP3_7_4
1612 IP3_3_0 }
1613 },
1614 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
1615 IP4_31_28
1616 IP4_27_24
1617 IP4_23_20
1618 IP4_19_16
1619 IP4_15_12
1620 IP4_11_8
1621 IP4_7_4
1622 IP4_3_0 }
1623 },
1624 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
1625 IP5_31_28
1626 IP5_27_24
1627 IP5_23_20
1628 IP5_19_16
1629 IP5_15_12
1630 IP5_11_8
1631 IP5_7_4
1632 IP5_3_0 }
1633 },
1634 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
1635 IP6_31_28
1636 IP6_27_24
1637 IP6_23_20
1638 IP6_19_16
1639 IP6_15_12
1640 IP6_11_8
1641 IP6_7_4
1642 IP6_3_0 }
1643 },
1644 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
1645 IP7_31_28
1646 IP7_27_24
1647 IP7_23_20
1648 IP7_19_16
1649 IP7_15_12
1650 IP7_11_8
1651 IP7_7_4
1652 IP7_3_0 }
1653 },
1654 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
1655 IP8_31_28
1656 IP8_27_24
1657 IP8_23_20
1658 IP8_19_16
1659 IP8_15_12
1660 IP8_11_8
1661 IP8_7_4
1662 IP8_3_0 }
1663 },
1664 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
1665 IP9_31_28
1666 IP9_27_24
1667 IP9_23_20
1668 IP9_19_16
1669 IP9_15_12
1670 IP9_11_8
1671 IP9_7_4
1672 IP9_3_0 }
1673 },
1674 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
1675 IP10_31_28
1676 IP10_27_24
1677 IP10_23_20
1678 IP10_19_16
1679 IP10_15_12
1680 IP10_11_8
1681 IP10_7_4
1682 IP10_3_0 }
1683 },
1684 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
1685 IP11_31_28
1686 IP11_27_24
1687 IP11_23_20
1688 IP11_19_16
1689 IP11_15_12
1690 IP11_11_8
1691 IP11_7_4
1692 IP11_3_0 }
1693 },
1694 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
1695 IP12_31_28
1696 IP12_27_24
1697 IP12_23_20
1698 IP12_19_16
1699 IP12_15_12
1700 IP12_11_8
1701 IP12_7_4
1702 IP12_3_0 }
1703 },
1704 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
1705 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1706 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1707 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1708 /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1709 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1710 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1711 IP13_7_4
1712 IP13_3_0 }
1713 },
1714#undef F_
1715#undef FM
1716
1717#define F_(x, y) x,
1718#define FM(x) FN_##x,
1719 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
1720 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
1721 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
1722 /* RESERVED 31 */
1723 0, 0,
1724 MOD_SEL0_30
1725 MOD_SEL0_29
1726 MOD_SEL0_28
1727 MOD_SEL0_27
1728 MOD_SEL0_26
1729 MOD_SEL0_25
1730 MOD_SEL0_24_23
1731 MOD_SEL0_22_21
1732 MOD_SEL0_20_19
1733 MOD_SEL0_18_17
1734 /* RESERVED 16 */
1735 0, 0,
1736 MOD_SEL0_15
1737 MOD_SEL0_14
1738 MOD_SEL0_13
1739 MOD_SEL0_12
1740 MOD_SEL0_11
1741 MOD_SEL0_10
1742 /* RESERVED 9, 8, 7, 6 */
1743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1744 MOD_SEL0_5
1745 MOD_SEL0_4
1746 MOD_SEL0_3
1747 MOD_SEL0_2
1748 MOD_SEL0_1
1749 MOD_SEL0_0 }
1750 },
1751 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
1752 1, 1, 1, 1, 1, 1, 2, 4, 4,
1753 4, 4, 4, 4) {
1754 MOD_SEL1_31
1755 MOD_SEL1_30
1756 MOD_SEL1_29
1757 MOD_SEL1_28
1758 MOD_SEL1_27
1759 MOD_SEL1_26
1760 /* RESERVED 25, 24 */
1761 0, 0, 0, 0,
1762 /* RESERVED 23, 22, 21, 20 */
1763 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1764 /* RESERVED 19, 18, 17, 16 */
1765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1766 /* RESERVED 15, 14, 13, 12 */
1767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1768 /* RESERVED 11, 10, 9, 8 */
1769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1770 /* RESERVED 7, 6, 5, 4 */
1771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1772 /* RESERVED 3, 2, 1, 0 */
1773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1774 },
1775 { },
1776};
1777
1778static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
1779{
1780 int bit = -EINVAL;
1781
1782 *pocctrl = 0xe6060380;
1783
1784 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
1785 bit = 29 - (pin - RCAR_GP_PIN(3, 0));
1786
1787 return bit;
1788}
1789
1790static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
1791 .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
1792};
1793
1794const struct sh_pfc_soc_info r8a77995_pinmux_info = {
1795 .name = "r8a77995_pfc",
1796 .ops = &r8a77995_pinmux_ops,
1797 .unlock_reg = 0xe6060000, /* PMMR */
1798
1799 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1800
1801 .pins = pinmux_pins,
1802 .nr_pins = ARRAY_SIZE(pinmux_pins),
1803 .groups = pinmux_groups,
1804 .nr_groups = ARRAY_SIZE(pinmux_groups),
1805 .functions = pinmux_functions,
1806 .nr_functions = ARRAY_SIZE(pinmux_functions),
1807
1808 .cfg_regs = pinmux_config_regs,
1809
1810 .pinmux_data = pinmux_data,
1811 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1812};
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index e7a92eec06c2..5c9d79981e6d 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -742,13 +742,16 @@ static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
742 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 742 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
743 const unsigned int *pins; 743 const unsigned int *pins;
744 unsigned int num_pins; 744 unsigned int num_pins;
745 unsigned int i; 745 unsigned int i, ret;
746 746
747 pins = pmx->pfc->info->groups[group].pins; 747 pins = pmx->pfc->info->groups[group].pins;
748 num_pins = pmx->pfc->info->groups[group].nr_pins; 748 num_pins = pmx->pfc->info->groups[group].nr_pins;
749 749
750 for (i = 0; i < num_pins; ++i) 750 for (i = 0; i < num_pins; ++i) {
751 sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); 751 ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
752 if (ret)
753 return ret;
754 }
752 755
753 return 0; 756 return 0;
754} 757}
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 4376397123de..8688b405e081 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -271,6 +271,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
271extern const struct sh_pfc_soc_info r8a7795_pinmux_info; 271extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
272extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; 272extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
273extern const struct sh_pfc_soc_info r8a7796_pinmux_info; 273extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
274extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
274extern const struct sh_pfc_soc_info sh7203_pinmux_info; 275extern const struct sh_pfc_soc_info sh7203_pinmux_info;
275extern const struct sh_pfc_soc_info sh7264_pinmux_info; 276extern const struct sh_pfc_soc_info sh7264_pinmux_info;
276extern const struct sh_pfc_soc_info sh7269_pinmux_info; 277extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@@ -389,9 +390,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
389 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) 390 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
390#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) 391#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
391 392
392#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ 393#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
393 PORT_GP_CFG_9(bank, fn, sfx, cfg), \ 394 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
394 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ 395 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
396#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
397
398#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
399 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
395 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \ 400 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
396 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) 401 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
397#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) 402#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
@@ -422,11 +427,19 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
422 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) 427 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
423#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) 428#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
424 429
425#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ 430#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
426 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ 431 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
427 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ 432 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
428 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ 433 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
429 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \ 434#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
435
436#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
437 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
438 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
439#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
440
441#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
442 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
430 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ 443 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
431 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) 444 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
432#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) 445#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 17:28:01 -0400