Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux into drm-next

Last feature request for 4.18.  Mostly vega20 support.
- Vega20 support
- clock and powergating for VCN
- misc bug fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180524152427.32713-1-alexander.deucher@amd.com

139 files changed, 6965 insertions, 2829 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 68e9f584c570..a51c5a960750 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -62,11 +62,13 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
 amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
 
 amdgpu-y += \
-        vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o
+        vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
+        vega20_reg_init.o
 
 # add DF block
 amdgpu-y += \
-        df_v1_7.o
+        df_v1_7.o \
+        df_v3_6.o
 
 # add GMC block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 03a2c0be0bf2..a59c07590cee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1401,6 +1401,8 @@ struct amdgpu_df_funcs {
                                                  bool enable);
         void (*get_clockgating_state)(struct amdgpu_device *adev,
                                       u32 *flags);
+        void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
+                                            bool enable);
 };
 /* Define the HW IP blocks will be used in driver , add more if necessary */
 enum amd_hw_ip_block_type {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index a0f48cb9b8f0..236915849cfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -322,3 +322,47 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 
         return ret;
 }
+
+union gfx_info {
+        struct  atom_gfx_info_v2_4 v24;
+};
+
+int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
+{
+        struct amdgpu_mode_info *mode_info = &adev->mode_info;
+        int index;
+        uint8_t frev, crev;
+        uint16_t data_offset;
+
+        index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                                            gfx_info);
+        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                   &frev, &crev, &data_offset)) {
+                union gfx_info *gfx_info = (union gfx_info *)
+                        (mode_info->atom_context->bios + data_offset);
+                switch (crev) {
+                case 4:
+                        adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se;
+                        adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh;
+                        adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se;
+                        adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se;
+                        adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs;
+                        adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
+                        adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
+                        adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
+                        adev->gfx.config.gs_prim_buffer_depth =
+                                le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
+                        adev->gfx.config.double_offchip_lds_buf =
+                                gfx_info->v24.gc_double_offchip_lds_buffer;
+                        adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
+                        adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
+                        adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
+                        adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
+                        return 0;
+                default:
+                        return -EINVAL;
+                }
+
+        }
+        return -EINVAL;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
index 7689c961c4ef..20f158fd3b76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
@@ -30,5 +30,6 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
+int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 5b3d3bf5b599..e950730f1933 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -400,6 +400,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
                         case CHIP_VEGA12:
                                 strcpy(fw_name, "amdgpu/vega12_smc.bin");
                                 break;
+                        case CHIP_VEGA20:
+                                strcpy(fw_name, "amdgpu/vega20_smc.bin");
+                                break;
                         default:
                                 DRM_ERROR("SMC firmware not supported\n");
                                 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index a8e531d604fa..c5bb36275e93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -173,9 +173,14 @@ static void amdgpu_ctx_do_release(struct kref *ref)
 
         ctx = container_of(ref, struct amdgpu_ctx, refcount);
 
-        for (i = 0; i < ctx->adev->num_rings; i++)
+        for (i = 0; i < ctx->adev->num_rings; i++) {
+
+                if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring)
+                        continue;
+
                 drm_sched_entity_fini(&ctx->adev->rings[i]->sched,
                         &ctx->rings[i].entity);
+        }
 
         amdgpu_ctx_fini(ref);
 }
@@ -452,12 +457,17 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
                 if (!ctx->adev)
                         return;
 
-                for (i = 0; i < ctx->adev->num_rings; i++)
+                for (i = 0; i < ctx->adev->num_rings; i++) {
+
+                        if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring)
+                                continue;
+
                         if (kref_read(&ctx->refcount) == 1)
                                 drm_sched_entity_do_release(&ctx->adev->rings[i]->sched,
                                                   &ctx->rings[i].entity);
                         else
                                 DRM_ERROR("ctx %p is still alive\n", ctx);
+                }
         }
 }
 
@@ -474,12 +484,17 @@ void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr)
                 if (!ctx->adev)
                         return;
 
-                for (i = 0; i < ctx->adev->num_rings; i++)
+                for (i = 0; i < ctx->adev->num_rings; i++) {
+
+                        if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring)
+                                continue;
+
                         if (kref_read(&ctx->refcount) == 1)
                                 drm_sched_entity_cleanup(&ctx->adev->rings[i]->sched,
                                         &ctx->rings[i].entity);
                         else
                                 DRM_ERROR("ctx %p is still alive\n", ctx);
+                }
         }
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9fb20a53d5b2..290e279abf0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -86,6 +86,7 @@ static const char *amdgpu_asic_name[] = {
         "VEGAM",
         "VEGA10",
         "VEGA12",
+        "VEGA20",
         "RAVEN",
         "LAST",
 };
@@ -1387,6 +1388,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
         case CHIP_KABINI:
         case CHIP_MULLINS:
 #endif
+        case CHIP_VEGA20:
         default:
                 return 0;
         case CHIP_VEGA10:
@@ -1521,6 +1523,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
 #endif
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
         case CHIP_RAVEN:
                 if (adev->asic_type == CHIP_RAVEN)
                         adev->family = AMDGPU_FAMILY_RV;
@@ -1715,6 +1718,7 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
                 /* skip CG for VCE/UVD, it's handled specially */
                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+                    adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
                     adev->ip_blocks[i].version->funcs->set_clockgating_state) {
                         /* enable clockgating to save power */
                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
@@ -1814,6 +1818,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
 
                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
+                        adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
                         adev->ip_blocks[i].version->funcs->set_clockgating_state) {
                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
@@ -2155,6 +2160,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
         case CHIP_FIJI:
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
         case CHIP_RAVEN:
 #endif
@@ -3172,7 +3178,6 @@ error:
 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
                               struct amdgpu_job *job, bool force)
 {
-        struct drm_atomic_state *state = NULL;
         int i, r, resched;
 
         if (!force && !amdgpu_device_ip_check_soft_reset(adev)) {
@@ -3195,10 +3200,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
         /* block TTM */
         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
 
-        /* store modesetting */
-        if (amdgpu_device_has_dc_support(adev))
-                state = drm_atomic_helper_suspend(adev->ddev);
-
         /* block all schedulers and reset given job's ring */
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
                 struct amdgpu_ring *ring = adev->rings[i];
@@ -3238,10 +3239,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
                 kthread_unpark(ring->sched.thread);
         }
 
-        if (amdgpu_device_has_dc_support(adev)) {
-                if (drm_atomic_helper_resume(adev->ddev, state))
-                        dev_info(adev->dev, "drm resume failed:%d\n", r);
-        } else {
+        if (!amdgpu_device_has_dc_support(adev)) {
                 drm_helper_resume_force_mode(adev->ddev);
         }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 739e7e09c8b0..b0bf2f24da48 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -560,6 +560,13 @@ static const struct pci_device_id pciidlist[] = {
         {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
         {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
         {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
+        /* Vega 20 */
+        {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
+        {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
+        {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
+        {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
+        {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
+        {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20|AMD_EXP_HW_SUPPORT},
         /* Raven */
         {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index d09fcab2398f..39ec6b8890a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -376,14 +376,14 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
         struct amdgpu_device *adev = ring->adev;
         uint64_t index;
 
-        if (ring != &adev->uvd.ring) {
+        if (ring != &adev->uvd.inst[ring->me].ring) {
                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
         } else {
                 /* put fence directly behind firmware */
                 index = ALIGN(adev->uvd.fw->size, 8);
-                ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
-                ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
+                ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
+                ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
         }
         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
         amdgpu_irq_get(adev, irq_src, irq_type);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index eb4785e51573..91517b166a3b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -286,7 +286,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
         struct drm_crtc *crtc;
         uint32_t ui32 = 0;
         uint64_t ui64 = 0;
-        int i, found;
+        int i, j, found;
         int ui32_size = sizeof(ui32);
 
         if (!info->return_size || !info->return_pointer)
@@ -348,7 +348,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         break;
                 case AMDGPU_HW_IP_UVD:
                         type = AMD_IP_BLOCK_TYPE_UVD;
-                        ring_mask = adev->uvd.ring.ready ? 1 : 0;
+                        for (i = 0; i < adev->uvd.num_uvd_inst; i++)
+                                ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i);
                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
                         ib_size_alignment = 16;
                         break;
@@ -361,8 +362,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         break;
                 case AMDGPU_HW_IP_UVD_ENC:
                         type = AMD_IP_BLOCK_TYPE_UVD;
-                        for (i = 0; i < adev->uvd.num_enc_rings; i++)
-                                ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
+                        for (i = 0; i < adev->uvd.num_uvd_inst; i++)
+                                for (j = 0; j < adev->uvd.num_enc_rings; j++)
+                                        ring_mask |=
+                                        ((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) <<
+                                        (j + i * adev->uvd.num_enc_rings));
                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
                         ib_size_alignment = 1;
                         break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c7d43e064fc7..9f1a5bd39ae8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -52,6 +52,7 @@ static int psp_sw_init(void *handle)
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 psp_v3_1_set_psp_funcs(psp);
                 break;
         case CHIP_RAVEN:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index 262c1267249e..8af16e81c7d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -66,6 +66,8 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
                                u32 ring,
                                struct amdgpu_ring **out_ring)
 {
+        u32 instance;
+
         switch (mapper->hw_ip) {
         case AMDGPU_HW_IP_GFX:
                 *out_ring = &adev->gfx.gfx_ring[ring];
@@ -77,13 +79,16 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
                 *out_ring = &adev->sdma.instance[ring].ring;
                 break;
         case AMDGPU_HW_IP_UVD:
-                *out_ring = &adev->uvd.ring;
+                instance = ring;
+                *out_ring = &adev->uvd.inst[instance].ring;
                 break;
         case AMDGPU_HW_IP_VCE:
                 *out_ring = &adev->vce.ring[ring];
                 break;
         case AMDGPU_HW_IP_UVD_ENC:
-                *out_ring = &adev->uvd.ring_enc[ring];
+                instance = ring / adev->uvd.num_enc_rings;
+                *out_ring =
+                &adev->uvd.inst[instance].ring_enc[ring%adev->uvd.num_enc_rings];
                 break;
         case AMDGPU_HW_IP_VCN_DEC:
                 *out_ring = &adev->vcn.ring_dec;
@@ -240,13 +245,14 @@ int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
                 ip_num_rings = adev->sdma.num_instances;
                 break;
         case AMDGPU_HW_IP_UVD:
-                ip_num_rings = 1;
+                ip_num_rings = adev->uvd.num_uvd_inst;
                 break;
         case AMDGPU_HW_IP_VCE:
                 ip_num_rings = adev->vce.num_rings;
                 break;
         case AMDGPU_HW_IP_UVD_ENC:
-                ip_num_rings = adev->uvd.num_enc_rings;
+                ip_num_rings =
+                        adev->uvd.num_enc_rings * adev->uvd.num_uvd_inst;
                 break;
         case AMDGPU_HW_IP_VCN_DEC:
                 ip_num_rings = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 49cad08b5c16..c6850b629d0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -362,6 +362,7 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
 
         dma_fence_put(ring->vmid_wait);
         ring->vmid_wait = NULL;
+        ring->me = 0;
 
         ring->adev->rings[ring->idx] = NULL;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 4f8dac2d36a5..1513124c5659 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -29,7 +29,7 @@
 #include <drm/drm_print.h>
 
 /* max number of rings */
-#define AMDGPU_MAX_RINGS                18
+#define AMDGPU_MAX_RINGS                21
 #define AMDGPU_MAX_GFX_RINGS            1
 #define AMDGPU_MAX_COMPUTE_RINGS        8
 #define AMDGPU_MAX_VCE_RINGS            3
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 69a2b25b3696..e93a0a237dc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -63,16 +63,44 @@ static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
 /*
  * Global memory.
  */
+
+/**
+ * amdgpu_ttm_mem_global_init - Initialize and acquire reference to
+ * memory object
+ *
+ * @ref: Object for initialization.
+ *
+ * This is called by drm_global_item_ref() when an object is being
+ * initialized.
+ */
 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
 {
         return ttm_mem_global_init(ref->object);
 }
 
+/**
+ * amdgpu_ttm_mem_global_release - Drop reference to a memory object
+ *
+ * @ref: Object being removed
+ *
+ * This is called by drm_global_item_unref() when an object is being
+ * released.
+ */
 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
 {
         ttm_mem_global_release(ref->object);
 }
 
+/**
+ * amdgpu_ttm_global_init - Initialize global TTM memory reference
+ *                                                      structures.
+ *
+ * @adev:       AMDGPU device for which the global structures need to be
+ *                      registered.
+ *
+ * This is called as part of the AMDGPU ttm init from amdgpu_ttm_init()
+ * during bring up.
+ */
 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
 {
         struct drm_global_reference *global_ref;
@@ -80,7 +108,9 @@ static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
         struct drm_sched_rq *rq;
         int r;
 
+        /* ensure reference is false in case init fails */
         adev->mman.mem_global_referenced = false;
+
         global_ref = &adev->mman.mem_global_ref;
         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
         global_ref->size = sizeof(struct ttm_mem_global);
@@ -146,6 +176,18 @@ static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
         return 0;
 }
 
+/**
+ * amdgpu_init_mem_type -       Initialize a memory manager for a specific
+ *                                                      type of memory request.
+ *
+ * @bdev:       The TTM BO device object (contains a reference to
+ *                      amdgpu_device)
+ * @type:       The type of memory requested
+ * @man:
+ *
+ * This is called by ttm_bo_init_mm() when a buffer object is being
+ * initialized.
+ */
 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
                                 struct ttm_mem_type_manager *man)
 {
@@ -161,6 +203,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
                 man->default_caching = TTM_PL_FLAG_CACHED;
                 break;
         case TTM_PL_TT:
+                /* GTT memory  */
                 man->func = &amdgpu_gtt_mgr_func;
                 man->gpu_offset = adev->gmc.gart_start;
                 man->available_caching = TTM_PL_MASK_CACHING;
@@ -193,6 +236,14 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
         return 0;
 }
 
+/**
+ * amdgpu_evict_flags - Compute placement flags
+ *
+ * @bo: The buffer object to evict
+ * @placement: Possible destination(s) for evicted BO
+ *
+ * Fill in placement data when ttm_bo_evict() is called
+ */
 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
                                 struct ttm_placement *placement)
 {
@@ -204,12 +255,14 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
         };
 
+        /* Don't handle scatter gather BOs */
         if (bo->type == ttm_bo_type_sg) {
                 placement->num_placement = 0;
                 placement->num_busy_placement = 0;
                 return;
         }
 
+        /* Object isn't an AMDGPU object so ignore */
         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
                 placement->placement = &placements;
                 placement->busy_placement = &placements;
@@ -217,10 +270,12 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
                 placement->num_busy_placement = 1;
                 return;
         }
+
         abo = ttm_to_amdgpu_bo(bo);
         switch (bo->mem.mem_type) {
         case TTM_PL_VRAM:
                 if (!adev->mman.buffer_funcs_enabled) {
+                        /* Move to system memory */
                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
                 } else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
@@ -238,6 +293,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
                         abo->placement.busy_placement = &abo->placements[1];
                         abo->placement.num_busy_placement = 1;
                 } else {
+                        /* Move to GTT memory */
                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
                 }
                 break;
@@ -248,6 +304,15 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
         *placement = abo->placement;
 }
 
+/**
+ * amdgpu_verify_access - Verify access for a mmap call
+ *
+ * @bo:         The buffer object to map
+ * @filp:       The file pointer from the process performing the mmap
+ *
+ * This is called by ttm_bo_mmap() to verify whether a process
+ * has the right to mmap a BO to their process space.
+ */
 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 {
         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
@@ -265,6 +330,15 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
                                           filp->private_data);
 }
 
+/**
+ * amdgpu_move_null - Register memory for a buffer object
+ *
+ * @bo:                 The bo to assign the memory to
+ * @new_mem:    The memory to be assigned.
+ *
+ * Assign the memory from new_mem to the memory of the buffer object
+ * bo.
+ */
 static void amdgpu_move_null(struct ttm_buffer_object *bo,
                              struct ttm_mem_reg *new_mem)
 {
@@ -275,6 +349,10 @@ static void amdgpu_move_null(struct ttm_buffer_object *bo,
         new_mem->mm_node = NULL;
 }
 
+/**
+ * amdgpu_mm_node_addr -        Compute the GPU relative offset of a GTT
+ *                                                      buffer.
+ */
 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
                                     struct drm_mm_node *mm_node,
                                     struct ttm_mem_reg *mem)
@@ -289,9 +367,10 @@ static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 }
 
 /**
- * amdgpu_find_mm_node - Helper function finds the drm_mm_node
- *  corresponding to @offset. It also modifies the offset to be
- *  within the drm_mm_node returned
+ * amdgpu_find_mm_node -        Helper function finds the drm_mm_node
+ *                                              corresponding to @offset. It also modifies
+ *                                                      the offset to be within the drm_mm_node
+ *                                                      returned
  */
 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
                                                unsigned long *offset)
@@ -430,7 +509,12 @@ error:
         return r;
 }
 
-
+/**
+ * amdgpu_move_blit - Copy an entire buffer to another buffer
+ *
+ * This is a helper called by amdgpu_bo_move() and
+ * amdgpu_move_vram_ram() to help move buffers to and from VRAM.
+ */
 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
                             bool evict, bool no_wait_gpu,
                             struct ttm_mem_reg *new_mem,
@@ -465,6 +549,11 @@ error:
         return r;
 }
 
+/**
+ * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
+ *
+ * Called by amdgpu_bo_move().
+ */
 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
                                 struct ttm_operation_ctx *ctx,
                                 struct ttm_mem_reg *new_mem)
@@ -477,6 +566,8 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
         int r;
 
         adev = amdgpu_ttm_adev(bo->bdev);
+
+        /* create space/pages for new_mem in GTT space */
         tmp_mem = *new_mem;
         tmp_mem.mm_node = NULL;
         placement.num_placement = 1;
@@ -491,25 +582,36 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
                 return r;
         }
 
+        /* set caching flags */
         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
         if (unlikely(r)) {
                 goto out_cleanup;
         }
 
+        /* Bind the memory to the GTT space */
         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
         if (unlikely(r)) {
                 goto out_cleanup;
         }
+
+        /* blit VRAM to GTT */
         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, &tmp_mem, old_mem);
         if (unlikely(r)) {
                 goto out_cleanup;
         }
+
+        /* move BO (in tmp_mem) to new_mem */
         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 out_cleanup:
         ttm_bo_mem_put(bo, &tmp_mem);
         return r;
 }
 
+/**
+ * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
+ *
+ * Called by amdgpu_bo_move().
+ */
 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
                                 struct ttm_operation_ctx *ctx,
                                 struct ttm_mem_reg *new_mem)
@@ -522,6 +624,8 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
         int r;
 
         adev = amdgpu_ttm_adev(bo->bdev);
+
+        /* make space in GTT for old_mem buffer */
         tmp_mem = *new_mem;
         tmp_mem.mm_node = NULL;
         placement.num_placement = 1;
@@ -535,10 +639,14 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
         if (unlikely(r)) {
                 return r;
         }
+
+        /* move/bind old memory to GTT space */
         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
         if (unlikely(r)) {
                 goto out_cleanup;
         }
+
+        /* copy to VRAM */
         r = amdgpu_move_blit(bo, true, ctx->no_wait_gpu, new_mem, old_mem);
         if (unlikely(r)) {
                 goto out_cleanup;
@@ -548,6 +656,11 @@ out_cleanup:
         return r;
 }
 
+/**
+ * amdgpu_bo_move - Move a buffer object to a new memory location
+ *
+ * Called by ttm_bo_handle_move_mem()
+ */
 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
                           struct ttm_operation_ctx *ctx,
                           struct ttm_mem_reg *new_mem)
@@ -613,6 +726,11 @@ memcpy:
         return 0;
 }
 
+/**
+ * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
+ *
+ * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
+ */
 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 {
         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
@@ -690,6 +808,14 @@ struct amdgpu_ttm_tt {
         uint32_t                last_set_pages;
 };
 
+/**
+ * amdgpu_ttm_tt_get_user_pages -       Pin pages of memory pointed to
+ *                                                                      by a USERPTR pointer to memory
+ *
+ * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos().
+ * This provides a wrapper around the get_user_pages() call to provide
+ * device accessible pages that back user memory.
+ */
 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 {
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -719,6 +845,7 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
                 }
         }
 
+        /* loop enough times using contiguous pages of memory */
         do {
                 unsigned num_pages = ttm->num_pages - pinned;
                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
@@ -757,6 +884,14 @@ release_pages:
         return r;
 }
 
+/**
+ * amdgpu_ttm_tt_set_user_pages -       Copy pages in, putting old pages
+ *                                                                      as necessary.
+ *
+ * Called by amdgpu_cs_list_validate().  This creates the page list
+ * that backs user memory and will ultimately be mapped into the device
+ * address space.
+ */
 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 {
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -771,6 +906,11 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
         }
 }
 
+/**
+ * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty
+ *
+ * Called while unpinning userptr pages
+ */
 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 {
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -789,7 +929,12 @@ void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
         }
 }
 
-/* prepare the sg table with the user pages */
+/**
+ * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the
+ *                                                              user pages
+ *
+ * Called by amdgpu_ttm_backend_bind()
+ **/
 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 {
         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
@@ -801,17 +946,20 @@ static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
         enum dma_data_direction direction = write ?
                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 
+        /* Allocate an SG array and squash pages into it */
         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
                                       ttm->num_pages << PAGE_SHIFT,
                                       GFP_KERNEL);
         if (r)
                 goto release_sg;
 
+        /* Map SG to device */
         r = -ENOMEM;
         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
         if (nents != ttm->sg->nents)
                 goto release_sg;
 
+        /* convert SG to linear array of pages and dma addresses */
         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
                                          gtt->ttm.dma_address, ttm->num_pages);
 
@@ -822,6 +970,9 @@ release_sg:
         return r;
 }
 
+/**
+ * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
+ */
 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 {
         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
@@ -835,9 +986,10 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
         if (!ttm->sg->sgl)
                 return;
 
-        /* free the sg table and pages again */
+        /* unmap the pages mapped to the device */
         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 
+        /* mark the pages as dirty */
         amdgpu_ttm_tt_mark_user_pages(ttm);
 
         sg_free_table(ttm->sg);
@@ -882,6 +1034,12 @@ gart_bind_fail:
         return r;
 }
 
+/**
+ * amdgpu_ttm_backend_bind - Bind GTT memory
+ *
+ * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
+ * This handles binding GTT memory to the device address space.
+ */
 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
                                    struct ttm_mem_reg *bo_mem)
 {
@@ -912,7 +1070,10 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
                 return 0;
         }
 
+        /* compute PTE flags relevant to this BO memory */
         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
+
+        /* bind pages into GART page tables */
         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
                 ttm->pages, gtt->ttm.dma_address, flags);
@@ -923,6 +1084,9 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
         return r;
 }
 
+/**
+ * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
+ */
 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 {
         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
@@ -938,6 +1102,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
             amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
                 return 0;
 
+        /* allocate GTT space */
         tmp = bo->mem;
         tmp.mm_node = NULL;
         placement.num_placement = 1;
@@ -953,7 +1118,10 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
         if (unlikely(r))
                 return r;
 
+        /* compute PTE flags for this buffer object */
         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
+
+        /* Bind pages */
         gtt->offset = (u64)tmp.start << PAGE_SHIFT;
         r = amdgpu_ttm_gart_bind(adev, bo, flags);
         if (unlikely(r)) {
@@ -969,6 +1137,12 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
         return 0;
 }
 
+/**
+ * amdgpu_ttm_recover_gart - Rebind GTT pages
+ *
+ * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
+ * rebind GTT pages during a GPU reset.
+ */
 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 {
         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
@@ -984,12 +1158,19 @@ int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
         return r;
 }
 
+/**
+ * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
+ *
+ * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
+ * ttm_tt_destroy().
+ */
 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 {
         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
         int r;
 
+        /* if the pages have userptr pinning then clear that first */
         if (gtt->userptr)
                 amdgpu_ttm_tt_unpin_userptr(ttm);
 
@@ -1021,6 +1202,13 @@ static struct ttm_backend_func amdgpu_backend_func = {
         .destroy = &amdgpu_ttm_backend_destroy,
 };
 
+/**
+ * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
+ *
+ * @bo: The buffer object to create a GTT ttm_tt object around
+ *
+ * Called by ttm_tt_create().
+ */
 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
                                            uint32_t page_flags)
 {
@@ -1034,6 +1222,8 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
                 return NULL;
         }
         gtt->ttm.ttm.func = &amdgpu_backend_func;
+
+        /* allocate space for the uninitialized page entries */
         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
                 kfree(gtt);
                 return NULL;
@@ -1041,6 +1231,12 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
         return &gtt->ttm.ttm;
 }
 
+/**
+ * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
+ *
+ * Map the pages of a ttm_tt object to an address space visible
+ * to the underlying device.
+ */
 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
                         struct ttm_operation_ctx *ctx)
 {
@@ -1048,6 +1244,7 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 
+        /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
         if (gtt && gtt->userptr) {
                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
                 if (!ttm->sg)
@@ -1072,9 +1269,17 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
         }
 #endif
 
+        /* fall back to generic helper to populate the page array
+         * and map them to the device */
         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
 }
 
+/**
+ * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
+ *
+ * Unmaps pages of a ttm_tt object from the device address space and
+ * unpopulates the page array backing it.
+ */
 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 {
         struct amdgpu_device *adev;
@@ -1100,9 +1305,21 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
         }
 #endif
 
+        /* fall back to generic helper to unmap and unpopulate array */
         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
 }
 
+/**
+ * amdgpu_ttm_tt_set_userptr -  Initialize userptr GTT ttm_tt
+ *                                                              for the current task
+ *
+ * @ttm: The ttm_tt object to bind this userptr object to
+ * @addr:  The address in the current tasks VM space to use
+ * @flags: Requirements of userptr object.
+ *
+ * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
+ * to current task
+ */
 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
                               uint32_t flags)
 {
@@ -1127,6 +1344,9 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
         return 0;
 }
 
+/**
+ * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
+ */
 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 {
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -1140,6 +1360,12 @@ struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
         return gtt->usertask->mm;
 }
 
+/**
+ * amdgpu_ttm_tt_affect_userptr -       Determine if a ttm_tt object lays
+ *                                                                      inside an address range for the
+ *                                                                      current task.
+ *
+ */
 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
                                   unsigned long end)
 {
@@ -1150,10 +1376,16 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
         if (gtt == NULL || !gtt->userptr)
                 return false;
 
+        /* Return false if no part of the ttm_tt object lies within
+         * the range
+         */
         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
         if (gtt->userptr > end || gtt->userptr + size <= start)
                 return false;
 
+        /* Search the lists of tasks that hold this mapping and see
+         * if current is one of them.  If it is return false.
+         */
         spin_lock(&gtt->guptasklock);
         list_for_each_entry(entry, &gtt->guptasks, list) {
                 if (entry->task == current) {
@@ -1168,6 +1400,10 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
         return true;
 }
 
+/**
+ * amdgpu_ttm_tt_userptr_invalidated -  Has the ttm_tt object been
+ *                                                                              invalidated?
+ */
 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
                                        int *last_invalidated)
 {
@@ -1178,6 +1414,12 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
         return prev_invalidated != *last_invalidated;
 }
 
+/**
+ * amdgpu_ttm_tt_userptr_needs_pages -  Have the pages backing this
+ *                                                                              ttm_tt object been invalidated
+ *                                                                              since the last time they've
+ *                                                                              been set?
+ */
 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
 {
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -1188,6 +1430,9 @@ bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
 }
 
+/**
+ * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
+ */
 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 {
         struct amdgpu_ttm_tt *gtt = (void *)ttm;
@@ -1198,6 +1443,12 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 }
 
+/**
+ * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
+ *
+ * @ttm: The ttm_tt object to compute the flags for
+ * @mem: The memory registry backing this ttm_tt object
+ */
 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
                                  struct ttm_mem_reg *mem)
 {
@@ -1222,6 +1473,16 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
         return flags;
 }
 
+/**
+ * amdgpu_ttm_bo_eviction_valuable -    Check to see if we can evict
+ *                                                                              a buffer object.
+ *
+ * Return true if eviction is sensible.  Called by
+ * ttm_mem_evict_first() on behalf of ttm_bo_mem_force_space()
+ * which tries to evict buffer objects until it can find space
+ * for a new object and by ttm_bo_force_list_clean() which is
+ * used to clean out a memory space.
+ */
 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
                                             const struct ttm_place *place)
 {
@@ -1268,6 +1529,19 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
         return ttm_bo_eviction_valuable(bo, place);
 }
 
+/**
+ * amdgpu_ttm_access_memory -   Read or Write memory that backs a
+ *                                                              buffer object.
+ *
+ * @bo:  The buffer object to read/write
+ * @offset:  Offset into buffer object
+ * @buf:  Secondary buffer to write/read from
+ * @len: Length in bytes of access
+ * @write:  true if writing
+ *
+ * This is used to access VRAM that backs a buffer object via MMIO
+ * access for debugging purposes.
+ */
 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
                                     unsigned long offset,
                                     void *buf, int len, int write)
@@ -1444,13 +1718,22 @@ error_create:
         adev->fw_vram_usage.reserved_bo = NULL;
         return r;
 }
-
+/**
+ * amdgpu_ttm_init -    Init the memory management (ttm) as well as
+ *                                              various gtt/vram related fields.
+ *
+ * This initializes all of the memory space pools that the TTM layer
+ * will need such as the GTT space (system memory mapped to the device),
+ * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
+ * can be mapped per VMID.
+ */
 int amdgpu_ttm_init(struct amdgpu_device *adev)
 {
         uint64_t gtt_size;
         int r;
         u64 vis_vram_limit;
 
+        /* initialize global references for vram/gtt */
         r = amdgpu_ttm_global_init(adev);
         if (r) {
                 return r;
@@ -1471,6 +1754,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
         /* We opt to avoid OOM on system pages allocations */
         adev->mman.bdev.no_retry = true;
 
+        /* Initialize VRAM pool with all of VRAM divided into pages */
         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
         if (r) {
@@ -1500,6 +1784,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
                 return r;
         }
 
+        /* allocate memory as required for VGA
+         * This is used for VGA emulation and pre-OS scanout buffers to
+         * avoid display artifacts while transitioning between pre-OS
+         * and driver.  */
         if (adev->gmc.stolen_size) {
                 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
                                             AMDGPU_GEM_DOMAIN_VRAM,
@@ -1511,6 +1799,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
 
+        /* Compute GTT size, either bsaed on 3/4th the size of RAM size
+         * or whatever the user passed on module init */
         if (amdgpu_gtt_size == -1) {
                 struct sysinfo si;
 
@@ -1521,6 +1811,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
         }
         else
                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+
+        /* Initialize GTT memory pool */
         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
         if (r) {
                 DRM_ERROR("Failed initializing GTT heap.\n");
@@ -1529,6 +1821,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
                  (unsigned)(gtt_size / (1024 * 1024)));
 
+        /* Initialize various on-chip memory pools */
         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
@@ -1568,6 +1861,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
                 }
         }
 
+        /* Register debugfs entries for amdgpu_ttm */
         r = amdgpu_ttm_debugfs_init(adev);
         if (r) {
                 DRM_ERROR("Failed to init debugfs\n");
@@ -1576,11 +1870,19 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
         return 0;
 }
 
+/**
+ * amdgpu_ttm_late_init -       Handle any late initialization for
+ *                                                      amdgpu_ttm
+ */
 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
 {
+        /* return the VGA stolen memory (if any) back to VRAM */
         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
 }
 
+/**
+ * amdgpu_ttm_fini - De-initialize the TTM memory pools
+ */
 void amdgpu_ttm_fini(struct amdgpu_device *adev)
 {
         if (!adev->mman.initialized)
@@ -1908,6 +2210,11 @@ static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
 #endif
 };
 
+/**
+ * amdgpu_ttm_vram_read - Linear read access to VRAM
+ *
+ * Accesses VRAM via MMIO for debugging purposes.
+ */
 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
                                     size_t size, loff_t *pos)
 {
@@ -1947,6 +2254,11 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
         return result;
 }
 
+/**
+ * amdgpu_ttm_vram_write - Linear write access to VRAM
+ *
+ * Accesses VRAM via MMIO for debugging purposes.
+ */
 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
                                     size_t size, loff_t *pos)
 {
@@ -1995,6 +2307,9 @@ static const struct file_operations amdgpu_ttm_vram_fops = {
 
 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
 
+/**
+ * amdgpu_ttm_gtt_read - Linear read access to GTT memory
+ */
 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
                                    size_t size, loff_t *pos)
 {
@@ -2042,6 +2357,13 @@ static const struct file_operations amdgpu_ttm_gtt_fops = {
 
 #endif
 
+/**
+ * amdgpu_iomem_read - Virtual read access to GPU mapped memory
+ *
+ * This function is used to read memory that has been mapped to the
+ * GPU and the known addresses are not physical addresses but instead
+ * bus addresses (e.g., what you'd put in an IB or ring buffer).
+ */
 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
                                  size_t size, loff_t *pos)
 {
@@ -2050,6 +2372,7 @@ static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
         ssize_t result = 0;
         int r;
 
+        /* retrieve the IOMMU domain if any for this device */
         dom = iommu_get_domain_for_dev(adev->dev);
 
         while (size) {
@@ -2062,6 +2385,10 @@ static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
 
                 bytes = bytes < size ? bytes : size;
 
+                /* Translate the bus address to a physical address.  If
+                 * the domain is NULL it means there is no IOMMU active
+                 * and the address translation is the identity
+                 */
                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
 
                 pfn = addr >> PAGE_SHIFT;
@@ -2086,6 +2413,13 @@ static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
         return result;
 }
 
+/**
+ * amdgpu_iomem_write - Virtual write access to GPU mapped memory
+ *
+ * This function is used to write memory that has been mapped to the
+ * GPU and the known addresses are not physical addresses but instead
+ * bus addresses (e.g., what you'd put in an IB or ring buffer).
+ */
 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
                                  size_t size, loff_t *pos)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 75592bd04d6a..f55f72a37ca8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -307,6 +307,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
                         return AMDGPU_FW_LOAD_DIRECT;
                 else
                         return AMDGPU_FW_LOAD_PSP;
+        case CHIP_VEGA20:
+                return AMDGPU_FW_LOAD_DIRECT;
         default:
                 DRM_ERROR("Unknown firmware load type\n");
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index de4d77af02ae..bcf68f80bbf0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -70,12 +70,14 @@
 
 #define FIRMWARE_VEGA10         "amdgpu/vega10_uvd.bin"
 #define FIRMWARE_VEGA12         "amdgpu/vega12_uvd.bin"
+#define FIRMWARE_VEGA20         "amdgpu/vega20_uvd.bin"
 
-#define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00)
-#define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00)
-#define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00)
-#define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00)
-#define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00)
+/* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */
+#define UVD_GPCOM_VCPU_CMD              0x03c3
+#define UVD_GPCOM_VCPU_DATA0    0x03c4
+#define UVD_GPCOM_VCPU_DATA1    0x03c5
+#define UVD_NO_OP                               0x03ff
+#define UVD_BASE_SI                             0x3800
 
 /**
  * amdgpu_uvd_cs_ctx - Command submission parser context
@@ -114,6 +116,7 @@ MODULE_FIRMWARE(FIRMWARE_VEGAM);
 
 MODULE_FIRMWARE(FIRMWARE_VEGA10);
 MODULE_FIRMWARE(FIRMWARE_VEGA12);
+MODULE_FIRMWARE(FIRMWARE_VEGA20);
 
 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
 
@@ -125,9 +128,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
         const char *fw_name;
         const struct common_firmware_header *hdr;
         unsigned version_major, version_minor, family_id;
-        int i, r;
+        int i, j, r;
 
-        INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
+        INIT_DELAYED_WORK(&adev->uvd.inst->idle_work, amdgpu_uvd_idle_work_handler);
 
         switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
@@ -177,6 +180,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
         case CHIP_VEGAM:
                 fw_name = FIRMWARE_VEGAM;
                 break;
+        case CHIP_VEGA20:
+                fw_name = FIRMWARE_VEGA20;
+                break;
         default:
                 return -EINVAL;
         }
@@ -231,28 +237,30 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
                 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 
-        r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
-                                    AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo,
-                                    &adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
-        if (r) {
-                dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
-                return r;
-        }
+        for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 
-        ring = &adev->uvd.ring;
-        rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-        r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity,
-                                  rq, NULL);
-        if (r != 0) {
-                DRM_ERROR("Failed setting up UVD run queue.\n");
-                return r;
-        }
+                r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
+                                            AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
+                                            &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
+                if (r) {
+                        dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
+                        return r;
+                }
 
-        for (i = 0; i < adev->uvd.max_handles; ++i) {
-                atomic_set(&adev->uvd.handles[i], 0);
-                adev->uvd.filp[i] = NULL;
-        }
+                ring = &adev->uvd.inst[j].ring;
+                rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+                r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst[j].entity,
+                                          rq, NULL);
+                if (r != 0) {
+                        DRM_ERROR("Failed setting up UVD(%d) run queue.\n", j);
+                        return r;
+                }
 
+                for (i = 0; i < adev->uvd.max_handles; ++i) {
+                        atomic_set(&adev->uvd.inst[j].handles[i], 0);
+                        adev->uvd.inst[j].filp[i] = NULL;
+                }
+        }
         /* from uvd v5.0 HW addressing capacity increased to 64 bits */
         if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
                 adev->uvd.address_64_bit = true;
@@ -279,20 +287,22 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 
 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 {
-        int i;
-        kfree(adev->uvd.saved_bo);
+        int i, j;
 
-        drm_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
+        for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+                kfree(adev->uvd.inst[j].saved_bo);
 
-        amdgpu_bo_free_kernel(&adev->uvd.vcpu_bo,
-                              &adev->uvd.gpu_addr,
-                              (void **)&adev->uvd.cpu_addr);
+                drm_sched_entity_fini(&adev->uvd.inst[j].ring.sched, &adev->uvd.inst[j].entity);
 
-        amdgpu_ring_fini(&adev->uvd.ring);
+                amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
+                                      &adev->uvd.inst[j].gpu_addr,
+                                      (void **)&adev->uvd.inst[j].cpu_addr);
 
-        for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
-                amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
+                amdgpu_ring_fini(&adev->uvd.inst[j].ring);
 
+                for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
+                        amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
+        }
         release_firmware(adev->uvd.fw);
 
         return 0;
@@ -302,32 +312,33 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 {
         unsigned size;
         void *ptr;
-        int i;
-
-        if (adev->uvd.vcpu_bo == NULL)
-                return 0;
+        int i, j;
 
-        cancel_delayed_work_sync(&adev->uvd.idle_work);
+        for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+                if (adev->uvd.inst[j].vcpu_bo == NULL)
+                        continue;
 
-        /* only valid for physical mode */
-        if (adev->asic_type < CHIP_POLARIS10) {
-                for (i = 0; i < adev->uvd.max_handles; ++i)
-                        if (atomic_read(&adev->uvd.handles[i]))
-                                break;
+                cancel_delayed_work_sync(&adev->uvd.inst[j].idle_work);
 
-                if (i == adev->uvd.max_handles)
-                        return 0;
-        }
+                /* only valid for physical mode */
+                if (adev->asic_type < CHIP_POLARIS10) {
+                        for (i = 0; i < adev->uvd.max_handles; ++i)
+                                if (atomic_read(&adev->uvd.inst[j].handles[i]))
+                                        break;
 
-        size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-        ptr = adev->uvd.cpu_addr;
+                        if (i == adev->uvd.max_handles)
+                                continue;
+                }
 
-        adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
-        if (!adev->uvd.saved_bo)
-                return -ENOMEM;
+                size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo);
+                ptr = adev->uvd.inst[j].cpu_addr;
 
-        memcpy_fromio(adev->uvd.saved_bo, ptr, size);
+                adev->uvd.inst[j].saved_bo = kmalloc(size, GFP_KERNEL);
+                if (!adev->uvd.inst[j].saved_bo)
+                        return -ENOMEM;
 
+                memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size);
+        }
         return 0;
 }
 
@@ -335,59 +346,65 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
 {
         unsigned size;
         void *ptr;
+        int i;
 
-        if (adev->uvd.vcpu_bo == NULL)
-                return -EINVAL;
+        for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+                if (adev->uvd.inst[i].vcpu_bo == NULL)
+                        return -EINVAL;
 
-        size = amdgpu_bo_size(adev->uvd.vcpu_bo);
-        ptr = adev->uvd.cpu_addr;
+                size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo);
+                ptr = adev->uvd.inst[i].cpu_addr;
 
-        if (adev->uvd.saved_bo != NULL) {
-                memcpy_toio(ptr, adev->uvd.saved_bo, size);
-                kfree(adev->uvd.saved_bo);
-                adev->uvd.saved_bo = NULL;
-        } else {
-                const struct common_firmware_header *hdr;
-                unsigned offset;
-
-                hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
-                if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
-                        offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
-                        memcpy_toio(adev->uvd.cpu_addr, adev->uvd.fw->data + offset,
-                                    le32_to_cpu(hdr->ucode_size_bytes));
-                        size -= le32_to_cpu(hdr->ucode_size_bytes);
-                        ptr += le32_to_cpu(hdr->ucode_size_bytes);
+                if (adev->uvd.inst[i].saved_bo != NULL) {
+                        memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size);
+                        kfree(adev->uvd.inst[i].saved_bo);
+                        adev->uvd.inst[i].saved_bo = NULL;
+                } else {
+                        const struct common_firmware_header *hdr;
+                        unsigned offset;
+
+                        hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
+                        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+                                offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
+                                memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset,
+                                            le32_to_cpu(hdr->ucode_size_bytes));
+                                size -= le32_to_cpu(hdr->ucode_size_bytes);
+                                ptr += le32_to_cpu(hdr->ucode_size_bytes);
+                        }
+                        memset_io(ptr, 0, size);
+                        /* to restore uvd fence seq */
+                        amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring);
                 }
-                memset_io(ptr, 0, size);
-                /* to restore uvd fence seq */
-                amdgpu_fence_driver_force_completion(&adev->uvd.ring);
         }
-
         return 0;
 }
 
 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
 {
-        struct amdgpu_ring *ring = &adev->uvd.ring;
-        int i, r;
+        struct amdgpu_ring *ring;
+        int i, j, r;
 
-        for (i = 0; i < adev->uvd.max_handles; ++i) {
-                uint32_t handle = atomic_read(&adev->uvd.handles[i]);
-                if (handle != 0 && adev->uvd.filp[i] == filp) {
-                        struct dma_fence *fence;
-
-                        r = amdgpu_uvd_get_destroy_msg(ring, handle,
-                                                       false, &fence);
-                        if (r) {
-                                DRM_ERROR("Error destroying UVD (%d)!\n", r);
-                                continue;
-                        }
+        for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+                ring = &adev->uvd.inst[j].ring;
+
+                for (i = 0; i < adev->uvd.max_handles; ++i) {
+                        uint32_t handle = atomic_read(&adev->uvd.inst[j].handles[i]);
+                        if (handle != 0 && adev->uvd.inst[j].filp[i] == filp) {
+                                struct dma_fence *fence;
+
+                                r = amdgpu_uvd_get_destroy_msg(ring, handle,
+                                                               false, &fence);
+                                if (r) {
+                                        DRM_ERROR("Error destroying UVD(%d) %d!\n", j, r);
+                                        continue;
+                                }
 
-                        dma_fence_wait(fence, false);
-                        dma_fence_put(fence);
+                                dma_fence_wait(fence, false);
+                                dma_fence_put(fence);
 
-                        adev->uvd.filp[i] = NULL;
-                        atomic_set(&adev->uvd.handles[i], 0);
+                                adev->uvd.inst[j].filp[i] = NULL;
+                                atomic_set(&adev->uvd.inst[j].handles[i], 0);
+                        }
                 }
         }
 }
@@ -662,15 +679,16 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
         void *ptr;
         long r;
         int i;
+        uint32_t ip_instance = ctx->parser->job->ring->me;
 
         if (offset & 0x3F) {
-                DRM_ERROR("UVD messages must be 64 byte aligned!\n");
+                DRM_ERROR("UVD(%d) messages must be 64 byte aligned!\n", ip_instance);
                 return -EINVAL;
         }
 
         r = amdgpu_bo_kmap(bo, &ptr);
         if (r) {
-                DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
+                DRM_ERROR("Failed mapping the UVD(%d) message (%ld)!\n", ip_instance, r);
                 return r;
         }
 
@@ -680,7 +698,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
         handle = msg[2];
 
         if (handle == 0) {
-                DRM_ERROR("Invalid UVD handle!\n");
+                DRM_ERROR("Invalid UVD(%d) handle!\n", ip_instance);
                 return -EINVAL;
         }
 
@@ -691,18 +709,18 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 
                 /* try to alloc a new handle */
                 for (i = 0; i < adev->uvd.max_handles; ++i) {
-                        if (atomic_read(&adev->uvd.handles[i]) == handle) {
-                                DRM_ERROR("Handle 0x%x already in use!\n", handle);
+                        if (atomic_read(&adev->uvd.inst[ip_instance].handles[i]) == handle) {
+                                DRM_ERROR("(%d)Handle 0x%x already in use!\n", ip_instance, handle);
                                 return -EINVAL;
                         }
 
-                        if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
-                                adev->uvd.filp[i] = ctx->parser->filp;
+                        if (!atomic_cmpxchg(&adev->uvd.inst[ip_instance].handles[i], 0, handle)) {
+                                adev->uvd.inst[ip_instance].filp[i] = ctx->parser->filp;
                                 return 0;
                         }
                 }
 
-                DRM_ERROR("No more free UVD handles!\n");
+                DRM_ERROR("No more free UVD(%d) handles!\n", ip_instance);
                 return -ENOSPC;
 
         case 1:
@@ -714,27 +732,27 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
 
                 /* validate the handle */
                 for (i = 0; i < adev->uvd.max_handles; ++i) {
-                        if (atomic_read(&adev->uvd.handles[i]) == handle) {
-                                if (adev->uvd.filp[i] != ctx->parser->filp) {
-                                        DRM_ERROR("UVD handle collision detected!\n");
+                        if (atomic_read(&adev->uvd.inst[ip_instance].handles[i]) == handle) {
+                                if (adev->uvd.inst[ip_instance].filp[i] != ctx->parser->filp) {
+                                        DRM_ERROR("UVD(%d) handle collision detected!\n", ip_instance);
                                         return -EINVAL;
                                 }
                                 return 0;
                         }
                 }
 
-                DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
+                DRM_ERROR("Invalid UVD(%d) handle 0x%x!\n", ip_instance, handle);
                 return -ENOENT;
 
         case 2:
                 /* it's a destroy msg, free the handle */
                 for (i = 0; i < adev->uvd.max_handles; ++i)
-                        atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
+                        atomic_cmpxchg(&adev->uvd.inst[ip_instance].handles[i], handle, 0);
                 amdgpu_bo_kunmap(bo);
                 return 0;
 
         default:
-                DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
+                DRM_ERROR("Illegal UVD(%d) message type (%d)!\n", ip_instance, msg_type);
                 return -EINVAL;
         }
         BUG();
@@ -805,7 +823,7 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
                 }
 
                 if ((cmd == 0 || cmd == 0x3) &&
-                    (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
+                    (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) {
                         DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
                                   start, end);
                         return -EINVAL;
@@ -973,6 +991,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
         uint64_t addr;
         long r;
         int i;
+        unsigned offset_idx = 0;
+        unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
 
         amdgpu_bo_kunmap(bo);
         amdgpu_bo_unpin(bo);
@@ -992,17 +1012,16 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
                 goto err;
 
         if (adev->asic_type >= CHIP_VEGA10) {
-                data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0);
-                data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0);
-                data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0);
-                data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0);
-        } else {
-                data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
-                data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
-                data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
-                data[3] = PACKET0(mmUVD_NO_OP, 0);
+                offset_idx = 1 + ring->me;
+                offset[1] = adev->reg_offset[UVD_HWIP][0][1];
+                offset[2] = adev->reg_offset[UVD_HWIP][1][1];
         }
 
+        data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
+        data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
+        data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
+        data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
+
         ib = &job->ibs[0];
         addr = amdgpu_bo_gpu_offset(bo);
         ib->ptr[0] = data[0];
@@ -1038,7 +1057,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
                 if (r)
                         goto err_free;
 
-                r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
+                r = amdgpu_job_submit(job, ring, &adev->uvd.inst[ring->me].entity,
                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
                 if (r)
                         goto err_free;
@@ -1126,8 +1145,15 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
 {
         struct amdgpu_device *adev =
-                container_of(work, struct amdgpu_device, uvd.idle_work.work);
-        unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
+                container_of(work, struct amdgpu_device, uvd.inst->idle_work.work);
+        unsigned fences = 0, i, j;
+
+        for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+                fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring);
+                for (j = 0; j < adev->uvd.num_enc_rings; ++j) {
+                        fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]);
+                }
+        }
 
         if (fences == 0) {
                 if (adev->pm.dpm_enabled) {
@@ -1141,7 +1167,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
                                                                AMD_CG_STATE_GATE);
                 }
         } else {
-                schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
+                schedule_delayed_work(&adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
         }
 }
 
@@ -1153,7 +1179,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
         if (amdgpu_sriov_vf(adev))
                 return;
 
-        set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
+        set_clocks = !cancel_delayed_work_sync(&adev->uvd.inst->idle_work);
         if (set_clocks) {
                 if (adev->pm.dpm_enabled) {
                         amdgpu_dpm_enable_uvd(adev, true);
@@ -1170,7 +1196,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
 {
         if (!amdgpu_sriov_vf(ring->adev))
-                schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
+                schedule_delayed_work(&ring->adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
 }
 
 /**
@@ -1184,27 +1210,28 @@ int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 {
         struct dma_fence *fence;
         long r;
+        uint32_t ip_instance = ring->me;
 
         r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
         if (r) {
-                DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
+                DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ip_instance, r);
                 goto error;
         }
 
         r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
         if (r) {
-                DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
+                DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ip_instance, r);
                 goto error;
         }
 
         r = dma_fence_wait_timeout(fence, false, timeout);
         if (r == 0) {
-                DRM_ERROR("amdgpu: IB test timed out.\n");
+                DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ip_instance);
                 r = -ETIMEDOUT;
         } else if (r < 0) {
-                DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+                DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ip_instance, r);
         } else {
-                DRM_DEBUG("ib test on ring %d succeeded\n",  ring->idx);
+                DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ip_instance, ring->idx);
                 r = 0;
         }
 
@@ -1232,7 +1259,7 @@ uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev)
                  * necessarily linear. So we need to count
                  * all non-zero handles.
                  */
-                if (atomic_read(&adev->uvd.handles[i]))
+                if (atomic_read(&adev->uvd.inst->handles[i]))
                         used_handles++;
         }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index 32ea20b99e53..b1579fba134c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -31,30 +31,37 @@
 #define AMDGPU_UVD_SESSION_SIZE         (50*1024)
 #define AMDGPU_UVD_FIRMWARE_OFFSET      256
 
+#define AMDGPU_MAX_UVD_INSTANCES                        2
+
 #define AMDGPU_UVD_FIRMWARE_SIZE(adev)    \
         (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
                                8) - AMDGPU_UVD_FIRMWARE_OFFSET)
 
-struct amdgpu_uvd {
+struct amdgpu_uvd_inst {
         struct amdgpu_bo        *vcpu_bo;
         void                    *cpu_addr;
         uint64_t                gpu_addr;
-        unsigned                fw_version;
         void                    *saved_bo;
-        unsigned                max_handles;
         atomic_t                handles[AMDGPU_MAX_UVD_HANDLES];
         struct drm_file         *filp[AMDGPU_MAX_UVD_HANDLES];
         struct delayed_work     idle_work;
-        const struct firmware   *fw;    /* UVD firmware */
         struct amdgpu_ring      ring;
         struct amdgpu_ring      ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
         struct amdgpu_irq_src   irq;
-        bool                    address_64_bit;
-        bool                    use_ctx_buf;
         struct drm_sched_entity entity;
         struct drm_sched_entity entity_enc;
         uint32_t                srbm_soft_reset;
+};
+
+struct amdgpu_uvd {
+        const struct firmware   *fw;    /* UVD firmware */
+        unsigned                fw_version;
+        unsigned                max_handles;
         unsigned                num_enc_rings;
+        uint8_t         num_uvd_inst;
+        bool                    address_64_bit;
+        bool                    use_ctx_buf;
+        struct amdgpu_uvd_inst          inst[AMDGPU_MAX_UVD_INSTANCES];
 };
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index a86322f5164f..23d960ec1cf2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -57,6 +57,7 @@
 
 #define FIRMWARE_VEGA10         "amdgpu/vega10_vce.bin"
 #define FIRMWARE_VEGA12         "amdgpu/vega12_vce.bin"
+#define FIRMWARE_VEGA20         "amdgpu/vega20_vce.bin"
 
 #ifdef CONFIG_DRM_AMDGPU_CIK
 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
@@ -76,6 +77,7 @@ MODULE_FIRMWARE(FIRMWARE_VEGAM);
 
 MODULE_FIRMWARE(FIRMWARE_VEGA10);
 MODULE_FIRMWARE(FIRMWARE_VEGA12);
+MODULE_FIRMWARE(FIRMWARE_VEGA20);
 
 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
 
@@ -143,6 +145,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
         case CHIP_VEGA12:
                 fw_name = FIRMWARE_VEGA12;
                 break;
+        case CHIP_VEGA20:
+                fw_name = FIRMWARE_VEGA20;
+                break;
 
         default:
                 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index e5d234cf804f..8851bcdfc260 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -205,13 +205,18 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
         struct amdgpu_device *adev =
                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
         unsigned fences = amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
+        unsigned i;
+
+        for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+                fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
+        }
 
         if (fences == 0) {
-                if (adev->pm.dpm_enabled) {
-                        /* might be used when with pg/cg
+                if (adev->pm.dpm_enabled)
                         amdgpu_dpm_enable_uvd(adev, false);
-                        */
-                }
+                else
+                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
+                                                               AMD_PG_STATE_GATE);
         } else {
                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
         }
@@ -223,9 +228,11 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
 
         if (set_clocks && adev->pm.dpm_enabled) {
-                /* might be used when with pg/cg
-                amdgpu_dpm_enable_uvd(adev, true);
-                */
+                if (adev->pm.dpm_enabled)
+                        amdgpu_dpm_enable_uvd(adev, true);
+                else
+                        amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
+                                                               AMD_PG_STATE_UNGATE);
         }
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2fd7db891689..181e6afa9847 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -45,6 +45,17 @@
 #define VCN_ENC_CMD_REG_WRITE           0x0000000b
 #define VCN_ENC_CMD_REG_WAIT            0x0000000c
 
+enum engine_status_constants {
+        UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
+        UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
+        UVD_STATUS__UVD_BUSY = 0x00000004,
+        GB_ADDR_CONFIG_DEFAULT = 0x26010011,
+        UVD_STATUS__IDLE = 0x2,
+        UVD_STATUS__BUSY = 0x5,
+        UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
+        UVD_STATUS__RBC_BUSY = 0x1,
+};
+
 struct amdgpu_vcn {
         struct amdgpu_bo        *vcpu_bo;
         void                    *cpu_addr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1a8f4e0dd023..ccba88cc8c54 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -119,9 +119,7 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
          * is currently evicted. add the bo to the evicted list to make sure it
          * is validated on next vm use to avoid fault.
          * */
-        spin_lock(&vm->status_lock);
         list_move_tail(&base->vm_status, &vm->evicted);
-        spin_unlock(&vm->status_lock);
 }
 
 /**
@@ -226,24 +224,16 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                               void *param)
 {
         struct ttm_bo_global *glob = adev->mman.bdev.glob;
-        int r;
-
-        spin_lock(&vm->status_lock);
-        while (!list_empty(&vm->evicted)) {
-                struct amdgpu_vm_bo_base *bo_base;
-                struct amdgpu_bo *bo;
+        struct amdgpu_vm_bo_base *bo_base, *tmp;
+        int r = 0;
 
-                bo_base = list_first_entry(&vm->evicted,
-                                           struct amdgpu_vm_bo_base,
-                                           vm_status);
-                spin_unlock(&vm->status_lock);
+        list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
+                struct amdgpu_bo *bo = bo_base->bo;
 
-                bo = bo_base->bo;
-                BUG_ON(!bo);
                 if (bo->parent) {
                         r = validate(param, bo);
                         if (r)
-                                return r;
+                                break;
 
                         spin_lock(&glob->lru_lock);
                         ttm_bo_move_to_lru_tail(&bo->tbo);
@@ -252,22 +242,29 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                         spin_unlock(&glob->lru_lock);
                 }
 
-                if (bo->tbo.type == ttm_bo_type_kernel &&
-                    vm->use_cpu_for_update) {
-                        r = amdgpu_bo_kmap(bo, NULL);
-                        if (r)
-                                return r;
-                }
-
-                spin_lock(&vm->status_lock);
-                if (bo->tbo.type != ttm_bo_type_kernel)
+                if (bo->tbo.type != ttm_bo_type_kernel) {
+                        spin_lock(&vm->moved_lock);
                         list_move(&bo_base->vm_status, &vm->moved);
-                else
+                        spin_unlock(&vm->moved_lock);
+                } else {
                         list_move(&bo_base->vm_status, &vm->relocated);
+                }
         }
-        spin_unlock(&vm->status_lock);
 
-        return 0;
+        spin_lock(&glob->lru_lock);
+        list_for_each_entry(bo_base, &vm->idle, vm_status) {
+                struct amdgpu_bo *bo = bo_base->bo;
+
+                if (!bo->parent)
+                        continue;
+
+                ttm_bo_move_to_lru_tail(&bo->tbo);
+                if (bo->shadow)
+                        ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
+        }
+        spin_unlock(&glob->lru_lock);
+
+        return r;
 }
 
 /**
@@ -279,13 +276,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
  */
 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
 {
-        bool ready;
-
-        spin_lock(&vm->status_lock);
-        ready = list_empty(&vm->evicted);
-        spin_unlock(&vm->status_lock);
-
-        return ready;
+        return list_empty(&vm->evicted);
 }
 
 /**
@@ -477,9 +468,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
                         pt->parent = amdgpu_bo_ref(parent->base.bo);
 
                         amdgpu_vm_bo_base_init(&entry->base, vm, pt);
-                        spin_lock(&vm->status_lock);
                         list_move(&entry->base.vm_status, &vm->relocated);
-                        spin_unlock(&vm->status_lock);
                 }
 
                 if (level < AMDGPU_VM_PTB) {
@@ -926,10 +915,8 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
                 if (!entry->base.bo)
                         continue;
 
-                spin_lock(&vm->status_lock);
-                if (list_empty(&entry->base.vm_status))
-                        list_add(&entry->base.vm_status, &vm->relocated);
-                spin_unlock(&vm->status_lock);
+                if (!entry->base.moved)
+                        list_move(&entry->base.vm_status, &vm->relocated);
                 amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
         }
 }
@@ -959,6 +946,14 @@ restart:
         params.adev = adev;
 
         if (vm->use_cpu_for_update) {
+                struct amdgpu_vm_bo_base *bo_base;
+
+                list_for_each_entry(bo_base, &vm->relocated, vm_status) {
+                        r = amdgpu_bo_kmap(bo_base->bo, NULL);
+                        if (unlikely(r))
+                                return r;
+                }
+
                 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
                 if (unlikely(r))
                         return r;
@@ -974,7 +969,6 @@ restart:
                 params.func = amdgpu_vm_do_set_ptes;
         }
 
-        spin_lock(&vm->status_lock);
         while (!list_empty(&vm->relocated)) {
                 struct amdgpu_vm_bo_base *bo_base, *parent;
                 struct amdgpu_vm_pt *pt, *entry;
@@ -983,14 +977,12 @@ restart:
                 bo_base = list_first_entry(&vm->relocated,
                                            struct amdgpu_vm_bo_base,
                                            vm_status);
-                list_del_init(&bo_base->vm_status);
-                spin_unlock(&vm->status_lock);
+                bo_base->moved = false;
+                list_move(&bo_base->vm_status, &vm->idle);
 
                 bo = bo_base->bo->parent;
-                if (!bo) {
-                        spin_lock(&vm->status_lock);
+                if (!bo)
                         continue;
-                }
 
                 parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base,
                                           bo_list);
@@ -999,12 +991,10 @@ restart:
 
                 amdgpu_vm_update_pde(&params, vm, pt, entry);
 
-                spin_lock(&vm->status_lock);
                 if (!vm->use_cpu_for_update &&
                     (ndw - params.ib->length_dw) < 32)
                         break;
         }
-        spin_unlock(&vm->status_lock);
 
         if (vm->use_cpu_for_update) {
                 /* Flush HDP */
@@ -1107,9 +1097,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
                 if (entry->huge) {
                         /* Add the entry to the relocated list to update it. */
                         entry->huge = false;
-                        spin_lock(&p->vm->status_lock);
                         list_move(&entry->base.vm_status, &p->vm->relocated);
-                        spin_unlock(&p->vm->status_lock);
                 }
                 return;
         }
@@ -1588,18 +1576,22 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
                 amdgpu_asic_flush_hdp(adev, NULL);
         }
 
-        spin_lock(&vm->status_lock);
+        spin_lock(&vm->moved_lock);
         list_del_init(&bo_va->base.vm_status);
+        spin_unlock(&vm->moved_lock);
 
         /* If the BO is not in its preferred location add it back to
          * the evicted list so that it gets validated again on the
          * next command submission.
          */
-        if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
-            !(bo->preferred_domains &
-            amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type)))
-                list_add_tail(&bo_va->base.vm_status, &vm->evicted);
-        spin_unlock(&vm->status_lock);
+        if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
+                uint32_t mem_type = bo->tbo.mem.mem_type;
+
+                if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
+                        list_add_tail(&bo_va->base.vm_status, &vm->evicted);
+                else
+                        list_add(&bo_va->base.vm_status, &vm->idle);
+        }
 
         list_splice_init(&bo_va->invalids, &bo_va->valids);
         bo_va->cleared = clear;
@@ -1808,19 +1800,18 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
                            struct amdgpu_vm *vm)
 {
+        struct amdgpu_bo_va *bo_va, *tmp;
+        struct list_head moved;
         bool clear;
-        int r = 0;
-
-        spin_lock(&vm->status_lock);
-        while (!list_empty(&vm->moved)) {
-                struct amdgpu_bo_va *bo_va;
-                struct reservation_object *resv;
+        int r;
 
-                bo_va = list_first_entry(&vm->moved,
-                        struct amdgpu_bo_va, base.vm_status);
-                spin_unlock(&vm->status_lock);
+        INIT_LIST_HEAD(&moved);
+        spin_lock(&vm->moved_lock);
+        list_splice_init(&vm->moved, &moved);
+        spin_unlock(&vm->moved_lock);
 
-                resv = bo_va->base.bo->tbo.resv;
+        list_for_each_entry_safe(bo_va, tmp, &moved, base.vm_status) {
+                struct reservation_object *resv = bo_va->base.bo->tbo.resv;
 
                 /* Per VM BOs never need to bo cleared in the page tables */
                 if (resv == vm->root.base.bo->tbo.resv)
@@ -1833,17 +1824,19 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
                         clear = true;
 
                 r = amdgpu_vm_bo_update(adev, bo_va, clear);
-                if (r)
+                if (r) {
+                        spin_lock(&vm->moved_lock);
+                        list_splice(&moved, &vm->moved);
+                        spin_unlock(&vm->moved_lock);
                         return r;
+                }
 
                 if (!clear && resv != vm->root.base.bo->tbo.resv)
                         reservation_object_unlock(resv);
 
-                spin_lock(&vm->status_lock);
         }
-        spin_unlock(&vm->status_lock);
 
-        return r;
+        return 0;
 }
 
 /**
@@ -1902,11 +1895,11 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
         if (mapping->flags & AMDGPU_PTE_PRT)
                 amdgpu_vm_prt_get(adev);
 
-        if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
-                spin_lock(&vm->status_lock);
-                if (list_empty(&bo_va->base.vm_status))
-                        list_add(&bo_va->base.vm_status, &vm->moved);
-                spin_unlock(&vm->status_lock);
+        if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
+            !bo_va->base.moved) {
+                spin_lock(&vm->moved_lock);
+                list_move(&bo_va->base.vm_status, &vm->moved);
+                spin_unlock(&vm->moved_lock);
         }
         trace_amdgpu_vm_bo_map(bo_va, mapping);
 }
@@ -2216,9 +2209,9 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 
         list_del(&bo_va->base.bo_list);
 
-        spin_lock(&vm->status_lock);
+        spin_lock(&vm->moved_lock);
         list_del(&bo_va->base.vm_status);
-        spin_unlock(&vm->status_lock);
+        spin_unlock(&vm->moved_lock);
 
         list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
                 list_del(&mapping->list);
@@ -2258,31 +2251,28 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 
         list_for_each_entry(bo_base, &bo->va, bo_list) {
                 struct amdgpu_vm *vm = bo_base->vm;
+                bool was_moved = bo_base->moved;
 
                 bo_base->moved = true;
                 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
-                        spin_lock(&bo_base->vm->status_lock);
                         if (bo->tbo.type == ttm_bo_type_kernel)
                                 list_move(&bo_base->vm_status, &vm->evicted);
                         else
                                 list_move_tail(&bo_base->vm_status,
                                                &vm->evicted);
-                        spin_unlock(&bo_base->vm->status_lock);
                         continue;
                 }
 
-                if (bo->tbo.type == ttm_bo_type_kernel) {
-                        spin_lock(&bo_base->vm->status_lock);
-                        if (list_empty(&bo_base->vm_status))
-                                list_add(&bo_base->vm_status, &vm->relocated);
-                        spin_unlock(&bo_base->vm->status_lock);
+                if (was_moved)
                         continue;
-                }
 
-                spin_lock(&bo_base->vm->status_lock);
-                if (list_empty(&bo_base->vm_status))
-                        list_add(&bo_base->vm_status, &vm->moved);
-                spin_unlock(&bo_base->vm->status_lock);
+                if (bo->tbo.type == ttm_bo_type_kernel) {
+                        list_move(&bo_base->vm_status, &vm->relocated);
+                } else {
+                        spin_lock(&bo_base->vm->moved_lock);
+                        list_move(&bo_base->vm_status, &vm->moved);
+                        spin_unlock(&bo_base->vm->moved_lock);
+                }
         }
 }
 
@@ -2391,10 +2381,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
         vm->va = RB_ROOT_CACHED;
         for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
                 vm->reserved_vmid[i] = NULL;
-        spin_lock_init(&vm->status_lock);
         INIT_LIST_HEAD(&vm->evicted);
         INIT_LIST_HEAD(&vm->relocated);
+        spin_lock_init(&vm->moved_lock);
         INIT_LIST_HEAD(&vm->moved);
+        INIT_LIST_HEAD(&vm->idle);
         INIT_LIST_HEAD(&vm->freed);
 
         /* create scheduler entity for page table updates */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 4cf678684a12..061b99a18cb8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -168,9 +168,6 @@ struct amdgpu_vm {
         /* tree of virtual addresses mapped */
         struct rb_root_cached   va;
 
-        /* protecting invalidated */
-        spinlock_t              status_lock;
-
         /* BOs who needs a validation */
         struct list_head        evicted;
 
@@ -179,6 +176,10 @@ struct amdgpu_vm {
 
         /* BOs moved, but not yet updated in the PT */
         struct list_head        moved;
+        spinlock_t              moved_lock;
+
+        /* All BOs of this VM not currently in the state machine */
+        struct list_head        idle;
 
         /* BO mappings freed, but not yet updated in the PT */
         struct list_head        freed;
@@ -187,9 +188,6 @@ struct amdgpu_vm {
         struct amdgpu_vm_pt     root;
         struct dma_fence        *last_update;
 
-        /* protecting freed */
-        spinlock_t              freed_lock;
-
         /* Scheduler entity for page table updates */
         struct drm_sched_entity entity;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index de7be3de0f41..dbf2ccd0c744 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -473,6 +473,7 @@ static int dce_virtual_hw_init(void *handle)
                 break;
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 break;
         default:
                 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
index 4ffda996660f..9935371db7ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
@@ -102,6 +102,13 @@ static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 }
 
+static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
+                                                bool enable)
+{
+        WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
+                       ForceParWrRMW, enable);
+}
+
 const struct amdgpu_df_funcs df_v1_7_funcs = {
         .init = df_v1_7_init,
         .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
@@ -109,4 +116,5 @@ const struct amdgpu_df_funcs df_v1_7_funcs = {
         .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
         .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
         .get_clockgating_state = df_v1_7_get_clockgating_state,
+        .enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
new file mode 100644
index 000000000000..60608b3df881
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "df_v3_6.h"
+
+#include "df/df_3_6_default.h"
+#include "df/df_3_6_offset.h"
+#include "df/df_3_6_sh_mask.h"
+
+static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
+                                       16, 32, 0, 0, 0, 2, 4, 8};
+
+static void df_v3_6_init(struct amdgpu_device *adev)
+{
+}
+
+static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
+                                          bool enable)
+{
+        u32 tmp;
+
+        if (enable) {
+                tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
+                tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
+                WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
+        } else
+                WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
+                             mmFabricConfigAccessControl_DEFAULT);
+}
+
+static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
+{
+        u32 tmp;
+
+        tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
+        tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
+        tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
+
+        return tmp;
+}
+
+static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
+{
+        int fb_channel_number;
+
+        fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
+        if (fb_channel_number > ARRAY_SIZE(df_v3_6_channel_number))
+                fb_channel_number = 0;
+
+        return df_v3_6_channel_number[fb_channel_number];
+}
+
+static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+                                                     bool enable)
+{
+        u32 tmp;
+
+        /* Put DF on broadcast mode */
+        adev->df_funcs->enable_broadcast_mode(adev, true);
+
+        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
+                tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+                tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+                tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
+                WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+        } else {
+                tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+                tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
+                tmp |= DF_V3_6_MGCG_DISABLE;
+                WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
+        }
+
+        /* Exit broadcast mode */
+        adev->df_funcs->enable_broadcast_mode(adev, false);
+}
+
+static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
+                                          u32 *flags)
+{
+        u32 tmp;
+
+        /* AMD_CG_SUPPORT_DF_MGCG */
+        tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
+        if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
+                *flags |= AMD_CG_SUPPORT_DF_MGCG;
+}
+
+const struct amdgpu_df_funcs df_v3_6_funcs = {
+        .init = df_v3_6_init,
+        .enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
+        .get_fb_channel_number = df_v3_6_get_fb_channel_number,
+        .get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
+        .update_medium_grain_clock_gating =
+                        df_v3_6_update_medium_grain_clock_gating,
+        .get_clockgating_state = df_v3_6_get_clockgating_state,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.h b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
new file mode 100644
index 000000000000..e79c58e5efcb
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __DF_V3_6_H__
+#define __DF_V3_6_H__
+
+#include "soc15_common.h"
+
+enum DF_V3_6_MGCG {
+        DF_V3_6_MGCG_DISABLE = 0,
+        DF_V3_6_MGCG_ENABLE_00_CYCLE_DELAY = 1,
+        DF_V3_6_MGCG_ENABLE_01_CYCLE_DELAY = 2,
+        DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY = 13,
+        DF_V3_6_MGCG_ENABLE_31_CYCLE_DELAY = 14,
+        DF_V3_6_MGCG_ENABLE_63_CYCLE_DELAY = 15
+};
+
+extern const struct amdgpu_df_funcs df_v3_6_funcs;
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fc1911834ab5..d7530fdfaad5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -27,6 +27,7 @@
 #include "amdgpu_gfx.h"
 #include "soc15.h"
 #include "soc15d.h"
+#include "amdgpu_atomfirmware.h"
 
 #include "gc/gc_9_0_offset.h"
 #include "gc/gc_9_0_sh_mask.h"
@@ -63,6 +64,13 @@ MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
+MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
+MODULE_FIRMWARE("amdgpu/vega20_me.bin");
+MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
+MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
+MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
+
 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
 MODULE_FIRMWARE("amdgpu/raven_me.bin");
@@ -72,29 +80,22 @@ MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
 
 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
 {
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
-        SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 };
 
 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
@@ -108,6 +109,20 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)
 };
 
+static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
+{
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
+        SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 {
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
@@ -241,6 +256,14 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
                                                 golden_settings_gc_9_2_1_vg12,
                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
                 break;
+        case CHIP_VEGA20:
+                soc15_program_register_sequence(adev,
+                                                golden_settings_gc_9_0,
+                                                ARRAY_SIZE(golden_settings_gc_9_0));
+                soc15_program_register_sequence(adev,
+                                                golden_settings_gc_9_0_vg20,
+                                                ARRAY_SIZE(golden_settings_gc_9_0_vg20));
+                break;
         case CHIP_RAVEN:
                 soc15_program_register_sequence(adev,
                                                  golden_settings_gc_9_1,
@@ -468,6 +491,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
         case CHIP_VEGA12:
                 chip_name = "vega12";
                 break;
+        case CHIP_VEGA20:
+                chip_name = "vega20";
+                break;
         case CHIP_RAVEN:
                 chip_name = "raven";
                 break;
@@ -1088,9 +1114,10 @@ static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
 };
 
-static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
+static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
 {
         u32 gb_addr_config;
+        int err;
 
         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
 
@@ -1112,6 +1139,20 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
                 DRM_INFO("fix gfx.config for vega12\n");
                 break;
+        case CHIP_VEGA20:
+                adev->gfx.config.max_hw_contexts = 8;
+                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+                gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
+                gb_addr_config &= ~0xf3e777ff;
+                gb_addr_config |= 0x22014042;
+                /* check vbios table if gpu info is not available */
+                err = amdgpu_atomfirmware_get_gfx_info(adev);
+                if (err)
+                        return err;
+                break;
         case CHIP_RAVEN:
                 adev->gfx.config.max_hw_contexts = 8;
                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
@@ -1161,6 +1202,8 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
                                         adev->gfx.config.gb_addr_config,
                                         GB_ADDR_CONFIG,
                                         PIPE_INTERLEAVE_SIZE));
+
+        return 0;
 }
 
 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
@@ -1394,6 +1437,7 @@ static int gfx_v9_0_sw_init(void *handle)
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
         case CHIP_RAVEN:
                 adev->gfx.mec.num_mec = 2;
                 break;
@@ -1521,7 +1565,9 @@ static int gfx_v9_0_sw_init(void *handle)
 
         adev->gfx.ce_ram_size = 0x8000;
 
-        gfx_v9_0_gpu_early_init(adev);
+        r = gfx_v9_0_gpu_early_init(adev);
+        if (r)
+                return r;
 
         r = gfx_v9_0_ngg_init(adev);
         if (r)
@@ -3688,6 +3734,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
         case CHIP_RAVEN:
                 gfx_v9_0_update_gfx_clock_gating(adev,
                                                  state == AMD_CG_STATE_GATE ? true : false);
@@ -4680,6 +4727,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
         case CHIP_RAVEN:
                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
                 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6cccf0e0acd7..3c0a85d4e4ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -675,6 +675,7 @@ static int gmc_v9_0_late_init(void *handle)
                         DRM_INFO("ECC is active.\n");
                 } else if (r == 0) {
                         DRM_INFO("ECC is not present.\n");
+                        adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
                 } else {
                         DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
                         return r;
@@ -693,10 +694,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
         amdgpu_device_vram_location(adev, &adev->gmc, base);
         amdgpu_device_gart_location(adev, mc);
         /* base offset of vram pages */
-        if (adev->flags & AMD_IS_APU)
-                adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
-        else
-                adev->vm_manager.vram_base_offset = 0;
+        adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 }
 
 /**
@@ -755,6 +753,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
                 switch (adev->asic_type) {
                 case CHIP_VEGA10:  /* all engines support GPUVM */
                 case CHIP_VEGA12:  /* all engines support GPUVM */
+                case CHIP_VEGA20:
                 default:
                         adev->gmc.gart_size = 512ULL << 20;
                         break;
@@ -860,6 +859,7 @@ static int gmc_v9_0_sw_init(void *handle)
                 break;
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 /*
                  * To fulfill 4-level page support,
                  * vm size is 256TB (48bit), maximum size of Vega10,
@@ -977,6 +977,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
 
         switch (adev->asic_type) {
         case CHIP_VEGA10:
+        case CHIP_VEGA20:
                 soc15_program_register_sequence(adev,
                                                 golden_settings_mmhub_1_0_0,
                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 43f925773b57..3d53c4413f13 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -734,6 +734,7 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
         case CHIP_RAVEN:
                 mmhub_v1_0_update_medium_grain_clock_gating(adev,
                                 state == AMD_CG_STATE_GATE ? true : false);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index df34dc79d444..365517c0121e 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -34,10 +34,19 @@
 #define smnCPM_CONTROL                                                                                  0x11180460
 #define smnPCIE_CNTL2                                                                                   0x11180070
 
+/* vega20 */
+#define mmRCC_DEV0_EPF0_STRAP0_VG20                                                                         0x0011
+#define mmRCC_DEV0_EPF0_STRAP0_VG20_BASE_IDX                                                                2
+
 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
 
+        if (adev->asic_type == CHIP_VEGA20)
+                tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_VG20);
+        else
+                tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
+
         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
 
@@ -75,10 +84,14 @@ static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instan
                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
 
         u32 doorbell_range = RREG32(reg);
+        u32 range = 2;
+
+        if (adev->asic_type == CHIP_VEGA20)
+                range = 8;
 
         if (use_doorbell) {
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
-                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
+                doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range);
         } else
                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
 
@@ -133,6 +146,9 @@ static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
 {
         uint32_t def, data;
 
+        if (adev->asic_type == CHIP_VEGA20)
+                return;
+
         /* NBIF_MGCG_CTRL_LCLK */
         def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 196e75def1f2..0c768e388ace 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -41,6 +41,9 @@ MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
 MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
 MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
+MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
+MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
+
 
 #define smnMP1_FIRMWARE_FLAGS 0x3010028
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 03a36cbe7557..ca53b3fba422 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -42,6 +42,8 @@ MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
+MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
 
 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
@@ -107,6 +109,28 @@ static const struct soc15_reg_golden golden_settings_sdma_4_1[] =
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0)
 };
 
+static const struct soc15_reg_golden golden_settings_sdma_4_2[] =
+{
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
+        SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
+};
+
 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 {
         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
@@ -139,6 +163,11 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
                                                 golden_settings_sdma_vg12,
                                                 ARRAY_SIZE(golden_settings_sdma_vg12));
                 break;
+        case CHIP_VEGA20:
+                soc15_program_register_sequence(adev,
+                                                golden_settings_sdma_4_2,
+                                                ARRAY_SIZE(golden_settings_sdma_4_2));
+                break;
         case CHIP_RAVEN:
                 soc15_program_register_sequence(adev,
                                                  golden_settings_sdma_4_1,
@@ -182,6 +211,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
         case CHIP_VEGA12:
                 chip_name = "vega12";
                 break;
+        case CHIP_VEGA20:
+                chip_name = "vega20";
+                break;
         case CHIP_RAVEN:
                 chip_name = "raven";
                 break;
@@ -1516,6 +1548,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
         case CHIP_RAVEN:
                 sdma_v4_0_update_medium_grain_clock_gating(adev,
                                 state == AMD_CG_STATE_GATE ? true : false);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 90065766fffb..68b4a22a8892 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -41,8 +41,6 @@
 #include "sdma1/sdma1_4_0_offset.h"
 #include "hdp/hdp_4_0_offset.h"
 #include "hdp/hdp_4_0_sh_mask.h"
-#include "mp/mp_9_0_offset.h"
-#include "mp/mp_9_0_sh_mask.h"
 #include "smuio/smuio_9_0_offset.h"
 #include "smuio/smuio_9_0_sh_mask.h"
 
@@ -53,6 +51,7 @@
 #include "gfxhub_v1_0.h"
 #include "mmhub_v1_0.h"
 #include "df_v1_7.h"
+#include "df_v3_6.h"
 #include "vega10_ih.h"
 #include "sdma_v4_0.h"
 #include "uvd_v7_0.h"
@@ -489,16 +488,24 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
         case CHIP_RAVEN:
                 vega10_reg_base_init(adev);
                 break;
+        case CHIP_VEGA20:
+                vega20_reg_base_init(adev);
+                break;
         default:
                 return -EINVAL;
         }
 
         if (adev->flags & AMD_IS_APU)
                 adev->nbio_funcs = &nbio_v7_0_funcs;
+        else if (adev->asic_type == CHIP_VEGA20)
+                adev->nbio_funcs = &nbio_v7_0_funcs;
         else
                 adev->nbio_funcs = &nbio_v6_1_funcs;
 
-        adev->df_funcs = &df_v1_7_funcs;
+        if (adev->asic_type == CHIP_VEGA20)
+                adev->df_funcs = &df_v3_6_funcs;
+        else
+                adev->df_funcs = &df_v1_7_funcs;
         adev->nbio_funcs->detect_hw_virt(adev);
 
         if (amdgpu_sriov_vf(adev))
@@ -507,12 +514,15 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
-                amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
-                if (!amdgpu_sriov_vf(adev))
-                        amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
+                if (adev->asic_type != CHIP_VEGA20) {
+                        amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+                        if (!amdgpu_sriov_vf(adev))
+                                amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
+                }
                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 #if defined(CONFIG_DRM_AMD_DC)
@@ -660,6 +670,27 @@ static int soc15_common_early_init(void *handle)
                 adev->pg_flags = 0;
                 adev->external_rev_id = adev->rev_id + 0x14;
                 break;
+        case CHIP_VEGA20:
+                adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+                        AMD_CG_SUPPORT_GFX_MGLS |
+                        AMD_CG_SUPPORT_GFX_CGCG |
+                        AMD_CG_SUPPORT_GFX_CGLS |
+                        AMD_CG_SUPPORT_GFX_3D_CGCG |
+                        AMD_CG_SUPPORT_GFX_3D_CGLS |
+                        AMD_CG_SUPPORT_GFX_CP_LS |
+                        AMD_CG_SUPPORT_MC_LS |
+                        AMD_CG_SUPPORT_MC_MGCG |
+                        AMD_CG_SUPPORT_SDMA_MGCG |
+                        AMD_CG_SUPPORT_SDMA_LS |
+                        AMD_CG_SUPPORT_BIF_MGCG |
+                        AMD_CG_SUPPORT_BIF_LS |
+                        AMD_CG_SUPPORT_HDP_MGCG |
+                        AMD_CG_SUPPORT_ROM_MGCG |
+                        AMD_CG_SUPPORT_VCE_MGCG |
+                        AMD_CG_SUPPORT_UVD_MGCG;
+                adev->pg_flags = 0;
+                adev->external_rev_id = adev->rev_id + 0x28;
+                break;
         case CHIP_RAVEN:
                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                         AMD_CG_SUPPORT_GFX_MGLS |
@@ -679,8 +710,10 @@ static int soc15_common_early_init(void *handle)
                         AMD_CG_SUPPORT_MC_MGCG |
                         AMD_CG_SUPPORT_MC_LS |
                         AMD_CG_SUPPORT_SDMA_MGCG |
-                        AMD_CG_SUPPORT_SDMA_LS;
-                adev->pg_flags = AMD_PG_SUPPORT_SDMA;
+                        AMD_CG_SUPPORT_SDMA_LS |
+                        AMD_CG_SUPPORT_VCN_MGCG;
+
+                adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
 
                 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
                         adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
@@ -872,6 +905,7 @@ static int soc15_common_set_clockgating_state(void *handle,
         switch (adev->asic_type) {
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 adev->nbio_funcs->update_medium_grain_clock_gating(adev,
                                 state == AMD_CG_STATE_GATE ? true : false);
                 adev->nbio_funcs->update_medium_grain_light_sleep(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index f70da8a29f86..1f714b7af520 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -55,5 +55,6 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
                                              const u32 array_size);
 
 int vega10_reg_base_init(struct amdgpu_device *adev);
+int vega20_reg_base_init(struct amdgpu_device *adev);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index def865067edd..0942f492d2e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -47,6 +47,21 @@
 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
         WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
 
+#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \
+        do {                                                    \
+                uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+                uint32_t loop = adev->usec_timeout;             \
+                while ((tmp_ & (mask)) != (expected_value)) {   \
+                        udelay(2);                              \
+                        tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+                        loop--;                                 \
+                        if (!loop) {                            \
+                                ret = -ETIMEDOUT;               \
+                                break;                          \
+                        }                                       \
+                }                                               \
+        } while (0)
+
 #endif
 
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 87cbb142dd0b..6fed3d7797a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -93,6 +93,7 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
 static int uvd_v4_2_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        adev->uvd.num_uvd_inst = 1;
 
         uvd_v4_2_set_ring_funcs(adev);
         uvd_v4_2_set_irq_funcs(adev);
@@ -107,7 +108,7 @@ static int uvd_v4_2_sw_init(void *handle)
         int r;
 
         /* UVD TRAP */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
         if (r)
                 return r;
 
@@ -119,9 +120,9 @@ static int uvd_v4_2_sw_init(void *handle)
         if (r)
                 return r;
 
-        ring = &adev->uvd.ring;
+        ring = &adev->uvd.inst->ring;
         sprintf(ring->name, "uvd");
-        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 
         return r;
 }
@@ -150,7 +151,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
 static int uvd_v4_2_hw_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
         uint32_t tmp;
         int r;
 
@@ -208,7 +209,7 @@ done:
 static int uvd_v4_2_hw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 
         if (RREG32(mmUVD_STATUS) != 0)
                 uvd_v4_2_stop(adev);
@@ -251,7 +252,7 @@ static int uvd_v4_2_resume(void *handle)
  */
 static int uvd_v4_2_start(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
         uint32_t rb_bufsz;
         int i, j, r;
         u32 tmp;
@@ -523,6 +524,18 @@ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
         amdgpu_ring_write(ring, ib->length_dw);
 }
 
+static void uvd_v4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+{
+        int i;
+
+        WARN_ON(ring->wptr % 2 || count % 2);
+
+        for (i = 0; i < count / 2; i++) {
+                amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
+                amdgpu_ring_write(ring, 0);
+        }
+}
+
 /**
  * uvd_v4_2_mc_resume - memory controller programming
  *
@@ -536,7 +549,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
         uint32_t size;
 
         /* programm the VCPU memory controller bits 0-27 */
-        addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
+        addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
         size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
         WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
@@ -553,11 +566,11 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 
         /* bits 28-31 */
-        addr = (adev->uvd.gpu_addr >> 28) & 0xF;
+        addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
         WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
 
         /* bits 32-39 */
-        addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
+        addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
         WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 
         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
@@ -664,7 +677,7 @@ static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
                                       struct amdgpu_iv_entry *entry)
 {
         DRM_DEBUG("IH: UVD TRAP\n");
-        amdgpu_fence_process(&adev->uvd.ring);
+        amdgpu_fence_process(&adev->uvd.inst->ring);
         return 0;
 }
 
@@ -732,7 +745,6 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
         .type = AMDGPU_RING_TYPE_UVD,
         .align_mask = 0xf,
-        .nop = PACKET0(mmUVD_NO_OP, 0),
         .support_64bit_ptrs = false,
         .get_rptr = uvd_v4_2_ring_get_rptr,
         .get_wptr = uvd_v4_2_ring_get_wptr,
@@ -745,7 +757,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
         .emit_fence = uvd_v4_2_ring_emit_fence,
         .test_ring = uvd_v4_2_ring_test_ring,
         .test_ib = amdgpu_uvd_ring_test_ib,
-        .insert_nop = amdgpu_ring_insert_nop,
+        .insert_nop = uvd_v4_2_ring_insert_nop,
         .pad_ib = amdgpu_ring_generic_pad_ib,
         .begin_use = amdgpu_uvd_ring_begin_use,
         .end_use = amdgpu_uvd_ring_end_use,
@@ -753,7 +765,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
 
 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
+        adev->uvd.inst->ring.funcs = &uvd_v4_2_ring_funcs;
 }
 
 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
@@ -763,8 +775,8 @@ static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
 
 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.irq.num_types = 1;
-        adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;
+        adev->uvd.inst->irq.num_types = 1;
+        adev->uvd.inst->irq.funcs = &uvd_v4_2_irq_funcs;
 }
 
 const struct amdgpu_ip_block_version uvd_v4_2_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 6445d55e7d5a..341ee6d55ce8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -89,6 +89,7 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 static int uvd_v5_0_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        adev->uvd.num_uvd_inst = 1;
 
         uvd_v5_0_set_ring_funcs(adev);
         uvd_v5_0_set_irq_funcs(adev);
@@ -103,7 +104,7 @@ static int uvd_v5_0_sw_init(void *handle)
         int r;
 
         /* UVD TRAP */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
         if (r)
                 return r;
 
@@ -115,9 +116,9 @@ static int uvd_v5_0_sw_init(void *handle)
         if (r)
                 return r;
 
-        ring = &adev->uvd.ring;
+        ring = &adev->uvd.inst->ring;
         sprintf(ring->name, "uvd");
-        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
 
         return r;
 }
@@ -144,7 +145,7 @@ static int uvd_v5_0_sw_fini(void *handle)
 static int uvd_v5_0_hw_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
         uint32_t tmp;
         int r;
 
@@ -204,7 +205,7 @@ done:
 static int uvd_v5_0_hw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 
         if (RREG32(mmUVD_STATUS) != 0)
                 uvd_v5_0_stop(adev);
@@ -253,9 +254,9 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
 
         /* programm memory controller bits 0-27 */
         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
-                        lower_32_bits(adev->uvd.gpu_addr));
+                        lower_32_bits(adev->uvd.inst->gpu_addr));
         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
-                        upper_32_bits(adev->uvd.gpu_addr));
+                        upper_32_bits(adev->uvd.inst->gpu_addr));
 
         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
@@ -287,7 +288,7 @@ static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  */
 static int uvd_v5_0_start(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
         uint32_t rb_bufsz, tmp;
         uint32_t lmi_swap_cntl;
         uint32_t mp_swap_cntl;
@@ -540,6 +541,18 @@ static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
         amdgpu_ring_write(ring, ib->length_dw);
 }
 
+static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+{
+        int i;
+
+        WARN_ON(ring->wptr % 2 || count % 2);
+
+        for (i = 0; i < count / 2; i++) {
+                amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
+                amdgpu_ring_write(ring, 0);
+        }
+}
+
 static bool uvd_v5_0_is_idle(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -586,7 +599,7 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
                                       struct amdgpu_iv_entry *entry)
 {
         DRM_DEBUG("IH: UVD TRAP\n");
-        amdgpu_fence_process(&adev->uvd.ring);
+        amdgpu_fence_process(&adev->uvd.inst->ring);
         return 0;
 }
 
@@ -840,7 +853,6 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
         .type = AMDGPU_RING_TYPE_UVD,
         .align_mask = 0xf,
-        .nop = PACKET0(mmUVD_NO_OP, 0),
         .support_64bit_ptrs = false,
         .get_rptr = uvd_v5_0_ring_get_rptr,
         .get_wptr = uvd_v5_0_ring_get_wptr,
@@ -853,7 +865,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
         .emit_fence = uvd_v5_0_ring_emit_fence,
         .test_ring = uvd_v5_0_ring_test_ring,
         .test_ib = amdgpu_uvd_ring_test_ib,
-        .insert_nop = amdgpu_ring_insert_nop,
+        .insert_nop = uvd_v5_0_ring_insert_nop,
         .pad_ib = amdgpu_ring_generic_pad_ib,
         .begin_use = amdgpu_uvd_ring_begin_use,
         .end_use = amdgpu_uvd_ring_end_use,
@@ -861,7 +873,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
 
 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs;
+        adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;
 }
 
 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
@@ -871,8 +883,8 @@ static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
 
 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.irq.num_types = 1;
-        adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
+        adev->uvd.inst->irq.num_types = 1;
+        adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;
 }
 
 const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index ca6ab56357b5..bfddf97dd13e 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -91,7 +91,7 @@ static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
-        if (ring == &adev->uvd.ring_enc[0])
+        if (ring == &adev->uvd.inst->ring_enc[0])
                 return RREG32(mmUVD_RB_RPTR);
         else
                 return RREG32(mmUVD_RB_RPTR2);
@@ -121,7 +121,7 @@ static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
-        if (ring == &adev->uvd.ring_enc[0])
+        if (ring == &adev->uvd.inst->ring_enc[0])
                 return RREG32(mmUVD_RB_WPTR);
         else
                 return RREG32(mmUVD_RB_WPTR2);
@@ -152,7 +152,7 @@ static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
-        if (ring == &adev->uvd.ring_enc[0])
+        if (ring == &adev->uvd.inst->ring_enc[0])
                 WREG32(mmUVD_RB_WPTR,
                         lower_32_bits(ring->wptr));
         else
@@ -375,6 +375,7 @@ error:
 static int uvd_v6_0_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        adev->uvd.num_uvd_inst = 1;
 
         if (!(adev->flags & AMD_IS_APU) &&
             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
@@ -399,14 +400,14 @@ static int uvd_v6_0_sw_init(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
         /* UVD TRAP */
-        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
+        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
         if (r)
                 return r;
 
         /* UVD ENC TRAP */
         if (uvd_v6_0_enc_support(adev)) {
                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-                        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
+                        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.inst->irq);
                         if (r)
                                 return r;
                 }
@@ -418,17 +419,17 @@ static int uvd_v6_0_sw_init(void *handle)
 
         if (!uvd_v6_0_enc_support(adev)) {
                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
-                        adev->uvd.ring_enc[i].funcs = NULL;
+                        adev->uvd.inst->ring_enc[i].funcs = NULL;
 
-                adev->uvd.irq.num_types = 1;
+                adev->uvd.inst->irq.num_types = 1;
                 adev->uvd.num_enc_rings = 0;
 
                 DRM_INFO("UVD ENC is disabled\n");
         } else {
                 struct drm_sched_rq *rq;
-                ring = &adev->uvd.ring_enc[0];
+                ring = &adev->uvd.inst->ring_enc[0];
                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-                r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
+                r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst->entity_enc,
                                           rq, NULL);
                 if (r) {
                         DRM_ERROR("Failed setting up UVD ENC run queue.\n");
@@ -440,17 +441,17 @@ static int uvd_v6_0_sw_init(void *handle)
         if (r)
                 return r;
 
-        ring = &adev->uvd.ring;
+        ring = &adev->uvd.inst->ring;
         sprintf(ring->name, "uvd");
-        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
         if (r)
                 return r;
 
         if (uvd_v6_0_enc_support(adev)) {
                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-                        ring = &adev->uvd.ring_enc[i];
+                        ring = &adev->uvd.inst->ring_enc[i];
                         sprintf(ring->name, "uvd_enc%d", i);
-                        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
+                        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
                         if (r)
                                 return r;
                 }
@@ -469,10 +470,10 @@ static int uvd_v6_0_sw_fini(void *handle)
                 return r;
 
         if (uvd_v6_0_enc_support(adev)) {
-                drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
+                drm_sched_entity_fini(&adev->uvd.inst->ring_enc[0].sched, &adev->uvd.inst->entity_enc);
 
                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
-                        amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
+                        amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
         }
 
         return amdgpu_uvd_sw_fini(adev);
@@ -488,7 +489,7 @@ static int uvd_v6_0_sw_fini(void *handle)
 static int uvd_v6_0_hw_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
         uint32_t tmp;
         int i, r;
 
@@ -532,7 +533,7 @@ static int uvd_v6_0_hw_init(void *handle)
 
         if (uvd_v6_0_enc_support(adev)) {
                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-                        ring = &adev->uvd.ring_enc[i];
+                        ring = &adev->uvd.inst->ring_enc[i];
                         ring->ready = true;
                         r = amdgpu_ring_test_ring(ring);
                         if (r) {
@@ -563,7 +564,7 @@ done:
 static int uvd_v6_0_hw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
 
         if (RREG32(mmUVD_STATUS) != 0)
                 uvd_v6_0_stop(adev);
@@ -611,9 +612,9 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 
         /* programm memory controller bits 0-27 */
         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
-                        lower_32_bits(adev->uvd.gpu_addr));
+                        lower_32_bits(adev->uvd.inst->gpu_addr));
         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
-                        upper_32_bits(adev->uvd.gpu_addr));
+                        upper_32_bits(adev->uvd.inst->gpu_addr));
 
         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
@@ -726,7 +727,7 @@ static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
  */
 static int uvd_v6_0_start(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring = &adev->uvd.inst->ring;
         uint32_t rb_bufsz, tmp;
         uint32_t lmi_swap_cntl;
         uint32_t mp_swap_cntl;
@@ -866,14 +867,14 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 
         if (uvd_v6_0_enc_support(adev)) {
-                ring = &adev->uvd.ring_enc[0];
+                ring = &adev->uvd.inst->ring_enc[0];
                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 
-                ring = &adev->uvd.ring_enc[1];
+                ring = &adev->uvd.inst->ring_enc[1];
                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
@@ -1099,6 +1100,18 @@ static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
         amdgpu_ring_write(ring, 0xE);
 }
 
+static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+{
+        int i;
+
+        WARN_ON(ring->wptr % 2 || count % 2);
+
+        for (i = 0; i < count / 2; i++) {
+                amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
+                amdgpu_ring_write(ring, 0);
+        }
+}
+
 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 {
         uint32_t seq = ring->fence_drv.sync_seq;
@@ -1158,10 +1171,10 @@ static bool uvd_v6_0_check_soft_reset(void *handle)
                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
 
         if (srbm_soft_reset) {
-                adev->uvd.srbm_soft_reset = srbm_soft_reset;
+                adev->uvd.inst->srbm_soft_reset = srbm_soft_reset;
                 return true;
         } else {
-                adev->uvd.srbm_soft_reset = 0;
+                adev->uvd.inst->srbm_soft_reset = 0;
                 return false;
         }
 }
@@ -1170,7 +1183,7 @@ static int uvd_v6_0_pre_soft_reset(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (!adev->uvd.srbm_soft_reset)
+        if (!adev->uvd.inst->srbm_soft_reset)
                 return 0;
 
         uvd_v6_0_stop(adev);
@@ -1182,9 +1195,9 @@ static int uvd_v6_0_soft_reset(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         u32 srbm_soft_reset;
 
-        if (!adev->uvd.srbm_soft_reset)
+        if (!adev->uvd.inst->srbm_soft_reset)
                 return 0;
-        srbm_soft_reset = adev->uvd.srbm_soft_reset;
+        srbm_soft_reset = adev->uvd.inst->srbm_soft_reset;
 
         if (srbm_soft_reset) {
                 u32 tmp;
@@ -1212,7 +1225,7 @@ static int uvd_v6_0_post_soft_reset(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (!adev->uvd.srbm_soft_reset)
+        if (!adev->uvd.inst->srbm_soft_reset)
                 return 0;
 
         mdelay(5);
@@ -1238,17 +1251,17 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 
         switch (entry->src_id) {
         case 124:
-                amdgpu_fence_process(&adev->uvd.ring);
+                amdgpu_fence_process(&adev->uvd.inst->ring);
                 break;
         case 119:
                 if (likely(uvd_v6_0_enc_support(adev)))
-                        amdgpu_fence_process(&adev->uvd.ring_enc[0]);
+                        amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]);
                 else
                         int_handled = false;
                 break;
         case 120:
                 if (likely(uvd_v6_0_enc_support(adev)))
-                        amdgpu_fence_process(&adev->uvd.ring_enc[1]);
+                        amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]);
                 else
                         int_handled = false;
                 break;
@@ -1531,7 +1544,6 @@ static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
         .type = AMDGPU_RING_TYPE_UVD,
         .align_mask = 0xf,
-        .nop = PACKET0(mmUVD_NO_OP, 0),
         .support_64bit_ptrs = false,
         .get_rptr = uvd_v6_0_ring_get_rptr,
         .get_wptr = uvd_v6_0_ring_get_wptr,
@@ -1547,7 +1559,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
         .test_ring = uvd_v6_0_ring_test_ring,
         .test_ib = amdgpu_uvd_ring_test_ib,
-        .insert_nop = amdgpu_ring_insert_nop,
+        .insert_nop = uvd_v6_0_ring_insert_nop,
         .pad_ib = amdgpu_ring_generic_pad_ib,
         .begin_use = amdgpu_uvd_ring_begin_use,
         .end_use = amdgpu_uvd_ring_end_use,
@@ -1612,10 +1624,10 @@ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
 {
         if (adev->asic_type >= CHIP_POLARIS10) {
-                adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
+                adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs;
                 DRM_INFO("UVD is enabled in VM mode\n");
         } else {
-                adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
+                adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs;
                 DRM_INFO("UVD is enabled in physical mode\n");
         }
 }
@@ -1625,7 +1637,7 @@ static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
         int i;
 
         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
-                adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
+                adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
 
         DRM_INFO("UVD ENC is enabled in VM mode\n");
 }
@@ -1638,11 +1650,11 @@ static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
 {
         if (uvd_v6_0_enc_support(adev))
-                adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
+                adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1;
         else
-                adev->uvd.irq.num_types = 1;
+                adev->uvd.inst->irq.num_types = 1;
 
-        adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
+        adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs;
 }
 
 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 0ca63d588670..57d32f21b3a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -40,6 +40,8 @@
 #include "mmhub/mmhub_1_0_offset.h"
 #include "mmhub/mmhub_1_0_sh_mask.h"
 
+#define UVD7_MAX_HW_INSTANCES_VEGA20                    2
+
 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -47,6 +49,11 @@ static int uvd_v7_0_start(struct amdgpu_device *adev);
 static void uvd_v7_0_stop(struct amdgpu_device *adev);
 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
 
+static int amdgpu_ih_clientid_uvds[] = {
+        SOC15_IH_CLIENTID_UVD,
+        SOC15_IH_CLIENTID_UVD1
+};
+
 /**
  * uvd_v7_0_ring_get_rptr - get read pointer
  *
@@ -58,7 +65,7 @@ static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
-        return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
+        return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
 }
 
 /**
@@ -72,10 +79,10 @@ static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
-        if (ring == &adev->uvd.ring_enc[0])
-                return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
+        if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
+                return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
         else
-                return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
+                return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
 }
 
 /**
@@ -89,7 +96,7 @@ static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
-        return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
+        return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
 }
 
 /**
@@ -106,10 +113,10 @@ static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
         if (ring->use_doorbell)
                 return adev->wb.wb[ring->wptr_offs];
 
-        if (ring == &adev->uvd.ring_enc[0])
-                return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
+        if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
+                return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
         else
-                return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
+                return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 }
 
 /**
@@ -123,7 +130,7 @@ static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
 
-        WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
+        WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 }
 
 /**
@@ -144,11 +151,11 @@ static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
                 return;
         }
 
-        if (ring == &adev->uvd.ring_enc[0])
-                WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
+        if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
+                WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
                         lower_32_bits(ring->wptr));
         else
-                WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
+                WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
                         lower_32_bits(ring->wptr));
 }
 
@@ -170,8 +177,8 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 
         r = amdgpu_ring_alloc(ring, 16);
         if (r) {
-                DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
-                          ring->idx, r);
+                DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n",
+                          ring->me, ring->idx, r);
                 return r;
         }
         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
@@ -184,11 +191,11 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
         }
 
         if (i < adev->usec_timeout) {
-                DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
-                         ring->idx, i);
+                DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
+                         ring->me, ring->idx, i);
         } else {
-                DRM_ERROR("amdgpu: ring %d test failed\n",
-                          ring->idx);
+                DRM_ERROR("amdgpu: (%d)ring %d test failed\n",
+                          ring->me, ring->idx);
                 r = -ETIMEDOUT;
         }
 
@@ -342,24 +349,24 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
         if (r) {
-                DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
+                DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r);
                 goto error;
         }
 
         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
         if (r) {
-                DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
+                DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r);
                 goto error;
         }
 
         r = dma_fence_wait_timeout(fence, false, timeout);
         if (r == 0) {
-                DRM_ERROR("amdgpu: IB test timed out.\n");
+                DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me);
                 r = -ETIMEDOUT;
         } else if (r < 0) {
-                DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
+                DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r);
         } else {
-                DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
+                DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx);
                 r = 0;
         }
 error:
@@ -370,6 +377,10 @@ error:
 static int uvd_v7_0_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        if (adev->asic_type == CHIP_VEGA20)
+                adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
+        else
+                adev->uvd.num_uvd_inst = 1;
 
         if (amdgpu_sriov_vf(adev))
                 adev->uvd.num_enc_rings = 1;
@@ -386,19 +397,21 @@ static int uvd_v7_0_sw_init(void *handle)
 {
         struct amdgpu_ring *ring;
         struct drm_sched_rq *rq;
-        int i, r;
+        int i, j, r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        /* UVD TRAP */
-        r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
-        if (r)
-                return r;
-
-        /* UVD ENC TRAP */
-        for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-                r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
+        for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+                /* UVD TRAP */
+                r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], 124, &adev->uvd.inst[j].irq);
                 if (r)
                         return r;
+
+                /* UVD ENC TRAP */
+                for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+                        r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + 119, &adev->uvd.inst[j].irq);
+                        if (r)
+                                return r;
+                }
         }
 
         r = amdgpu_uvd_sw_init(adev);
@@ -415,43 +428,48 @@ static int uvd_v7_0_sw_init(void *handle)
                 DRM_INFO("PSP loading UVD firmware\n");
         }
 
-        ring = &adev->uvd.ring_enc[0];
-        rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-        r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
-                                  rq, NULL);
-        if (r) {
-                DRM_ERROR("Failed setting up UVD ENC run queue.\n");
-                return r;
+        for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+                ring = &adev->uvd.inst[j].ring_enc[0];
+                rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
+                r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst[j].entity_enc,
+                                          rq, NULL);
+                if (r) {
+                        DRM_ERROR("(%d)Failed setting up UVD ENC run queue.\n", j);
+                        return r;
+                }
         }
 
         r = amdgpu_uvd_resume(adev);
         if (r)
                 return r;
-        if (!amdgpu_sriov_vf(adev)) {
-                ring = &adev->uvd.ring;
-                sprintf(ring->name, "uvd");
-                r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
-                if (r)
-                        return r;
-        }
 
-        for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-                ring = &adev->uvd.ring_enc[i];
-                sprintf(ring->name, "uvd_enc%d", i);
-                if (amdgpu_sriov_vf(adev)) {
-                        ring->use_doorbell = true;
-
-                        /* currently only use the first enconding ring for
-                         * sriov, so set unused location for other unused rings.
-                         */
-                        if (i == 0)
-                                ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
-                        else
-                                ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
+        for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+                if (!amdgpu_sriov_vf(adev)) {
+                        ring = &adev->uvd.inst[j].ring;
+                        sprintf(ring->name, "uvd<%d>", j);
+                        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
+                        if (r)
+                                return r;
+                }
+
+                for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+                        ring = &adev->uvd.inst[j].ring_enc[i];
+                        sprintf(ring->name, "uvd_enc%d<%d>", i, j);
+                        if (amdgpu_sriov_vf(adev)) {
+                                ring->use_doorbell = true;
+
+                                /* currently only use the first enconding ring for
+                                 * sriov, so set unused location for other unused rings.
+                                 */
+                                if (i == 0)
+                                        ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
+                                else
+                                        ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
+                        }
+                        r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
+                        if (r)
+                                return r;
                 }
-                r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
-                if (r)
-                        return r;
         }
 
         r = amdgpu_virt_alloc_mm_table(adev);
@@ -463,7 +481,7 @@ static int uvd_v7_0_sw_init(void *handle)
 
 static int uvd_v7_0_sw_fini(void *handle)
 {
-        int i, r;
+        int i, j, r;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
         amdgpu_virt_free_mm_table(adev);
@@ -472,11 +490,12 @@ static int uvd_v7_0_sw_fini(void *handle)
         if (r)
                 return r;
 
-        drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
-
-        for (i = 0; i < adev->uvd.num_enc_rings; ++i)
-                amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
+        for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+                drm_sched_entity_fini(&adev->uvd.inst[j].ring_enc[0].sched, &adev->uvd.inst[j].entity_enc);
 
+                for (i = 0; i < adev->uvd.num_enc_rings; ++i)
+                        amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
+        }
         return amdgpu_uvd_sw_fini(adev);
 }
 
@@ -490,9 +509,9 @@ static int uvd_v7_0_sw_fini(void *handle)
 static int uvd_v7_0_hw_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring;
         uint32_t tmp;
-        int i, r;
+        int i, j, r;
 
         if (amdgpu_sriov_vf(adev))
                 r = uvd_v7_0_sriov_start(adev);
@@ -501,57 +520,60 @@ static int uvd_v7_0_hw_init(void *handle)
         if (r)
                 goto done;
 
-        if (!amdgpu_sriov_vf(adev)) {
-                ring->ready = true;
-                r = amdgpu_ring_test_ring(ring);
-                if (r) {
-                        ring->ready = false;
-                        goto done;
-                }
-
-                r = amdgpu_ring_alloc(ring, 10);
-                if (r) {
-                        DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
-                        goto done;
+        for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
+                ring = &adev->uvd.inst[j].ring;
+
+                if (!amdgpu_sriov_vf(adev)) {
+                        ring->ready = true;
+                        r = amdgpu_ring_test_ring(ring);
+                        if (r) {
+                                ring->ready = false;
+                                goto done;
+                        }
+
+                        r = amdgpu_ring_alloc(ring, 10);
+                        if (r) {
+                                DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
+                                goto done;
+                        }
+
+                        tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
+                                mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
+                        amdgpu_ring_write(ring, tmp);
+                        amdgpu_ring_write(ring, 0xFFFFF);
+
+                        tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
+                                mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
+                        amdgpu_ring_write(ring, tmp);
+                        amdgpu_ring_write(ring, 0xFFFFF);
+
+                        tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
+                                mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
+                        amdgpu_ring_write(ring, tmp);
+                        amdgpu_ring_write(ring, 0xFFFFF);
+
+                        /* Clear timeout status bits */
+                        amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
+                                mmUVD_SEMA_TIMEOUT_STATUS), 0));
+                        amdgpu_ring_write(ring, 0x8);
+
+                        amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
+                                mmUVD_SEMA_CNTL), 0));
+                        amdgpu_ring_write(ring, 3);
+
+                        amdgpu_ring_commit(ring);
                 }
 
-                tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
-                        mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
-                amdgpu_ring_write(ring, tmp);
-                amdgpu_ring_write(ring, 0xFFFFF);
-
-                tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
-                        mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
-                amdgpu_ring_write(ring, tmp);
-                amdgpu_ring_write(ring, 0xFFFFF);
-
-                tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,
-                        mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
-                amdgpu_ring_write(ring, tmp);
-                amdgpu_ring_write(ring, 0xFFFFF);
-
-                /* Clear timeout status bits */
-                amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
-                        mmUVD_SEMA_TIMEOUT_STATUS), 0));
-                amdgpu_ring_write(ring, 0x8);
-
-                amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,
-                        mmUVD_SEMA_CNTL), 0));
-                amdgpu_ring_write(ring, 3);
-
-                amdgpu_ring_commit(ring);
-        }
-
-        for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-                ring = &adev->uvd.ring_enc[i];
-                ring->ready = true;
-                r = amdgpu_ring_test_ring(ring);
-                if (r) {
-                        ring->ready = false;
-                        goto done;
+                for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+                        ring = &adev->uvd.inst[j].ring_enc[i];
+                        ring->ready = true;
+                        r = amdgpu_ring_test_ring(ring);
+                        if (r) {
+                                ring->ready = false;
+                                goto done;
+                        }
                 }
         }
-
 done:
         if (!r)
                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
@@ -569,7 +591,7 @@ done:
 static int uvd_v7_0_hw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        int i;
 
         if (!amdgpu_sriov_vf(adev))
                 uvd_v7_0_stop(adev);
@@ -578,7 +600,8 @@ static int uvd_v7_0_hw_fini(void *handle)
                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
         }
 
-        ring->ready = false;
+        for (i = 0; i < adev->uvd.num_uvd_inst; ++i)
+                adev->uvd.inst[i].ring.ready = false;
 
         return 0;
 }
@@ -618,48 +641,51 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 {
         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
         uint32_t offset;
+        int i;
 
-        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-                WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
-                        lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
-                WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
-                        upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
-                offset = 0;
-        } else {
-                WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
-                        lower_32_bits(adev->uvd.gpu_addr));
-                WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
-                        upper_32_bits(adev->uvd.gpu_addr));
-                offset = size;
-        }
+        for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+                if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+                        WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+                                lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
+                        WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+                                upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
+                        offset = 0;
+                } else {
+                        WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
+                                lower_32_bits(adev->uvd.inst[i].gpu_addr));
+                        WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
+                                upper_32_bits(adev->uvd.inst[i].gpu_addr));
+                        offset = size;
+                }
 
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
-                                AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
-
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
-                        lower_32_bits(adev->uvd.gpu_addr + offset));
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
-                        upper_32_bits(adev->uvd.gpu_addr + offset));
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
-
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
-                        lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
-                        upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
-                        AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
-
-        WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
-                        adev->gfx.config.gb_addr_config);
-        WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
-                        adev->gfx.config.gb_addr_config);
-        WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
-                        adev->gfx.config.gb_addr_config);
-
-        WREG32_SOC15(UVD, 0, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
+                WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
+                                        AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+                WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
+
+                WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
+                                lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
+                WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
+                                upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
+                WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
+                WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
+
+                WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
+                                lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
+                WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
+                                upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
+                WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
+                WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
+                                AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
+
+                WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
+                                adev->gfx.config.gb_addr_config);
+                WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
+                                adev->gfx.config.gb_addr_config);
+                WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
+                                adev->gfx.config.gb_addr_config);
+
+                WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
+        }
 }
 
 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
@@ -669,6 +695,7 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
         uint64_t addr = table->gpu_addr;
         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
         uint32_t size;
+        int i;
 
         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 
@@ -688,11 +715,12 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
         /* 4, set resp to zero */
         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 
-        WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
-        adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
-        adev->uvd.ring_enc[0].wptr = 0;
-        adev->uvd.ring_enc[0].wptr_old = 0;
-
+        for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+                WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
+                adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
+                adev->uvd.inst[i].ring_enc[0].wptr = 0;
+                adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
+        }
         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 
@@ -725,6 +753,7 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
         struct mmsch_v1_0_cmd_end end = { {0} };
         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
+        uint8_t i = 0;
 
         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
@@ -742,120 +771,121 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 
                 init_table += header->uvd_table_offset;
 
-                ring = &adev->uvd.ring;
-                ring->wptr = 0;
-                size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
-
-                MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
-                                                   0xFFFFFFFF, 0x00000004);
-                /* mc resume*/
-                if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
-                                                    lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
-                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
-                                                    upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
-                        offset = 0;
-                } else {
-                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
-                                                    lower_32_bits(adev->uvd.gpu_addr));
-                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
-                                                    upper_32_bits(adev->uvd.gpu_addr));
-                        offset = size;
+                for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+                        ring = &adev->uvd.inst[i].ring;
+                        ring->wptr = 0;
+                        size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
+
+                        MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
+                                                           0xFFFFFFFF, 0x00000004);
+                        /* mc resume*/
+                        if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+                                                            lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+                                                            upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
+                                offset = 0;
+                        } else {
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+                                                            lower_32_bits(adev->uvd.inst[i].gpu_addr));
+                                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+                                                            upper_32_bits(adev->uvd.inst[i].gpu_addr));
+                                offset = size;
+                        }
+
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
+                                                    AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
+
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+                                                    lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+                                                    upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
+
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+                                                    lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+                                                    upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
+                                                    AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
+
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
+                        /* mc resume end*/
+
+                        /* disable clock gating */
+                        MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
+                                                           ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
+
+                        /* disable interupt */
+                        MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
+                                                           ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
+
+                        /* stall UMC and register bus before resetting VCPU */
+                        MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
+                                                           ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
+                                                           UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+                        /* put LMI, VCPU, RBC etc... into reset */
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
+                                                    (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
+                                                               UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
+                                                               UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
+                                                               UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
+                                                               UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
+                                                               UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
+                                                               UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
+                                                               UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
+
+                        /* initialize UVD memory controller */
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
+                                                    (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
+                                                               UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+                                                               UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+                                                               UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
+                                                               UVD_LMI_CTRL__REQ_MODE_MASK |
+                                                               0x00100000L));
+
+                        /* take all subblocks out of reset, except VCPU */
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
+                                                    UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+
+                        /* enable VCPU clock */
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
+                                                    UVD_VCPU_CNTL__CLK_EN_MASK);
+
+                        /* enable master interrupt */
+                        MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
+                                                           ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
+                                                           (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
+
+                        /* clear the bit 4 of UVD_STATUS */
+                        MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
+                                                           ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
+
+                        /* force RBC into idle state */
+                        size = order_base_2(ring->ring_size);
+                        tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
+                        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
+
+                        ring = &adev->uvd.inst[i].ring_enc[0];
+                        ring->wptr = 0;
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
+
+                        /* boot up the VCPU */
+                        MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
+
+                        /* enable UMC */
+                        MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
+                                                                                           ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
+
+                        MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
                 }
-
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
-                                            AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
-
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
-                                            lower_32_bits(adev->uvd.gpu_addr + offset));
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
-                                            upper_32_bits(adev->uvd.gpu_addr + offset));
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
-
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
-                                            lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
-                                            upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
-                                            AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
-
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
-                /* mc resume end*/
-
-                /* disable clock gating */
-                MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL),
-                                                   ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
-
-                /* disable interupt */
-                MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
-                                                   ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
-
-                /* stall UMC and register bus before resetting VCPU */
-                MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
-                                                   ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
-                                                   UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
-                /* put LMI, VCPU, RBC etc... into reset */
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
-                                            (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
-                                                       UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
-                                                       UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
-                                                       UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
-                                                       UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
-                                                       UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
-                                                       UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
-                                                       UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
-
-                /* initialize UVD memory controller */
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL),
-                                            (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
-                                                       UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
-                                                       UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
-                                                       UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
-                                                       UVD_LMI_CTRL__REQ_MODE_MASK |
-                                                       0x00100000L));
-
-                /* take all subblocks out of reset, except VCPU */
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
-                                            UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
-
-                /* enable VCPU clock */
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
-                                            UVD_VCPU_CNTL__CLK_EN_MASK);
-
-                /* enable master interrupt */
-                MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
-                                                   ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
-                                                   (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
-
-                /* clear the bit 4 of UVD_STATUS */
-                MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS),
-                                                   ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
-
-                /* force RBC into idle state */
-                size = order_base_2(ring->ring_size);
-                tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
-                tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp);
-
-                ring = &adev->uvd.ring_enc[0];
-                ring->wptr = 0;
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
-
-                /* boot up the VCPU */
-                MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0);
-
-                /* enable UMC */
-                MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
-                                                                                   ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
-
-                MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0x02, 0x02);
-
                 /* add end packet */
                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
@@ -874,15 +904,17 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
  */
 static int uvd_v7_0_start(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *ring = &adev->uvd.ring;
+        struct amdgpu_ring *ring;
         uint32_t rb_bufsz, tmp;
         uint32_t lmi_swap_cntl;
         uint32_t mp_swap_cntl;
-        int i, j, r;
+        int i, j, k, r;
 
-        /* disable DPG */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
-                        ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
+        for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
+                /* disable DPG */
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
+                                ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
+        }
 
         /* disable byte swapping */
         lmi_swap_cntl = 0;
@@ -890,157 +922,159 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
 
         uvd_v7_0_mc_resume(adev);
 
-        /* disable clock gating */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_CGC_CTRL), 0,
-                        ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
-
-        /* disable interupt */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
-                        ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
-        /* stall UMC and register bus before resetting VCPU */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
-                        UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
-                        ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-        mdelay(1);
-
-        /* put LMI, VCPU, RBC etc... into reset */
-        WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
-                UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
-                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
-                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
-                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
-                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
-                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
-                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
-                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
-        mdelay(5);
+        for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
+                ring = &adev->uvd.inst[k].ring;
+                /* disable clock gating */
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
+                                ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 
-        /* initialize UVD memory controller */
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
-                (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
-                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
-                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
-                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
-                UVD_LMI_CTRL__REQ_MODE_MASK |
-                0x00100000L);
+                /* disable interupt */
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
+                                ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+                /* stall UMC and register bus before resetting VCPU */
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
+                                UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
+                                ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+                mdelay(1);
+
+                /* put LMI, VCPU, RBC etc... into reset */
+                WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
+                        UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
+                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
+                        UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
+                        UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
+                        UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
+                        UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
+                        UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
+                        UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
+                mdelay(5);
+
+                /* initialize UVD memory controller */
+                WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
+                        (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
+                        UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+                        UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+                        UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
+                        UVD_LMI_CTRL__REQ_MODE_MASK |
+                        0x00100000L);
 
 #ifdef __BIG_ENDIAN
-        /* swap (8 in 32) RB and IB */
-        lmi_swap_cntl = 0xa;
-        mp_swap_cntl = 0;
+                /* swap (8 in 32) RB and IB */
+                lmi_swap_cntl = 0xa;
+                mp_swap_cntl = 0;
 #endif
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
-        WREG32_SOC15(UVD, 0, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
-
-        WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
-        WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
-        WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
-        WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
-        WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
-        WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
-
-        /* take all subblocks out of reset, except VCPU */
-        WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
-                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
-        mdelay(5);
+                WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
+                WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 
-        /* enable VCPU clock */
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
-                        UVD_VCPU_CNTL__CLK_EN_MASK);
+                WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
+                WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
+                WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
+                WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
+                WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
+                WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
 
-        /* enable UMC */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
-                        ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+                /* take all subblocks out of reset, except VCPU */
+                WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
+                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+                mdelay(5);
+
+                /* enable VCPU clock */
+                WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
+                                UVD_VCPU_CNTL__CLK_EN_MASK);
+
+                /* enable UMC */
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
+                                ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 
-        /* boot up the VCPU */
-        WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
-        mdelay(10);
+                /* boot up the VCPU */
+                WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
+                mdelay(10);
 
-        for (i = 0; i < 10; ++i) {
-                uint32_t status;
+                for (i = 0; i < 10; ++i) {
+                        uint32_t status;
 
-                for (j = 0; j < 100; ++j) {
-                        status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
+                        for (j = 0; j < 100; ++j) {
+                                status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
+                                if (status & 2)
+                                        break;
+                                mdelay(10);
+                        }
+                        r = 0;
                         if (status & 2)
                                 break;
+
+                        DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
+                        WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
+                                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
+                                        ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
                         mdelay(10);
+                        WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
+                                        ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+                        mdelay(10);
+                        r = -1;
                 }
-                r = 0;
-                if (status & 2)
-                        break;
-
-                DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
-                WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
-                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
-                                ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
-                mdelay(10);
-                WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
-                                ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
-                mdelay(10);
-                r = -1;
-        }
 
-        if (r) {
-                DRM_ERROR("UVD not responding, giving up!!!\n");
-                return r;
-        }
-        /* enable master interrupt */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
-                (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
-                ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
-
-        /* clear the bit 4 of UVD_STATUS */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
-                        ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
-
-        /* force RBC into idle state */
-        rb_bufsz = order_base_2(ring->ring_size);
-        tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
-        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
-        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
-        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
-        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
-        tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
-        WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
-
-        /* set the write pointer delay */
-        WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
-
-        /* set the wb address */
-        WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
-                        (upper_32_bits(ring->gpu_addr) >> 2));
-
-        /* programm the RB_BASE for ring buffer */
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
-                        lower_32_bits(ring->gpu_addr));
-        WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
-                        upper_32_bits(ring->gpu_addr));
-
-        /* Initialize the ring buffer's read and write pointers */
-        WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
-
-        ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
-        WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
-                        lower_32_bits(ring->wptr));
-
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
-                        ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
-
-        ring = &adev->uvd.ring_enc[0];
-        WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
-        WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
-        WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
-        WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
-        WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
+                if (r) {
+                        DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
+                        return r;
+                }
+                /* enable master interrupt */
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
+                        (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
+                        ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 
-        ring = &adev->uvd.ring_enc[1];
-        WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
-        WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
-        WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
-        WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
-        WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
+                /* clear the bit 4 of UVD_STATUS */
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
+                                ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 
+                /* force RBC into idle state */
+                rb_bufsz = order_base_2(ring->ring_size);
+                tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+                tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+                tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+                tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
+                tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+                tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+                WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
+
+                /* set the write pointer delay */
+                WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
+
+                /* set the wb address */
+                WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
+                                (upper_32_bits(ring->gpu_addr) >> 2));
+
+                /* programm the RB_BASE for ring buffer */
+                WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
+                                lower_32_bits(ring->gpu_addr));
+                WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
+                                upper_32_bits(ring->gpu_addr));
+
+                /* Initialize the ring buffer's read and write pointers */
+                WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
+
+                ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
+                WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
+                                lower_32_bits(ring->wptr));
+
+                WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
+                                ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
+
+                ring = &adev->uvd.inst[k].ring_enc[0];
+                WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+                WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+                WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
+                WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+                WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
+
+                ring = &adev->uvd.inst[k].ring_enc[1];
+                WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+                WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+                WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+                WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+                WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
+        }
         return 0;
 }
 
@@ -1053,26 +1087,30 @@ static int uvd_v7_0_start(struct amdgpu_device *adev)
  */
 static void uvd_v7_0_stop(struct amdgpu_device *adev)
 {
-        /* force RBC into idle state */
-        WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
-
-        /* Stall UMC and register bus before resetting VCPU */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
-                        UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
-                        ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-        mdelay(1);
-
-        /* put VCPU into reset */
-        WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
-                        UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
-        mdelay(5);
+        uint8_t i = 0;
 
-        /* disable VCPU clock */
-        WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
+        for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
+                /* force RBC into idle state */
+                WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
+
+                /* Stall UMC and register bus before resetting VCPU */
+                WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
+                                UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
+                                ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+                mdelay(1);
+
+                /* put VCPU into reset */
+                WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
+                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
+                mdelay(5);
 
-        /* Unstall UMC and register bus */
-        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
-                        ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+                /* disable VCPU clock */
+                WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
+
+                /* Unstall UMC and register bus */
+                WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
+                                ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+        }
 }
 
 /**
@@ -1091,26 +1129,26 @@ static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq
         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
         amdgpu_ring_write(ring, seq);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
         amdgpu_ring_write(ring, addr & 0xffffffff);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
         amdgpu_ring_write(ring, 0);
 
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
         amdgpu_ring_write(ring, 0);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
         amdgpu_ring_write(ring, 0);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
         amdgpu_ring_write(ring, 2);
 }
 
@@ -1159,30 +1197,30 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
         unsigned i;
         int r;
 
-        WREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
+        WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
         r = amdgpu_ring_alloc(ring, 3);
         if (r) {
-                DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
-                          ring->idx, r);
+                DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n",
+                          ring->me, ring->idx, r);
                 return r;
         }
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
         amdgpu_ring_write(ring, 0xDEADBEEF);
         amdgpu_ring_commit(ring);
         for (i = 0; i < adev->usec_timeout; i++) {
-                tmp = RREG32_SOC15(UVD, 0, mmUVD_CONTEXT_ID);
+                tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
                 if (tmp == 0xDEADBEEF)
                         break;
                 DRM_UDELAY(1);
         }
 
         if (i < adev->usec_timeout) {
-                DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
-                         ring->idx, i);
+                DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
+                         ring->me, ring->idx, i);
         } else {
-                DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
-                          ring->idx, tmp);
+                DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n",
+                          ring->me, ring->idx, tmp);
                 r = -EINVAL;
         }
         return r;
@@ -1203,17 +1241,17 @@ static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
         struct amdgpu_device *adev = ring->adev;
 
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
         amdgpu_ring_write(ring, vmid);
 
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
         amdgpu_ring_write(ring, ib->length_dw);
 }
 
@@ -1241,13 +1279,13 @@ static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
         struct amdgpu_device *adev = ring->adev;
 
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
         amdgpu_ring_write(ring, reg << 2);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
         amdgpu_ring_write(ring, val);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
         amdgpu_ring_write(ring, 8);
 }
 
@@ -1257,16 +1295,16 @@ static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
         struct amdgpu_device *adev = ring->adev;
 
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
         amdgpu_ring_write(ring, reg << 2);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
         amdgpu_ring_write(ring, val);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
         amdgpu_ring_write(ring, mask);
         amdgpu_ring_write(ring,
-                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
+                PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
         amdgpu_ring_write(ring, 12);
 }
 
@@ -1287,12 +1325,15 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 {
-        int i;
         struct amdgpu_device *adev = ring->adev;
+        int i;
 
-        for (i = 0; i < count; i++)
-                amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
+        WARN_ON(ring->wptr % 2 || count % 2);
 
+        for (i = 0; i < count / 2; i++) {
+                amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
+                amdgpu_ring_write(ring, 0);
+        }
 }
 
 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
@@ -1359,16 +1400,16 @@ static bool uvd_v7_0_check_soft_reset(void *handle)
 
         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
-            (RREG32_SOC15(UVD, 0, mmUVD_STATUS) &
+            (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
                     AMDGPU_UVD_STATUS_BUSY_MASK))
                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
 
         if (srbm_soft_reset) {
-                adev->uvd.srbm_soft_reset = srbm_soft_reset;
+                adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
                 return true;
         } else {
-                adev->uvd.srbm_soft_reset = 0;
+                adev->uvd.inst[ring->me].srbm_soft_reset = 0;
                 return false;
         }
 }
@@ -1377,7 +1418,7 @@ static int uvd_v7_0_pre_soft_reset(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (!adev->uvd.srbm_soft_reset)
+        if (!adev->uvd.inst[ring->me].srbm_soft_reset)
                 return 0;
 
         uvd_v7_0_stop(adev);
@@ -1389,9 +1430,9 @@ static int uvd_v7_0_soft_reset(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         u32 srbm_soft_reset;
 
-        if (!adev->uvd.srbm_soft_reset)
+        if (!adev->uvd.inst[ring->me].srbm_soft_reset)
                 return 0;
-        srbm_soft_reset = adev->uvd.srbm_soft_reset;
+        srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
 
         if (srbm_soft_reset) {
                 u32 tmp;
@@ -1419,7 +1460,7 @@ static int uvd_v7_0_post_soft_reset(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-        if (!adev->uvd.srbm_soft_reset)
+        if (!adev->uvd.inst[ring->me].srbm_soft_reset)
                 return 0;
 
         mdelay(5);
@@ -1441,17 +1482,32 @@ static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
                                       struct amdgpu_irq_src *source,
                                       struct amdgpu_iv_entry *entry)
 {
+        uint32_t ip_instance;
+
+        switch (entry->client_id) {
+        case SOC15_IH_CLIENTID_UVD:
+                ip_instance = 0;
+                break;
+        case SOC15_IH_CLIENTID_UVD1:
+                ip_instance = 1;
+                break;
+        default:
+                DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
+                return 0;
+        }
+
         DRM_DEBUG("IH: UVD TRAP\n");
+
         switch (entry->src_id) {
         case 124:
-                amdgpu_fence_process(&adev->uvd.ring);
+                amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
                 break;
         case 119:
-                amdgpu_fence_process(&adev->uvd.ring_enc[0]);
+                amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
                 break;
         case 120:
                 if (!amdgpu_sriov_vf(adev))
-                        amdgpu_fence_process(&adev->uvd.ring_enc[1]);
+                        amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
                 break;
         default:
                 DRM_ERROR("Unhandled interrupt: %d %d\n",
@@ -1467,9 +1523,9 @@ static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
 {
         uint32_t data, data1, data2, suvd_flags;
 
-        data = RREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL);
-        data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
-        data2 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL);
+        data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
+        data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
+        data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
 
         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
@@ -1513,18 +1569,18 @@ static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
         data1 |= suvd_flags;
 
-        WREG32_SOC15(UVD, 0, mmUVD_CGC_CTRL, data);
-        WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, 0);
-        WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
-        WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_CTRL, data2);
+        WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
+        WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
+        WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
+        WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
 }
 
 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
 {
         uint32_t data, data1, cgc_flags, suvd_flags;
 
-        data = RREG32_SOC15(UVD, 0, mmUVD_CGC_GATE);
-        data1 = RREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE);
+        data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
+        data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
 
         cgc_flags = UVD_CGC_GATE__SYS_MASK |
                 UVD_CGC_GATE__UDEC_MASK |
@@ -1556,8 +1612,8 @@ static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
         data |= cgc_flags;
         data1 |= suvd_flags;
 
-        WREG32_SOC15(UVD, 0, mmUVD_CGC_GATE, data);
-        WREG32_SOC15(UVD, 0, mmUVD_SUVD_CGC_GATE, data1);
+        WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
+        WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
 }
 
 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
@@ -1616,7 +1672,7 @@ static int uvd_v7_0_set_powergating_state(void *handle,
         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
                 return 0;
 
-        WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
+        WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
 
         if (state == AMD_PG_STATE_GATE) {
                 uvd_v7_0_stop(adev);
@@ -1657,7 +1713,6 @@ const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
         .type = AMDGPU_RING_TYPE_UVD,
         .align_mask = 0xf,
-        .nop = PACKET0(0x81ff, 0),
         .support_64bit_ptrs = false,
         .vmhub = AMDGPU_MMHUB,
         .get_rptr = uvd_v7_0_ring_get_rptr,
@@ -1719,18 +1774,27 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
 
 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.ring.funcs = &uvd_v7_0_ring_vm_funcs;
-        DRM_INFO("UVD is enabled in VM mode\n");
+        int i;
+
+        for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+                adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
+                adev->uvd.inst[i].ring.me = i;
+                DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
+        }
 }
 
 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
 {
-        int i;
+        int i, j;
 
-        for (i = 0; i < adev->uvd.num_enc_rings; ++i)
-                adev->uvd.ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
+        for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+                for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+                        adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
+                        adev->uvd.inst[j].ring_enc[i].me = j;
+                }
 
-        DRM_INFO("UVD ENC is enabled in VM mode\n");
+                DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
+        }
 }
 
 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
@@ -1740,8 +1804,12 @@ static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
 
 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
-        adev->uvd.irq.funcs = &uvd_v7_0_irq_funcs;
+        int i;
+
+        for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
+                adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
+                adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
+        }
 }
 
 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 0501746b6c2c..110b294ebed3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -35,7 +35,6 @@
 #include "mmhub/mmhub_9_1_offset.h"
 #include "mmhub/mmhub_9_1_sh_mask.h"
 
-static int vcn_v1_0_start(struct amdgpu_device *adev);
 static int vcn_v1_0_stop(struct amdgpu_device *adev);
 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
@@ -146,10 +145,6 @@ static int vcn_v1_0_hw_init(void *handle)
         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
         int i, r;
 
-        r = vcn_v1_0_start(adev);
-        if (r)
-                goto done;
-
         ring->ready = true;
         r = amdgpu_ring_test_ring(ring);
         if (r) {
@@ -185,11 +180,9 @@ static int vcn_v1_0_hw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         struct amdgpu_ring *ring = &adev->vcn.ring_dec;
-        int r;
 
-        r = vcn_v1_0_stop(adev);
-        if (r)
-                return r;
+        if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
+                vcn_v1_0_stop(adev);
 
         ring->ready = false;
 
@@ -288,14 +281,14 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
  *
  * Disable clock gating for VCN block
  */
-static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw)
+static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 {
         uint32_t data;
 
         /* JPEG disable CGC */
         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 
-        if (sw)
+        if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
         else
                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
@@ -310,7 +303,7 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw)
 
         /* UVD disable CGC */
         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
-        if (sw)
+        if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
         else
                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
@@ -415,13 +408,13 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw)
  *
  * Enable clock gating for VCN block
  */
-static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw)
+static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 {
         uint32_t data = 0;
 
         /* enable JPEG CGC */
         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
-        if (sw)
+        if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
         else
                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
@@ -435,7 +428,7 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw)
 
         /* enable UVD CGC */
         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
-        if (sw)
+        if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
         else
                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
@@ -480,6 +473,94 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw)
         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 }
 
+static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
+{
+        uint32_t data = 0;
+        int ret;
+
+        if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+                data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
+
+                WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
+                SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
+        } else {
+                data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
+                        | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
+                WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
+                SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
+        }
+
+        /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
+
+        data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
+        data &= ~0x103;
+        if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
+                data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
+
+        WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
+}
+
+static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
+{
+        uint32_t data = 0;
+        int ret;
+
+        if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+                /* Before power off, this indicator has to be turned on */
+                data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
+                data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
+                data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
+                WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
+
+
+                data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
+                        | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
+
+                WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
+
+                data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
+                        | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
+                SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
+        }
+}
+
 /**
  * vcn_v1_0_start - start VCN block
  *
@@ -499,8 +580,9 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
 
         vcn_v1_0_mc_resume(adev);
 
+        vcn_1_0_disable_static_power_gating(adev);
         /* disable clock gating */
-        vcn_v1_0_disable_clock_gating(adev, true);
+        vcn_v1_0_disable_clock_gating(adev);
 
         /* disable interupt */
         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
@@ -680,16 +762,45 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev)
         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 
-        /* enable clock gating */
-        vcn_v1_0_enable_clock_gating(adev, true);
+        WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
 
+        vcn_v1_0_enable_clock_gating(adev);
+        vcn_1_0_enable_static_power_gating(adev);
         return 0;
 }
 
+bool vcn_v1_0_is_idle(void *handle)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2);
+}
+
+int vcn_v1_0_wait_for_idle(void *handle)
+{
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int ret = 0;
+
+        SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret);
+
+        return ret;
+}
+
 static int vcn_v1_0_set_clockgating_state(void *handle,
                                           enum amd_clockgating_state state)
 {
-        /* needed for driver unload*/
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+
+        if (enable) {
+                /* wait for STATUS to clear */
+                if (vcn_v1_0_is_idle(handle))
+                        return -EBUSY;
+                vcn_v1_0_enable_clock_gating(adev);
+        } else {
+                /* disable HW gating and enable Sw gating */
+                vcn_v1_0_disable_clock_gating(adev);
+        }
         return 0;
 }
 
@@ -1048,16 +1159,36 @@ static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
         return 0;
 }
 
-static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
+static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 {
-        int i;
         struct amdgpu_device *adev = ring->adev;
+        int i;
 
-        for (i = 0; i < count; i++)
-                amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
+        WARN_ON(ring->wptr % 2 || count % 2);
 
+        for (i = 0; i < count / 2; i++) {
+                amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
+                amdgpu_ring_write(ring, 0);
+        }
 }
 
+static int vcn_v1_0_set_powergating_state(void *handle,
+                                          enum amd_powergating_state state)
+{
+        /* This doesn't actually powergate the VCN block.
+         * That's done in the dpm code via the SMC.  This
+         * just re-inits the block as necessary.  The actual
+         * gating still happens in the dpm code.  We should
+         * revisit this when there is a cleaner line between
+         * the smc and the hw blocks
+         */
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        if (state == AMD_PG_STATE_GATE)
+                return vcn_v1_0_stop(adev);
+        else
+                return vcn_v1_0_start(adev);
+}
 
 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
         .name = "vcn_v1_0",
@@ -1069,20 +1200,19 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
         .hw_fini = vcn_v1_0_hw_fini,
         .suspend = vcn_v1_0_suspend,
         .resume = vcn_v1_0_resume,
-        .is_idle = NULL /* vcn_v1_0_is_idle */,
-        .wait_for_idle = NULL /* vcn_v1_0_wait_for_idle */,
+        .is_idle = vcn_v1_0_is_idle,
+        .wait_for_idle = vcn_v1_0_wait_for_idle,
         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
-        .set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */,
+        .set_powergating_state = vcn_v1_0_set_powergating_state,
 };
 
 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
         .type = AMDGPU_RING_TYPE_VCN_DEC,
         .align_mask = 0xf,
-        .nop = PACKET0(0x81ff, 0),
         .support_64bit_ptrs = false,
         .vmhub = AMDGPU_MMHUB,
         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
@@ -1101,7 +1231,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
         .test_ring = amdgpu_vcn_dec_ring_test_ring,
         .test_ib = amdgpu_vcn_dec_ring_test_ib,
-        .insert_nop = vcn_v1_0_ring_insert_nop,
+        .insert_nop = vcn_v1_0_dec_ring_insert_nop,
         .insert_start = vcn_v1_0_dec_ring_insert_start,
         .insert_end = vcn_v1_0_dec_ring_insert_end,
         .pad_ib = amdgpu_ring_generic_pad_ib,
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
new file mode 100644
index 000000000000..52778de93ab0
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "soc15.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "vega20_ip_offset.h"
+
+int vega20_reg_base_init(struct amdgpu_device *adev)
+{
+        /* HW has more IP blocks,  only initialized the blocke beend by our driver  */
+        uint32_t i;
+        for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+                adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+                adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+                adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+                adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+                adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+                adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+                adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
+                adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
+                adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+                adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
+                adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+                adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
+                adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
+                adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+        }
+        return 0;
+}
+
+
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index e6ca72c0d347..d5d4586e6176 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -34,10 +34,4 @@ config DEBUG_KERNEL_DC
           if you want to hit
           kdgb_break in assert.
 
-config DRM_AMD_DC_VEGAM
-        bool "VEGAM support"
-        depends on DRM_AMD_DC
-        help
-         Choose this option if you want to have
-         VEGAM support for display engine
 endmenu
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f2f54a9df56f..1ce10bc2d37b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -911,6 +911,7 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
                 drm_mode_connector_update_edid_property(connector, NULL);
                 aconnector->num_modes = 0;
                 aconnector->dc_sink = NULL;
+                aconnector->edid = NULL;
         }
 
         mutex_unlock(&dev->mode_config.mutex);
@@ -1115,6 +1116,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
 
         if (adev->asic_type == CHIP_VEGA10 ||
             adev->asic_type == CHIP_VEGA12 ||
+            adev->asic_type == CHIP_VEGA20 ||
             adev->asic_type == CHIP_RAVEN)
                 client_id = SOC15_IH_CLIENTID_DCE;
 
@@ -1513,11 +1515,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
         case CHIP_POLARIS11:
         case CHIP_POLARIS10:
         case CHIP_POLARIS12:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case CHIP_VEGAM:
-#endif
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 if (dce110_register_irq_handlers(dm->adev)) {
                         DRM_ERROR("DM: Failed to initialize IRQ\n");
                         goto fail;
@@ -1708,9 +1709,7 @@ static int dm_early_init(void *handle)
                 adev->mode_info.plane_type = dm_plane_type_default;
                 break;
         case CHIP_POLARIS10:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case CHIP_VEGAM:
-#endif
                 adev->mode_info.num_crtc = 6;
                 adev->mode_info.num_hpd = 6;
                 adev->mode_info.num_dig = 6;
@@ -1718,6 +1717,7 @@ static int dm_early_init(void *handle)
                 break;
         case CHIP_VEGA10:
         case CHIP_VEGA12:
+        case CHIP_VEGA20:
                 adev->mode_info.num_crtc = 6;
                 adev->mode_info.num_hpd = 6;
                 adev->mode_info.num_dig = 6;
@@ -1966,6 +1966,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
 
         if (adev->asic_type == CHIP_VEGA10 ||
             adev->asic_type == CHIP_VEGA12 ||
+            adev->asic_type == CHIP_VEGA20 ||
             adev->asic_type == CHIP_RAVEN) {
                 /* Fill GFX9 params */
                 plane_state->tiling_info.gfx9.num_pipes =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index e3d90e918d1b..b329393307e5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -88,9 +88,9 @@ static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut,
                         g = drm_color_lut_extract(lut[i].green, 16);
                         b = drm_color_lut_extract(lut[i].blue, 16);
 
-                        gamma->entries.red[i] = dal_fixed31_32_from_int(r);
-                        gamma->entries.green[i] = dal_fixed31_32_from_int(g);
-                        gamma->entries.blue[i] = dal_fixed31_32_from_int(b);
+                        gamma->entries.red[i] = dc_fixpt_from_int(r);
+                        gamma->entries.green[i] = dc_fixpt_from_int(g);
+                        gamma->entries.blue[i] = dc_fixpt_from_int(b);
                 }
                 return;
         }
@@ -101,9 +101,9 @@ static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut,
                 g = drm_color_lut_extract(lut[i].green, 16);
                 b = drm_color_lut_extract(lut[i].blue, 16);
 
-                gamma->entries.red[i] = dal_fixed31_32_from_fraction(r, MAX_DRM_LUT_VALUE);
-                gamma->entries.green[i] = dal_fixed31_32_from_fraction(g, MAX_DRM_LUT_VALUE);
-                gamma->entries.blue[i] = dal_fixed31_32_from_fraction(b, MAX_DRM_LUT_VALUE);
+                gamma->entries.red[i] = dc_fixpt_from_fraction(r, MAX_DRM_LUT_VALUE);
+                gamma->entries.green[i] = dc_fixpt_from_fraction(g, MAX_DRM_LUT_VALUE);
+                gamma->entries.blue[i] = dc_fixpt_from_fraction(b, MAX_DRM_LUT_VALUE);
         }
 }
 
@@ -208,7 +208,7 @@ void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc)
         for (i = 0; i < 12; i++) {
                 /* Skip 4th element */
                 if (i % 4 == 3) {
-                        stream->gamut_remap_matrix.matrix[i] = dal_fixed31_32_zero;
+                        stream->gamut_remap_matrix.matrix[i] = dc_fixpt_zero;
                         continue;
                 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index ca0b08bfa2cf..bd449351803f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -330,11 +330,6 @@ bool dm_helpers_dp_mst_send_payload_allocation(
         return true;
 }
 
-bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, enum dc_log_type event)
-{
-        return true;
-}
-
 void dm_dtn_log_begin(struct dc_context *ctx)
 {}
 
diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile b/drivers/gpu/drm/amd/display/dc/basics/Makefile
index bca33bd9a0d2..b49ea96b5dae 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile
@@ -24,7 +24,7 @@
 # It provides the general basic services required by other DAL
 # subcomponents.
 
-BASICS = conversion.o fixpt31_32.o fixpt32_32.o \
+BASICS = conversion.o fixpt31_32.o \
         logger.o log_helpers.o vector.o
 
 AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
index 310964915a83..50b47f11875c 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/conversion.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
@@ -41,22 +41,22 @@ uint16_t fixed_point_to_int_frac(
 
         uint16_t result;
 
-        uint16_t d = (uint16_t)dal_fixed31_32_floor(
-                dal_fixed31_32_abs(
+        uint16_t d = (uint16_t)dc_fixpt_floor(
+                dc_fixpt_abs(
                         arg));
 
         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
-                numerator = (uint16_t)dal_fixed31_32_round(
-                        dal_fixed31_32_mul_int(
+                numerator = (uint16_t)dc_fixpt_round(
+                        dc_fixpt_mul_int(
                                 arg,
                                 divisor));
         else {
-                numerator = dal_fixed31_32_floor(
-                        dal_fixed31_32_sub(
-                                dal_fixed31_32_from_int(
+                numerator = dc_fixpt_floor(
+                        dc_fixpt_sub(
+                                dc_fixpt_from_int(
                                         1LL << integer_bits),
-                                dal_fixed31_32_recip(
-                                        dal_fixed31_32_from_int(
+                                dc_fixpt_recip(
+                                        dc_fixpt_from_int(
                                                 divisor))));
         }
 
@@ -66,8 +66,8 @@ uint16_t fixed_point_to_int_frac(
                 result = (uint16_t)(
                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
 
-        if ((result != 0) && dal_fixed31_32_lt(
-                arg, dal_fixed31_32_zero))
+        if ((result != 0) && dc_fixpt_lt(
+                arg, dc_fixpt_zero))
                 result |= 1 << (integer_bits + fractional_bits);
 
         return result;
@@ -84,15 +84,15 @@ void convert_float_matrix(
         uint32_t buffer_size)
 {
         const struct fixed31_32 min_2_13 =
-                dal_fixed31_32_from_fraction(S2D13_MIN, DIVIDER);
+                dc_fixpt_from_fraction(S2D13_MIN, DIVIDER);
         const struct fixed31_32 max_2_13 =
-                dal_fixed31_32_from_fraction(S2D13_MAX, DIVIDER);
+                dc_fixpt_from_fraction(S2D13_MAX, DIVIDER);
         uint32_t i;
 
         for (i = 0; i < buffer_size; ++i) {
                 uint32_t reg_value =
                                 fixed_point_to_int_frac(
-                                        dal_fixed31_32_clamp(
+                                        dc_fixpt_clamp(
                                                 flt[i],
                                                 min_2_13,
                                                 max_2_13),
diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 7191c3213743..e61dd97d0928 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -64,9 +64,7 @@ static inline unsigned long long complete_integer_division_u64(
 #define GET_FRACTIONAL_PART(x) \
         (FRACTIONAL_PART_MASK & (x))
 
-struct fixed31_32 dal_fixed31_32_from_fraction(
-        long long numerator,
-        long long denominator)
+struct fixed31_32 dc_fixpt_from_fraction(long long numerator, long long denominator)
 {
         struct fixed31_32 res;
 
@@ -118,63 +116,7 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
         return res;
 }
 
-struct fixed31_32 dal_fixed31_32_from_int_nonconst(
-        long long arg)
-{
-        struct fixed31_32 res;
-
-        ASSERT((LONG_MIN <= arg) && (arg <= LONG_MAX));
-
-        res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
-
-        return res;
-}
-
-struct fixed31_32 dal_fixed31_32_shl(
-        struct fixed31_32 arg,
-        unsigned char shift)
-{
-        struct fixed31_32 res;
-
-        ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
-                ((arg.value < 0) && (arg.value >= LLONG_MIN >> shift)));
-
-        res.value = arg.value << shift;
-
-        return res;
-}
-
-struct fixed31_32 dal_fixed31_32_add(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2)
-{
-        struct fixed31_32 res;
-
-        ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
-                ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
-
-        res.value = arg1.value + arg2.value;
-
-        return res;
-}
-
-struct fixed31_32 dal_fixed31_32_sub(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2)
-{
-        struct fixed31_32 res;
-
-        ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
-                ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
-
-        res.value = arg1.value - arg2.value;
-
-        return res;
-}
-
-struct fixed31_32 dal_fixed31_32_mul(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2)
+struct fixed31_32 dc_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
         struct fixed31_32 res;
 
@@ -213,7 +155,7 @@ struct fixed31_32 dal_fixed31_32_mul(
         tmp = arg1_fra * arg2_fra;
 
         tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
-                (tmp >= (unsigned long long)dal_fixed31_32_half.value);
+                (tmp >= (unsigned long long)dc_fixpt_half.value);
 
         ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
 
@@ -225,8 +167,7 @@ struct fixed31_32 dal_fixed31_32_mul(
         return res;
 }
 
-struct fixed31_32 dal_fixed31_32_sqr(
-        struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg)
 {
         struct fixed31_32 res;
 
@@ -257,7 +198,7 @@ struct fixed31_32 dal_fixed31_32_sqr(
         tmp = arg_fra * arg_fra;
 
         tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
-                (tmp >= (unsigned long long)dal_fixed31_32_half.value);
+                (tmp >= (unsigned long long)dc_fixpt_half.value);
 
         ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
 
@@ -266,8 +207,7 @@ struct fixed31_32 dal_fixed31_32_sqr(
         return res;
 }
 
-struct fixed31_32 dal_fixed31_32_recip(
-        struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_recip(struct fixed31_32 arg)
 {
         /*
          * @note
@@ -276,41 +216,40 @@ struct fixed31_32 dal_fixed31_32_recip(
 
         ASSERT(arg.value);
 
-        return dal_fixed31_32_from_fraction(
-                dal_fixed31_32_one.value,
+        return dc_fixpt_from_fraction(
+                dc_fixpt_one.value,
                 arg.value);
 }
 
-struct fixed31_32 dal_fixed31_32_sinc(
-        struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_sinc(struct fixed31_32 arg)
 {
         struct fixed31_32 square;
 
-        struct fixed31_32 res = dal_fixed31_32_one;
+        struct fixed31_32 res = dc_fixpt_one;
 
         int n = 27;
 
         struct fixed31_32 arg_norm = arg;
 
-        if (dal_fixed31_32_le(
-                dal_fixed31_32_two_pi,
-                dal_fixed31_32_abs(arg))) {
-                arg_norm = dal_fixed31_32_sub(
+        if (dc_fixpt_le(
+                dc_fixpt_two_pi,
+                dc_fixpt_abs(arg))) {
+                arg_norm = dc_fixpt_sub(
                         arg_norm,
-                        dal_fixed31_32_mul_int(
-                                dal_fixed31_32_two_pi,
+                        dc_fixpt_mul_int(
+                                dc_fixpt_two_pi,
                                 (int)div64_s64(
                                         arg_norm.value,
-                                        dal_fixed31_32_two_pi.value)));
+                                        dc_fixpt_two_pi.value)));
         }
 
-        square = dal_fixed31_32_sqr(arg_norm);
+        square = dc_fixpt_sqr(arg_norm);
 
         do {
-                res = dal_fixed31_32_sub(
-                        dal_fixed31_32_one,
-                        dal_fixed31_32_div_int(
-                                dal_fixed31_32_mul(
+                res = dc_fixpt_sub(
+                        dc_fixpt_one,
+                        dc_fixpt_div_int(
+                                dc_fixpt_mul(
                                         square,
                                         res),
                                 n * (n - 1)));
@@ -319,37 +258,35 @@ struct fixed31_32 dal_fixed31_32_sinc(
         } while (n > 2);
 
         if (arg.value != arg_norm.value)
-                res = dal_fixed31_32_div(
-                        dal_fixed31_32_mul(res, arg_norm),
+                res = dc_fixpt_div(
+                        dc_fixpt_mul(res, arg_norm),
                         arg);
 
         return res;
 }
 
-struct fixed31_32 dal_fixed31_32_sin(
-        struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_sin(struct fixed31_32 arg)
 {
-        return dal_fixed31_32_mul(
+        return dc_fixpt_mul(
                 arg,
-                dal_fixed31_32_sinc(arg));
+                dc_fixpt_sinc(arg));
 }
 
-struct fixed31_32 dal_fixed31_32_cos(
-        struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_cos(struct fixed31_32 arg)
 {
         /* TODO implement argument normalization */
 
-        const struct fixed31_32 square = dal_fixed31_32_sqr(arg);
+        const struct fixed31_32 square = dc_fixpt_sqr(arg);
 
-        struct fixed31_32 res = dal_fixed31_32_one;
+        struct fixed31_32 res = dc_fixpt_one;
 
         int n = 26;
 
         do {
-                res = dal_fixed31_32_sub(
-                        dal_fixed31_32_one,
-                        dal_fixed31_32_div_int(
-                                dal_fixed31_32_mul(
+                res = dc_fixpt_sub(
+                        dc_fixpt_one,
+                        dc_fixpt_div_int(
+                                dc_fixpt_mul(
                                         square,
                                         res),
                                 n * (n - 1)));
@@ -367,37 +304,35 @@ struct fixed31_32 dal_fixed31_32_cos(
  *
  * Calculated as Taylor series.
  */
-static struct fixed31_32 fixed31_32_exp_from_taylor_series(
-        struct fixed31_32 arg)
+static struct fixed31_32 fixed31_32_exp_from_taylor_series(struct fixed31_32 arg)
 {
         unsigned int n = 9;
 
-        struct fixed31_32 res = dal_fixed31_32_from_fraction(
+        struct fixed31_32 res = dc_fixpt_from_fraction(
                 n + 2,
                 n + 1);
         /* TODO find correct res */
 
-        ASSERT(dal_fixed31_32_lt(arg, dal_fixed31_32_one));
+        ASSERT(dc_fixpt_lt(arg, dc_fixpt_one));
 
         do
-                res = dal_fixed31_32_add(
-                        dal_fixed31_32_one,
-                        dal_fixed31_32_div_int(
-                                dal_fixed31_32_mul(
+                res = dc_fixpt_add(
+                        dc_fixpt_one,
+                        dc_fixpt_div_int(
+                                dc_fixpt_mul(
                                         arg,
                                         res),
                                 n));
         while (--n != 1);
 
-        return dal_fixed31_32_add(
-                dal_fixed31_32_one,
-                dal_fixed31_32_mul(
+        return dc_fixpt_add(
+                dc_fixpt_one,
+                dc_fixpt_mul(
                         arg,
                         res));
 }
 
-struct fixed31_32 dal_fixed31_32_exp(
-        struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_exp(struct fixed31_32 arg)
 {
         /*
          * @brief
@@ -406,44 +341,43 @@ struct fixed31_32 dal_fixed31_32_exp(
          * where m = round(x / ln(2)), r = x - m * ln(2)
          */
 
-        if (dal_fixed31_32_le(
-                dal_fixed31_32_ln2_div_2,
-                dal_fixed31_32_abs(arg))) {
-                int m = dal_fixed31_32_round(
-                        dal_fixed31_32_div(
+        if (dc_fixpt_le(
+                dc_fixpt_ln2_div_2,
+                dc_fixpt_abs(arg))) {
+                int m = dc_fixpt_round(
+                        dc_fixpt_div(
                                 arg,
-                                dal_fixed31_32_ln2));
+                                dc_fixpt_ln2));
 
-                struct fixed31_32 r = dal_fixed31_32_sub(
+                struct fixed31_32 r = dc_fixpt_sub(
                         arg,
-                        dal_fixed31_32_mul_int(
-                                dal_fixed31_32_ln2,
+                        dc_fixpt_mul_int(
+                                dc_fixpt_ln2,
                                 m));
 
                 ASSERT(m != 0);
 
-                ASSERT(dal_fixed31_32_lt(
-                        dal_fixed31_32_abs(r),
-                        dal_fixed31_32_one));
+                ASSERT(dc_fixpt_lt(
+                        dc_fixpt_abs(r),
+                        dc_fixpt_one));
 
                 if (m > 0)
-                        return dal_fixed31_32_shl(
+                        return dc_fixpt_shl(
                                 fixed31_32_exp_from_taylor_series(r),
                                 (unsigned char)m);
                 else
-                        return dal_fixed31_32_div_int(
+                        return dc_fixpt_div_int(
                                 fixed31_32_exp_from_taylor_series(r),
                                 1LL << -m);
         } else if (arg.value != 0)
                 return fixed31_32_exp_from_taylor_series(arg);
         else
-                return dal_fixed31_32_one;
+                return dc_fixpt_one;
 }
 
-struct fixed31_32 dal_fixed31_32_log(
-        struct fixed31_32 arg)
+struct fixed31_32 dc_fixpt_log(struct fixed31_32 arg)
 {
-        struct fixed31_32 res = dal_fixed31_32_neg(dal_fixed31_32_one);
+        struct fixed31_32 res = dc_fixpt_neg(dc_fixpt_one);
         /* TODO improve 1st estimation */
 
         struct fixed31_32 error;
@@ -453,15 +387,15 @@ struct fixed31_32 dal_fixed31_32_log(
         /* TODO if arg is zero, return -INF */
 
         do {
-                struct fixed31_32 res1 = dal_fixed31_32_add(
-                        dal_fixed31_32_sub(
+                struct fixed31_32 res1 = dc_fixpt_add(
+                        dc_fixpt_sub(
                                 res,
-                                dal_fixed31_32_one),
-                        dal_fixed31_32_div(
+                                dc_fixpt_one),
+                        dc_fixpt_div(
                                 arg,
-                                dal_fixed31_32_exp(res)));
+                                dc_fixpt_exp(res)));
 
-                error = dal_fixed31_32_sub(
+                error = dc_fixpt_sub(
                         res,
                         res1);
 
@@ -472,66 +406,11 @@ struct fixed31_32 dal_fixed31_32_log(
         return res;
 }
 
-struct fixed31_32 dal_fixed31_32_pow(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2)
-{
-        return dal_fixed31_32_exp(
-                dal_fixed31_32_mul(
-                        dal_fixed31_32_log(arg1),
-                        arg2));
-}
-
-int dal_fixed31_32_floor(
-        struct fixed31_32 arg)
-{
-        unsigned long long arg_value = abs_i64(arg.value);
-
-        if (arg.value >= 0)
-                return (int)GET_INTEGER_PART(arg_value);
-        else
-                return -(int)GET_INTEGER_PART(arg_value);
-}
-
-int dal_fixed31_32_round(
-        struct fixed31_32 arg)
-{
-        unsigned long long arg_value = abs_i64(arg.value);
-
-        const long long summand = dal_fixed31_32_half.value;
-
-        ASSERT(LLONG_MAX - (long long)arg_value >= summand);
-
-        arg_value += summand;
-
-        if (arg.value >= 0)
-                return (int)GET_INTEGER_PART(arg_value);
-        else
-                return -(int)GET_INTEGER_PART(arg_value);
-}
-
-int dal_fixed31_32_ceil(
-        struct fixed31_32 arg)
-{
-        unsigned long long arg_value = abs_i64(arg.value);
-
-        const long long summand = dal_fixed31_32_one.value -
-                dal_fixed31_32_epsilon.value;
-
-        ASSERT(LLONG_MAX - (long long)arg_value >= summand);
-
-        arg_value += summand;
-
-        if (arg.value >= 0)
-                return (int)GET_INTEGER_PART(arg_value);
-        else
-                return -(int)GET_INTEGER_PART(arg_value);
-}
 
 /* this function is a generic helper to translate fixed point value to
  * specified integer format that will consist of integer_bits integer part and
  * fractional_bits fractional part. For example it is used in
- * dal_fixed31_32_u2d19 to receive 2 bits integer part and 19 bits fractional
+ * dc_fixpt_u2d19 to receive 2 bits integer part and 19 bits fractional
  * part in 32 bits. It is used in hw programming (scaler)
  */
 
@@ -570,35 +449,30 @@ static inline unsigned int clamp_ux_dy(
                 return min_clamp;
 }
 
-unsigned int dal_fixed31_32_u2d19(
-        struct fixed31_32 arg)
+unsigned int dc_fixpt_u2d19(struct fixed31_32 arg)
 {
         return ux_dy(arg.value, 2, 19);
 }
 
-unsigned int dal_fixed31_32_u0d19(
-        struct fixed31_32 arg)
+unsigned int dc_fixpt_u0d19(struct fixed31_32 arg)
 {
         return ux_dy(arg.value, 0, 19);
 }
 
-unsigned int dal_fixed31_32_clamp_u0d14(
-        struct fixed31_32 arg)
+unsigned int dc_fixpt_clamp_u0d14(struct fixed31_32 arg)
 {
         return clamp_ux_dy(arg.value, 0, 14, 1);
 }
 
-unsigned int dal_fixed31_32_clamp_u0d10(
-        struct fixed31_32 arg)
+unsigned int dc_fixpt_clamp_u0d10(struct fixed31_32 arg)
 {
         return clamp_ux_dy(arg.value, 0, 10, 1);
 }
 
-int dal_fixed31_32_s4d19(
-        struct fixed31_32 arg)
+int dc_fixpt_s4d19(struct fixed31_32 arg)
 {
         if (arg.value < 0)
-                return -(int)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
+                return -(int)ux_dy(dc_fixpt_abs(arg).value, 4, 19);
         else
                 return ux_dy(arg.value, 4, 19);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c
deleted file mode 100644
index 4d3aaa82a07b..000000000000
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt32_32.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/fixed32_32.h"
-
-static uint64_t u64_div(uint64_t n, uint64_t d)
-{
-        uint32_t i = 0;
-        uint64_t r;
-        uint64_t q = div64_u64_rem(n, d, &r);
-
-        for (i = 0; i < 32; ++i) {
-                uint64_t sbit = q & (1ULL<<63);
-
-                r <<= 1;
-                r |= sbit ? 1 : 0;
-                q <<= 1;
-                if (r >= d) {
-                        r -= d;
-                        q |= 1;
-                }
-        }
-
-        if (2*r >= d)
-                q += 1;
-        return q;
-}
-
-struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d)
-{
-        struct fixed32_32 fx;
-
-        fx.value = u64_div((uint64_t)n << 32, (uint64_t)d << 32);
-        return fx;
-}
-
-struct fixed32_32 dal_fixed32_32_add(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs)
-{
-        struct fixed32_32 fx = {lhs.value + rhs.value};
-
-        ASSERT(fx.value >= rhs.value);
-        return fx;
-}
-
-struct fixed32_32 dal_fixed32_32_add_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-        struct fixed32_32 fx = {lhs.value + ((uint64_t)rhs << 32)};
-
-        ASSERT(fx.value >= (uint64_t)rhs << 32);
-        return fx;
-
-}
-struct fixed32_32 dal_fixed32_32_sub(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs)
-{
-        struct fixed32_32 fx;
-
-        ASSERT(lhs.value >= rhs.value);
-        fx.value = lhs.value - rhs.value;
-        return fx;
-}
-
-struct fixed32_32 dal_fixed32_32_sub_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-        struct fixed32_32 fx;
-
-        ASSERT(lhs.value >= ((uint64_t)rhs<<32));
-        fx.value = lhs.value - ((uint64_t)rhs<<32);
-        return fx;
-}
-
-struct fixed32_32 dal_fixed32_32_mul(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs)
-{
-        struct fixed32_32 fx;
-        uint64_t lhs_int = lhs.value>>32;
-        uint64_t lhs_frac = (uint32_t)lhs.value;
-        uint64_t rhs_int = rhs.value>>32;
-        uint64_t rhs_frac = (uint32_t)rhs.value;
-        uint64_t ahbh = lhs_int * rhs_int;
-        uint64_t ahbl = lhs_int * rhs_frac;
-        uint64_t albh = lhs_frac * rhs_int;
-        uint64_t albl = lhs_frac * rhs_frac;
-
-        ASSERT((ahbh>>32) == 0);
-
-        fx.value = (ahbh<<32) + ahbl + albh + (albl>>32);
-        return fx;
-
-}
-
-struct fixed32_32 dal_fixed32_32_mul_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-        struct fixed32_32 fx;
-        uint64_t lhsi = (lhs.value>>32) * (uint64_t)rhs;
-        uint64_t lhsf;
-
-        ASSERT((lhsi>>32) == 0);
-        lhsf = ((uint32_t)lhs.value) * (uint64_t)rhs;
-        ASSERT((lhsi<<32) + lhsf >= lhsf);
-        fx.value = (lhsi<<32) + lhsf;
-        return fx;
-}
-
-struct fixed32_32 dal_fixed32_32_div(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs)
-{
-        struct fixed32_32 fx;
-
-        fx.value = u64_div(lhs.value, rhs.value);
-        return fx;
-}
-
-struct fixed32_32 dal_fixed32_32_div_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-        struct fixed32_32 fx;
-
-        fx.value = u64_div(lhs.value, (uint64_t)rhs << 32);
-        return fx;
-}
-
-uint32_t dal_fixed32_32_ceil(struct fixed32_32 v)
-{
-        ASSERT((uint32_t)v.value ? (v.value >> 32) + 1 >= 1 : true);
-        return (v.value>>32) + ((uint32_t)v.value ? 1 : 0);
-}
-
-uint32_t dal_fixed32_32_round(struct fixed32_32 v)
-{
-        ASSERT(v.value + (1ULL<<31) >= (1ULL<<31));
-        return (v.value + (1ULL<<31))>>32;
-}
-
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 854678a0c54b..021451549ff7 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -94,7 +94,6 @@ void dc_conn_log(struct dc_context *ctx,
                         dm_logger_append(&entry, "%2.2X ", hex_data[i]);
 
         dm_logger_append(&entry, "^\n");
-        dm_helpers_dc_conn_log(ctx, &entry, event);
 
 fail:
         dm_logger_close(&entry);
diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index 31bee054f43a..738a818d58d1 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -61,7 +61,7 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
                 {LOG_EVENT_UNDERFLOW,       "Underflow"},
                 {LOG_IF_TRACE,              "InterfaceTrace"},
                 {LOG_DTN,                   "DTN"},
-                {LOG_PROFILING,             "Profiling"}
+                {LOG_DISPLAYSTATS,          "DisplayStats"}
 };
 
 
@@ -402,3 +402,4 @@ cleanup:
                 entry->max_buf_bytes = 0;
         }
 }
+
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 10a5807a7e8b..b8cef7af3c4a 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1330,6 +1330,9 @@ static enum bp_result bios_parser_get_firmware_info(
                         case 2:
                                 result = get_firmware_info_v3_2(bp, info);
                                 break;
+                        case 3:
+                                result = get_firmware_info_v3_2(bp, info);
+                                break;
                         default:
                                 break;
                         }
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
index be066c49b984..253bbb1eea60 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
@@ -51,9 +51,7 @@ bool dal_bios_parser_init_cmd_tbl_helper(
                 return true;
 
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
                 *h = dal_cmd_tbl_helper_dce112_get_table();
                 return true;
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 9b9e06995805..bbbcef566c55 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -52,9 +52,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
                 return true;
 
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
                 *h = dal_cmd_tbl_helper_dce112_get_table2();
                 return true;
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c b/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c
index 7243c37f569e..31d167bc548f 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/custom_float.c
@@ -36,41 +36,41 @@ static bool build_custom_float(
         uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1;
 
         const struct fixed31_32 mantissa_constant_plus_max_fraction =
-                dal_fixed31_32_from_fraction(
+                dc_fixpt_from_fraction(
                         (1LL << (format->mantissa_bits + 1)) - 1,
                         1LL << format->mantissa_bits);
 
         struct fixed31_32 mantiss;
 
-        if (dal_fixed31_32_eq(
+        if (dc_fixpt_eq(
                 value,
-                dal_fixed31_32_zero)) {
+                dc_fixpt_zero)) {
                 *negative = false;
                 *mantissa = 0;
                 *exponenta = 0;
                 return true;
         }
 
-        if (dal_fixed31_32_lt(
+        if (dc_fixpt_lt(
                 value,
-                dal_fixed31_32_zero)) {
+                dc_fixpt_zero)) {
                 *negative = format->sign;
-                value = dal_fixed31_32_neg(value);
+                value = dc_fixpt_neg(value);
         } else {
                 *negative = false;
         }
 
-        if (dal_fixed31_32_lt(
+        if (dc_fixpt_lt(
                 value,
-                dal_fixed31_32_one)) {
+                dc_fixpt_one)) {
                 uint32_t i = 1;
 
                 do {
-                        value = dal_fixed31_32_shl(value, 1);
+                        value = dc_fixpt_shl(value, 1);
                         ++i;
-                } while (dal_fixed31_32_lt(
+                } while (dc_fixpt_lt(
                         value,
-                        dal_fixed31_32_one));
+                        dc_fixpt_one));
 
                 --i;
 
@@ -81,15 +81,15 @@ static bool build_custom_float(
                 }
 
                 *exponenta = exp_offset - i;
-        } else if (dal_fixed31_32_le(
+        } else if (dc_fixpt_le(
                 mantissa_constant_plus_max_fraction,
                 value)) {
                 uint32_t i = 1;
 
                 do {
-                        value = dal_fixed31_32_shr(value, 1);
+                        value = dc_fixpt_shr(value, 1);
                         ++i;
-                } while (dal_fixed31_32_lt(
+                } while (dc_fixpt_lt(
                         mantissa_constant_plus_max_fraction,
                         value));
 
@@ -98,23 +98,23 @@ static bool build_custom_float(
                 *exponenta = exp_offset;
         }
 
-        mantiss = dal_fixed31_32_sub(
+        mantiss = dc_fixpt_sub(
                 value,
-                dal_fixed31_32_one);
+                dc_fixpt_one);
 
-        if (dal_fixed31_32_lt(
+        if (dc_fixpt_lt(
                         mantiss,
-                        dal_fixed31_32_zero) ||
-                dal_fixed31_32_lt(
-                        dal_fixed31_32_one,
+                        dc_fixpt_zero) ||
+                dc_fixpt_lt(
+                        dc_fixpt_one,
                         mantiss))
-                mantiss = dal_fixed31_32_zero;
+                mantiss = dc_fixpt_zero;
         else
-                mantiss = dal_fixed31_32_shl(
+                mantiss = dc_fixpt_shl(
                         mantiss,
                         format->mantissa_bits);
 
-        *mantissa = dal_fixed31_32_floor(mantiss);
+        *mantissa = dc_fixpt_floor(mantiss);
 
         return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
index 4ee3c26f7c13..2c4e8f0cb2dc 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
@@ -59,10 +59,8 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi
                         return BW_CALCS_VERSION_POLARIS10;
                 if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
                         return BW_CALCS_VERSION_POLARIS11;
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
                         return BW_CALCS_VERSION_VEGAM;
-#endif
                 return BW_CALCS_VERSION_INVALID;
 
         case FAMILY_AI:
@@ -2151,11 +2149,9 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
                 dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
                 break;
         case BW_CALCS_VERSION_POLARIS10:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
                 /* TODO: Treat VEGAM the same as P10 for now
                  * Need to tune the para for VEGAM if needed */
         case BW_CALCS_VERSION_VEGAM:
-#endif
                 vbios.memory_type = bw_def_gddr5;
                 vbios.dram_channel_width_in_bits = 32;
                 vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a102c192328d..49a4ea45466d 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -873,14 +873,14 @@ bool dcn_validate_bandwidth(
                         }
 
                         if (pipe->plane_state->rotation % 2 == 0) {
-                                ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+                                ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
                                         || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
-                                ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+                                ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
                                         || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
                         } else {
-                                ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+                                ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
                                         || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
-                                ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+                                ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
                                         || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
                         }
                         v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b44cf52090a5..2fa521812d23 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -469,6 +469,13 @@ static void link_disconnect_sink(struct dc_link *link)
         link->dpcd_sink_count = 0;
 }
 
+static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
+{
+        dc_sink_release(link->local_sink);
+        link->local_sink = prev_sink;
+}
+
+
 static bool detect_dp(
         struct dc_link *link,
         struct display_sink_capability *sink_caps,
@@ -551,6 +558,17 @@ static bool detect_dp(
         return true;
 }
 
+static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
+{
+        if (old_edid->length != new_edid->length)
+                return false;
+
+        if (new_edid->length == 0)
+                return false;
+
+        return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
+}
+
 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 {
         struct dc_sink_init_data sink_init_data = { 0 };
@@ -558,9 +576,13 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
         uint8_t i;
         bool converter_disable_audio = false;
         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
+        bool same_edid = false;
         enum dc_edid_status edid_status;
         struct dc_context *dc_ctx = link->ctx;
         struct dc_sink *sink = NULL;
+        struct dc_sink *prev_sink = NULL;
+        struct dpcd_caps prev_dpcd_caps;
+        bool same_dpcd = true;
         enum dc_connection_type new_connection_type = dc_connection_none;
         DC_LOGGER_INIT(link->ctx->logger);
         if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
@@ -575,6 +597,11 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                         link->local_sink)
                 return true;
 
+        prev_sink = link->local_sink;
+        if (prev_sink != NULL) {
+                dc_sink_retain(prev_sink);
+                memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
+        }
         link_disconnect_sink(link);
 
         if (new_connection_type != dc_connection_none) {
@@ -616,14 +643,25 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                                 link,
                                 &sink_caps,
                                 &converter_disable_audio,
-                                aud_support, reason))
+                                aud_support, reason)) {
+                                if (prev_sink != NULL)
+                                        dc_sink_release(prev_sink);
                                 return false;
+                        }
 
+                        // Check if dpcp block is the same
+                        if (prev_sink != NULL) {
+                                if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
+                                        same_dpcd = false;
+                        }
                         /* Active dongle downstream unplug */
                         if (link->type == dc_connection_active_dongle
                                         && link->dpcd_caps.sink_count.
-                                        bits.SINK_COUNT == 0)
+                                        bits.SINK_COUNT == 0) {
+                                if (prev_sink != NULL)
+                                        dc_sink_release(prev_sink);
                                 return true;
+                        }
 
                         if (link->type == dc_connection_mst_branch) {
                                 LINK_INFO("link=%d, mst branch is now Connected\n",
@@ -631,9 +669,11 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                                 /* Need to setup mst link_cap struct here
                                  * otherwise dc_link_detect() will leave mst link_cap
                                  * empty which leads to allocate_mst_payload() has "0"
-                                 * pbn_per_slot value leading to exception on dal_fixed31_32_div()
+                                 * pbn_per_slot value leading to exception on dc_fixpt_div()
                                  */
                                 link->verified_link_cap = link->reported_link_cap;
+                                if (prev_sink != NULL)
+                                        dc_sink_release(prev_sink);
                                 return false;
                         }
 
@@ -643,6 +683,8 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                 default:
                         DC_ERROR("Invalid connector type! signal:%d\n",
                                 link->connector_signal);
+                        if (prev_sink != NULL)
+                                dc_sink_release(prev_sink);
                         return false;
                 } /* switch() */
 
@@ -665,6 +707,8 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                 sink = dc_sink_create(&sink_init_data);
                 if (!sink) {
                         DC_ERROR("Failed to create sink!\n");
+                        if (prev_sink != NULL)
+                                dc_sink_release(prev_sink);
                         return false;
                 }
 
@@ -688,22 +732,33 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                         break;
                 }
 
-                if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
-                        sink_caps.transaction_type ==
-                        DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
-                        /*
-                         * TODO debug why Dell 2413 doesn't like
-                         *  two link trainings
-                         */
+                // Check if edid is the same
+                if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
+                        same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 
-                        /* deal with non-mst cases */
-                        dp_hbr_verify_link_cap(link, &link->reported_link_cap);
-                }
+                // If both edid and dpcd are the same, then discard new sink and revert back to original sink
+                if ((same_edid) && (same_dpcd)) {
+                        link_disconnect_remap(prev_sink, link);
+                        sink = prev_sink;
+                        prev_sink = NULL;
+                } else {
+                        if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
+                                        sink_caps.transaction_type ==
+                                                DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
+                                /*
+                                 * TODO debug why Dell 2413 doesn't like
+                                 *  two link trainings
+                                 */
+
+                                /* deal with non-mst cases */
+                                dp_hbr_verify_link_cap(link, &link->reported_link_cap);
+                        }
 
-                /* HDMI-DVI Dongle */
-                if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
-                                !sink->edid_caps.edid_hdmi)
-                        sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
+                        /* HDMI-DVI Dongle */
+                        if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
+                                        !sink->edid_caps.edid_hdmi)
+                                sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
+                }
 
                 /* Connectivity log: detection */
                 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
@@ -762,10 +817,14 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
                 sink_caps.signal = SIGNAL_TYPE_NONE;
         }
 
-        LINK_INFO("link=%d, dc_sink_in=%p is now %s\n",
+        LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
                 link->link_index, sink,
                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
-                        "Disconnected":"Connected"));
+                        "Disconnected":"Connected"), prev_sink,
+                        same_dpcd, same_edid);
+
+        if (prev_sink != NULL)
+                dc_sink_release(prev_sink);
 
         return true;
 }
@@ -2059,10 +2118,10 @@ static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
                         &stream->sink->link->cur_link_settings;
         uint32_t link_rate_in_mbps =
                         link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
-        struct fixed31_32 mbps = dal_fixed31_32_from_int(
+        struct fixed31_32 mbps = dc_fixpt_from_int(
                         link_rate_in_mbps * link_settings->lane_count);
 
-        return dal_fixed31_32_div_int(mbps, 54);
+        return dc_fixpt_div_int(mbps, 54);
 }
 
 static int get_color_depth(enum dc_color_depth color_depth)
@@ -2103,7 +2162,7 @@ static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
         numerator = 64 * PEAK_FACTOR_X1000;
         denominator = 54 * 8 * 1000 * 1000;
         kbps *= numerator;
-        peak_kbps = dal_fixed31_32_from_fraction(kbps, denominator);
+        peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
 
         return peak_kbps;
 }
@@ -2230,7 +2289,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
         /* slot X.Y for only current stream */
         pbn_per_slot = get_pbn_per_slot(stream);
         pbn = get_pbn_from_timing(pipe_ctx);
-        avg_time_slots_per_mtp = dal_fixed31_32_div(pbn, pbn_per_slot);
+        avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
 
         stream_encoder->funcs->set_mst_bandwidth(
                 stream_encoder,
@@ -2247,7 +2306,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
         struct link_encoder *link_encoder = link->link_enc;
         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
         struct dp_mst_stream_allocation_table proposed_table = {0};
-        struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
+        struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
         uint8_t i;
         bool mst_mode = (link->type == dc_connection_mst_branch);
         DC_LOGGER_INIT(link->ctx->logger);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 7c866a7d5e77..82cd1d6e6e59 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -11,8 +11,6 @@
 #include "dc_link_dp.h"
 #include "dc_link_ddc.h"
 #include "dm_helpers.h"
-#include "dce/dce_link_encoder.h"
-#include "dce/dce_stream_encoder.h"
 #include "dpcd_defs.h"
 
 enum dc_status core_link_read_dpcd(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9eb731fb5251..751f3ac9d921 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -79,10 +79,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
                                 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
                         dc_version = DCE_VERSION_11_2;
                 }
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
                 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
                         dc_version = DCE_VERSION_11_22;
-#endif
                 break;
         case FAMILY_AI:
                 dc_version = DCE_VERSION_12_0;
@@ -129,9 +127,7 @@ struct resource_pool *dc_create_resource_pool(
                         num_virtual_links, dc, asic_id);
                 break;
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
                 res_pool = dce112_create_resource_pool(
                         num_virtual_links, dc);
                 break;
@@ -500,9 +496,9 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
         data->viewport_c.x = data->viewport.x / vpc_div;
         data->viewport_c.y = data->viewport.y / vpc_div;
         data->inits.h_c = (data->viewport.x % vpc_div) != 0 ?
-                        dal_fixed31_32_half : dal_fixed31_32_zero;
+                        dc_fixpt_half : dc_fixpt_zero;
         data->inits.v_c = (data->viewport.y % vpc_div) != 0 ?
-                        dal_fixed31_32_half : dal_fixed31_32_zero;
+                        dc_fixpt_half : dc_fixpt_zero;
         /* Round up, assume original video size always even dimensions */
         data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
         data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
@@ -631,10 +627,10 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
                         pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
                 rect_swap_helper(&surf_src);
 
-        pipe_ctx->plane_res.scl_data.ratios.horz = dal_fixed31_32_from_fraction(
+        pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
                                         surf_src.width,
                                         plane_state->dst_rect.width);
-        pipe_ctx->plane_res.scl_data.ratios.vert = dal_fixed31_32_from_fraction(
+        pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
                                         surf_src.height,
                                         plane_state->dst_rect.height);
 
@@ -656,6 +652,14 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
                 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
                 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
         }
+        pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
+                        pipe_ctx->plane_res.scl_data.ratios.horz, 19);
+        pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
+                        pipe_ctx->plane_res.scl_data.ratios.vert, 19);
+        pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
+                        pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
+        pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
+                        pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
 }
 
 static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip)
@@ -692,32 +696,33 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
          *      init_bot = init + scaling_ratio
          *      init_c = init + truncated_vp_c_offset(from calculate viewport)
          */
-        data->inits.h = dal_fixed31_32_div_int(
-                        dal_fixed31_32_add_int(data->ratios.horz, data->taps.h_taps + 1), 2);
+        data->inits.h = dc_fixpt_truncate(dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19);
+
+        data->inits.h_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.h_c, dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2)), 19);
 
-        data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_div_int(
-                        dal_fixed31_32_add_int(data->ratios.horz_c, data->taps.h_taps_c + 1), 2));
+        data->inits.v = dc_fixpt_truncate(dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19);
 
-        data->inits.v = dal_fixed31_32_div_int(
-                        dal_fixed31_32_add_int(data->ratios.vert, data->taps.v_taps + 1), 2);
+        data->inits.v_c = dc_fixpt_truncate(dc_fixpt_add(data->inits.v_c, dc_fixpt_div_int(
+                        dc_fixpt_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2)), 19);
 
-        data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_div_int(
-                        dal_fixed31_32_add_int(data->ratios.vert_c, data->taps.v_taps_c + 1), 2));
 
 
         /* Adjust for viewport end clip-off */
         if ((data->viewport.x + data->viewport.width) < (src.x + src.width) && !flip_horz_scan_dir) {
                 int vp_clip = src.x + src.width - data->viewport.width - data->viewport.x;
-                int int_part = dal_fixed31_32_floor(
-                                dal_fixed31_32_sub(data->inits.h, data->ratios.horz));
+                int int_part = dc_fixpt_floor(
+                                dc_fixpt_sub(data->inits.h, data->ratios.horz));
 
                 int_part = int_part > 0 ? int_part : 0;
                 data->viewport.width += int_part < vp_clip ? int_part : vp_clip;
         }
         if ((data->viewport.y + data->viewport.height) < (src.y + src.height) && !flip_vert_scan_dir) {
                 int vp_clip = src.y + src.height - data->viewport.height - data->viewport.y;
-                int int_part = dal_fixed31_32_floor(
-                                dal_fixed31_32_sub(data->inits.v, data->ratios.vert));
+                int int_part = dc_fixpt_floor(
+                                dc_fixpt_sub(data->inits.v, data->ratios.vert));
 
                 int_part = int_part > 0 ? int_part : 0;
                 data->viewport.height += int_part < vp_clip ? int_part : vp_clip;
@@ -725,8 +730,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
         if ((data->viewport_c.x + data->viewport_c.width) < (src.x + src.width) / vpc_div && !flip_horz_scan_dir) {
                 int vp_clip = (src.x + src.width) / vpc_div -
                                 data->viewport_c.width - data->viewport_c.x;
-                int int_part = dal_fixed31_32_floor(
-                                dal_fixed31_32_sub(data->inits.h_c, data->ratios.horz_c));
+                int int_part = dc_fixpt_floor(
+                                dc_fixpt_sub(data->inits.h_c, data->ratios.horz_c));
 
                 int_part = int_part > 0 ? int_part : 0;
                 data->viewport_c.width += int_part < vp_clip ? int_part : vp_clip;
@@ -734,8 +739,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
         if ((data->viewport_c.y + data->viewport_c.height) < (src.y + src.height) / vpc_div && !flip_vert_scan_dir) {
                 int vp_clip = (src.y + src.height) / vpc_div -
                                 data->viewport_c.height - data->viewport_c.y;
-                int int_part = dal_fixed31_32_floor(
-                                dal_fixed31_32_sub(data->inits.v_c, data->ratios.vert_c));
+                int int_part = dc_fixpt_floor(
+                                dc_fixpt_sub(data->inits.v_c, data->ratios.vert_c));
 
                 int_part = int_part > 0 ? int_part : 0;
                 data->viewport_c.height += int_part < vp_clip ? int_part : vp_clip;
@@ -745,9 +750,9 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
         if (data->viewport.x && !flip_horz_scan_dir) {
                 int int_part;
 
-                data->inits.h = dal_fixed31_32_add(data->inits.h, dal_fixed31_32_mul_int(
+                data->inits.h = dc_fixpt_add(data->inits.h, dc_fixpt_mul_int(
                                 data->ratios.horz, recout_skip->width));
-                int_part = dal_fixed31_32_floor(data->inits.h) - data->viewport.x;
+                int_part = dc_fixpt_floor(data->inits.h) - data->viewport.x;
                 if (int_part < data->taps.h_taps) {
                         int int_adj = data->viewport.x >= (data->taps.h_taps - int_part) ?
                                                 (data->taps.h_taps - int_part) : data->viewport.x;
@@ -760,15 +765,15 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
                         int_part = data->taps.h_taps;
                 }
                 data->inits.h.value &= 0xffffffff;
-                data->inits.h = dal_fixed31_32_add_int(data->inits.h, int_part);
+                data->inits.h = dc_fixpt_add_int(data->inits.h, int_part);
         }
 
         if (data->viewport_c.x && !flip_horz_scan_dir) {
                 int int_part;
 
-                data->inits.h_c = dal_fixed31_32_add(data->inits.h_c, dal_fixed31_32_mul_int(
+                data->inits.h_c = dc_fixpt_add(data->inits.h_c, dc_fixpt_mul_int(
                                 data->ratios.horz_c, recout_skip->width));
-                int_part = dal_fixed31_32_floor(data->inits.h_c) - data->viewport_c.x;
+                int_part = dc_fixpt_floor(data->inits.h_c) - data->viewport_c.x;
                 if (int_part < data->taps.h_taps_c) {
                         int int_adj = data->viewport_c.x >= (data->taps.h_taps_c - int_part) ?
                                         (data->taps.h_taps_c - int_part) : data->viewport_c.x;
@@ -781,15 +786,15 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
                         int_part = data->taps.h_taps_c;
                 }
                 data->inits.h_c.value &= 0xffffffff;
-                data->inits.h_c = dal_fixed31_32_add_int(data->inits.h_c, int_part);
+                data->inits.h_c = dc_fixpt_add_int(data->inits.h_c, int_part);
         }
 
         if (data->viewport.y && !flip_vert_scan_dir) {
                 int int_part;
 
-                data->inits.v = dal_fixed31_32_add(data->inits.v, dal_fixed31_32_mul_int(
+                data->inits.v = dc_fixpt_add(data->inits.v, dc_fixpt_mul_int(
                                 data->ratios.vert, recout_skip->height));
-                int_part = dal_fixed31_32_floor(data->inits.v) - data->viewport.y;
+                int_part = dc_fixpt_floor(data->inits.v) - data->viewport.y;
                 if (int_part < data->taps.v_taps) {
                         int int_adj = data->viewport.y >= (data->taps.v_taps - int_part) ?
                                                 (data->taps.v_taps - int_part) : data->viewport.y;
@@ -802,15 +807,15 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
                         int_part = data->taps.v_taps;
                 }
                 data->inits.v.value &= 0xffffffff;
-                data->inits.v = dal_fixed31_32_add_int(data->inits.v, int_part);
+                data->inits.v = dc_fixpt_add_int(data->inits.v, int_part);
         }
 
         if (data->viewport_c.y && !flip_vert_scan_dir) {
                 int int_part;
 
-                data->inits.v_c = dal_fixed31_32_add(data->inits.v_c, dal_fixed31_32_mul_int(
+                data->inits.v_c = dc_fixpt_add(data->inits.v_c, dc_fixpt_mul_int(
                                 data->ratios.vert_c, recout_skip->height));
-                int_part = dal_fixed31_32_floor(data->inits.v_c) - data->viewport_c.y;
+                int_part = dc_fixpt_floor(data->inits.v_c) - data->viewport_c.y;
                 if (int_part < data->taps.v_taps_c) {
                         int int_adj = data->viewport_c.y >= (data->taps.v_taps_c - int_part) ?
                                         (data->taps.v_taps_c - int_part) : data->viewport_c.y;
@@ -823,12 +828,12 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r
                         int_part = data->taps.v_taps_c;
                 }
                 data->inits.v_c.value &= 0xffffffff;
-                data->inits.v_c = dal_fixed31_32_add_int(data->inits.v_c, int_part);
+                data->inits.v_c = dc_fixpt_add_int(data->inits.v_c, int_part);
         }
 
         /* Interlaced inits based on final vert inits */
-        data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert);
-        data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c);
+        data->inits.v_bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
+        data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
 
         if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
                         pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index cd4f4341cb53..9cfde0ccf4e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -75,6 +75,7 @@ struct dc_caps {
         bool dynamic_audio;
         bool is_apu;
         bool dual_link_dvi;
+        bool post_blend_color_processing;
 };
 
 struct dc_dcc_surface_param {
@@ -203,6 +204,7 @@ struct dc_debug {
         bool clock_trace;
         bool validation_trace;
         bool bandwidth_calcs_trace;
+        int max_downscale_src_width;
 
         /* stutter efficiency related */
         bool disable_stutter;
@@ -239,6 +241,8 @@ struct dc_debug {
         bool az_endpoint_mute_only;
         bool always_use_regamma;
         bool p010_mpo_support;
+        bool recovery_enabled;
+
 };
 struct dc_state;
 struct resource_pool;
@@ -499,18 +503,18 @@ struct dc_surface_update {
         struct dc_plane_state *surface;
 
         /* isr safe update parameters.  null means no updates */
-        struct dc_flip_addrs *flip_addr;
-        struct dc_plane_info *plane_info;
-        struct dc_scaling_info *scaling_info;
+        const struct dc_flip_addrs *flip_addr;
+        const struct dc_plane_info *plane_info;
+        const struct dc_scaling_info *scaling_info;
 
         /* following updates require alloc/sleep/spin that is not isr safe,
          * null means no updates
          */
-        struct dc_gamma *gamma;
-        struct dc_transfer_func *in_transfer_func;
+        const struct dc_gamma *gamma;
+        const struct dc_transfer_func *in_transfer_func;
 
-        struct dc_csc_transform *input_csc_color_matrix;
-        struct fixed31_32 *coeff_reduction_factor;
+        const struct dc_csc_transform *input_csc_color_matrix;
+        const struct fixed31_32 *coeff_reduction_factor;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 2726b02e006b..90bccd5ccaa2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -26,6 +26,8 @@
 #ifndef DC_DP_TYPES_H
 #define DC_DP_TYPES_H
 
+#include "os_types.h"
+
 enum dc_lane_count {
         LANE_COUNT_UNKNOWN = 0,
         LANE_COUNT_ONE = 1,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 9defe3b17617..76df2534c4a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -25,7 +25,7 @@
 #ifndef DC_TYPES_H_
 #define DC_TYPES_H_
 
-#include "fixed32_32.h"
+#include "os_types.h"
 #include "fixed31_32.h"
 #include "irq_types.h"
 #include "dc_dp_types.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index fe92a1222803..29294db1a96b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -26,7 +26,7 @@
 #include "dce_abm.h"
 #include "dm_services.h"
 #include "reg_helper.h"
-#include "fixed32_32.h"
+#include "fixed31_32.h"
 #include "dc.h"
 
 #include "atom.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 223db98a568a..599c7ab6befe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -590,9 +590,7 @@ static uint32_t dce110_get_pix_clk_dividers(
                         pll_settings, pix_clk_params);
                 break;
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
         case DCE_VERSION_12_0:
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
         case DCN_VERSION_1_0:
@@ -659,12 +657,12 @@ static uint32_t dce110_get_d_to_pixel_rate_in_hz(
                         return 0;
                 }
 
-                pix_rate = dal_fixed31_32_from_int(clk_src->ref_freq_khz);
-                pix_rate = dal_fixed31_32_mul_int(pix_rate, 1000);
-                pix_rate = dal_fixed31_32_mul_int(pix_rate, phase);
-                pix_rate = dal_fixed31_32_div_int(pix_rate, modulo);
+                pix_rate = dc_fixpt_from_int(clk_src->ref_freq_khz);
+                pix_rate = dc_fixpt_mul_int(pix_rate, 1000);
+                pix_rate = dc_fixpt_mul_int(pix_rate, phase);
+                pix_rate = dc_fixpt_div_int(pix_rate, modulo);
 
-                return dal_fixed31_32_round(pix_rate);
+                return dc_fixpt_round(pix_rate);
         } else {
                 return dce110_get_dp_pixel_rate_from_combo_phy_pll(cs, pix_clk_params, pll_settings);
         }
@@ -713,12 +711,12 @@ static bool calculate_ss(
                 const struct spread_spectrum_data *ss_data,
                 struct delta_sigma_data *ds_data)
 {
-        struct fixed32_32 fb_div;
-        struct fixed32_32 ss_amount;
-        struct fixed32_32 ss_nslip_amount;
-        struct fixed32_32 ss_ds_frac_amount;
-        struct fixed32_32 ss_step_size;
-        struct fixed32_32 modulation_time;
+        struct fixed31_32 fb_div;
+        struct fixed31_32 ss_amount;
+        struct fixed31_32 ss_nslip_amount;
+        struct fixed31_32 ss_ds_frac_amount;
+        struct fixed31_32 ss_step_size;
+        struct fixed31_32 modulation_time;
 
         if (ds_data == NULL)
                 return false;
@@ -733,42 +731,42 @@ static bool calculate_ss(
 
         /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
         /* 6 decimal point support in fractional feedback divider */
-        fb_div  = dal_fixed32_32_from_fraction(
+        fb_div  = dc_fixpt_from_fraction(
                 pll_settings->fract_feedback_divider, 1000000);
-        fb_div = dal_fixed32_32_add_int(fb_div, pll_settings->feedback_divider);
+        fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
 
         ds_data->ds_frac_amount = 0;
         /*spreadSpectrumPercentage is in the unit of .01%,
          * so have to divided by 100 * 100*/
-        ss_amount = dal_fixed32_32_mul(
-                fb_div, dal_fixed32_32_from_fraction(ss_data->percentage,
+        ss_amount = dc_fixpt_mul(
+                fb_div, dc_fixpt_from_fraction(ss_data->percentage,
                                         100 * ss_data->percentage_divider));
-        ds_data->feedback_amount = dal_fixed32_32_floor(ss_amount);
+        ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
 
-        ss_nslip_amount = dal_fixed32_32_sub(ss_amount,
-                dal_fixed32_32_from_int(ds_data->feedback_amount));
-        ss_nslip_amount = dal_fixed32_32_mul_int(ss_nslip_amount, 10);
-        ds_data->nfrac_amount = dal_fixed32_32_floor(ss_nslip_amount);
+        ss_nslip_amount = dc_fixpt_sub(ss_amount,
+                dc_fixpt_from_int(ds_data->feedback_amount));
+        ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
+        ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
 
-        ss_ds_frac_amount = dal_fixed32_32_sub(ss_nslip_amount,
-                dal_fixed32_32_from_int(ds_data->nfrac_amount));
-        ss_ds_frac_amount = dal_fixed32_32_mul_int(ss_ds_frac_amount, 65536);
-        ds_data->ds_frac_amount = dal_fixed32_32_floor(ss_ds_frac_amount);
+        ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
+                dc_fixpt_from_int(ds_data->nfrac_amount));
+        ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
+        ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
 
         /* compute SS_STEP_SIZE_DSFRAC */
-        modulation_time = dal_fixed32_32_from_fraction(
+        modulation_time = dc_fixpt_from_fraction(
                 pll_settings->reference_freq * 1000,
                 pll_settings->reference_divider * ss_data->modulation_freq_hz);
 
         if (ss_data->flags.CENTER_SPREAD)
-                modulation_time = dal_fixed32_32_div_int(modulation_time, 4);
+                modulation_time = dc_fixpt_div_int(modulation_time, 4);
         else
-                modulation_time = dal_fixed32_32_div_int(modulation_time, 2);
+                modulation_time = dc_fixpt_div_int(modulation_time, 2);
 
-        ss_step_size = dal_fixed32_32_div(ss_amount, modulation_time);
+        ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
         /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
-        ss_step_size = dal_fixed32_32_mul_int(ss_step_size, 65536 * 10);
-        ds_data->ds_frac_size =  dal_fixed32_32_floor(ss_step_size);
+        ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
+        ds_data->ds_frac_size =  dc_fixpt_floor(ss_step_size);
 
         return true;
 }
@@ -982,9 +980,7 @@ static bool dce110_program_pix_clk(
 
                 break;
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
         case DCE_VERSION_12_0:
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
         case DCN_VERSION_1_0:
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 78e6beb6cf26..8a581c67bf2d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -26,7 +26,7 @@
 #include "dce_clocks.h"
 #include "dm_services.h"
 #include "reg_helper.h"
-#include "fixed32_32.h"
+#include "fixed31_32.h"
 #include "bios_parser_interface.h"
 #include "dc.h"
 #include "dmcu.h"
@@ -35,7 +35,7 @@
 #endif
 #include "core_types.h"
 #include "dc_types.h"
-
+#include "dal_asic_id.h"
 
 #define TO_DCE_CLOCKS(clocks)\
         container_of(clocks, struct dce_disp_clk, base)
@@ -228,19 +228,19 @@ static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
          generated according to average value (case as with previous ASICs)
           */
         if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
-                struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
-                                dal_fixed32_32_from_fraction(
+                struct fixed31_32 ss_percentage = dc_fixpt_div_int(
+                                dc_fixpt_from_fraction(
                                                 clk_dce->dprefclk_ss_percentage,
                                                 clk_dce->dprefclk_ss_divider), 200);
-                struct fixed32_32 adj_dp_ref_clk_khz;
+                struct fixed31_32 adj_dp_ref_clk_khz;
 
-                ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
+                ss_percentage = dc_fixpt_sub(dc_fixpt_one,
                                                                 ss_percentage);
                 adj_dp_ref_clk_khz =
-                        dal_fixed32_32_mul_int(
+                        dc_fixpt_mul_int(
                                 ss_percentage,
                                 dp_ref_clk_khz);
-                dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
+                dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
         }
 
         return dp_ref_clk_khz;
@@ -256,19 +256,19 @@ static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)
         int dp_ref_clk_khz = 600000;
 
         if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
-                struct fixed32_32 ss_percentage = dal_fixed32_32_div_int(
-                                dal_fixed32_32_from_fraction(
+                struct fixed31_32 ss_percentage = dc_fixpt_div_int(
+                                dc_fixpt_from_fraction(
                                                 clk_dce->dprefclk_ss_percentage,
                                                 clk_dce->dprefclk_ss_divider), 200);
-                struct fixed32_32 adj_dp_ref_clk_khz;
+                struct fixed31_32 adj_dp_ref_clk_khz;
 
-                ss_percentage = dal_fixed32_32_sub(dal_fixed32_32_one,
+                ss_percentage = dc_fixpt_sub(dc_fixpt_one,
                                                                 ss_percentage);
                 adj_dp_ref_clk_khz =
-                        dal_fixed32_32_mul_int(
+                        dc_fixpt_mul_int(
                                 ss_percentage,
                                 dp_ref_clk_khz);
-                dp_ref_clk_khz = dal_fixed32_32_floor(adj_dp_ref_clk_khz);
+                dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
         }
 
         return dp_ref_clk_khz;
@@ -413,9 +413,12 @@ static int dce112_set_clock(
         /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
         dce_clk_params.target_clock_frequency = 0;
         dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
-        dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
+        if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev))
+                dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
                         (dce_clk_params.pll_id ==
                                         CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
+        else
+                dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
 
         bp->funcs->set_dce_clock(bp, &dce_clk_params);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 2ee3d9bf1062..a576b8bbb3cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -28,7 +28,7 @@
 #include "dce_dmcu.h"
 #include "dm_services.h"
 #include "reg_helper.h"
-#include "fixed32_32.h"
+#include "fixed31_32.h"
 #include "dc.h"
 
 #define TO_DCE_DMCU(dmcu)\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
index d737e911971b..5d9506b3d46b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c
@@ -195,13 +195,13 @@ static void dce_ipp_program_input_lut(
 
         for (i = 0; i < gamma->num_entries; i++) {
                 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
-                                dal_fixed31_32_round(
+                                dc_fixpt_round(
                                         gamma->entries.red[i]));
                 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
-                                dal_fixed31_32_round(
+                                dc_fixpt_round(
                                         gamma->entries.green[i]));
                 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
-                                dal_fixed31_32_round(
+                                dc_fixpt_round(
                                         gamma->entries.blue[i]));
         }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
index 6243450b41b7..48862bebf29e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_scl_filters.c
@@ -1014,11 +1014,11 @@ static const uint16_t filter_8tap_64p_183[264] = {
 
 const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_3tap_16p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_3tap_16p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_3tap_16p_150;
         else
                 return filter_3tap_16p_183;
@@ -1026,11 +1026,11 @@ const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio)
 
 const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_3tap_64p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_3tap_64p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_3tap_64p_150;
         else
                 return filter_3tap_64p_183;
@@ -1038,11 +1038,11 @@ const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio)
 
 const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_4tap_16p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_4tap_16p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_4tap_16p_150;
         else
                 return filter_4tap_16p_183;
@@ -1050,11 +1050,11 @@ const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio)
 
 const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_4tap_64p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_4tap_64p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_4tap_64p_150;
         else
                 return filter_4tap_64p_183;
@@ -1062,11 +1062,11 @@ const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio)
 
 const uint16_t *get_filter_5tap_64p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_5tap_64p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_5tap_64p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_5tap_64p_150;
         else
                 return filter_5tap_64p_183;
@@ -1074,11 +1074,11 @@ const uint16_t *get_filter_5tap_64p(struct fixed31_32 ratio)
 
 const uint16_t *get_filter_6tap_64p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_6tap_64p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_6tap_64p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_6tap_64p_150;
         else
                 return filter_6tap_64p_183;
@@ -1086,11 +1086,11 @@ const uint16_t *get_filter_6tap_64p(struct fixed31_32 ratio)
 
 const uint16_t *get_filter_7tap_64p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_7tap_64p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_7tap_64p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_7tap_64p_150;
         else
                 return filter_7tap_64p_183;
@@ -1098,11 +1098,11 @@ const uint16_t *get_filter_7tap_64p(struct fixed31_32 ratio)
 
 const uint16_t *get_filter_8tap_64p(struct fixed31_32 ratio)
 {
-        if (ratio.value < dal_fixed31_32_one.value)
+        if (ratio.value < dc_fixpt_one.value)
                 return filter_8tap_64p_upscale;
-        else if (ratio.value < dal_fixed31_32_from_fraction(4, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(4, 3).value)
                 return filter_8tap_64p_117;
-        else if (ratio.value < dal_fixed31_32_from_fraction(5, 3).value)
+        else if (ratio.value < dc_fixpt_from_fraction(5, 3).value)
                 return filter_8tap_64p_150;
         else
                 return filter_8tap_64p_183;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index e265a0abe361..0a6d483dc046 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -683,11 +683,11 @@ static void dce110_stream_encoder_set_mst_bandwidth(
         struct fixed31_32 avg_time_slots_per_mtp)
 {
         struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
-        uint32_t x = dal_fixed31_32_floor(
+        uint32_t x = dc_fixpt_floor(
                 avg_time_slots_per_mtp);
-        uint32_t y = dal_fixed31_32_ceil(
-                dal_fixed31_32_shl(
-                        dal_fixed31_32_sub_int(
+        uint32_t y = dc_fixpt_ceil(
+                dc_fixpt_shl(
+                        dc_fixpt_sub_int(
                                 avg_time_slots_per_mtp,
                                 x),
                         26));
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index 832c5daada35..a02e719d7794 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -41,7 +41,7 @@
 #define DC_LOGGER \
         xfm_dce->base.ctx->logger
 
-#define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
+#define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
 #define GAMUT_MATRIX_SIZE 12
 #define SCL_PHASES 16
 
@@ -256,27 +256,27 @@ static void calculate_inits(
         struct fixed31_32 v_init;
 
         inits->h_int_scale_ratio =
-                dal_fixed31_32_u2d19(data->ratios.horz) << 5;
+                dc_fixpt_u2d19(data->ratios.horz) << 5;
         inits->v_int_scale_ratio =
-                dal_fixed31_32_u2d19(data->ratios.vert) << 5;
+                dc_fixpt_u2d19(data->ratios.vert) << 5;
 
         h_init =
-                dal_fixed31_32_div_int(
-                        dal_fixed31_32_add(
+                dc_fixpt_div_int(
+                        dc_fixpt_add(
                                 data->ratios.horz,
-                                dal_fixed31_32_from_int(data->taps.h_taps + 1)),
+                                dc_fixpt_from_int(data->taps.h_taps + 1)),
                                 2);
-        inits->h_init.integer = dal_fixed31_32_floor(h_init);
-        inits->h_init.fraction = dal_fixed31_32_u0d19(h_init) << 5;
+        inits->h_init.integer = dc_fixpt_floor(h_init);
+        inits->h_init.fraction = dc_fixpt_u0d19(h_init) << 5;
 
         v_init =
-                dal_fixed31_32_div_int(
-                        dal_fixed31_32_add(
+                dc_fixpt_div_int(
+                        dc_fixpt_add(
                                 data->ratios.vert,
-                                dal_fixed31_32_from_int(data->taps.v_taps + 1)),
+                                dc_fixpt_from_int(data->taps.v_taps + 1)),
                                 2);
-        inits->v_init.integer = dal_fixed31_32_floor(v_init);
-        inits->v_init.fraction = dal_fixed31_32_u0d19(v_init) << 5;
+        inits->v_init.integer = dc_fixpt_floor(v_init);
+        inits->v_init.fraction = dc_fixpt_u0d19(v_init) << 5;
 }
 
 static void program_scl_ratios_inits(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2288d0aa773b..a92fb0aa2ff3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -509,19 +509,19 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 
-        arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-                                             dal_fixed31_32_from_int(region_start));
-        arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-                                             dal_fixed31_32_from_int(region_end));
+        arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
+                                             dc_fixpt_from_int(region_start));
+        arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
+                                             dc_fixpt_from_int(region_end));
 
         y_r = rgb_resulted[0].red;
         y_g = rgb_resulted[0].green;
         y_b = rgb_resulted[0].blue;
 
-        y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
+        y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 
         arr_points[0].y = y1_min;
-        arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y,
+        arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
                                                  arr_points[0].x);
 
         y_r = rgb_resulted[hw_points - 1].red;
@@ -531,21 +531,21 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
         /* see comment above, m_arrPoints[1].y should be the Y value for the
          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
          */
-        y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
+        y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 
         arr_points[1].y = y3_max;
 
-        arr_points[1].slope = dal_fixed31_32_zero;
+        arr_points[1].slope = dc_fixpt_zero;
 
         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
                 /* for PQ, we want to have a straight line from last HW X point,
                  * and the slope to be such that we hit 1.0 at 10000 nits.
                  */
-                const struct fixed31_32 end_value = dal_fixed31_32_from_int(125);
+                const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 
-                arr_points[1].slope = dal_fixed31_32_div(
-                                dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-                                dal_fixed31_32_sub(end_value, arr_points[1].x));
+                arr_points[1].slope = dc_fixpt_div(
+                                dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
+                                dc_fixpt_sub(end_value, arr_points[1].x));
         }
 
         regamma_params->hw_points_num = hw_points;
@@ -569,16 +569,16 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
         i = 1;
 
         while (i != hw_points + 1) {
-                if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
+                if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
                         rgb_plus_1->red = rgb->red;
-                if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
+                if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
                         rgb_plus_1->green = rgb->green;
-                if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
+                if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
                         rgb_plus_1->blue = rgb->blue;
 
-                rgb->delta_red = dal_fixed31_32_sub(rgb_plus_1->red, rgb->red);
-                rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
-                rgb->delta_blue = dal_fixed31_32_sub(rgb_plus_1->blue, rgb->blue);
+                rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
+                rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
+                rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 
                 ++rgb_plus_1;
                 ++rgb;
@@ -2269,74 +2269,6 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
 
         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
 }
-
-/**
- * TODO REMOVE, USE UPDATE INSTEAD
- */
-static void set_plane_config(
-        const struct dc *dc,
-        struct pipe_ctx *pipe_ctx,
-        struct resource_context *res_ctx)
-{
-        struct mem_input *mi = pipe_ctx->plane_res.mi;
-        struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-        struct xfm_grph_csc_adjustment adjust;
-        struct out_csc_color_matrix tbl_entry;
-        unsigned int i;
-
-        memset(&adjust, 0, sizeof(adjust));
-        memset(&tbl_entry, 0, sizeof(tbl_entry));
-        adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
-
-        dce_enable_fe_clock(dc->hwseq, mi->inst, true);
-
-        set_default_colors(pipe_ctx);
-        if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
-                tbl_entry.color_space =
-                        pipe_ctx->stream->output_color_space;
-
-                for (i = 0; i < 12; i++)
-                        tbl_entry.regval[i] =
-                        pipe_ctx->stream->csc_color_matrix.matrix[i];
-
-                pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
-                                (pipe_ctx->plane_res.xfm, &tbl_entry);
-        }
-
-        if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
-                adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
-
-                for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
-                        adjust.temperature_matrix[i] =
-                                pipe_ctx->stream->gamut_remap_matrix.matrix[i];
-        }
-
-        pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
-
-        pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
-        program_scaler(dc, pipe_ctx);
-
-        program_surface_visibility(dc, pipe_ctx);
-
-        mi->funcs->mem_input_program_surface_config(
-                        mi,
-                        plane_state->format,
-                        &plane_state->tiling_info,
-                        &plane_state->plane_size,
-                        plane_state->rotation,
-                        NULL,
-                        false);
-        if (mi->funcs->set_blank)
-                mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
-
-        if (dc->config.gpu_vm_support)
-                mi->funcs->mem_input_program_pte_vm(
-                                pipe_ctx->plane_res.mi,
-                                plane_state->format,
-                                &plane_state->tiling_info,
-                                plane_state->rotation);
-}
-
 static void update_plane_addr(const struct dc *dc,
                 struct pipe_ctx *pipe_ctx)
 {
@@ -3023,7 +2955,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
         .init_hw = init_hw,
         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
-        .set_plane_config = set_plane_config,
         .update_plane_addr = update_plane_addr,
         .update_pending_status = dce110_update_pending_status,
         .set_input_transfer_func = dce110_set_input_transfer_func,
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index 8ba3c12fc608..a7dce060204f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -373,13 +373,13 @@ static void calculate_inits(
         struct rect *chroma_viewport)
 {
         inits->h_int_scale_ratio_luma =
-                dal_fixed31_32_u2d19(data->ratios.horz) << 5;
+                dc_fixpt_u2d19(data->ratios.horz) << 5;
         inits->v_int_scale_ratio_luma =
-                dal_fixed31_32_u2d19(data->ratios.vert) << 5;
+                dc_fixpt_u2d19(data->ratios.vert) << 5;
         inits->h_int_scale_ratio_chroma =
-                dal_fixed31_32_u2d19(data->ratios.horz_c) << 5;
+                dc_fixpt_u2d19(data->ratios.horz_c) << 5;
         inits->v_int_scale_ratio_chroma =
-                dal_fixed31_32_u2d19(data->ratios.vert_c) << 5;
+                dc_fixpt_u2d19(data->ratios.vert_c) << 5;
 
         inits->h_init_luma.integer = 1;
         inits->v_init_luma.integer = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index fda01574d1ba..2d58daccc005 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -814,14 +814,25 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
         dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
 }
 
+static uint32_t read_pipe_fuses(struct dc_context *ctx)
+{
+        uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
+        /* VG20 support max 6 pipes */
+        value = value & 0x3f;
+        return value;
+}
+
 static bool construct(
         uint8_t num_virtual_links,
         struct dc *dc,
         struct dce110_resource_pool *pool)
 {
         unsigned int i;
+        int j;
         struct dc_context *ctx = dc->ctx;
         struct irq_service_init_data irq_init_data;
+        bool harvest_enabled = ASICREV_IS_VEGA20_P(ctx->asic_id.hw_internal_rev);
+        uint32_t pipe_fuses;
 
         ctx->dc_bios->regs = &bios_regs;
 
@@ -915,28 +926,41 @@ static bool construct(
         if (!pool->base.irqs)
                 goto irqs_create_fail;
 
+        /* retrieve valid pipe fuses */
+        if (harvest_enabled)
+                pipe_fuses = read_pipe_fuses(ctx);
+
+        /* index to valid pipe resource */
+        j = 0;
         for (i = 0; i < pool->base.pipe_count; i++) {
-                pool->base.timing_generators[i] =
+                if (harvest_enabled) {
+                        if ((pipe_fuses & (1 << i)) != 0) {
+                                dm_error("DC: skip invalid pipe %d!\n", i);
+                                continue;
+                        }
+                }
+
+                pool->base.timing_generators[j] =
                                 dce120_timing_generator_create(
                                         ctx,
                                         i,
                                         &dce120_tg_offsets[i]);
-                if (pool->base.timing_generators[i] == NULL) {
+                if (pool->base.timing_generators[j] == NULL) {
                         BREAK_TO_DEBUGGER();
                         dm_error("DC: failed to create tg!\n");
                         goto controller_create_fail;
                 }
 
-                pool->base.mis[i] = dce120_mem_input_create(ctx, i);
+                pool->base.mis[j] = dce120_mem_input_create(ctx, i);
 
-                if (pool->base.mis[i] == NULL) {
+                if (pool->base.mis[j] == NULL) {
                         BREAK_TO_DEBUGGER();
                         dm_error(
                                 "DC: failed to create memory input!\n");
                         goto controller_create_fail;
                 }
 
-                pool->base.ipps[i] = dce120_ipp_create(ctx, i);
+                pool->base.ipps[j] = dce120_ipp_create(ctx, i);
                 if (pool->base.ipps[i] == NULL) {
                         BREAK_TO_DEBUGGER();
                         dm_error(
@@ -944,7 +968,7 @@ static bool construct(
                         goto controller_create_fail;
                 }
 
-                pool->base.transforms[i] = dce120_transform_create(ctx, i);
+                pool->base.transforms[j] = dce120_transform_create(ctx, i);
                 if (pool->base.transforms[i] == NULL) {
                         BREAK_TO_DEBUGGER();
                         dm_error(
@@ -952,16 +976,23 @@ static bool construct(
                         goto res_create_fail;
                 }
 
-                pool->base.opps[i] = dce120_opp_create(
+                pool->base.opps[j] = dce120_opp_create(
                         ctx,
                         i);
-                if (pool->base.opps[i] == NULL) {
+                if (pool->base.opps[j] == NULL) {
                         BREAK_TO_DEBUGGER();
                         dm_error(
                                 "DC: failed to create output pixel processor!\n");
                 }
+
+                /* check next valid pipe */
+                j++;
         }
 
+        /* valid pipe num */
+        pool->base.pipe_count = j;
+        pool->base.timing_generator_count = j;
+
         if (!resource_construct(num_virtual_links, dc, &pool->base,
                          &res_create_funcs))
                 goto res_create_fail;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
index 5c69743a4b4f..84f52c63d95c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile
@@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
                 dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
                 dcn10_hubp.o dcn10_mpc.o \
                 dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
-                dcn10_hubbub.o dcn10_stream_encoder.o
+                dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o
 
 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 96d5878e9ccd..5d95a997fd9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -169,7 +169,7 @@ bool cm_helper_convert_to_custom_float(
         }
 
         if (fixpoint == true)
-                arr_points[1].custom_float_y = dal_fixed31_32_clamp_u0d14(arr_points[1].y);
+                arr_points[1].custom_float_y = dc_fixpt_clamp_u0d14(arr_points[1].y);
         else if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
                 &arr_points[1].custom_float_y)) {
                 BREAK_TO_DEBUGGER();
@@ -327,19 +327,19 @@ bool cm_helper_translate_curve_to_hw_format(
         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 
-        arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-                                             dal_fixed31_32_from_int(region_start));
-        arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-                                             dal_fixed31_32_from_int(region_end));
+        arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
+                                             dc_fixpt_from_int(region_start));
+        arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
+                                             dc_fixpt_from_int(region_end));
 
         y_r = rgb_resulted[0].red;
         y_g = rgb_resulted[0].green;
         y_b = rgb_resulted[0].blue;
 
-        y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
+        y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 
         arr_points[0].y = y1_min;
-        arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x);
+        arr_points[0].slope = dc_fixpt_div(arr_points[0].y, arr_points[0].x);
         y_r = rgb_resulted[hw_points - 1].red;
         y_g = rgb_resulted[hw_points - 1].green;
         y_b = rgb_resulted[hw_points - 1].blue;
@@ -347,22 +347,22 @@ bool cm_helper_translate_curve_to_hw_format(
         /* see comment above, m_arrPoints[1].y should be the Y value for the
          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
          */
-        y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
+        y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 
         arr_points[1].y = y3_max;
 
-        arr_points[1].slope = dal_fixed31_32_zero;
+        arr_points[1].slope = dc_fixpt_zero;
 
         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
                 /* for PQ, we want to have a straight line from last HW X point,
                  * and the slope to be such that we hit 1.0 at 10000 nits.
                  */
                 const struct fixed31_32 end_value =
-                                dal_fixed31_32_from_int(125);
+                                dc_fixpt_from_int(125);
 
-                arr_points[1].slope = dal_fixed31_32_div(
-                        dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-                        dal_fixed31_32_sub(end_value, arr_points[1].x));
+                arr_points[1].slope = dc_fixpt_div(
+                        dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
+                        dc_fixpt_sub(end_value, arr_points[1].x));
         }
 
         lut_params->hw_points_num = hw_points;
@@ -386,24 +386,24 @@ bool cm_helper_translate_curve_to_hw_format(
 
         i = 1;
         while (i != hw_points + 1) {
-                if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
+                if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
                         rgb_plus_1->red = rgb->red;
-                if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
+                if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
                         rgb_plus_1->green = rgb->green;
-                if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
+                if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
                         rgb_plus_1->blue = rgb->blue;
 
-                rgb->delta_red   = dal_fixed31_32_sub(rgb_plus_1->red,   rgb->red);
-                rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
-                rgb->delta_blue  = dal_fixed31_32_sub(rgb_plus_1->blue,  rgb->blue);
+                rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);
+                rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
+                rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);
 
                 if (fixpoint == true) {
-                        rgb->delta_red_reg   = dal_fixed31_32_clamp_u0d10(rgb->delta_red);
-                        rgb->delta_green_reg = dal_fixed31_32_clamp_u0d10(rgb->delta_green);
-                        rgb->delta_blue_reg  = dal_fixed31_32_clamp_u0d10(rgb->delta_blue);
-                        rgb->red_reg         = dal_fixed31_32_clamp_u0d14(rgb->red);
-                        rgb->green_reg       = dal_fixed31_32_clamp_u0d14(rgb->green);
-                        rgb->blue_reg        = dal_fixed31_32_clamp_u0d14(rgb->blue);
+                        rgb->delta_red_reg   = dc_fixpt_clamp_u0d10(rgb->delta_red);
+                        rgb->delta_green_reg = dc_fixpt_clamp_u0d10(rgb->delta_green);
+                        rgb->delta_blue_reg  = dc_fixpt_clamp_u0d10(rgb->delta_blue);
+                        rgb->red_reg         = dc_fixpt_clamp_u0d14(rgb->red);
+                        rgb->green_reg       = dc_fixpt_clamp_u0d14(rgb->green);
+                        rgb->blue_reg        = dc_fixpt_clamp_u0d14(rgb->blue);
                 }
 
                 ++rgb_plus_1;
@@ -489,19 +489,19 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 
-        arr_points[0].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-                                             dal_fixed31_32_from_int(region_start));
-        arr_points[1].x = dal_fixed31_32_pow(dal_fixed31_32_from_int(2),
-                                             dal_fixed31_32_from_int(region_end));
+        arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
+                                             dc_fixpt_from_int(region_start));
+        arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
+                                             dc_fixpt_from_int(region_end));
 
         y_r = rgb_resulted[0].red;
         y_g = rgb_resulted[0].green;
         y_b = rgb_resulted[0].blue;
 
-        y1_min = dal_fixed31_32_min(y_r, dal_fixed31_32_min(y_g, y_b));
+        y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 
         arr_points[0].y = y1_min;
-        arr_points[0].slope = dal_fixed31_32_div(arr_points[0].y, arr_points[0].x);
+        arr_points[0].slope = dc_fixpt_div(arr_points[0].y, arr_points[0].x);
         y_r = rgb_resulted[hw_points - 1].red;
         y_g = rgb_resulted[hw_points - 1].green;
         y_b = rgb_resulted[hw_points - 1].blue;
@@ -509,22 +509,22 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
         /* see comment above, m_arrPoints[1].y should be the Y value for the
          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
          */
-        y3_max = dal_fixed31_32_max(y_r, dal_fixed31_32_max(y_g, y_b));
+        y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 
         arr_points[1].y = y3_max;
 
-        arr_points[1].slope = dal_fixed31_32_zero;
+        arr_points[1].slope = dc_fixpt_zero;
 
         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
                 /* for PQ, we want to have a straight line from last HW X point,
                  * and the slope to be such that we hit 1.0 at 10000 nits.
                  */
                 const struct fixed31_32 end_value =
-                                dal_fixed31_32_from_int(125);
+                                dc_fixpt_from_int(125);
 
-                arr_points[1].slope = dal_fixed31_32_div(
-                        dal_fixed31_32_sub(dal_fixed31_32_one, arr_points[1].y),
-                        dal_fixed31_32_sub(end_value, arr_points[1].x));
+                arr_points[1].slope = dc_fixpt_div(
+                        dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
+                        dc_fixpt_sub(end_value, arr_points[1].x));
         }
 
         lut_params->hw_points_num = hw_points;
@@ -548,16 +548,16 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
 
         i = 1;
         while (i != hw_points + 1) {
-                if (dal_fixed31_32_lt(rgb_plus_1->red, rgb->red))
+                if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
                         rgb_plus_1->red = rgb->red;
-                if (dal_fixed31_32_lt(rgb_plus_1->green, rgb->green))
+                if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
                         rgb_plus_1->green = rgb->green;
-                if (dal_fixed31_32_lt(rgb_plus_1->blue, rgb->blue))
+                if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
                         rgb_plus_1->blue = rgb->blue;
 
-                rgb->delta_red   = dal_fixed31_32_sub(rgb_plus_1->red,   rgb->red);
-                rgb->delta_green = dal_fixed31_32_sub(rgb_plus_1->green, rgb->green);
-                rgb->delta_blue  = dal_fixed31_32_sub(rgb_plus_1->blue,  rgb->blue);
+                rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);
+                rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
+                rgb->delta_blue  = dc_fixpt_sub(rgb_plus_1->blue,  rgb->blue);
 
                 ++rgb_plus_1;
                 ++rgb;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 8c4d9e523331..46a35c7f01df 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -130,7 +130,7 @@ void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
         /* Gamut remap in bypass */
 }
 
-#define IDENTITY_RATIO(ratio) (dal_fixed31_32_u2d19(ratio) == (1 << 19))
+#define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
 
 
 bool dpp_get_optimal_number_of_taps(
@@ -152,6 +152,11 @@ bool dpp_get_optimal_number_of_taps(
                 scl_data->format == PIXEL_FORMAT_FP16)
                 return false;
 
+        if (scl_data->viewport.width > scl_data->h_active &&
+                dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
+                scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
+                return false;
+
         /* TODO: add lb check */
 
         /* No support for programming ratio of 4, drop to 3.99999.. */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 4f373c97804f..116977eb24e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -811,13 +811,13 @@ void dpp1_program_input_lut(
         REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0);
         for (i = 0; i < gamma->num_entries; i++) {
                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
-                                dal_fixed31_32_round(
+                                dc_fixpt_round(
                                         gamma->entries.red[i]));
                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
-                                dal_fixed31_32_round(
+                                dc_fixpt_round(
                                         gamma->entries.green[i]));
                 REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR,
-                                dal_fixed31_32_round(
+                                dc_fixpt_round(
                                         gamma->entries.blue[i]));
         }
         // Power off LUT memory
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index 3eb824debf43..4ddd6273d5a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -169,7 +169,7 @@ static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
                 const struct scaler_data *data,
                 bool dbg_always_scale)
 {
-        const long long one = dal_fixed31_32_one.value;
+        const long long one = dc_fixpt_one.value;
 
         if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
                 /* DSCL is processing data in fixed format */
@@ -464,8 +464,8 @@ static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *d
         int num_part_y, num_part_c;
         int vtaps = scl_data->taps.v_taps;
         int vtaps_c = scl_data->taps.v_taps_c;
-        int ceil_vratio = dal_fixed31_32_ceil(scl_data->ratios.vert);
-        int ceil_vratio_c = dal_fixed31_32_ceil(scl_data->ratios.vert_c);
+        int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
+        int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
         enum lb_memory_config mem_cfg = LB_MEMORY_CONFIG_0;
 
         if (dpp->base.ctx->dc->debug.use_max_lb)
@@ -565,52 +565,52 @@ static void dpp1_dscl_set_manual_ratio_init(
         uint32_t init_int = 0;
 
         REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
-                        SCL_H_SCALE_RATIO, dal_fixed31_32_u2d19(data->ratios.horz) << 5);
+                        SCL_H_SCALE_RATIO, dc_fixpt_u2d19(data->ratios.horz) << 5);
 
         REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
-                        SCL_V_SCALE_RATIO, dal_fixed31_32_u2d19(data->ratios.vert) << 5);
+                        SCL_V_SCALE_RATIO, dc_fixpt_u2d19(data->ratios.vert) << 5);
 
         REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
-                        SCL_H_SCALE_RATIO_C, dal_fixed31_32_u2d19(data->ratios.horz_c) << 5);
+                        SCL_H_SCALE_RATIO_C, dc_fixpt_u2d19(data->ratios.horz_c) << 5);
 
         REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
-                        SCL_V_SCALE_RATIO_C, dal_fixed31_32_u2d19(data->ratios.vert_c) << 5);
+                        SCL_V_SCALE_RATIO_C, dc_fixpt_u2d19(data->ratios.vert_c) << 5);
 
         /*
          * 0.24 format for fraction, first five bits zeroed
          */
-        init_frac = dal_fixed31_32_u0d19(data->inits.h) << 5;
-        init_int = dal_fixed31_32_floor(data->inits.h);
+        init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
+        init_int = dc_fixpt_floor(data->inits.h);
         REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
                 SCL_H_INIT_FRAC, init_frac,
                 SCL_H_INIT_INT, init_int);
 
-        init_frac = dal_fixed31_32_u0d19(data->inits.h_c) << 5;
-        init_int = dal_fixed31_32_floor(data->inits.h_c);
+        init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
+        init_int = dc_fixpt_floor(data->inits.h_c);
         REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
                 SCL_H_INIT_FRAC_C, init_frac,
                 SCL_H_INIT_INT_C, init_int);
 
-        init_frac = dal_fixed31_32_u0d19(data->inits.v) << 5;
-        init_int = dal_fixed31_32_floor(data->inits.v);
+        init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
+        init_int = dc_fixpt_floor(data->inits.v);
         REG_SET_2(SCL_VERT_FILTER_INIT, 0,
                 SCL_V_INIT_FRAC, init_frac,
                 SCL_V_INIT_INT, init_int);
 
-        init_frac = dal_fixed31_32_u0d19(data->inits.v_bot) << 5;
-        init_int = dal_fixed31_32_floor(data->inits.v_bot);
+        init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
+        init_int = dc_fixpt_floor(data->inits.v_bot);
         REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
                 SCL_V_INIT_FRAC_BOT, init_frac,
                 SCL_V_INIT_INT_BOT, init_int);
 
-        init_frac = dal_fixed31_32_u0d19(data->inits.v_c) << 5;
-        init_int = dal_fixed31_32_floor(data->inits.v_c);
+        init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
+        init_int = dc_fixpt_floor(data->inits.v_c);
         REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
                 SCL_V_INIT_FRAC_C, init_frac,
                 SCL_V_INIT_INT_C, init_int);
 
-        init_frac = dal_fixed31_32_u0d19(data->inits.v_c_bot) << 5;
-        init_int = dal_fixed31_32_floor(data->inits.v_c_bot);
+        init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
+        init_int = dc_fixpt_floor(data->inits.v_c_bot);
         REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
                 SCL_V_INIT_FRAC_BOT_C, init_frac,
                 SCL_V_INIT_INT_BOT_C, init_int);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index b9fb14a3224b..943143efbb82 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -476,6 +476,14 @@ void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
                         DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
 }
 
+void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)
+{
+        uint32_t reset_en = reset ? 1 : 0;
+
+        REG_UPDATE(DCHUBBUB_SOFT_RESET,
+                        DCHUBBUB_GLOBAL_SOFT_RESET, reset_en);
+}
+
 static bool hubbub1_dcc_support_swizzle(
                 enum swizzle_mode_values swizzle,
                 unsigned int bytes_per_element,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index f479f54e5bb2..6315a0e6b0d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -48,7 +48,8 @@
         SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\
         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
         SR(DCHUBBUB_TEST_DEBUG_INDEX), \
-        SR(DCHUBBUB_TEST_DEBUG_DATA)
+        SR(DCHUBBUB_TEST_DEBUG_DATA),\
+        SR(DCHUBBUB_SOFT_RESET)
 
 #define HUBBUB_SR_WATERMARK_REG_LIST()\
         SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\
@@ -105,6 +106,7 @@ struct dcn_hubbub_registers {
         uint32_t DCHUBBUB_SDPIF_AGP_BOT;
         uint32_t DCHUBBUB_SDPIF_AGP_TOP;
         uint32_t DCHUBBUB_CRC_CTRL;
+        uint32_t DCHUBBUB_SOFT_RESET;
 };
 
 /* set field name */
@@ -114,6 +116,7 @@ struct dcn_hubbub_registers {
 
 #define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\
                 HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \
+                HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \
                 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \
                 HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \
                 HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \
@@ -143,6 +146,7 @@ struct dcn_hubbub_registers {
                 type DCHUBBUB_ARB_SAT_LEVEL;\
                 type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\
                 type DCHUBBUB_GLOBAL_TIMER_REFDIV;\
+                type DCHUBBUB_GLOBAL_SOFT_RESET; \
                 type SDPIF_FB_TOP;\
                 type SDPIF_FB_BASE;\
                 type SDPIF_FB_OFFSET;\
@@ -201,6 +205,7 @@ void hubbub1_toggle_watermark_change_req(
 void hubbub1_wm_read_state(struct hubbub *hubbub,
                 struct dcn_hubbub_wm *wm);
 
+void hubbub1_soft_reset(struct hubbub *hubbub, bool reset);
 void hubbub1_construct(struct hubbub *hubbub,
         struct dc_context *ctx,
         const struct dcn_hubbub_registers *hubbub_regs,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 0cbc83edd37f..d2ab78b35a7a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -78,6 +78,27 @@ static void hubp1_disconnect(struct hubp *hubp)
                         CURSOR_ENABLE, 0);
 }
 
+static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
+{
+        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+        uint32_t disable = disable_hubp ? 1 : 0;
+
+        REG_UPDATE(DCHUBP_CNTL,
+                        HUBP_DISABLE, disable);
+}
+
+static unsigned int hubp1_get_underflow_status(struct hubp *hubp)
+{
+        uint32_t hubp_underflow = 0;
+        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
+
+        REG_GET(DCHUBP_CNTL,
+                HUBP_UNDERFLOW_STATUS,
+                &hubp_underflow);
+
+        return hubp_underflow;
+}
+
 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
 {
         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
@@ -1054,8 +1075,8 @@ void hubp1_cursor_set_position(
         ASSERT(param->h_scale_ratio.value);
 
         if (param->h_scale_ratio.value)
-                dst_x_offset = dal_fixed31_32_floor(dal_fixed31_32_div(
-                                dal_fixed31_32_from_int(dst_x_offset),
+                dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
+                                dc_fixpt_from_int(dst_x_offset),
                                 param->h_scale_ratio));
 
         if (src_x_offset >= (int)param->viewport_width)
@@ -1117,6 +1138,9 @@ static struct hubp_funcs dcn10_hubp_funcs = {
         .hubp_clk_cntl = hubp1_clk_cntl,
         .hubp_vtg_sel = hubp1_vtg_sel,
         .hubp_read_state = hubp1_read_state,
+        .hubp_disable_control =  hubp1_disable_control,
+        .hubp_get_underflow_status = hubp1_get_underflow_status,
+
 };
 
 /*****************************************/
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index fe9b8c4a91ca..af384034398f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -253,6 +253,7 @@
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
         HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
+        HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
         HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
@@ -421,6 +422,7 @@
 
 #define DCN_HUBP_REG_FIELD_LIST(type) \
         type HUBP_BLANK_EN;\
+        type HUBP_DISABLE;\
         type HUBP_TTU_DISABLE;\
         type HUBP_NO_OUTSTANDING_REQ;\
         type HUBP_VTG_SEL;\
@@ -723,4 +725,5 @@ void hubp1_read_state(struct hubp *hubp);
 
 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
 
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 572fa601a0eb..f8e0576af6e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -127,24 +127,26 @@ static void dcn10_log_hubp_states(struct dc *dc)
 
                 hubp->funcs->hubp_read_state(hubp);
 
-                DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
-                                "  %6d  %8d  %7d  %8xh",
-                                hubp->inst,
-                                s->pixel_format,
-                                s->inuse_addr_hi,
-                                s->viewport_width,
-                                s->viewport_height,
-                                s->rotation_angle,
-                                s->h_mirror_en,
-                                s->sw_mode,
-                                s->dcc_en,
-                                s->blank_en,
-                                s->ttu_disable,
-                                s->underflow_status);
-                DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
-                DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
-                DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
-                DTN_INFO("\n");
+                if (!s->blank_en) {
+                        DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
+                                        "  %6d  %8d  %7d  %8xh",
+                                        hubp->inst,
+                                        s->pixel_format,
+                                        s->inuse_addr_hi,
+                                        s->viewport_width,
+                                        s->viewport_height,
+                                        s->rotation_angle,
+                                        s->h_mirror_en,
+                                        s->sw_mode,
+                                        s->dcc_en,
+                                        s->blank_en,
+                                        s->ttu_disable,
+                                        s->underflow_status);
+                        DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
+                        DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
+                        DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
+                        DTN_INFO("\n");
+                }
         }
 
         DTN_INFO("\n=========RQ========\n");
@@ -155,16 +157,17 @@ static void dcn10_log_hubp_states(struct dc *dc)
                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 
-                DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
-                        i, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
-                        rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
-                        rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
-                        rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
-                        rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
-                        rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
-                        rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
-                        rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
-                        rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
+                if (!s->blank_en)
+                        DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
+                                pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
+                                rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
+                                rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
+                                rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
+                                rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
+                                rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
+                                rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
+                                rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
+                                rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
         }
 
         DTN_INFO("========DLG========\n");
@@ -179,27 +182,28 @@ static void dcn10_log_hubp_states(struct dc *dc)
                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 
-                DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
-                        "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
-                        "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
-                        i, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
-                        dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
-                        dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
-                        dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
-                        dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
-                        dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
-                        dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
-                        dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
-                        dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
-                        dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
-                        dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
-                        dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
-                        dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
-                        dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
-                        dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
-                        dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
-                        dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
-                        dlg_regs->xfc_reg_remote_surface_flip_latency);
+                if (!s->blank_en)
+                        DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
+                                "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
+                                "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
+                                pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
+                                dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
+                                dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
+                                dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
+                                dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
+                                dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
+                                dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
+                                dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
+                                dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
+                                dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
+                                dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
+                                dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
+                                dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
+                                dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
+                                dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
+                                dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
+                                dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
+                                dlg_regs->xfc_reg_remote_surface_flip_latency);
         }
 
         DTN_INFO("========TTU========\n");
@@ -210,14 +214,15 @@ static void dcn10_log_hubp_states(struct dc *dc)
                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 
-                DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
-                        i, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
-                        ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
-                        ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
-                        ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
-                        ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
-                        ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
-                        ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
+                if (!s->blank_en)
+                        DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
+                                pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
+                                ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
+                                ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
+                                ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
+                                ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
+                                ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
+                                ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
         }
         DTN_INFO("\n");
 }
@@ -321,6 +326,12 @@ void dcn10_log_hw_state(struct dc *dc)
                                 s.h_total,
                                 s.v_total,
                                 s.underflow_occurred_status);
+
+                // Clear underflow for debug purposes
+                // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
+                // This function is called only from Windows or Diags test environment, hence it's safe to clear
+                // it from here without affecting the original intent.
+                tg->funcs->clear_optc_underflow(tg);
         }
         DTN_INFO("\n");
 
@@ -747,6 +758,90 @@ static void reset_back_end_for_pipe(
                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 }
 
+static bool dcn10_hw_wa_force_recovery(struct dc *dc)
+{
+        struct hubp *hubp ;
+        unsigned int i;
+        bool need_recover = true;
+
+        if (!dc->debug.recovery_enabled)
+                return false;
+
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                struct pipe_ctx *pipe_ctx =
+                        &dc->current_state->res_ctx.pipe_ctx[i];
+                if (pipe_ctx != NULL) {
+                        hubp = pipe_ctx->plane_res.hubp;
+                        if (hubp != NULL) {
+                                if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
+                                        /* one pipe underflow, we will reset all the pipes*/
+                                        need_recover = true;
+                                }
+                        }
+                }
+        }
+        if (!need_recover)
+                return false;
+        /*
+        DCHUBP_CNTL:HUBP_BLANK_EN=1
+        DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
+        DCHUBP_CNTL:HUBP_DISABLE=1
+        DCHUBP_CNTL:HUBP_DISABLE=0
+        DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
+        DCSURF_PRIMARY_SURFACE_ADDRESS
+        DCHUBP_CNTL:HUBP_BLANK_EN=0
+        */
+
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                struct pipe_ctx *pipe_ctx =
+                        &dc->current_state->res_ctx.pipe_ctx[i];
+                if (pipe_ctx != NULL) {
+                        hubp = pipe_ctx->plane_res.hubp;
+                        /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
+                        if (hubp != NULL)
+                                hubp->funcs->set_hubp_blank_en(hubp, true);
+                }
+        }
+        /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
+        hubbub1_soft_reset(dc->res_pool->hubbub, true);
+
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                struct pipe_ctx *pipe_ctx =
+                        &dc->current_state->res_ctx.pipe_ctx[i];
+                if (pipe_ctx != NULL) {
+                        hubp = pipe_ctx->plane_res.hubp;
+                        /*DCHUBP_CNTL:HUBP_DISABLE=1*/
+                        if (hubp != NULL)
+                                hubp->funcs->hubp_disable_control(hubp, true);
+                }
+        }
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                struct pipe_ctx *pipe_ctx =
+                        &dc->current_state->res_ctx.pipe_ctx[i];
+                if (pipe_ctx != NULL) {
+                        hubp = pipe_ctx->plane_res.hubp;
+                        /*DCHUBP_CNTL:HUBP_DISABLE=0*/
+                        if (hubp != NULL)
+                                hubp->funcs->hubp_disable_control(hubp, true);
+                }
+        }
+        /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
+        hubbub1_soft_reset(dc->res_pool->hubbub, false);
+        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+                struct pipe_ctx *pipe_ctx =
+                        &dc->current_state->res_ctx.pipe_ctx[i];
+                if (pipe_ctx != NULL) {
+                        hubp = pipe_ctx->plane_res.hubp;
+                        /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
+                        if (hubp != NULL)
+                                hubp->funcs->set_hubp_blank_en(hubp, true);
+                }
+        }
+        return true;
+
+}
+
+
 static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 {
         static bool should_log_hw_state; /* prevent hw state log by default */
@@ -755,13 +850,17 @@ static void dcn10_verify_allow_pstate_change_high(struct dc *dc)
                 if (should_log_hw_state) {
                         dcn10_log_hw_state(dc);
                 }
-
                 BREAK_TO_DEBUGGER();
+                if (dcn10_hw_wa_force_recovery(dc)) {
+                /*check again*/
+                        if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
+                                BREAK_TO_DEBUGGER();
+                }
         }
 }
 
 /* trigger HW to start disconnect plane from stream on the next vsync */
-static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
+void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
         struct hubp *hubp = pipe_ctx->plane_res.hubp;
         int dpp_id = pipe_ctx->plane_res.dpp->inst;
@@ -944,7 +1043,7 @@ static void dcn10_init_hw(struct dc *dc)
                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 
-                plane_atomic_disconnect(dc, pipe_ctx);
+                hwss1_plane_atomic_disconnect(dc, pipe_ctx);
         }
 
         for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -1685,22 +1784,22 @@ static uint16_t fixed_point_to_int_frac(
 
         uint16_t result;
 
-        uint16_t d = (uint16_t)dal_fixed31_32_floor(
-                dal_fixed31_32_abs(
+        uint16_t d = (uint16_t)dc_fixpt_floor(
+                dc_fixpt_abs(
                         arg));
 
         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
-                numerator = (uint16_t)dal_fixed31_32_floor(
-                        dal_fixed31_32_mul_int(
+                numerator = (uint16_t)dc_fixpt_floor(
+                        dc_fixpt_mul_int(
                                 arg,
                                 divisor));
         else {
-                numerator = dal_fixed31_32_floor(
-                        dal_fixed31_32_sub(
-                                dal_fixed31_32_from_int(
+                numerator = dc_fixpt_floor(
+                        dc_fixpt_sub(
+                                dc_fixpt_from_int(
                                         1LL << integer_bits),
-                                dal_fixed31_32_recip(
-                                        dal_fixed31_32_from_int(
+                                dc_fixpt_recip(
+                                        dc_fixpt_from_int(
                                                 divisor))));
         }
 
@@ -1710,8 +1809,8 @@ static uint16_t fixed_point_to_int_frac(
                 result = (uint16_t)(
                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
 
-        if ((result != 0) && dal_fixed31_32_lt(
-                arg, dal_fixed31_32_zero))
+        if ((result != 0) && dc_fixpt_lt(
+                arg, dc_fixpt_zero))
                 result |= 1 << (integer_bits + fractional_bits);
 
         return result;
@@ -1725,8 +1824,8 @@ void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
                         && plane_state->input_csc_color_matrix.enable_adjustment
                         && plane_state->coeff_reduction_factor.value != 0) {
                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
-                        dal_fixed31_32_mul(plane_state->coeff_reduction_factor,
-                                        dal_fixed31_32_from_fraction(256, 255)),
+                        dc_fixpt_mul(plane_state->coeff_reduction_factor,
+                                        dc_fixpt_from_fraction(256, 255)),
                                 2,
                                 13);
                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
@@ -1995,7 +2094,7 @@ static void dcn10_blank_pixel_data(
 
 static void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
 {
-        struct fixed31_32 multiplier = dal_fixed31_32_from_fraction(
+        struct fixed31_32 multiplier = dc_fixpt_from_fraction(
                         pipe_ctx->plane_state->sdr_white_level, 80);
         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
         struct custom_float_format fmt;
@@ -2179,7 +2278,7 @@ static void dcn10_apply_ctx_for_surface(
                         old_pipe_ctx->plane_state &&
                         old_pipe_ctx->stream_res.tg == tg) {
 
-                        plane_atomic_disconnect(dc, old_pipe_ctx);
+                        hwss1_plane_atomic_disconnect(dc, old_pipe_ctx);
                         removed_pipe[i] = true;
 
                         DC_LOG_DC(
@@ -2487,15 +2586,6 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
 }
 
-static void set_plane_config(
-        const struct dc *dc,
-        struct pipe_ctx *pipe_ctx,
-        struct resource_context *res_ctx)
-{
-        /* TODO */
-        program_gamut_remap(pipe_ctx);
-}
-
 static void dcn10_config_stereo_parameters(
                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
 {
@@ -2673,7 +2763,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
         .init_hw = dcn10_init_hw,
         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
-        .set_plane_config = set_plane_config,
         .update_plane_addr = dcn10_update_plane_addr,
         .update_dchub = dcn10_update_dchub,
         .update_pending_status = dcn10_update_pending_status,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index 6c526b5095d9..44f734b73f9e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -37,4 +37,6 @@ extern void fill_display_configs(
 
 bool is_rgb_cspace(enum dc_color_space output_color_space);
 
+void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
+
 #endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
new file mode 100644
index 000000000000..21fa40ac0786
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -0,0 +1,1362 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn10_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "gpio_service_interface.h"
+
+#define CTX \
+        enc10->base.ctx
+#define DC_LOGGER \
+        enc10->base.ctx->logger
+
+#define REG(reg)\
+        (enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+        enc10->link_shift->field_name, enc10->link_mask->field_name
+
+
+/*
+ * @brief
+ * Trigger Source Select
+ * ASIC-dependent, actual values for register programming
+ */
+#define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
+#define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
+
+enum {
+        DP_MST_UPDATE_MAX_RETRY = 50
+};
+
+
+
+static void aux_initialize(struct dcn10_link_encoder *enc10);
+
+
+static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
+        .validate_output_with_stream =
+                dcn10_link_encoder_validate_output_with_stream,
+        .hw_init = dcn10_link_encoder_hw_init,
+        .setup = dcn10_link_encoder_setup,
+        .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+        .enable_dp_output = dcn10_link_encoder_enable_dp_output,
+        .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
+        .disable_output = dcn10_link_encoder_disable_output,
+        .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+        .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+        .update_mst_stream_allocation_table =
+                dcn10_link_encoder_update_mst_stream_allocation_table,
+        .psr_program_dp_dphy_fast_training =
+                        dcn10_psr_program_dp_dphy_fast_training,
+        .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+        .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+        .enable_hpd = dcn10_link_encoder_enable_hpd,
+        .disable_hpd = dcn10_link_encoder_disable_hpd,
+        .is_dig_enabled = dcn10_is_dig_enabled,
+        .destroy = dcn10_link_encoder_destroy
+};
+
+static enum bp_result link_transmitter_control(
+        struct dcn10_link_encoder *enc10,
+        struct bp_transmitter_control *cntl)
+{
+        enum bp_result result;
+        struct dc_bios *bp = enc10->base.ctx->dc_bios;
+
+        result = bp->funcs->transmitter_control(bp, cntl);
+
+        return result;
+}
+
+static void enable_phy_bypass_mode(
+        struct dcn10_link_encoder *enc10,
+        bool enable)
+{
+        /* This register resides in DP back end block;
+         * transmitter is used for the offset
+         */
+        REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
+
+}
+
+static void disable_prbs_symbols(
+        struct dcn10_link_encoder *enc10,
+        bool disable)
+{
+        /* This register resides in DP back end block;
+         * transmitter is used for the offset
+         */
+        REG_UPDATE_4(DP_DPHY_CNTL,
+                        DPHY_ATEST_SEL_LANE0, disable,
+                        DPHY_ATEST_SEL_LANE1, disable,
+                        DPHY_ATEST_SEL_LANE2, disable,
+                        DPHY_ATEST_SEL_LANE3, disable);
+}
+
+static void disable_prbs_mode(
+        struct dcn10_link_encoder *enc10)
+{
+        REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
+}
+
+static void program_pattern_symbols(
+        struct dcn10_link_encoder *enc10,
+        uint16_t pattern_symbols[8])
+{
+        /* This register resides in DP back end block;
+         * transmitter is used for the offset
+         */
+        REG_SET_3(DP_DPHY_SYM0, 0,
+                        DPHY_SYM1, pattern_symbols[0],
+                        DPHY_SYM2, pattern_symbols[1],
+                        DPHY_SYM3, pattern_symbols[2]);
+
+        /* This register resides in DP back end block;
+         * transmitter is used for the offset
+         */
+        REG_SET_3(DP_DPHY_SYM1, 0,
+                        DPHY_SYM4, pattern_symbols[3],
+                        DPHY_SYM5, pattern_symbols[4],
+                        DPHY_SYM6, pattern_symbols[5]);
+
+        /* This register resides in DP back end block;
+         * transmitter is used for the offset
+         */
+        REG_SET_2(DP_DPHY_SYM2, 0,
+                        DPHY_SYM7, pattern_symbols[6],
+                        DPHY_SYM8, pattern_symbols[7]);
+}
+
+static void set_dp_phy_pattern_d102(
+        struct dcn10_link_encoder *enc10)
+{
+        /* Disable PHY Bypass mode to setup the test pattern */
+        enable_phy_bypass_mode(enc10, false);
+
+        /* For 10-bit PRBS or debug symbols
+         * please use the following sequence:
+         *
+         * Enable debug symbols on the lanes
+         */
+        disable_prbs_symbols(enc10, true);
+
+        /* Disable PRBS mode */
+        disable_prbs_mode(enc10);
+
+        /* Program debug symbols to be output */
+        {
+                uint16_t pattern_symbols[8] = {
+                        0x2AA, 0x2AA, 0x2AA, 0x2AA,
+                        0x2AA, 0x2AA, 0x2AA, 0x2AA
+                };
+
+                program_pattern_symbols(enc10, pattern_symbols);
+        }
+
+        /* Enable phy bypass mode to enable the test pattern */
+
+        enable_phy_bypass_mode(enc10, true);
+}
+
+static void set_link_training_complete(
+        struct dcn10_link_encoder *enc10,
+        bool complete)
+{
+        /* This register resides in DP back end block;
+         * transmitter is used for the offset
+         */
+        REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
+
+}
+
+void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
+        struct link_encoder *enc,
+        uint32_t index)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        /* Write Training Pattern */
+
+        REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
+
+        /* Set HW Register Training Complete to false */
+
+        set_link_training_complete(enc10, false);
+
+        /* Disable PHY Bypass mode to output Training Pattern */
+
+        enable_phy_bypass_mode(enc10, false);
+
+        /* Disable PRBS mode */
+        disable_prbs_mode(enc10);
+}
+
+static void setup_panel_mode(
+        struct dcn10_link_encoder *enc10,
+        enum dp_panel_mode panel_mode)
+{
+        uint32_t value;
+
+        ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
+        value = REG_READ(DP_DPHY_INTERNAL_CTRL);
+
+        switch (panel_mode) {
+        case DP_PANEL_MODE_EDP:
+                value = 0x1;
+                break;
+        case DP_PANEL_MODE_SPECIAL:
+                value = 0x11;
+                break;
+        default:
+                value = 0x0;
+                break;
+        }
+
+        REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
+}
+
+static void set_dp_phy_pattern_symbol_error(
+        struct dcn10_link_encoder *enc10)
+{
+        /* Disable PHY Bypass mode to setup the test pattern */
+        enable_phy_bypass_mode(enc10, false);
+
+        /* program correct panel mode*/
+        setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
+
+        /* A PRBS23 pattern is used for most DP electrical measurements. */
+
+        /* Enable PRBS symbols on the lanes */
+        disable_prbs_symbols(enc10, false);
+
+        /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
+        REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
+                        DPHY_PRBS_SEL, 1,
+                        DPHY_PRBS_EN, 1);
+
+        /* Enable phy bypass mode to enable the test pattern */
+        enable_phy_bypass_mode(enc10, true);
+}
+
+static void set_dp_phy_pattern_prbs7(
+        struct dcn10_link_encoder *enc10)
+{
+        /* Disable PHY Bypass mode to setup the test pattern */
+        enable_phy_bypass_mode(enc10, false);
+
+        /* A PRBS7 pattern is used for most DP electrical measurements. */
+
+        /* Enable PRBS symbols on the lanes */
+        disable_prbs_symbols(enc10, false);
+
+        /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
+        REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
+                        DPHY_PRBS_SEL, 0,
+                        DPHY_PRBS_EN, 1);
+
+        /* Enable phy bypass mode to enable the test pattern */
+        enable_phy_bypass_mode(enc10, true);
+}
+
+static void set_dp_phy_pattern_80bit_custom(
+        struct dcn10_link_encoder *enc10,
+        const uint8_t *pattern)
+{
+        /* Disable PHY Bypass mode to setup the test pattern */
+        enable_phy_bypass_mode(enc10, false);
+
+        /* Enable debug symbols on the lanes */
+
+        disable_prbs_symbols(enc10, true);
+
+        /* Enable PHY bypass mode to enable the test pattern */
+        /* TODO is it really needed ? */
+
+        enable_phy_bypass_mode(enc10, true);
+
+        /* Program 80 bit custom pattern */
+        {
+                uint16_t pattern_symbols[8];
+
+                pattern_symbols[0] =
+                        ((pattern[1] & 0x03) << 8) | pattern[0];
+                pattern_symbols[1] =
+                        ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
+                pattern_symbols[2] =
+                        ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
+                pattern_symbols[3] =
+                        (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
+                pattern_symbols[4] =
+                        ((pattern[6] & 0x03) << 8) | pattern[5];
+                pattern_symbols[5] =
+                        ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
+                pattern_symbols[6] =
+                        ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
+                pattern_symbols[7] =
+                        (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
+
+                program_pattern_symbols(enc10, pattern_symbols);
+        }
+
+        /* Enable phy bypass mode to enable the test pattern */
+
+        enable_phy_bypass_mode(enc10, true);
+}
+
+static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
+        struct dcn10_link_encoder *enc10,
+        unsigned int cp2520_pattern)
+{
+
+        /* previously there is a register DP_HBR2_EYE_PATTERN
+         * that is enabled to get the pattern.
+         * But it does not work with the latest spec change,
+         * so we are programming the following registers manually.
+         *
+         * The following settings have been confirmed
+         * by Nick Chorney and Sandra Liu
+         */
+
+        /* Disable PHY Bypass mode to setup the test pattern */
+
+        enable_phy_bypass_mode(enc10, false);
+
+        /* Setup DIG encoder in DP SST mode */
+        enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
+
+        /* ensure normal panel mode. */
+        setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
+
+        /* no vbid after BS (SR)
+         * DP_LINK_FRAMING_CNTL changed history Sandra Liu
+         * 11000260 / 11000104 / 110000FC
+         */
+        REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
+                        DP_IDLE_BS_INTERVAL, 0xFC,
+                        DP_VBID_DISABLE, 1,
+                        DP_VID_ENHANCED_FRAME_MODE, 1);
+
+        /* swap every BS with SR */
+        REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
+
+        /* select cp2520 patterns */
+        if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
+                REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
+                                DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
+        else
+                /* pre-DCE11 can only generate CP2520 pattern 2 */
+                ASSERT(cp2520_pattern == 2);
+
+        /* set link training complete */
+        set_link_training_complete(enc10, true);
+
+        /* disable video stream */
+        REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
+
+        /* Disable PHY Bypass mode to setup the test pattern */
+        enable_phy_bypass_mode(enc10, false);
+}
+
+static void set_dp_phy_pattern_passthrough_mode(
+        struct dcn10_link_encoder *enc10,
+        enum dp_panel_mode panel_mode)
+{
+        /* program correct panel mode */
+        setup_panel_mode(enc10, panel_mode);
+
+        /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
+         * in case we were doing HBR2 compliance pattern before
+         */
+        REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
+                        DP_IDLE_BS_INTERVAL, 0x2000,
+                        DP_VBID_DISABLE, 0,
+                        DP_VID_ENHANCED_FRAME_MODE, 1);
+
+        REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
+
+        /* set link training complete */
+        set_link_training_complete(enc10, true);
+
+        /* Disable PHY Bypass mode to setup the test pattern */
+        enable_phy_bypass_mode(enc10, false);
+
+        /* Disable PRBS mode */
+        disable_prbs_mode(enc10);
+}
+
+/* return value is bit-vector */
+static uint8_t get_frontend_source(
+        enum engine_id engine)
+{
+        switch (engine) {
+        case ENGINE_ID_DIGA:
+                return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
+        case ENGINE_ID_DIGB:
+                return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
+        case ENGINE_ID_DIGC:
+                return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
+        case ENGINE_ID_DIGD:
+                return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
+        case ENGINE_ID_DIGE:
+                return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
+        case ENGINE_ID_DIGF:
+                return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
+        case ENGINE_ID_DIGG:
+                return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
+        default:
+                ASSERT_CRITICAL(false);
+                return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
+        }
+}
+
+static void configure_encoder(
+        struct dcn10_link_encoder *enc10,
+        const struct dc_link_settings *link_settings)
+{
+        /* set number of lanes */
+
+        REG_SET(DP_CONFIG, 0,
+                        DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
+
+        /* setup scrambler */
+        REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
+}
+
+void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
+                        bool exit_link_training_required)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+        if (exit_link_training_required)
+                REG_UPDATE(DP_DPHY_FAST_TRAINING,
+                                DPHY_RX_FAST_TRAINING_CAPABLE, 1);
+        else {
+                REG_UPDATE(DP_DPHY_FAST_TRAINING,
+                                DPHY_RX_FAST_TRAINING_CAPABLE, 0);
+                /*In DCE 11, we are able to pre-program a Force SR register
+                 * to be able to trigger SR symbol after 5 idle patterns
+                 * transmitted. Upon PSR Exit, DMCU can trigger
+                 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
+                 * DPHY_LOAD_BS_COUNT_START and the internal counter
+                 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
+                 * replaced by SR symbol once.
+                 */
+
+                REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
+        }
+}
+
+void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
+                        unsigned int sdp_transmit_line_num_deadline)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+        REG_UPDATE_2(DP_SEC_CNTL1,
+                DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
+                DP_SEC_GSP0_PRIORITY, 1);
+}
+
+bool dcn10_is_dig_enabled(struct link_encoder *enc)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        uint32_t value;
+
+        REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
+        return value;
+}
+
+static void link_encoder_disable(struct dcn10_link_encoder *enc10)
+{
+        /* reset training pattern */
+        REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
+                        DPHY_TRAINING_PATTERN_SEL, 0);
+
+        /* reset training complete */
+        REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
+
+        /* reset panel mode */
+        setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
+}
+
+static void hpd_initialize(
+        struct dcn10_link_encoder *enc10)
+{
+        /* Associate HPD with DIG_BE */
+        enum hpd_source_id hpd_source = enc10->base.hpd_source;
+
+        REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
+}
+
+bool dcn10_link_encoder_validate_dvi_output(
+        const struct dcn10_link_encoder *enc10,
+        enum signal_type connector_signal,
+        enum signal_type signal,
+        const struct dc_crtc_timing *crtc_timing)
+{
+        uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
+
+        if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+                max_pixel_clock *= 2;
+
+        /* This handles the case of HDMI downgrade to DVI we don't want to
+         * we don't want to cap the pixel clock if the DDI is not DVI.
+         */
+        if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
+                        connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
+                max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
+
+        /* DVI only support RGB pixel encoding */
+        if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
+                return false;
+
+        /*connect DVI via adpater's HDMI connector*/
+        if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+                connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
+                signal != SIGNAL_TYPE_HDMI_TYPE_A &&
+                crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
+                return false;
+        if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
+                return false;
+
+        if (crtc_timing->pix_clk_khz > max_pixel_clock)
+                return false;
+
+        /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
+        switch (crtc_timing->display_color_depth) {
+        case COLOR_DEPTH_666:
+        case COLOR_DEPTH_888:
+        break;
+        case COLOR_DEPTH_101010:
+        case COLOR_DEPTH_161616:
+                if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
+                        return false;
+        break;
+        default:
+                return false;
+        }
+
+        return true;
+}
+
+static bool dcn10_link_encoder_validate_hdmi_output(
+        const struct dcn10_link_encoder *enc10,
+        const struct dc_crtc_timing *crtc_timing,
+        int adjusted_pix_clk_khz)
+{
+        enum dc_color_depth max_deep_color =
+                        enc10->base.features.max_hdmi_deep_color;
+
+        if (max_deep_color < crtc_timing->display_color_depth)
+                return false;
+
+        if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
+                return false;
+        if (adjusted_pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
+                return false;
+
+        if ((adjusted_pix_clk_khz == 0) ||
+                (adjusted_pix_clk_khz > enc10->base.features.max_hdmi_pixel_clock))
+                return false;
+
+        /* DCE11 HW does not support 420 */
+        if (!enc10->base.features.ycbcr420_supported &&
+                        crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+                return false;
+
+        if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
+                adjusted_pix_clk_khz >= 300000)
+                return false;
+        return true;
+}
+
+bool dcn10_link_encoder_validate_dp_output(
+        const struct dcn10_link_encoder *enc10,
+        const struct dc_crtc_timing *crtc_timing)
+{
+        /* default RGB only */
+        if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
+                return true;
+
+        if (enc10->base.features.flags.bits.IS_YCBCR_CAPABLE)
+                return true;
+
+        /* for DCE 8.x or later DP Y-only feature,
+         * we need ASIC cap + FeatureSupportDPYonly, not support 666
+         */
+        if (crtc_timing->flags.Y_ONLY &&
+                enc10->base.features.flags.bits.IS_YCBCR_CAPABLE &&
+                crtc_timing->display_color_depth != COLOR_DEPTH_666)
+                return true;
+
+        return false;
+}
+
+void dcn10_link_encoder_construct(
+        struct dcn10_link_encoder *enc10,
+        const struct encoder_init_data *init_data,
+        const struct encoder_feature_support *enc_features,
+        const struct dcn10_link_enc_registers *link_regs,
+        const struct dcn10_link_enc_aux_registers *aux_regs,
+        const struct dcn10_link_enc_hpd_registers *hpd_regs,
+        const struct dcn10_link_enc_shift *link_shift,
+        const struct dcn10_link_enc_mask *link_mask)
+{
+        struct bp_encoder_cap_info bp_cap_info = {0};
+        const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+        enum bp_result result = BP_RESULT_OK;
+
+        enc10->base.funcs = &dcn10_lnk_enc_funcs;
+        enc10->base.ctx = init_data->ctx;
+        enc10->base.id = init_data->encoder;
+
+        enc10->base.hpd_source = init_data->hpd_source;
+        enc10->base.connector = init_data->connector;
+
+        enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+        enc10->base.features = *enc_features;
+
+        enc10->base.transmitter = init_data->transmitter;
+
+        /* set the flag to indicate whether driver poll the I2C data pin
+         * while doing the DP sink detect
+         */
+
+/*      if (dal_adapter_service_is_feature_supported(as,
+                FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+                enc10->base.features.flags.bits.
+                        DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+        enc10->base.output_signals =
+                SIGNAL_TYPE_DVI_SINGLE_LINK |
+                SIGNAL_TYPE_DVI_DUAL_LINK |
+                SIGNAL_TYPE_LVDS |
+                SIGNAL_TYPE_DISPLAY_PORT |
+                SIGNAL_TYPE_DISPLAY_PORT_MST |
+                SIGNAL_TYPE_EDP |
+                SIGNAL_TYPE_HDMI_TYPE_A;
+
+        /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
+         * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
+         * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
+         * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
+         * Prefer DIG assignment is decided by board design.
+         * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
+         * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
+         * By this, adding DIGG should not hurt DCE 8.0.
+         * This will let DCE 8.1 share DCE 8.0 as much as possible
+         */
+
+        enc10->link_regs = link_regs;
+        enc10->aux_regs = aux_regs;
+        enc10->hpd_regs = hpd_regs;
+        enc10->link_shift = link_shift;
+        enc10->link_mask = link_mask;
+
+        switch (enc10->base.transmitter) {
+        case TRANSMITTER_UNIPHY_A:
+                enc10->base.preferred_engine = ENGINE_ID_DIGA;
+        break;
+        case TRANSMITTER_UNIPHY_B:
+                enc10->base.preferred_engine = ENGINE_ID_DIGB;
+        break;
+        case TRANSMITTER_UNIPHY_C:
+                enc10->base.preferred_engine = ENGINE_ID_DIGC;
+        break;
+        case TRANSMITTER_UNIPHY_D:
+                enc10->base.preferred_engine = ENGINE_ID_DIGD;
+        break;
+        case TRANSMITTER_UNIPHY_E:
+                enc10->base.preferred_engine = ENGINE_ID_DIGE;
+        break;
+        case TRANSMITTER_UNIPHY_F:
+                enc10->base.preferred_engine = ENGINE_ID_DIGF;
+        break;
+        case TRANSMITTER_UNIPHY_G:
+                enc10->base.preferred_engine = ENGINE_ID_DIGG;
+        break;
+        default:
+                ASSERT_CRITICAL(false);
+                enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+        }
+
+        /* default to one to mirror Windows behavior */
+        enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+        result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
+                                                enc10->base.id, &bp_cap_info);
+
+        /* Override features with DCE-specific values */
+        if (result == BP_RESULT_OK) {
+                enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+                                bp_cap_info.DP_HBR2_EN;
+                enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+                                bp_cap_info.DP_HBR3_EN;
+                enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+        } else {
+                DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+                                __func__,
+                                result);
+        }
+}
+
+bool dcn10_link_encoder_validate_output_with_stream(
+        struct link_encoder *enc,
+        const struct dc_stream_state *stream)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        bool is_valid;
+
+        switch (stream->signal) {
+        case SIGNAL_TYPE_DVI_SINGLE_LINK:
+        case SIGNAL_TYPE_DVI_DUAL_LINK:
+                is_valid = dcn10_link_encoder_validate_dvi_output(
+                        enc10,
+                        stream->sink->link->connector_signal,
+                        stream->signal,
+                        &stream->timing);
+        break;
+        case SIGNAL_TYPE_HDMI_TYPE_A:
+                is_valid = dcn10_link_encoder_validate_hdmi_output(
+                                enc10,
+                                &stream->timing,
+                                stream->phy_pix_clk);
+        break;
+        case SIGNAL_TYPE_DISPLAY_PORT:
+        case SIGNAL_TYPE_DISPLAY_PORT_MST:
+                is_valid = dcn10_link_encoder_validate_dp_output(
+                                        enc10, &stream->timing);
+        break;
+        case SIGNAL_TYPE_EDP:
+                is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
+        break;
+        case SIGNAL_TYPE_VIRTUAL:
+                is_valid = true;
+                break;
+        default:
+                is_valid = false;
+        break;
+        }
+
+        return is_valid;
+}
+
+void dcn10_link_encoder_hw_init(
+        struct link_encoder *enc)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        struct bp_transmitter_control cntl = { 0 };
+        enum bp_result result;
+
+        cntl.action = TRANSMITTER_CONTROL_INIT;
+        cntl.engine_id = ENGINE_ID_UNKNOWN;
+        cntl.transmitter = enc10->base.transmitter;
+        cntl.connector_obj_id = enc10->base.connector;
+        cntl.lanes_number = LANE_COUNT_FOUR;
+        cntl.coherent = false;
+        cntl.hpd_sel = enc10->base.hpd_source;
+
+        if (enc10->base.connector.id == CONNECTOR_ID_EDP)
+                cntl.signal = SIGNAL_TYPE_EDP;
+
+        result = link_transmitter_control(enc10, &cntl);
+
+        if (result != BP_RESULT_OK) {
+                DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+                        __func__);
+                BREAK_TO_DEBUGGER();
+                return;
+        }
+
+        if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
+                cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
+
+                result = link_transmitter_control(enc10, &cntl);
+
+                ASSERT(result == BP_RESULT_OK);
+
+        }
+        aux_initialize(enc10);
+
+        /* reinitialize HPD.
+         * hpd_initialize() will pass DIG_FE id to HW context.
+         * All other routine within HW context will use fe_engine_offset
+         * as DIG_FE id even caller pass DIG_FE id.
+         * So this routine must be called first.
+         */
+        hpd_initialize(enc10);
+}
+
+void dcn10_link_encoder_destroy(struct link_encoder **enc)
+{
+        kfree(TO_DCN10_LINK_ENC(*enc));
+        *enc = NULL;
+}
+
+void dcn10_link_encoder_setup(
+        struct link_encoder *enc,
+        enum signal_type signal)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+        switch (signal) {
+        case SIGNAL_TYPE_EDP:
+        case SIGNAL_TYPE_DISPLAY_PORT:
+                /* DP SST */
+                REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
+                break;
+        case SIGNAL_TYPE_LVDS:
+                /* LVDS */
+                REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
+                break;
+        case SIGNAL_TYPE_DVI_SINGLE_LINK:
+        case SIGNAL_TYPE_DVI_DUAL_LINK:
+                /* TMDS-DVI */
+                REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
+                break;
+        case SIGNAL_TYPE_HDMI_TYPE_A:
+                /* TMDS-HDMI */
+                REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
+                break;
+        case SIGNAL_TYPE_DISPLAY_PORT_MST:
+                /* DP MST */
+                REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
+                break;
+        default:
+                ASSERT_CRITICAL(false);
+                /* invalid mode ! */
+                break;
+        }
+
+}
+
+/* TODO: still need depth or just pass in adjusted pixel clock? */
+void dcn10_link_encoder_enable_tmds_output(
+        struct link_encoder *enc,
+        enum clock_source_id clock_source,
+        enum dc_color_depth color_depth,
+        enum signal_type signal,
+        uint32_t pixel_clock)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        struct bp_transmitter_control cntl = { 0 };
+        enum bp_result result;
+
+        /* Enable the PHY */
+
+        cntl.action = TRANSMITTER_CONTROL_ENABLE;
+        cntl.engine_id = enc->preferred_engine;
+        cntl.transmitter = enc10->base.transmitter;
+        cntl.pll_id = clock_source;
+        cntl.signal = signal;
+        if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+                cntl.lanes_number = 8;
+        else
+                cntl.lanes_number = 4;
+
+        cntl.hpd_sel = enc10->base.hpd_source;
+
+        cntl.pixel_clock = pixel_clock;
+        cntl.color_depth = color_depth;
+
+        result = link_transmitter_control(enc10, &cntl);
+
+        if (result != BP_RESULT_OK) {
+                DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+                        __func__);
+                BREAK_TO_DEBUGGER();
+        }
+}
+
+/* enables DP PHY output */
+void dcn10_link_encoder_enable_dp_output(
+        struct link_encoder *enc,
+        const struct dc_link_settings *link_settings,
+        enum clock_source_id clock_source)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        struct bp_transmitter_control cntl = { 0 };
+        enum bp_result result;
+
+        /* Enable the PHY */
+
+        /* number_of_lanes is used for pixel clock adjust,
+         * but it's not passed to asic_control.
+         * We need to set number of lanes manually.
+         */
+        configure_encoder(enc10, link_settings);
+
+        cntl.action = TRANSMITTER_CONTROL_ENABLE;
+        cntl.engine_id = enc->preferred_engine;
+        cntl.transmitter = enc10->base.transmitter;
+        cntl.pll_id = clock_source;
+        cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
+        cntl.lanes_number = link_settings->lane_count;
+        cntl.hpd_sel = enc10->base.hpd_source;
+        cntl.pixel_clock = link_settings->link_rate
+                                                * LINK_RATE_REF_FREQ_IN_KHZ;
+        /* TODO: check if undefined works */
+        cntl.color_depth = COLOR_DEPTH_UNDEFINED;
+
+        result = link_transmitter_control(enc10, &cntl);
+
+        if (result != BP_RESULT_OK) {
+                DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+                        __func__);
+                BREAK_TO_DEBUGGER();
+        }
+}
+
+/* enables DP PHY output in MST mode */
+void dcn10_link_encoder_enable_dp_mst_output(
+        struct link_encoder *enc,
+        const struct dc_link_settings *link_settings,
+        enum clock_source_id clock_source)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        struct bp_transmitter_control cntl = { 0 };
+        enum bp_result result;
+
+        /* Enable the PHY */
+
+        /* number_of_lanes is used for pixel clock adjust,
+         * but it's not passed to asic_control.
+         * We need to set number of lanes manually.
+         */
+        configure_encoder(enc10, link_settings);
+
+        cntl.action = TRANSMITTER_CONTROL_ENABLE;
+        cntl.engine_id = ENGINE_ID_UNKNOWN;
+        cntl.transmitter = enc10->base.transmitter;
+        cntl.pll_id = clock_source;
+        cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
+        cntl.lanes_number = link_settings->lane_count;
+        cntl.hpd_sel = enc10->base.hpd_source;
+        cntl.pixel_clock = link_settings->link_rate
+                                                * LINK_RATE_REF_FREQ_IN_KHZ;
+        /* TODO: check if undefined works */
+        cntl.color_depth = COLOR_DEPTH_UNDEFINED;
+
+        result = link_transmitter_control(enc10, &cntl);
+
+        if (result != BP_RESULT_OK) {
+                DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+                        __func__);
+                BREAK_TO_DEBUGGER();
+        }
+}
+/*
+ * @brief
+ * Disable transmitter and its encoder
+ */
+void dcn10_link_encoder_disable_output(
+        struct link_encoder *enc,
+        enum signal_type signal)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        struct bp_transmitter_control cntl = { 0 };
+        enum bp_result result;
+
+        if (!dcn10_is_dig_enabled(enc)) {
+                /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
+                return;
+        }
+        /* Power-down RX and disable GPU PHY should be paired.
+         * Disabling PHY without powering down RX may cause
+         * symbol lock loss, on which we will get DP Sink interrupt.
+         */
+
+        /* There is a case for the DP active dongles
+         * where we want to disable the PHY but keep RX powered,
+         * for those we need to ignore DP Sink interrupt
+         * by checking lane count that has been set
+         * on the last do_enable_output().
+         */
+
+        /* disable transmitter */
+        cntl.action = TRANSMITTER_CONTROL_DISABLE;
+        cntl.transmitter = enc10->base.transmitter;
+        cntl.hpd_sel = enc10->base.hpd_source;
+        cntl.signal = signal;
+        cntl.connector_obj_id = enc10->base.connector;
+
+        result = link_transmitter_control(enc10, &cntl);
+
+        if (result != BP_RESULT_OK) {
+                DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
+                        __func__);
+                BREAK_TO_DEBUGGER();
+                return;
+        }
+
+        /* disable encoder */
+        if (dc_is_dp_signal(signal))
+                link_encoder_disable(enc10);
+}
+
+void dcn10_link_encoder_dp_set_lane_settings(
+        struct link_encoder *enc,
+        const struct link_training_settings *link_settings)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        union dpcd_training_lane_set training_lane_set = { { 0 } };
+        int32_t lane = 0;
+        struct bp_transmitter_control cntl = { 0 };
+
+        if (!link_settings) {
+                BREAK_TO_DEBUGGER();
+                return;
+        }
+
+        cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
+        cntl.transmitter = enc10->base.transmitter;
+        cntl.connector_obj_id = enc10->base.connector;
+        cntl.lanes_number = link_settings->link_settings.lane_count;
+        cntl.hpd_sel = enc10->base.hpd_source;
+        cntl.pixel_clock = link_settings->link_settings.link_rate *
+                                                LINK_RATE_REF_FREQ_IN_KHZ;
+
+        for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
+                /* translate lane settings */
+
+                training_lane_set.bits.VOLTAGE_SWING_SET =
+                        link_settings->lane_settings[lane].VOLTAGE_SWING;
+                training_lane_set.bits.PRE_EMPHASIS_SET =
+                        link_settings->lane_settings[lane].PRE_EMPHASIS;
+
+                /* post cursor 2 setting only applies to HBR2 link rate */
+                if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
+                        /* this is passed to VBIOS
+                         * to program post cursor 2 level
+                         */
+                        training_lane_set.bits.POST_CURSOR2_SET =
+                                link_settings->lane_settings[lane].POST_CURSOR2;
+                }
+
+                cntl.lane_select = lane;
+                cntl.lane_settings = training_lane_set.raw;
+
+                /* call VBIOS table to set voltage swing and pre-emphasis */
+                link_transmitter_control(enc10, &cntl);
+        }
+}
+
+/* set DP PHY test and training patterns */
+void dcn10_link_encoder_dp_set_phy_pattern(
+        struct link_encoder *enc,
+        const struct encoder_set_dp_phy_pattern_param *param)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+        switch (param->dp_phy_pattern) {
+        case DP_TEST_PATTERN_TRAINING_PATTERN1:
+                dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
+                break;
+        case DP_TEST_PATTERN_TRAINING_PATTERN2:
+                dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
+                break;
+        case DP_TEST_PATTERN_TRAINING_PATTERN3:
+                dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
+                break;
+        case DP_TEST_PATTERN_TRAINING_PATTERN4:
+                dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
+                break;
+        case DP_TEST_PATTERN_D102:
+                set_dp_phy_pattern_d102(enc10);
+                break;
+        case DP_TEST_PATTERN_SYMBOL_ERROR:
+                set_dp_phy_pattern_symbol_error(enc10);
+                break;
+        case DP_TEST_PATTERN_PRBS7:
+                set_dp_phy_pattern_prbs7(enc10);
+                break;
+        case DP_TEST_PATTERN_80BIT_CUSTOM:
+                set_dp_phy_pattern_80bit_custom(
+                        enc10, param->custom_pattern);
+                break;
+        case DP_TEST_PATTERN_CP2520_1:
+                set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
+                break;
+        case DP_TEST_PATTERN_CP2520_2:
+                set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
+                break;
+        case DP_TEST_PATTERN_CP2520_3:
+                set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
+                break;
+        case DP_TEST_PATTERN_VIDEO_MODE: {
+                set_dp_phy_pattern_passthrough_mode(
+                        enc10, param->dp_panel_mode);
+                break;
+        }
+
+        default:
+                /* invalid phy pattern */
+                ASSERT_CRITICAL(false);
+                break;
+        }
+}
+
+static void fill_stream_allocation_row_info(
+        const struct link_mst_stream_allocation *stream_allocation,
+        uint32_t *src,
+        uint32_t *slots)
+{
+        const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
+
+        if (stream_enc) {
+                *src = stream_enc->id;
+                *slots = stream_allocation->slot_count;
+        } else {
+                *src = 0;
+                *slots = 0;
+        }
+}
+
+/* programs DP MST VC payload allocation */
+void dcn10_link_encoder_update_mst_stream_allocation_table(
+        struct link_encoder *enc,
+        const struct link_mst_stream_allocation_table *table)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        uint32_t value0 = 0;
+        uint32_t value1 = 0;
+        uint32_t value2 = 0;
+        uint32_t slots = 0;
+        uint32_t src = 0;
+        uint32_t retries = 0;
+
+        /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
+
+        /* --- Set MSE Stream Attribute -
+         * Setup VC Payload Table on Tx Side,
+         * Issue allocation change trigger
+         * to commit payload on both tx and rx side
+         */
+
+        /* we should clean-up table each time */
+
+        if (table->stream_count >= 1) {
+                fill_stream_allocation_row_info(
+                        &table->stream_allocations[0],
+                        &src,
+                        &slots);
+        } else {
+                src = 0;
+                slots = 0;
+        }
+
+        REG_UPDATE_2(DP_MSE_SAT0,
+                        DP_MSE_SAT_SRC0, src,
+                        DP_MSE_SAT_SLOT_COUNT0, slots);
+
+        if (table->stream_count >= 2) {
+                fill_stream_allocation_row_info(
+                        &table->stream_allocations[1],
+                        &src,
+                        &slots);
+        } else {
+                src = 0;
+                slots = 0;
+        }
+
+        REG_UPDATE_2(DP_MSE_SAT0,
+                        DP_MSE_SAT_SRC1, src,
+                        DP_MSE_SAT_SLOT_COUNT1, slots);
+
+        if (table->stream_count >= 3) {
+                fill_stream_allocation_row_info(
+                        &table->stream_allocations[2],
+                        &src,
+                        &slots);
+        } else {
+                src = 0;
+                slots = 0;
+        }
+
+        REG_UPDATE_2(DP_MSE_SAT1,
+                        DP_MSE_SAT_SRC2, src,
+                        DP_MSE_SAT_SLOT_COUNT2, slots);
+
+        if (table->stream_count >= 4) {
+                fill_stream_allocation_row_info(
+                        &table->stream_allocations[3],
+                        &src,
+                        &slots);
+        } else {
+                src = 0;
+                slots = 0;
+        }
+
+        REG_UPDATE_2(DP_MSE_SAT1,
+                        DP_MSE_SAT_SRC3, src,
+                        DP_MSE_SAT_SLOT_COUNT3, slots);
+
+        /* --- wait for transaction finish */
+
+        /* send allocation change trigger (ACT) ?
+         * this step first sends the ACT,
+         * then double buffers the SAT into the hardware
+         * making the new allocation active on the DP MST mode link
+         */
+
+        /* DP_MSE_SAT_UPDATE:
+         * 0 - No Action
+         * 1 - Update SAT with trigger
+         * 2 - Update SAT without trigger
+         */
+        REG_UPDATE(DP_MSE_SAT_UPDATE,
+                        DP_MSE_SAT_UPDATE, 1);
+
+        /* wait for update to complete
+         * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
+         * then wait for the transmission
+         * of at least 16 MTP headers on immediate local link.
+         * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
+         * a value of 1 indicates that DP MST mode
+         * is in the 16 MTP keepout region after a VC has been added.
+         * MST stream bandwidth (VC rate) can be configured
+         * after this bit is cleared
+         */
+        do {
+                udelay(10);
+
+                value0 = REG_READ(DP_MSE_SAT_UPDATE);
+
+                REG_GET(DP_MSE_SAT_UPDATE,
+                                DP_MSE_SAT_UPDATE, &value1);
+
+                REG_GET(DP_MSE_SAT_UPDATE,
+                                DP_MSE_16_MTP_KEEPOUT, &value2);
+
+                /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
+                if (!value1 && !value2)
+                        break;
+                ++retries;
+        } while (retries < DP_MST_UPDATE_MAX_RETRY);
+}
+
+void dcn10_link_encoder_connect_dig_be_to_fe(
+        struct link_encoder *enc,
+        enum engine_id engine,
+        bool connect)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+        uint32_t field;
+
+        if (engine != ENGINE_ID_UNKNOWN) {
+
+                REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
+
+                if (connect)
+                        field |= get_frontend_source(engine);
+                else
+                        field &= ~get_frontend_source(engine);
+
+                REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
+        }
+}
+
+
+#define HPD_REG(reg)\
+        (enc10->hpd_regs->reg)
+
+#define HPD_REG_READ(reg_name) \
+                dm_read_reg(CTX, HPD_REG(reg_name))
+
+#define HPD_REG_UPDATE_N(reg_name, n, ...)      \
+                generic_reg_update_ex(CTX, \
+                                HPD_REG(reg_name), \
+                                HPD_REG_READ(reg_name), \
+                                n, __VA_ARGS__)
+
+#define HPD_REG_UPDATE(reg_name, field, val)    \
+                HPD_REG_UPDATE_N(reg_name, 1, \
+                                FN(reg_name, field), val)
+
+void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+        HPD_REG_UPDATE(DC_HPD_CONTROL,
+                        DC_HPD_EN, 1);
+}
+
+void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
+{
+        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+        HPD_REG_UPDATE(DC_HPD_CONTROL,
+                        DC_HPD_EN, 0);
+}
+
+
+#define AUX_REG(reg)\
+        (enc10->aux_regs->reg)
+
+#define AUX_REG_READ(reg_name) \
+                dm_read_reg(CTX, AUX_REG(reg_name))
+
+#define AUX_REG_UPDATE_N(reg_name, n, ...)      \
+                generic_reg_update_ex(CTX, \
+                                AUX_REG(reg_name), \
+                                AUX_REG_READ(reg_name), \
+                                n, __VA_ARGS__)
+
+#define AUX_REG_UPDATE(reg_name, field, val)    \
+                AUX_REG_UPDATE_N(reg_name, 1, \
+                                FN(reg_name, field), val)
+
+#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2)   \
+                AUX_REG_UPDATE_N(reg, 2,\
+                                FN(reg, f1), v1,\
+                                FN(reg, f2), v2)
+
+static void aux_initialize(
+        struct dcn10_link_encoder *enc10)
+{
+        enum hpd_source_id hpd_source = enc10->base.hpd_source;
+
+        AUX_REG_UPDATE_2(AUX_CONTROL,
+                        AUX_HPD_SEL, hpd_source,
+                        AUX_LS_READ_EN, 0);
+
+        /* 1/4 window (the maximum allowed) */
+        AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
+                        AUX_RX_RECEIVE_WINDOW, 1);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
new file mode 100644
index 000000000000..2a97cdb2cfbb
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN10_H__
+#define __DC_LINK_ENCODER__DCN10_H__
+
+#include "link_encoder.h"
+
+#define TO_DCN10_LINK_ENC(link_encoder)\
+        container_of(link_encoder, struct dcn10_link_encoder, base)
+
+
+#define AUX_REG_LIST(id)\
+        SRI(AUX_CONTROL, DP_AUX, id), \
+        SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
+
+#define HPD_REG_LIST(id)\
+        SRI(DC_HPD_CONTROL, HPD, id)
+
+#define LE_DCN_COMMON_REG_LIST(id) \
+        SRI(DIG_BE_CNTL, DIG, id), \
+        SRI(DIG_BE_EN_CNTL, DIG, id), \
+        SRI(DP_CONFIG, DP, id), \
+        SRI(DP_DPHY_CNTL, DP, id), \
+        SRI(DP_DPHY_PRBS_CNTL, DP, id), \
+        SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
+        SRI(DP_DPHY_SYM0, DP, id), \
+        SRI(DP_DPHY_SYM1, DP, id), \
+        SRI(DP_DPHY_SYM2, DP, id), \
+        SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
+        SRI(DP_LINK_CNTL, DP, id), \
+        SRI(DP_LINK_FRAMING_CNTL, DP, id), \
+        SRI(DP_MSE_SAT0, DP, id), \
+        SRI(DP_MSE_SAT1, DP, id), \
+        SRI(DP_MSE_SAT2, DP, id), \
+        SRI(DP_MSE_SAT_UPDATE, DP, id), \
+        SRI(DP_SEC_CNTL, DP, id), \
+        SRI(DP_VID_STREAM_CNTL, DP, id), \
+        SRI(DP_DPHY_FAST_TRAINING, DP, id), \
+        SRI(DP_SEC_CNTL1, DP, id), \
+        SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
+        SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+        SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
+
+#define LE_DCN10_REG_LIST(id)\
+        LE_DCN_COMMON_REG_LIST(id)
+
+struct dcn10_link_enc_aux_registers {
+        uint32_t AUX_CONTROL;
+        uint32_t AUX_DPHY_RX_CONTROL0;
+};
+
+struct dcn10_link_enc_hpd_registers {
+        uint32_t DC_HPD_CONTROL;
+};
+
+struct dcn10_link_enc_registers {
+        uint32_t DIG_BE_CNTL;
+        uint32_t DIG_BE_EN_CNTL;
+        uint32_t DP_CONFIG;
+        uint32_t DP_DPHY_CNTL;
+        uint32_t DP_DPHY_INTERNAL_CTRL;
+        uint32_t DP_DPHY_PRBS_CNTL;
+        uint32_t DP_DPHY_SCRAM_CNTL;
+        uint32_t DP_DPHY_SYM0;
+        uint32_t DP_DPHY_SYM1;
+        uint32_t DP_DPHY_SYM2;
+        uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
+        uint32_t DP_LINK_CNTL;
+        uint32_t DP_LINK_FRAMING_CNTL;
+        uint32_t DP_MSE_SAT0;
+        uint32_t DP_MSE_SAT1;
+        uint32_t DP_MSE_SAT2;
+        uint32_t DP_MSE_SAT_UPDATE;
+        uint32_t DP_SEC_CNTL;
+        uint32_t DP_VID_STREAM_CNTL;
+        uint32_t DP_DPHY_FAST_TRAINING;
+        uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
+        uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
+        uint32_t DP_SEC_CNTL1;
+};
+
+#define LE_SF(reg_name, field_name, post_fix)\
+        .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
+        LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
+        LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
+        LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
+        LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
+        LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
+        LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
+        LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
+        LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
+        LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
+        LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
+        LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
+        LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
+        LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
+        LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
+        LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
+        LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
+        LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
+        LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
+        LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
+        LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
+        LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
+        LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
+        LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
+        LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
+        LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
+        LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
+        LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
+        LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
+        LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
+
+#define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
+        type DIG_ENABLE;\
+        type DIG_HPD_SELECT;\
+        type DIG_MODE;\
+        type DIG_FE_SOURCE_SELECT;\
+        type DPHY_BYPASS;\
+        type DPHY_ATEST_SEL_LANE0;\
+        type DPHY_ATEST_SEL_LANE1;\
+        type DPHY_ATEST_SEL_LANE2;\
+        type DPHY_ATEST_SEL_LANE3;\
+        type DPHY_PRBS_EN;\
+        type DPHY_PRBS_SEL;\
+        type DPHY_SYM1;\
+        type DPHY_SYM2;\
+        type DPHY_SYM3;\
+        type DPHY_SYM4;\
+        type DPHY_SYM5;\
+        type DPHY_SYM6;\
+        type DPHY_SYM7;\
+        type DPHY_SYM8;\
+        type DPHY_SCRAMBLER_BS_COUNT;\
+        type DPHY_SCRAMBLER_ADVANCE;\
+        type DPHY_RX_FAST_TRAINING_CAPABLE;\
+        type DPHY_LOAD_BS_COUNT;\
+        type DPHY_TRAINING_PATTERN_SEL;\
+        type DP_DPHY_HBR2_PATTERN_CONTROL;\
+        type DP_LINK_TRAINING_COMPLETE;\
+        type DP_IDLE_BS_INTERVAL;\
+        type DP_VBID_DISABLE;\
+        type DP_VID_ENHANCED_FRAME_MODE;\
+        type DP_VID_STREAM_ENABLE;\
+        type DP_UDI_LANES;\
+        type DP_SEC_GSP0_LINE_NUM;\
+        type DP_SEC_GSP0_PRIORITY;\
+        type DP_MSE_SAT_SRC0;\
+        type DP_MSE_SAT_SRC1;\
+        type DP_MSE_SAT_SRC2;\
+        type DP_MSE_SAT_SRC3;\
+        type DP_MSE_SAT_SLOT_COUNT0;\
+        type DP_MSE_SAT_SLOT_COUNT1;\
+        type DP_MSE_SAT_SLOT_COUNT2;\
+        type DP_MSE_SAT_SLOT_COUNT3;\
+        type DP_MSE_SAT_UPDATE;\
+        type DP_MSE_16_MTP_KEEPOUT;\
+        type AUX_HPD_SEL;\
+        type AUX_LS_READ_EN;\
+        type AUX_RX_RECEIVE_WINDOW;\
+        type DC_HPD_EN
+
+struct dcn10_link_enc_shift {
+        DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+};
+
+struct dcn10_link_enc_mask {
+        DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+};
+
+struct dcn10_link_encoder {
+        struct link_encoder base;
+        const struct dcn10_link_enc_registers *link_regs;
+        const struct dcn10_link_enc_aux_registers *aux_regs;
+        const struct dcn10_link_enc_hpd_registers *hpd_regs;
+        const struct dcn10_link_enc_shift *link_shift;
+        const struct dcn10_link_enc_mask *link_mask;
+};
+
+
+void dcn10_link_encoder_construct(
+        struct dcn10_link_encoder *enc10,
+        const struct encoder_init_data *init_data,
+        const struct encoder_feature_support *enc_features,
+        const struct dcn10_link_enc_registers *link_regs,
+        const struct dcn10_link_enc_aux_registers *aux_regs,
+        const struct dcn10_link_enc_hpd_registers *hpd_regs,
+        const struct dcn10_link_enc_shift *link_shift,
+        const struct dcn10_link_enc_mask *link_mask);
+
+bool dcn10_link_encoder_validate_dvi_output(
+        const struct dcn10_link_encoder *enc10,
+        enum signal_type connector_signal,
+        enum signal_type signal,
+        const struct dc_crtc_timing *crtc_timing);
+
+bool dcn10_link_encoder_validate_rgb_output(
+        const struct dcn10_link_encoder *enc10,
+        const struct dc_crtc_timing *crtc_timing);
+
+bool dcn10_link_encoder_validate_dp_output(
+        const struct dcn10_link_encoder *enc10,
+        const struct dc_crtc_timing *crtc_timing);
+
+bool dcn10_link_encoder_validate_wireless_output(
+        const struct dcn10_link_encoder *enc10,
+        const struct dc_crtc_timing *crtc_timing);
+
+bool dcn10_link_encoder_validate_output_with_stream(
+        struct link_encoder *enc,
+        const struct dc_stream_state *stream);
+
+/****************** HW programming ************************/
+
+/* initialize HW */  /* why do we initialze aux in here? */
+void dcn10_link_encoder_hw_init(struct link_encoder *enc);
+
+void dcn10_link_encoder_destroy(struct link_encoder **enc);
+
+/* program DIG_MODE in DIG_BE */
+/* TODO can this be combined with enable_output? */
+void dcn10_link_encoder_setup(
+        struct link_encoder *enc,
+        enum signal_type signal);
+
+/* enables TMDS PHY output */
+/* TODO: still need depth or just pass in adjusted pixel clock? */
+void dcn10_link_encoder_enable_tmds_output(
+        struct link_encoder *enc,
+        enum clock_source_id clock_source,
+        enum dc_color_depth color_depth,
+        enum signal_type signal,
+        uint32_t pixel_clock);
+
+/* enables DP PHY output */
+void dcn10_link_encoder_enable_dp_output(
+        struct link_encoder *enc,
+        const struct dc_link_settings *link_settings,
+        enum clock_source_id clock_source);
+
+/* enables DP PHY output in MST mode */
+void dcn10_link_encoder_enable_dp_mst_output(
+        struct link_encoder *enc,
+        const struct dc_link_settings *link_settings,
+        enum clock_source_id clock_source);
+
+/* disable PHY output */
+void dcn10_link_encoder_disable_output(
+        struct link_encoder *enc,
+        enum signal_type signal);
+
+/* set DP lane settings */
+void dcn10_link_encoder_dp_set_lane_settings(
+        struct link_encoder *enc,
+        const struct link_training_settings *link_settings);
+
+void dcn10_link_encoder_dp_set_phy_pattern(
+        struct link_encoder *enc,
+        const struct encoder_set_dp_phy_pattern_param *param);
+
+/* programs DP MST VC payload allocation */
+void dcn10_link_encoder_update_mst_stream_allocation_table(
+        struct link_encoder *enc,
+        const struct link_mst_stream_allocation_table *table);
+
+void dcn10_link_encoder_connect_dig_be_to_fe(
+        struct link_encoder *enc,
+        enum engine_id engine,
+        bool connect);
+
+void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
+        struct link_encoder *enc,
+        uint32_t index);
+
+void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
+
+void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
+
+void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
+                        bool exit_link_training_required);
+
+void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
+                        unsigned int sdp_transmit_line_num_deadline);
+
+bool dcn10_is_dig_enabled(struct link_encoder *enc);
+
+#endif /* __DC_LINK_ENCODER__DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index c734b7fa5835..f2fbce0e3fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -360,7 +360,7 @@ void optc1_program_timing(
 
 }
 
-static void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
+void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
 {
         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
@@ -1257,20 +1257,20 @@ void optc1_read_otg_state(struct optc *optc1,
                         OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
 }
 
-static void optc1_clear_optc_underflow(struct timing_generator *optc)
+void optc1_clear_optc_underflow(struct timing_generator *optc)
 {
         struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
         REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
 }
 
-static void optc1_tg_init(struct timing_generator *optc)
+void optc1_tg_init(struct timing_generator *optc)
 {
         optc1_set_blank_data_double_buffer(optc, true);
         optc1_clear_optc_underflow(optc);
 }
 
-static bool optc1_is_tg_enabled(struct timing_generator *optc)
+bool optc1_is_tg_enabled(struct timing_generator *optc)
 {
         struct optc *optc1 = DCN10TG_FROM_TG(optc);
         uint32_t otg_enabled = 0;
@@ -1281,7 +1281,7 @@ static bool optc1_is_tg_enabled(struct timing_generator *optc)
 
 }
 
-static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
+bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
 {
         struct optc *optc1 = DCN10TG_FROM_TG(optc);
         uint32_t underflow_occurred = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 89e09e5327a2..c62052f46460 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -497,4 +497,14 @@ void optc1_program_stereo(struct timing_generator *optc,
 
 bool optc1_is_stereo_left_eye(struct timing_generator *optc);
 
+void optc1_clear_optc_underflow(struct timing_generator *optc);
+
+void optc1_tg_init(struct timing_generator *optc);
+
+bool optc1_is_tg_enabled(struct timing_generator *optc);
+
+bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);
+
+void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
+
 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 2c0a3150bf2d..df5cb2d1d164 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -38,7 +38,7 @@
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "dce110/dce110_hw_sequencer.h"
 #include "dcn10/dcn10_opp.h"
-#include "dce/dce_link_encoder.h"
+#include "dcn10/dcn10_link_encoder.h"
 #include "dcn10/dcn10_stream_encoder.h"
 #include "dce/dce_clocks.h"
 #include "dce/dce_clock_source.h"
@@ -214,13 +214,11 @@ static const struct dce_aduio_mask audio_mask = {
         AUX_REG_LIST(id)\
 }
 
-static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
                 aux_regs(0),
                 aux_regs(1),
                 aux_regs(2),
-                aux_regs(3),
-                aux_regs(4),
-                aux_regs(5)
+                aux_regs(3)
 };
 
 #define hpd_regs(id)\
@@ -228,13 +226,11 @@ static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
         HPD_REG_LIST(id)\
 }
 
-static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
                 hpd_regs(0),
                 hpd_regs(1),
                 hpd_regs(2),
-                hpd_regs(3),
-                hpd_regs(4),
-                hpd_regs(5)
+                hpd_regs(3)
 };
 
 #define link_regs(id)\
@@ -243,14 +239,19 @@ static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 }
 
-static const struct dce110_link_enc_registers link_enc_regs[] = {
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
         link_regs(0),
         link_regs(1),
         link_regs(2),
-        link_regs(3),
-        link_regs(4),
-        link_regs(5),
-        link_regs(6),
+        link_regs(3)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+                LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+                LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
 };
 
 #define ipp_regs(id)\
@@ -446,6 +447,8 @@ static const struct dc_debug debug_defaults_drv = {
                 .vsr_support = true,
                 .performance_trace = false,
                 .az_endpoint_mute_only = true,
+                .recovery_enabled = false, /*enable this by default after testing.*/
+                .max_downscale_src_width = 3840,
 };
 
 static const struct dc_debug debug_defaults_diags = {
@@ -581,20 +584,22 @@ static const struct encoder_feature_support link_enc_feature = {
 struct link_encoder *dcn10_link_encoder_create(
         const struct encoder_init_data *enc_init_data)
 {
-        struct dce110_link_encoder *enc110 =
-                kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
+        struct dcn10_link_encoder *enc10 =
+                kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
 
-        if (!enc110)
+        if (!enc10)
                 return NULL;
 
-        dce110_link_encoder_construct(enc110,
+        dcn10_link_encoder_construct(enc10,
                                       enc_init_data,
                                       &link_enc_feature,
                                       &link_enc_regs[enc_init_data->transmitter],
                                       &link_enc_aux_regs[enc_init_data->channel - 1],
-                                      &link_enc_hpd_regs[enc_init_data->hpd_source]);
+                                      &link_enc_hpd_regs[enc_init_data->hpd_source],
+                                      &le_shift,
+                                      &le_mask);
 
-        return &enc110->base;
+        return &enc10->base;
 }
 
 struct clock_source *dcn10_clock_source_create(
@@ -1021,6 +1026,7 @@ static bool construct(
         dc->caps.max_cursor_size = 256;
         dc->caps.max_slave_planes = 1;
         dc->caps.is_apu = true;
+        dc->caps.post_blend_color_processing = false;
 
         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
                 dc->debug = debug_defaults_drv;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index befd8639ad55..653b7b2efe2e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -603,11 +603,11 @@ void enc1_stream_encoder_set_mst_bandwidth(
         struct fixed31_32 avg_time_slots_per_mtp)
 {
         struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
-        uint32_t x = dal_fixed31_32_floor(
+        uint32_t x = dc_fixpt_floor(
                 avg_time_slots_per_mtp);
-        uint32_t y = dal_fixed31_32_ceil(
-                dal_fixed31_32_shl(
-                        dal_fixed31_32_sub_int(
+        uint32_t y = dc_fixpt_ceil(
+                dc_fixpt_shl(
+                        dc_fixpt_sub_int(
                                 avg_time_slots_per_mtp,
                                 x),
                         26));
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 8eafe1af8a5e..4ff9b2bba178 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -355,10 +355,6 @@ void dm_perf_trace_timestamp(const char *func_name, unsigned int line);
 /*
  * Debug and verification hooks
  */
-bool dm_helpers_dc_conn_log(
-                struct dc_context *ctx,
-                struct log_entry *entry,
-                enum dc_log_type event);
 
 void dm_dtn_log_begin(struct dc_context *ctx);
 void dm_dtn_log_append_v(struct dc_context *ctx, const char *msg, ...);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index b1ad3553f900..47c19f8fe7d1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -108,4 +108,17 @@ enum output_standard {
         dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt
 };
 
+enum mpc_combine_affinity {
+        dm_mpc_always_when_possible,
+        dm_mpc_reduce_voltage,
+        dm_mpc_reduce_voltage_and_clocks
+};
+
+enum self_refresh_affinity {
+        dm_try_to_allow_self_refresh_and_mclk_switch,
+        dm_allow_self_refresh_and_mclk_switch,
+        dm_allow_self_refresh,
+        dm_neither_self_refresh_nor_mclk_switch
+};
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index ce750edc1e5f..7fa0375939ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -25,39 +25,39 @@
 #ifndef __DISPLAY_MODE_STRUCTS_H__
 #define __DISPLAY_MODE_STRUCTS_H__
 
-typedef struct _vcs_dpi_voltage_scaling_st      voltage_scaling_st;
-typedef struct _vcs_dpi_soc_bounding_box_st     soc_bounding_box_st;
-typedef struct _vcs_dpi_ip_params_st    ip_params_st;
-typedef struct _vcs_dpi_display_pipe_source_params_st   display_pipe_source_params_st;
-typedef struct _vcs_dpi_display_output_params_st        display_output_params_st;
-typedef struct _vcs_dpi_display_bandwidth_st    display_bandwidth_st;
-typedef struct _vcs_dpi_scaler_ratio_depth_st   scaler_ratio_depth_st;
-typedef struct _vcs_dpi_scaler_taps_st  scaler_taps_st;
-typedef struct _vcs_dpi_display_pipe_dest_params_st     display_pipe_dest_params_st;
-typedef struct _vcs_dpi_display_pipe_params_st  display_pipe_params_st;
-typedef struct _vcs_dpi_display_clocks_and_cfg_st       display_clocks_and_cfg_st;
-typedef struct _vcs_dpi_display_e2e_pipe_params_st      display_e2e_pipe_params_st;
-typedef struct _vcs_dpi_dchub_buffer_sizing_st  dchub_buffer_sizing_st;
-typedef struct _vcs_dpi_watermarks_perf_st      watermarks_perf_st;
-typedef struct _vcs_dpi_cstate_pstate_watermarks_st     cstate_pstate_watermarks_st;
-typedef struct _vcs_dpi_wm_calc_pipe_params_st  wm_calc_pipe_params_st;
-typedef struct _vcs_dpi_vratio_pre_st   vratio_pre_st;
-typedef struct _vcs_dpi_display_data_rq_misc_params_st  display_data_rq_misc_params_st;
-typedef struct _vcs_dpi_display_data_rq_sizing_params_st        display_data_rq_sizing_params_st;
-typedef struct _vcs_dpi_display_data_rq_dlg_params_st   display_data_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_cur_rq_dlg_params_st    display_cur_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_rq_dlg_params_st        display_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_rq_sizing_params_st     display_rq_sizing_params_st;
-typedef struct _vcs_dpi_display_rq_misc_params_st       display_rq_misc_params_st;
-typedef struct _vcs_dpi_display_rq_params_st    display_rq_params_st;
-typedef struct _vcs_dpi_display_dlg_regs_st     display_dlg_regs_st;
-typedef struct _vcs_dpi_display_ttu_regs_st     display_ttu_regs_st;
-typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
-typedef struct _vcs_dpi_display_rq_regs_st      display_rq_regs_st;
-typedef struct _vcs_dpi_display_dlg_sys_params_st       display_dlg_sys_params_st;
-typedef struct _vcs_dpi_display_dlg_prefetch_param_st   display_dlg_prefetch_param_st;
-typedef struct _vcs_dpi_display_pipe_clock_st   display_pipe_clock_st;
-typedef struct _vcs_dpi_display_arb_params_st   display_arb_params_st;
+typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st;
+typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
+typedef struct _vcs_dpi_ip_params_st ip_params_st;
+typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
+typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
+typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st;
+typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
+typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
+typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
+typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
+typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
+typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
+typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st;
+typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st;
+typedef struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_watermarks_st;
+typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st;
+typedef struct _vcs_dpi_vratio_pre_st vratio_pre_st;
+typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
+typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
+typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
+typedef struct _vcs_dpi_display_cur_rq_dlg_params_st display_cur_rq_dlg_params_st;
+typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
+typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
+typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
+typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st;
+typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st;
+typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
+typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
+typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
+typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
+typedef struct _vcs_dpi_display_dlg_prefetch_param_st display_dlg_prefetch_param_st;
+typedef struct _vcs_dpi_display_pipe_clock_st display_pipe_clock_st;
+typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
 
 struct _vcs_dpi_voltage_scaling_st {
         int state;
@@ -72,89 +72,107 @@ struct _vcs_dpi_voltage_scaling_st {
         double dppclk_mhz;
 };
 
-struct  _vcs_dpi_soc_bounding_box_st    {
-        double  sr_exit_time_us;
-        double  sr_enter_plus_exit_time_us;
-        double  urgent_latency_us;
-        double  writeback_latency_us;
-        double  ideal_dram_bw_after_urgent_percent;
-        unsigned int    max_request_size_bytes;
-        double  downspread_percent;
-        double  dram_page_open_time_ns;
-        double  dram_rw_turnaround_time_ns;
-        double  dram_return_buffer_per_channel_bytes;
-        double  dram_channel_width_bytes;
+struct _vcs_dpi_soc_bounding_box_st {
+        double sr_exit_time_us;
+        double sr_enter_plus_exit_time_us;
+        double urgent_latency_us;
+        double urgent_latency_pixel_data_only_us;
+        double urgent_latency_pixel_mixed_with_vm_data_us;
+        double urgent_latency_vm_data_only_us;
+        double writeback_latency_us;
+        double ideal_dram_bw_after_urgent_percent;
+        double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
+        double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
+        double pct_ideal_dram_sdp_bw_after_urgent_vm_only;
+        double max_avg_sdp_bw_use_normal_percent;
+        double max_avg_dram_bw_use_normal_percent;
+        unsigned int max_request_size_bytes;
+        double downspread_percent;
+        double dram_page_open_time_ns;
+        double dram_rw_turnaround_time_ns;
+        double dram_return_buffer_per_channel_bytes;
+        double dram_channel_width_bytes;
         double fabric_datapath_to_dcn_data_return_bytes;
         double dcn_downspread_percent;
         double dispclk_dppclk_vco_speed_mhz;
         double dfs_vco_period_ps;
-        unsigned int    round_trip_ping_latency_dcfclk_cycles;
-        unsigned int    urgent_out_of_order_return_per_channel_bytes;
-        unsigned int    channel_interleave_bytes;
-        unsigned int    num_banks;
-        unsigned int    num_chans;
-        unsigned int    vmm_page_size_bytes;
-        double  dram_clock_change_latency_us;
-        double  writeback_dram_clock_change_latency_us;
-        unsigned int    return_bus_width_bytes;
-        unsigned int    voltage_override;
-        double  xfc_bus_transport_time_us;
-        double  xfc_xbuf_latency_tolerance_us;
+        unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
+        unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
+        unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
+        unsigned int round_trip_ping_latency_dcfclk_cycles;
+        unsigned int urgent_out_of_order_return_per_channel_bytes;
+        unsigned int channel_interleave_bytes;
+        unsigned int num_banks;
+        unsigned int num_chans;
+        unsigned int vmm_page_size_bytes;
+        double dram_clock_change_latency_us;
+        double writeback_dram_clock_change_latency_us;
+        unsigned int return_bus_width_bytes;
+        unsigned int voltage_override;
+        double xfc_bus_transport_time_us;
+        double xfc_xbuf_latency_tolerance_us;
+        int use_urgent_burst_bw;
         struct _vcs_dpi_voltage_scaling_st clock_limits[7];
 };
 
-struct  _vcs_dpi_ip_params_st   {
-        unsigned int    max_inter_dcn_tile_repeaters;
-        unsigned int    num_dsc;
-        unsigned int    odm_capable;
-        unsigned int    rob_buffer_size_kbytes;
-        unsigned int    det_buffer_size_kbytes;
-        unsigned int    dpte_buffer_size_in_pte_reqs;
-        unsigned int    pde_proc_buffer_size_64k_reqs;
-        unsigned int    dpp_output_buffer_pixels;
-        unsigned int    opp_output_buffer_lines;
-        unsigned int    pixel_chunk_size_kbytes;
-        unsigned char   pte_enable;
-        unsigned int    pte_chunk_size_kbytes;
-        unsigned int    meta_chunk_size_kbytes;
-        unsigned int    writeback_chunk_size_kbytes;
-        unsigned int    line_buffer_size_bits;
-        unsigned int    max_line_buffer_lines;
-        unsigned int    writeback_luma_buffer_size_kbytes;
-        unsigned int    writeback_chroma_buffer_size_kbytes;
-        unsigned int    writeback_chroma_line_buffer_width_pixels;
-        unsigned int    max_page_table_levels;
-        unsigned int    max_num_dpp;
-        unsigned int    max_num_otg;
-        unsigned int    cursor_chunk_size;
-        unsigned int    cursor_buffer_size;
-        unsigned int    max_num_wb;
-        unsigned int    max_dchub_pscl_bw_pix_per_clk;
-        unsigned int    max_pscl_lb_bw_pix_per_clk;
-        unsigned int    max_lb_vscl_bw_pix_per_clk;
-        unsigned int    max_vscl_hscl_bw_pix_per_clk;
-        double  max_hscl_ratio;
-        double  max_vscl_ratio;
-        unsigned int    hscl_mults;
-        unsigned int    vscl_mults;
-        unsigned int    max_hscl_taps;
-        unsigned int    max_vscl_taps;
-        unsigned int    xfc_supported;
-        unsigned int    xfc_fill_constant_bytes;
-        double  dispclk_ramp_margin_percent;
-        double  xfc_fill_bw_overhead_percent;
-        double  underscan_factor;
-        unsigned int    min_vblank_lines;
-        unsigned int    dppclk_delay_subtotal;
-        unsigned int    dispclk_delay_subtotal;
-        unsigned int    dcfclk_cstate_latency;
-        unsigned int    dppclk_delay_scl;
-        unsigned int    dppclk_delay_scl_lb_only;
-        unsigned int    dppclk_delay_cnvc_formatter;
-        unsigned int    dppclk_delay_cnvc_cursor;
-        unsigned int    is_line_buffer_bpp_fixed;
-        unsigned int    line_buffer_fixed_bpp;
-        unsigned int    dcc_supported;
+struct _vcs_dpi_ip_params_st {
+        bool gpuvm_enable;
+        bool hostvm_enable;
+        unsigned int gpuvm_max_page_table_levels;
+        unsigned int hostvm_max_page_table_levels;
+        unsigned int hostvm_cached_page_table_levels;
+        unsigned int pte_group_size_bytes;
+        unsigned int max_inter_dcn_tile_repeaters;
+        unsigned int num_dsc;
+        unsigned int odm_capable;
+        unsigned int rob_buffer_size_kbytes;
+        unsigned int det_buffer_size_kbytes;
+        unsigned int dpte_buffer_size_in_pte_reqs;
+        unsigned int pde_proc_buffer_size_64k_reqs;
+        unsigned int dpp_output_buffer_pixels;
+        unsigned int opp_output_buffer_lines;
+        unsigned int pixel_chunk_size_kbytes;
+        unsigned char pte_enable;
+        unsigned int pte_chunk_size_kbytes;
+        unsigned int meta_chunk_size_kbytes;
+        unsigned int writeback_chunk_size_kbytes;
+        unsigned int line_buffer_size_bits;
+        unsigned int max_line_buffer_lines;
+        unsigned int writeback_luma_buffer_size_kbytes;
+        unsigned int writeback_chroma_buffer_size_kbytes;
+        unsigned int writeback_chroma_line_buffer_width_pixels;
+        unsigned int max_page_table_levels;
+        unsigned int max_num_dpp;
+        unsigned int max_num_otg;
+        unsigned int cursor_chunk_size;
+        unsigned int cursor_buffer_size;
+        unsigned int max_num_wb;
+        unsigned int max_dchub_pscl_bw_pix_per_clk;
+        unsigned int max_pscl_lb_bw_pix_per_clk;
+        unsigned int max_lb_vscl_bw_pix_per_clk;
+        unsigned int max_vscl_hscl_bw_pix_per_clk;
+        double max_hscl_ratio;
+        double max_vscl_ratio;
+        unsigned int hscl_mults;
+        unsigned int vscl_mults;
+        unsigned int max_hscl_taps;
+        unsigned int max_vscl_taps;
+        unsigned int xfc_supported;
+        unsigned int xfc_fill_constant_bytes;
+        double dispclk_ramp_margin_percent;
+        double xfc_fill_bw_overhead_percent;
+        double underscan_factor;
+        unsigned int min_vblank_lines;
+        unsigned int dppclk_delay_subtotal;
+        unsigned int dispclk_delay_subtotal;
+        unsigned int dcfclk_cstate_latency;
+        unsigned int dppclk_delay_scl;
+        unsigned int dppclk_delay_scl_lb_only;
+        unsigned int dppclk_delay_cnvc_formatter;
+        unsigned int dppclk_delay_cnvc_cursor;
+        unsigned int is_line_buffer_bpp_fixed;
+        unsigned int line_buffer_fixed_bpp;
+        unsigned int dcc_supported;
 
         unsigned int IsLineBufferBppFixed;
         unsigned int LineBufferFixedBpp;
@@ -169,41 +187,45 @@ struct _vcs_dpi_display_xfc_params_st {
         int xfc_slv_chunk_size_bytes;
 };
 
-struct  _vcs_dpi_display_pipe_source_params_st  {
-        int     source_format;
-        unsigned char   dcc;
-        unsigned int    dcc_override;
-        unsigned int    dcc_rate;
-        unsigned char   dcc_use_global;
-        unsigned char   vm;
-        unsigned char   vm_levels_force_en;
-        unsigned int    vm_levels_force;
-        int     source_scan;
-        int     sw_mode;
-        int     macro_tile_size;
-        unsigned char   is_display_sw;
-        unsigned int    viewport_width;
-        unsigned int    viewport_height;
-        unsigned int    viewport_y_y;
-        unsigned int    viewport_y_c;
-        unsigned int    viewport_width_c;
-        unsigned int    viewport_height_c;
-        unsigned int    data_pitch;
-        unsigned int    data_pitch_c;
-        unsigned int    meta_pitch;
-        unsigned int    meta_pitch_c;
-        unsigned int    cur0_src_width;
-        int     cur0_bpp;
-        unsigned int    cur1_src_width;
-        int     cur1_bpp;
-        int     num_cursors;
-        unsigned char   is_hsplit;
-        unsigned char   dynamic_metadata_enable;
-        unsigned int    dynamic_metadata_lines_before_active;
-        unsigned int    dynamic_metadata_xmit_bytes;
-        unsigned int    hsplit_grp;
-        unsigned char   xfc_enable;
-        unsigned char   xfc_slave;
+struct _vcs_dpi_display_pipe_source_params_st {
+        int source_format;
+        unsigned char dcc;
+        unsigned int dcc_override;
+        unsigned int dcc_rate;
+        unsigned char dcc_use_global;
+        unsigned char vm;
+        bool gpuvm;    // gpuvm enabled
+        bool hostvm;    // hostvm enabled
+        bool gpuvm_levels_force_en;
+        unsigned int gpuvm_levels_force;
+        bool hostvm_levels_force_en;
+        unsigned int hostvm_levels_force;
+        int source_scan;
+        int sw_mode;
+        int macro_tile_size;
+        unsigned char is_display_sw;
+        unsigned int viewport_width;
+        unsigned int viewport_height;
+        unsigned int viewport_y_y;
+        unsigned int viewport_y_c;
+        unsigned int viewport_width_c;
+        unsigned int viewport_height_c;
+        unsigned int data_pitch;
+        unsigned int data_pitch_c;
+        unsigned int meta_pitch;
+        unsigned int meta_pitch_c;
+        unsigned int cur0_src_width;
+        int cur0_bpp;
+        unsigned int cur1_src_width;
+        int cur1_bpp;
+        int num_cursors;
+        unsigned char is_hsplit;
+        unsigned char dynamic_metadata_enable;
+        unsigned int dynamic_metadata_lines_before_active;
+        unsigned int dynamic_metadata_xmit_bytes;
+        unsigned int hsplit_grp;
+        unsigned char xfc_enable;
+        unsigned char xfc_slave;
         struct _vcs_dpi_display_xfc_params_st xfc_params;
 };
 struct writeback_st {
@@ -219,335 +241,335 @@ struct writeback_st {
         double wb_vratio;
 };
 
-struct  _vcs_dpi_display_output_params_st       {
-        int     dp_lanes;
-        int     output_bpp;
-        int     dsc_enable;
-        int     wb_enable;
-        int     num_active_wb;
-        int     opp_input_bpc;
-        int     output_type;
-        int     output_format;
-        int     output_standard;
-        int     dsc_slices;
+struct _vcs_dpi_display_output_params_st {
+        int dp_lanes;
+        int output_bpp;
+        int dsc_enable;
+        int wb_enable;
+        int num_active_wb;
+        int output_bpc;
+        int output_type;
+        int output_format;
+        int output_standard;
+        int dsc_slices;
         struct writeback_st wb;
 };
 
-struct  _vcs_dpi_display_bandwidth_st   {
-        double  total_bw_consumed_gbps;
-        double  guaranteed_urgent_return_bw_gbps;
-};
-
-struct  _vcs_dpi_scaler_ratio_depth_st  {
-        double  hscl_ratio;
-        double  vscl_ratio;
-        double  hscl_ratio_c;
-        double  vscl_ratio_c;
-        double  vinit;
-        double  vinit_c;
-        double  vinit_bot;
-        double  vinit_bot_c;
-        int     lb_depth;
-        int     scl_enable;
-};
-
-struct  _vcs_dpi_scaler_taps_st {
-        unsigned int    htaps;
-        unsigned int    vtaps;
-        unsigned int    htaps_c;
-        unsigned int    vtaps_c;
-};
-
-struct  _vcs_dpi_display_pipe_dest_params_st    {
-        unsigned int    recout_width;
-        unsigned int    recout_height;
-        unsigned int    full_recout_width;
-        unsigned int    full_recout_height;
-        unsigned int    hblank_start;
-        unsigned int    hblank_end;
-        unsigned int    vblank_start;
-        unsigned int    vblank_end;
-        unsigned int    htotal;
-        unsigned int    vtotal;
-        unsigned int    vactive;
-        unsigned int    hactive;
-        unsigned int    vstartup_start;
-        unsigned int    vupdate_offset;
-        unsigned int    vupdate_width;
-        unsigned int    vready_offset;
-        unsigned char   interlaced;
-        unsigned char   underscan;
-        double  pixel_rate_mhz;
-        unsigned char   synchronized_vblank_all_planes;
-        unsigned char   otg_inst;
-        unsigned char   odm_split_cnt;
-        unsigned char   odm_combine;
-};
-
-struct  _vcs_dpi_display_pipe_params_st {
-        display_pipe_source_params_st   src;
-        display_pipe_dest_params_st     dest;
-        scaler_ratio_depth_st   scale_ratio_depth;
-        scaler_taps_st  scale_taps;
-};
-
-struct  _vcs_dpi_display_clocks_and_cfg_st      {
-        int     voltage;
-        double  dppclk_mhz;
-        double  refclk_mhz;
-        double  dispclk_mhz;
-        double  dcfclk_mhz;
-        double  socclk_mhz;
-};
-
-struct  _vcs_dpi_display_e2e_pipe_params_st     {
-        display_pipe_params_st  pipe;
-        display_output_params_st        dout;
-        display_clocks_and_cfg_st       clks_cfg;
-};
-
-struct  _vcs_dpi_dchub_buffer_sizing_st {
-        unsigned int    swath_width_y;
-        unsigned int    swath_height_y;
-        unsigned int    swath_height_c;
-        unsigned int    detail_buffer_size_y;
-};
-
-struct  _vcs_dpi_watermarks_perf_st     {
-        double  stutter_eff_in_active_region_percent;
-        double  urgent_latency_supported_us;
-        double  non_urgent_latency_supported_us;
-        double  dram_clock_change_margin_us;
-        double  dram_access_eff_percent;
-};
-
-struct  _vcs_dpi_cstate_pstate_watermarks_st    {
-        double  cstate_exit_us;
-        double  cstate_enter_plus_exit_us;
-        double  pstate_change_us;
-};
-
-struct  _vcs_dpi_wm_calc_pipe_params_st {
-        unsigned int    num_dpp;
-        int     voltage;
-        int     output_type;
-        double  dcfclk_mhz;
-        double  socclk_mhz;
-        double  dppclk_mhz;
-        double  pixclk_mhz;
-        unsigned char   interlace_en;
-        unsigned char   pte_enable;
-        unsigned char   dcc_enable;
-        double  dcc_rate;
-        double  bytes_per_pixel_c;
-        double  bytes_per_pixel_y;
-        unsigned int    swath_width_y;
-        unsigned int    swath_height_y;
-        unsigned int    swath_height_c;
-        unsigned int    det_buffer_size_y;
-        double  h_ratio;
-        double  v_ratio;
-        unsigned int    h_taps;
-        unsigned int    h_total;
-        unsigned int    v_total;
-        unsigned int    v_active;
-        unsigned int    e2e_index;
-        double  display_pipe_line_delivery_time;
-        double  read_bw;
-        unsigned int    lines_in_det_y;
-        unsigned int    lines_in_det_y_rounded_down_to_swath;
-        double  full_det_buffering_time;
-        double  dcfclk_deepsleep_mhz_per_plane;
-};
-
-struct  _vcs_dpi_vratio_pre_st  {
-        double  vratio_pre_l;
-        double  vratio_pre_c;
-};
-
-struct  _vcs_dpi_display_data_rq_misc_params_st {
-        unsigned int    full_swath_bytes;
-        unsigned int    stored_swath_bytes;
-        unsigned int    blk256_height;
-        unsigned int    blk256_width;
-        unsigned int    req_height;
-        unsigned int    req_width;
-};
-
-struct  _vcs_dpi_display_data_rq_sizing_params_st       {
-        unsigned int    chunk_bytes;
-        unsigned int    min_chunk_bytes;
-        unsigned int    meta_chunk_bytes;
-        unsigned int    min_meta_chunk_bytes;
-        unsigned int    mpte_group_bytes;
-        unsigned int    dpte_group_bytes;
-};
-
-struct  _vcs_dpi_display_data_rq_dlg_params_st  {
-        unsigned int    swath_width_ub;
-        unsigned int    swath_height;
-        unsigned int    req_per_swath_ub;
-        unsigned int    meta_pte_bytes_per_frame_ub;
-        unsigned int    dpte_req_per_row_ub;
-        unsigned int    dpte_groups_per_row_ub;
-        unsigned int    dpte_row_height;
-        unsigned int    dpte_bytes_per_row_ub;
-        unsigned int    meta_chunks_per_row_ub;
-        unsigned int    meta_req_per_row_ub;
-        unsigned int    meta_row_height;
-        unsigned int    meta_bytes_per_row_ub;
-};
-
-struct  _vcs_dpi_display_cur_rq_dlg_params_st   {
-        unsigned char   enable;
-        unsigned int    swath_height;
-        unsigned int    req_per_line;
-};
-
-struct  _vcs_dpi_display_rq_dlg_params_st       {
-        display_data_rq_dlg_params_st   rq_l;
-        display_data_rq_dlg_params_st   rq_c;
-        display_cur_rq_dlg_params_st    rq_cur0;
-};
-
-struct  _vcs_dpi_display_rq_sizing_params_st    {
-        display_data_rq_sizing_params_st        rq_l;
-        display_data_rq_sizing_params_st        rq_c;
-};
-
-struct  _vcs_dpi_display_rq_misc_params_st      {
-        display_data_rq_misc_params_st  rq_l;
-        display_data_rq_misc_params_st  rq_c;
-};
-
-struct  _vcs_dpi_display_rq_params_st   {
-        unsigned char   yuv420;
-        unsigned char   yuv420_10bpc;
-        display_rq_misc_params_st       misc;
-        display_rq_sizing_params_st     sizing;
-        display_rq_dlg_params_st        dlg;
-};
-
-struct  _vcs_dpi_display_dlg_regs_st    {
-        unsigned int    refcyc_h_blank_end;
-        unsigned int    dlg_vblank_end;
-        unsigned int    min_dst_y_next_start;
-        unsigned int    refcyc_per_htotal;
-        unsigned int    refcyc_x_after_scaler;
-        unsigned int    dst_y_after_scaler;
-        unsigned int    dst_y_prefetch;
-        unsigned int    dst_y_per_vm_vblank;
-        unsigned int    dst_y_per_row_vblank;
-        unsigned int    dst_y_per_vm_flip;
-        unsigned int    dst_y_per_row_flip;
-        unsigned int    ref_freq_to_pix_freq;
-        unsigned int    vratio_prefetch;
-        unsigned int    vratio_prefetch_c;
-        unsigned int    refcyc_per_pte_group_vblank_l;
-        unsigned int    refcyc_per_pte_group_vblank_c;
-        unsigned int    refcyc_per_meta_chunk_vblank_l;
-        unsigned int    refcyc_per_meta_chunk_vblank_c;
-        unsigned int    refcyc_per_pte_group_flip_l;
-        unsigned int    refcyc_per_pte_group_flip_c;
-        unsigned int    refcyc_per_meta_chunk_flip_l;
-        unsigned int    refcyc_per_meta_chunk_flip_c;
-        unsigned int    dst_y_per_pte_row_nom_l;
-        unsigned int    dst_y_per_pte_row_nom_c;
-        unsigned int    refcyc_per_pte_group_nom_l;
-        unsigned int    refcyc_per_pte_group_nom_c;
-        unsigned int    dst_y_per_meta_row_nom_l;
-        unsigned int    dst_y_per_meta_row_nom_c;
-        unsigned int    refcyc_per_meta_chunk_nom_l;
-        unsigned int    refcyc_per_meta_chunk_nom_c;
-        unsigned int    refcyc_per_line_delivery_pre_l;
-        unsigned int    refcyc_per_line_delivery_pre_c;
-        unsigned int    refcyc_per_line_delivery_l;
-        unsigned int    refcyc_per_line_delivery_c;
-        unsigned int    chunk_hdl_adjust_cur0;
-        unsigned int    chunk_hdl_adjust_cur1;
-        unsigned int    vready_after_vcount0;
-        unsigned int    dst_y_offset_cur0;
-        unsigned int    dst_y_offset_cur1;
-        unsigned int    xfc_reg_transfer_delay;
-        unsigned int    xfc_reg_precharge_delay;
-        unsigned int    xfc_reg_remote_surface_flip_latency;
-        unsigned int    xfc_reg_prefetch_margin;
-        unsigned int    dst_y_delta_drq_limit;
-};
-
-struct  _vcs_dpi_display_ttu_regs_st    {
-        unsigned int    qos_level_low_wm;
-        unsigned int    qos_level_high_wm;
-        unsigned int    min_ttu_vblank;
-        unsigned int    qos_level_flip;
-        unsigned int    refcyc_per_req_delivery_l;
-        unsigned int    refcyc_per_req_delivery_c;
-        unsigned int    refcyc_per_req_delivery_cur0;
-        unsigned int    refcyc_per_req_delivery_cur1;
-        unsigned int    refcyc_per_req_delivery_pre_l;
-        unsigned int    refcyc_per_req_delivery_pre_c;
-        unsigned int    refcyc_per_req_delivery_pre_cur0;
-        unsigned int    refcyc_per_req_delivery_pre_cur1;
-        unsigned int    qos_level_fixed_l;
-        unsigned int    qos_level_fixed_c;
-        unsigned int    qos_level_fixed_cur0;
-        unsigned int    qos_level_fixed_cur1;
-        unsigned int    qos_ramp_disable_l;
-        unsigned int    qos_ramp_disable_c;
-        unsigned int    qos_ramp_disable_cur0;
-        unsigned int    qos_ramp_disable_cur1;
-};
-
-struct  _vcs_dpi_display_data_rq_regs_st        {
-        unsigned int    chunk_size;
-        unsigned int    min_chunk_size;
-        unsigned int    meta_chunk_size;
-        unsigned int    min_meta_chunk_size;
-        unsigned int    dpte_group_size;
-        unsigned int    mpte_group_size;
-        unsigned int    swath_height;
-        unsigned int    pte_row_height_linear;
-};
-
-struct  _vcs_dpi_display_rq_regs_st     {
-        display_data_rq_regs_st rq_regs_l;
-        display_data_rq_regs_st rq_regs_c;
-        unsigned int    drq_expansion_mode;
-        unsigned int    prq_expansion_mode;
-        unsigned int    mrq_expansion_mode;
-        unsigned int    crq_expansion_mode;
-        unsigned int    plane1_base_address;
-};
-
-struct  _vcs_dpi_display_dlg_sys_params_st      {
-        double  t_mclk_wm_us;
-        double  t_urg_wm_us;
-        double  t_sr_wm_us;
-        double  t_extra_us;
-        double  mem_trip_us;
-        double  t_srx_delay_us;
-        double  deepsleep_dcfclk_mhz;
-        double  total_flip_bw;
-        unsigned int    total_flip_bytes;
-};
-
-struct  _vcs_dpi_display_dlg_prefetch_param_st  {
-        double  prefetch_bw;
-        unsigned int    flip_bytes;
-};
-
-struct  _vcs_dpi_display_pipe_clock_st  {
-        double  dcfclk_mhz;
-        double  dispclk_mhz;
-        double  socclk_mhz;
-        double  dscclk_mhz[6];
-        double  dppclk_mhz[6];
-};
-
-struct  _vcs_dpi_display_arb_params_st  {
-        int     max_req_outstanding;
-        int     min_req_outstanding;
-        int     sat_level_us;
+struct _vcs_dpi_display_bandwidth_st {
+        double total_bw_consumed_gbps;
+        double guaranteed_urgent_return_bw_gbps;
+};
+
+struct _vcs_dpi_scaler_ratio_depth_st {
+        double hscl_ratio;
+        double vscl_ratio;
+        double hscl_ratio_c;
+        double vscl_ratio_c;
+        double vinit;
+        double vinit_c;
+        double vinit_bot;
+        double vinit_bot_c;
+        int lb_depth;
+        int scl_enable;
+};
+
+struct _vcs_dpi_scaler_taps_st {
+        unsigned int htaps;
+        unsigned int vtaps;
+        unsigned int htaps_c;
+        unsigned int vtaps_c;
+};
+
+struct _vcs_dpi_display_pipe_dest_params_st {
+        unsigned int recout_width;
+        unsigned int recout_height;
+        unsigned int full_recout_width;
+        unsigned int full_recout_height;
+        unsigned int hblank_start;
+        unsigned int hblank_end;
+        unsigned int vblank_start;
+        unsigned int vblank_end;
+        unsigned int htotal;
+        unsigned int vtotal;
+        unsigned int vactive;
+        unsigned int hactive;
+        unsigned int vstartup_start;
+        unsigned int vupdate_offset;
+        unsigned int vupdate_width;
+        unsigned int vready_offset;
+        unsigned char interlaced;
+        unsigned char underscan;
+        double pixel_rate_mhz;
+        unsigned char synchronized_vblank_all_planes;
+        unsigned char otg_inst;
+        unsigned char odm_split_cnt;
+        unsigned char odm_combine;
+};
+
+struct _vcs_dpi_display_pipe_params_st {
+        display_pipe_source_params_st src;
+        display_pipe_dest_params_st dest;
+        scaler_ratio_depth_st scale_ratio_depth;
+        scaler_taps_st scale_taps;
+};
+
+struct _vcs_dpi_display_clocks_and_cfg_st {
+        int voltage;
+        double dppclk_mhz;
+        double refclk_mhz;
+        double dispclk_mhz;
+        double dcfclk_mhz;
+        double socclk_mhz;
+};
+
+struct _vcs_dpi_display_e2e_pipe_params_st {
+        display_pipe_params_st pipe;
+        display_output_params_st dout;
+        display_clocks_and_cfg_st clks_cfg;
+};
+
+struct _vcs_dpi_dchub_buffer_sizing_st {
+        unsigned int swath_width_y;
+        unsigned int swath_height_y;
+        unsigned int swath_height_c;
+        unsigned int detail_buffer_size_y;
+};
+
+struct _vcs_dpi_watermarks_perf_st {
+        double stutter_eff_in_active_region_percent;
+        double urgent_latency_supported_us;
+        double non_urgent_latency_supported_us;
+        double dram_clock_change_margin_us;
+        double dram_access_eff_percent;
+};
+
+struct _vcs_dpi_cstate_pstate_watermarks_st {
+        double cstate_exit_us;
+        double cstate_enter_plus_exit_us;
+        double pstate_change_us;
+};
+
+struct _vcs_dpi_wm_calc_pipe_params_st {
+        unsigned int num_dpp;
+        int voltage;
+        int output_type;
+        double dcfclk_mhz;
+        double socclk_mhz;
+        double dppclk_mhz;
+        double pixclk_mhz;
+        unsigned char interlace_en;
+        unsigned char pte_enable;
+        unsigned char dcc_enable;
+        double dcc_rate;
+        double bytes_per_pixel_c;
+        double bytes_per_pixel_y;
+        unsigned int swath_width_y;
+        unsigned int swath_height_y;
+        unsigned int swath_height_c;
+        unsigned int det_buffer_size_y;
+        double h_ratio;
+        double v_ratio;
+        unsigned int h_taps;
+        unsigned int h_total;
+        unsigned int v_total;
+        unsigned int v_active;
+        unsigned int e2e_index;
+        double display_pipe_line_delivery_time;
+        double read_bw;
+        unsigned int lines_in_det_y;
+        unsigned int lines_in_det_y_rounded_down_to_swath;
+        double full_det_buffering_time;
+        double dcfclk_deepsleep_mhz_per_plane;
+};
+
+struct _vcs_dpi_vratio_pre_st {
+        double vratio_pre_l;
+        double vratio_pre_c;
+};
+
+struct _vcs_dpi_display_data_rq_misc_params_st {
+        unsigned int full_swath_bytes;
+        unsigned int stored_swath_bytes;
+        unsigned int blk256_height;
+        unsigned int blk256_width;
+        unsigned int req_height;
+        unsigned int req_width;
+};
+
+struct _vcs_dpi_display_data_rq_sizing_params_st {
+        unsigned int chunk_bytes;
+        unsigned int min_chunk_bytes;
+        unsigned int meta_chunk_bytes;
+        unsigned int min_meta_chunk_bytes;
+        unsigned int mpte_group_bytes;
+        unsigned int dpte_group_bytes;
+};
+
+struct _vcs_dpi_display_data_rq_dlg_params_st {
+        unsigned int swath_width_ub;
+        unsigned int swath_height;
+        unsigned int req_per_swath_ub;
+        unsigned int meta_pte_bytes_per_frame_ub;
+        unsigned int dpte_req_per_row_ub;
+        unsigned int dpte_groups_per_row_ub;
+        unsigned int dpte_row_height;
+        unsigned int dpte_bytes_per_row_ub;
+        unsigned int meta_chunks_per_row_ub;
+        unsigned int meta_req_per_row_ub;
+        unsigned int meta_row_height;
+        unsigned int meta_bytes_per_row_ub;
+};
+
+struct _vcs_dpi_display_cur_rq_dlg_params_st {
+        unsigned char enable;
+        unsigned int swath_height;
+        unsigned int req_per_line;
+};
+
+struct _vcs_dpi_display_rq_dlg_params_st {
+        display_data_rq_dlg_params_st rq_l;
+        display_data_rq_dlg_params_st rq_c;
+        display_cur_rq_dlg_params_st rq_cur0;
+};
+
+struct _vcs_dpi_display_rq_sizing_params_st {
+        display_data_rq_sizing_params_st rq_l;
+        display_data_rq_sizing_params_st rq_c;
+};
+
+struct _vcs_dpi_display_rq_misc_params_st {
+        display_data_rq_misc_params_st rq_l;
+        display_data_rq_misc_params_st rq_c;
+};
+
+struct _vcs_dpi_display_rq_params_st {
+        unsigned char yuv420;
+        unsigned char yuv420_10bpc;
+        display_rq_misc_params_st misc;
+        display_rq_sizing_params_st sizing;
+        display_rq_dlg_params_st dlg;
+};
+
+struct _vcs_dpi_display_dlg_regs_st {
+        unsigned int refcyc_h_blank_end;
+        unsigned int dlg_vblank_end;
+        unsigned int min_dst_y_next_start;
+        unsigned int refcyc_per_htotal;
+        unsigned int refcyc_x_after_scaler;
+        unsigned int dst_y_after_scaler;
+        unsigned int dst_y_prefetch;
+        unsigned int dst_y_per_vm_vblank;
+        unsigned int dst_y_per_row_vblank;
+        unsigned int dst_y_per_vm_flip;
+        unsigned int dst_y_per_row_flip;
+        unsigned int ref_freq_to_pix_freq;
+        unsigned int vratio_prefetch;
+        unsigned int vratio_prefetch_c;
+        unsigned int refcyc_per_pte_group_vblank_l;
+        unsigned int refcyc_per_pte_group_vblank_c;
+        unsigned int refcyc_per_meta_chunk_vblank_l;
+        unsigned int refcyc_per_meta_chunk_vblank_c;
+        unsigned int refcyc_per_pte_group_flip_l;
+        unsigned int refcyc_per_pte_group_flip_c;
+        unsigned int refcyc_per_meta_chunk_flip_l;
+        unsigned int refcyc_per_meta_chunk_flip_c;
+        unsigned int dst_y_per_pte_row_nom_l;
+        unsigned int dst_y_per_pte_row_nom_c;
+        unsigned int refcyc_per_pte_group_nom_l;
+        unsigned int refcyc_per_pte_group_nom_c;
+        unsigned int dst_y_per_meta_row_nom_l;
+        unsigned int dst_y_per_meta_row_nom_c;
+        unsigned int refcyc_per_meta_chunk_nom_l;
+        unsigned int refcyc_per_meta_chunk_nom_c;
+        unsigned int refcyc_per_line_delivery_pre_l;
+        unsigned int refcyc_per_line_delivery_pre_c;
+        unsigned int refcyc_per_line_delivery_l;
+        unsigned int refcyc_per_line_delivery_c;
+        unsigned int chunk_hdl_adjust_cur0;
+        unsigned int chunk_hdl_adjust_cur1;
+        unsigned int vready_after_vcount0;
+        unsigned int dst_y_offset_cur0;
+        unsigned int dst_y_offset_cur1;
+        unsigned int xfc_reg_transfer_delay;
+        unsigned int xfc_reg_precharge_delay;
+        unsigned int xfc_reg_remote_surface_flip_latency;
+        unsigned int xfc_reg_prefetch_margin;
+        unsigned int dst_y_delta_drq_limit;
+};
+
+struct _vcs_dpi_display_ttu_regs_st {
+        unsigned int qos_level_low_wm;
+        unsigned int qos_level_high_wm;
+        unsigned int min_ttu_vblank;
+        unsigned int qos_level_flip;
+        unsigned int refcyc_per_req_delivery_l;
+        unsigned int refcyc_per_req_delivery_c;
+        unsigned int refcyc_per_req_delivery_cur0;
+        unsigned int refcyc_per_req_delivery_cur1;
+        unsigned int refcyc_per_req_delivery_pre_l;
+        unsigned int refcyc_per_req_delivery_pre_c;
+        unsigned int refcyc_per_req_delivery_pre_cur0;
+        unsigned int refcyc_per_req_delivery_pre_cur1;
+        unsigned int qos_level_fixed_l;
+        unsigned int qos_level_fixed_c;
+        unsigned int qos_level_fixed_cur0;
+        unsigned int qos_level_fixed_cur1;
+        unsigned int qos_ramp_disable_l;
+        unsigned int qos_ramp_disable_c;
+        unsigned int qos_ramp_disable_cur0;
+        unsigned int qos_ramp_disable_cur1;
+};
+
+struct _vcs_dpi_display_data_rq_regs_st {
+        unsigned int chunk_size;
+        unsigned int min_chunk_size;
+        unsigned int meta_chunk_size;
+        unsigned int min_meta_chunk_size;
+        unsigned int dpte_group_size;
+        unsigned int mpte_group_size;
+        unsigned int swath_height;
+        unsigned int pte_row_height_linear;
+};
+
+struct _vcs_dpi_display_rq_regs_st {
+        display_data_rq_regs_st rq_regs_l;
+        display_data_rq_regs_st rq_regs_c;
+        unsigned int drq_expansion_mode;
+        unsigned int prq_expansion_mode;
+        unsigned int mrq_expansion_mode;
+        unsigned int crq_expansion_mode;
+        unsigned int plane1_base_address;
+};
+
+struct _vcs_dpi_display_dlg_sys_params_st {
+        double t_mclk_wm_us;
+        double t_urg_wm_us;
+        double t_sr_wm_us;
+        double t_extra_us;
+        double mem_trip_us;
+        double t_srx_delay_us;
+        double deepsleep_dcfclk_mhz;
+        double total_flip_bw;
+        unsigned int total_flip_bytes;
+};
+
+struct _vcs_dpi_display_dlg_prefetch_param_st {
+        double prefetch_bw;
+        unsigned int flip_bytes;
+};
+
+struct _vcs_dpi_display_pipe_clock_st {
+        double dcfclk_mhz;
+        double dispclk_mhz;
+        double socclk_mhz;
+        double dscclk_mhz[6];
+        double dppclk_mhz[6];
+};
+
+struct _vcs_dpi_display_arb_params_st {
+        int max_req_outstanding;
+        int min_req_outstanding;
+        int sat_level_us;
 };
 
 #endif /*__DISPLAY_MODE_STRUCTS_H__*/
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
index f9cf08357989..e8ce08567cd8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
@@ -35,6 +35,16 @@ static inline double dml_min(double a, double b)
         return (double) dcn_bw_min2(a, b);
 }
 
+static inline double dml_min3(double a, double b, double c)
+{
+        return dml_min(dml_min(a, b), c);
+}
+
+static inline double dml_min4(double a, double b, double c, double d)
+{
+        return dml_min(dml_min(a, b), dml_min(c, d));
+}
+
 static inline double dml_max(double a, double b)
 {
         return (double) dcn_bw_max2(a, b);
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 61fe484da1a0..0caee3523017 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -75,9 +75,7 @@ bool dal_hw_factory_init(
                 return true;
         case DCE_VERSION_11_0:
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
                 dal_hw_factory_dce110_init(factory);
                 return true;
         case DCE_VERSION_12_0:
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 910ae2b7bf64..55c707488541 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -72,9 +72,7 @@ bool dal_hw_translate_init(
         case DCE_VERSION_10_0:
         case DCE_VERSION_11_0:
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
                 dal_hw_translate_dce110_init(translate);
                 return true;
         case DCE_VERSION_12_0:
diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
index c3d7c320fdba..14dc8c94d862 100644
--- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
+++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
@@ -83,9 +83,7 @@ struct i2caux *dal_i2caux_create(
         case DCE_VERSION_8_3:
                 return dal_i2caux_dce80_create(ctx);
         case DCE_VERSION_11_2:
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         case DCE_VERSION_11_22:
-#endif
                 return dal_i2caux_dce112_create(ctx);
         case DCE_VERSION_11_0:
                 return dal_i2caux_dce110_create(ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
index 933ea7a1e18b..eece165206f9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
@@ -43,9 +43,7 @@ enum bw_calcs_version {
         BW_CALCS_VERSION_POLARIS10,
         BW_CALCS_VERSION_POLARIS11,
         BW_CALCS_VERSION_POLARIS12,
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         BW_CALCS_VERSION_VEGAM,
-#endif
         BW_CALCS_VERSION_STONEY,
         BW_CALCS_VERSION_VEGA10
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 331f8ff57ed7..97df82cddf82 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -121,6 +121,8 @@ struct hubp_funcs {
         void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
         void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
         void (*hubp_read_state)(struct hubp *hubp);
+        void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);
+        unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
 
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 29abf3ecb39c..63fc6c499789 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -83,11 +83,6 @@ struct hw_sequencer_funcs {
                         int num_planes,
                         struct dc_state *context);
 
-        void (*set_plane_config)(
-                        const struct dc *dc,
-                        struct pipe_ctx *pipe_ctx,
-                        struct resource_context *res_ctx);
-
         void (*program_gamut_remap)(
                         struct pipe_ctx *pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/irq_types.h b/drivers/gpu/drm/amd/display/dc/irq_types.h
index cc3b1bc6cedd..0b5f3a278c22 100644
--- a/drivers/gpu/drm/amd/display/dc/irq_types.h
+++ b/drivers/gpu/drm/amd/display/dc/irq_types.h
@@ -26,6 +26,8 @@
 #ifndef __DAL_IRQ_TYPES_H__
 #define __DAL_IRQ_TYPES_H__
 
+#include "os_types.h"
+
 struct dc_context;
 
 typedef void (*interrupt_handler)(void *);
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 1b987b6a347d..25029ed42d89 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -86,6 +86,7 @@
 #define VI_POLARIS10_P_A0 80
 #define VI_POLARIS11_M_A0 90
 #define VI_POLARIS12_V_A0 100
+#define VI_VEGAM_A0 110
 
 #define VI_UNKNOWN 0xFF
 
@@ -98,14 +99,9 @@
                 (eChipRev < VI_POLARIS11_M_A0))
 #define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) &&  \
                 (eChipRev < VI_POLARIS12_V_A0))
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
-#define VI_VEGAM_A0 110
 #define ASIC_REV_IS_POLARIS12_V(eChipRev) ((eChipRev >= VI_POLARIS12_V_A0) && \
                 (eChipRev < VI_VEGAM_A0))
 #define ASIC_REV_IS_VEGAM(eChipRev) (eChipRev >= VI_VEGAM_A0)
-#else
-#define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0)
-#endif
 
 /* DCE11 */
 #define CZ_CARRIZO_A0 0x01
@@ -117,17 +113,19 @@
         ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
 
 /* DCE12 */
+#define AI_UNKNOWN 0xFF
 
 #define AI_GREENLAND_P_A0 1
 #define AI_GREENLAND_P_A1 2
 #define AI_UNKNOWN 0xFF
 
 #define AI_VEGA12_P_A0 20
+#define AI_VEGA20_P_A0 40
 #define ASICREV_IS_GREENLAND_M(eChipRev)  (eChipRev < AI_VEGA12_P_A0)
 #define ASICREV_IS_GREENLAND_P(eChipRev)  (eChipRev < AI_VEGA12_P_A0)
 
-#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
-#define ASICREV_IS_VEGA12_p(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_UNKNOWN))
+#define ASICREV_IS_VEGA12_P(eChipRev) ((eChipRev >= AI_VEGA12_P_A0) && (eChipRev < AI_VEGA20_P_A0))
+#define ASICREV_IS_VEGA20_P(eChipRev) ((eChipRev >= AI_VEGA20_P_A0) && (eChipRev < AI_UNKNOWN))
 
 /* DCN1_0 */
 #define INTERNAL_REV_RAVEN_A0             0x00    /* First spin of Raven */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 5b1f8cef0c22..840142b65f8b 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -40,9 +40,7 @@ enum dce_version {
         DCE_VERSION_10_0,
         DCE_VERSION_11_0,
         DCE_VERSION_11_2,
-#if defined(CONFIG_DRM_AMD_DC_VEGAM)
         DCE_VERSION_11_22,
-#endif
         DCE_VERSION_12_0,
         DCE_VERSION_MAX,
         DCN_VERSION_1_0,
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index 16cbdb43d856..bb0d4ebba9f0 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -27,6 +27,12 @@
 #define __DAL_FIXED31_32_H__
 
 #define FIXED31_32_BITS_PER_FRACTIONAL_PART 32
+#ifndef LLONG_MIN
+#define LLONG_MIN (1LL<<63)
+#endif
+#ifndef LLONG_MAX
+#define LLONG_MAX (-1LL>>1)
+#endif
 
 /*
  * @brief
@@ -45,21 +51,22 @@ struct fixed31_32 {
         long long value;
 };
 
+
 /*
  * @brief
  * Useful constants
  */
 
-static const struct fixed31_32 dal_fixed31_32_zero = { 0 };
-static const struct fixed31_32 dal_fixed31_32_epsilon = { 1LL };
-static const struct fixed31_32 dal_fixed31_32_half = { 0x80000000LL };
-static const struct fixed31_32 dal_fixed31_32_one = { 0x100000000LL };
+static const struct fixed31_32 dc_fixpt_zero = { 0 };
+static const struct fixed31_32 dc_fixpt_epsilon = { 1LL };
+static const struct fixed31_32 dc_fixpt_half = { 0x80000000LL };
+static const struct fixed31_32 dc_fixpt_one = { 0x100000000LL };
 
-static const struct fixed31_32 dal_fixed31_32_pi = { 13493037705LL };
-static const struct fixed31_32 dal_fixed31_32_two_pi = { 26986075409LL };
-static const struct fixed31_32 dal_fixed31_32_e = { 11674931555LL };
-static const struct fixed31_32 dal_fixed31_32_ln2 = { 2977044471LL };
-static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL };
+static const struct fixed31_32 dc_fixpt_pi = { 13493037705LL };
+static const struct fixed31_32 dc_fixpt_two_pi = { 26986075409LL };
+static const struct fixed31_32 dc_fixpt_e = { 11674931555LL };
+static const struct fixed31_32 dc_fixpt_ln2 = { 2977044471LL };
+static const struct fixed31_32 dc_fixpt_ln2_div_2 = { 1488522236LL };
 
 /*
  * @brief
@@ -70,24 +77,19 @@ static const struct fixed31_32 dal_fixed31_32_ln2_div_2 = { 1488522236LL };
  * @brief
  * result = numerator / denominator
  */
-struct fixed31_32 dal_fixed31_32_from_fraction(
-        long long numerator,
-        long long denominator);
+struct fixed31_32 dc_fixpt_from_fraction(long long numerator, long long denominator);
 
 /*
  * @brief
  * result = arg
  */
-struct fixed31_32 dal_fixed31_32_from_int_nonconst(long long arg);
-static inline struct fixed31_32 dal_fixed31_32_from_int(long long arg)
+static inline struct fixed31_32 dc_fixpt_from_int(int arg)
 {
-        if (__builtin_constant_p(arg)) {
-                struct fixed31_32 res;
-                BUILD_BUG_ON((LONG_MIN > arg) || (arg > LONG_MAX));
-                res.value = arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
-                return res;
-        } else
-                return dal_fixed31_32_from_int_nonconst(arg);
+        struct fixed31_32 res;
+
+        res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART;
+
+        return res;
 }
 
 /*
@@ -99,7 +101,7 @@ static inline struct fixed31_32 dal_fixed31_32_from_int(long long arg)
  * @brief
  * result = -arg
  */
-static inline struct fixed31_32 dal_fixed31_32_neg(struct fixed31_32 arg)
+static inline struct fixed31_32 dc_fixpt_neg(struct fixed31_32 arg)
 {
         struct fixed31_32 res;
 
@@ -112,10 +114,10 @@ static inline struct fixed31_32 dal_fixed31_32_neg(struct fixed31_32 arg)
  * @brief
  * result = abs(arg) := (arg >= 0) ? arg : -arg
  */
-static inline struct fixed31_32 dal_fixed31_32_abs(struct fixed31_32 arg)
+static inline struct fixed31_32 dc_fixpt_abs(struct fixed31_32 arg)
 {
         if (arg.value < 0)
-                return dal_fixed31_32_neg(arg);
+                return dc_fixpt_neg(arg);
         else
                 return arg;
 }
@@ -129,8 +131,7 @@ static inline struct fixed31_32 dal_fixed31_32_abs(struct fixed31_32 arg)
  * @brief
  * result = arg1 < arg2
  */
-static inline bool dal_fixed31_32_lt(struct fixed31_32 arg1,
-                                     struct fixed31_32 arg2)
+static inline bool dc_fixpt_lt(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
         return arg1.value < arg2.value;
 }
@@ -139,8 +140,7 @@ static inline bool dal_fixed31_32_lt(struct fixed31_32 arg1,
  * @brief
  * result = arg1 <= arg2
  */
-static inline bool dal_fixed31_32_le(struct fixed31_32 arg1,
-                                     struct fixed31_32 arg2)
+static inline bool dc_fixpt_le(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
         return arg1.value <= arg2.value;
 }
@@ -149,8 +149,7 @@ static inline bool dal_fixed31_32_le(struct fixed31_32 arg1,
  * @brief
  * result = arg1 == arg2
  */
-static inline bool dal_fixed31_32_eq(struct fixed31_32 arg1,
-                                     struct fixed31_32 arg2)
+static inline bool dc_fixpt_eq(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
         return arg1.value == arg2.value;
 }
@@ -159,8 +158,7 @@ static inline bool dal_fixed31_32_eq(struct fixed31_32 arg1,
  * @brief
  * result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2
  */
-static inline struct fixed31_32 dal_fixed31_32_min(struct fixed31_32 arg1,
-                                                   struct fixed31_32 arg2)
+static inline struct fixed31_32 dc_fixpt_min(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
         if (arg1.value <= arg2.value)
                 return arg1;
@@ -172,8 +170,7 @@ static inline struct fixed31_32 dal_fixed31_32_min(struct fixed31_32 arg1,
  * @brief
  * result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1
  */
-static inline struct fixed31_32 dal_fixed31_32_max(struct fixed31_32 arg1,
-                                                   struct fixed31_32 arg2)
+static inline struct fixed31_32 dc_fixpt_max(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
         if (arg1.value <= arg2.value)
                 return arg2;
@@ -187,14 +184,14 @@ static inline struct fixed31_32 dal_fixed31_32_max(struct fixed31_32 arg1,
  * result = | arg, when min_value < arg < max_value
  *          | max_value, when arg >= max_value
  */
-static inline struct fixed31_32 dal_fixed31_32_clamp(
+static inline struct fixed31_32 dc_fixpt_clamp(
         struct fixed31_32 arg,
         struct fixed31_32 min_value,
         struct fixed31_32 max_value)
 {
-        if (dal_fixed31_32_le(arg, min_value))
+        if (dc_fixpt_le(arg, min_value))
                 return min_value;
-        else if (dal_fixed31_32_le(max_value, arg))
+        else if (dc_fixpt_le(max_value, arg))
                 return max_value;
         else
                 return arg;
@@ -209,21 +206,30 @@ static inline struct fixed31_32 dal_fixed31_32_clamp(
  * @brief
  * result = arg << shift
  */
-struct fixed31_32 dal_fixed31_32_shl(
-        struct fixed31_32 arg,
-        unsigned char shift);
+static inline struct fixed31_32 dc_fixpt_shl(struct fixed31_32 arg, unsigned char shift)
+{
+        ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||
+                ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift))));
+
+        arg.value = arg.value << shift;
+
+        return arg;
+}
 
 /*
  * @brief
  * result = arg >> shift
  */
-static inline struct fixed31_32 dal_fixed31_32_shr(
-        struct fixed31_32 arg,
-        unsigned char shift)
+static inline struct fixed31_32 dc_fixpt_shr(struct fixed31_32 arg, unsigned char shift)
 {
-        struct fixed31_32 res;
-        res.value = arg.value >> shift;
-        return res;
+        bool negative = arg.value < 0;
+
+        if (negative)
+                arg.value = -arg.value;
+        arg.value = arg.value >> shift;
+        if (negative)
+                arg.value = -arg.value;
+        return arg;
 }
 
 /*
@@ -235,38 +241,50 @@ static inline struct fixed31_32 dal_fixed31_32_shr(
  * @brief
  * result = arg1 + arg2
  */
-struct fixed31_32 dal_fixed31_32_add(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2);
+static inline struct fixed31_32 dc_fixpt_add(struct fixed31_32 arg1, struct fixed31_32 arg2)
+{
+        struct fixed31_32 res;
+
+        ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||
+                ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value)));
+
+        res.value = arg1.value + arg2.value;
+
+        return res;
+}
 
 /*
  * @brief
  * result = arg1 + arg2
  */
-static inline struct fixed31_32 dal_fixed31_32_add_int(struct fixed31_32 arg1,
-                                                       int arg2)
+static inline struct fixed31_32 dc_fixpt_add_int(struct fixed31_32 arg1, int arg2)
 {
-        return dal_fixed31_32_add(arg1,
-                                  dal_fixed31_32_from_int(arg2));
+        return dc_fixpt_add(arg1, dc_fixpt_from_int(arg2));
 }
 
 /*
  * @brief
  * result = arg1 - arg2
  */
-struct fixed31_32 dal_fixed31_32_sub(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2);
+static inline struct fixed31_32 dc_fixpt_sub(struct fixed31_32 arg1, struct fixed31_32 arg2)
+{
+        struct fixed31_32 res;
+
+        ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||
+                ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value)));
+
+        res.value = arg1.value - arg2.value;
+
+        return res;
+}
 
 /*
  * @brief
  * result = arg1 - arg2
  */
-static inline struct fixed31_32 dal_fixed31_32_sub_int(struct fixed31_32 arg1,
-                                                       int arg2)
+static inline struct fixed31_32 dc_fixpt_sub_int(struct fixed31_32 arg1, int arg2)
 {
-        return dal_fixed31_32_sub(arg1,
-                                  dal_fixed31_32_from_int(arg2));
+        return dc_fixpt_sub(arg1, dc_fixpt_from_int(arg2));
 }
 
 
@@ -279,49 +297,40 @@ static inline struct fixed31_32 dal_fixed31_32_sub_int(struct fixed31_32 arg1,
  * @brief
  * result = arg1 * arg2
  */
-struct fixed31_32 dal_fixed31_32_mul(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2);
+struct fixed31_32 dc_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2);
 
 
 /*
  * @brief
  * result = arg1 * arg2
  */
-static inline struct fixed31_32 dal_fixed31_32_mul_int(struct fixed31_32 arg1,
-                                                       int arg2)
+static inline struct fixed31_32 dc_fixpt_mul_int(struct fixed31_32 arg1, int arg2)
 {
-        return dal_fixed31_32_mul(arg1,
-                                  dal_fixed31_32_from_int(arg2));
+        return dc_fixpt_mul(arg1, dc_fixpt_from_int(arg2));
 }
 
 /*
  * @brief
  * result = square(arg) := arg * arg
  */
-struct fixed31_32 dal_fixed31_32_sqr(
-        struct fixed31_32 arg);
+struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg);
 
 /*
  * @brief
  * result = arg1 / arg2
  */
-static inline struct fixed31_32 dal_fixed31_32_div_int(struct fixed31_32 arg1,
-                                                       long long arg2)
+static inline struct fixed31_32 dc_fixpt_div_int(struct fixed31_32 arg1, long long arg2)
 {
-        return dal_fixed31_32_from_fraction(arg1.value,
-                                            dal_fixed31_32_from_int(arg2).value);
+        return dc_fixpt_from_fraction(arg1.value, dc_fixpt_from_int(arg2).value);
 }
 
 /*
  * @brief
  * result = arg1 / arg2
  */
-static inline struct fixed31_32 dal_fixed31_32_div(struct fixed31_32 arg1,
-                                                   struct fixed31_32 arg2)
+static inline struct fixed31_32 dc_fixpt_div(struct fixed31_32 arg1, struct fixed31_32 arg2)
 {
-        return dal_fixed31_32_from_fraction(arg1.value,
-                                            arg2.value);
+        return dc_fixpt_from_fraction(arg1.value, arg2.value);
 }
 
 /*
@@ -336,8 +345,7 @@ static inline struct fixed31_32 dal_fixed31_32_div(struct fixed31_32 arg1,
  * @note
  * No special actions taken in case argument is zero.
  */
-struct fixed31_32 dal_fixed31_32_recip(
-        struct fixed31_32 arg);
+struct fixed31_32 dc_fixpt_recip(struct fixed31_32 arg);
 
 /*
  * @brief
@@ -352,8 +360,7 @@ struct fixed31_32 dal_fixed31_32_recip(
  * Argument specified in radians,
  * internally it's normalized to [-2pi...2pi] range.
  */
-struct fixed31_32 dal_fixed31_32_sinc(
-        struct fixed31_32 arg);
+struct fixed31_32 dc_fixpt_sinc(struct fixed31_32 arg);
 
 /*
  * @brief
@@ -363,8 +370,7 @@ struct fixed31_32 dal_fixed31_32_sinc(
  * Argument specified in radians,
  * internally it's normalized to [-2pi...2pi] range.
  */
-struct fixed31_32 dal_fixed31_32_sin(
-        struct fixed31_32 arg);
+struct fixed31_32 dc_fixpt_sin(struct fixed31_32 arg);
 
 /*
  * @brief
@@ -376,8 +382,7 @@ struct fixed31_32 dal_fixed31_32_sin(
  * passing arguments outside that range
  * will cause incorrect result!
  */
-struct fixed31_32 dal_fixed31_32_cos(
-        struct fixed31_32 arg);
+struct fixed31_32 dc_fixpt_cos(struct fixed31_32 arg);
 
 /*
  * @brief
@@ -391,8 +396,7 @@ struct fixed31_32 dal_fixed31_32_cos(
  * @note
  * Currently, function is verified for abs(arg) <= 1.
  */
-struct fixed31_32 dal_fixed31_32_exp(
-        struct fixed31_32 arg);
+struct fixed31_32 dc_fixpt_exp(struct fixed31_32 arg);
 
 /*
  * @brief
@@ -404,8 +408,7 @@ struct fixed31_32 dal_fixed31_32_exp(
  * Currently, no special actions taken
  * in case of invalid argument(s). Take care!
  */
-struct fixed31_32 dal_fixed31_32_log(
-        struct fixed31_32 arg);
+struct fixed31_32 dc_fixpt_log(struct fixed31_32 arg);
 
 /*
  * @brief
@@ -419,9 +422,13 @@ struct fixed31_32 dal_fixed31_32_log(
  * @note
  * Currently, abs(arg1) should be less than 1. Take care!
  */
-struct fixed31_32 dal_fixed31_32_pow(
-        struct fixed31_32 arg1,
-        struct fixed31_32 arg2);
+static inline struct fixed31_32 dc_fixpt_pow(struct fixed31_32 arg1, struct fixed31_32 arg2)
+{
+        return dc_fixpt_exp(
+                dc_fixpt_mul(
+                        dc_fixpt_log(arg1),
+                        arg2));
+}
 
 /*
  * @brief
@@ -432,22 +439,56 @@ struct fixed31_32 dal_fixed31_32_pow(
  * @brief
  * result = floor(arg) := greatest integer lower than or equal to arg
  */
-int dal_fixed31_32_floor(
-        struct fixed31_32 arg);
+static inline int dc_fixpt_floor(struct fixed31_32 arg)
+{
+        unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+
+        if (arg.value >= 0)
+                return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
+        else
+                return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
+}
 
 /*
  * @brief
  * result = round(arg) := integer nearest to arg
  */
-int dal_fixed31_32_round(
-        struct fixed31_32 arg);
+static inline int dc_fixpt_round(struct fixed31_32 arg)
+{
+        unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+
+        const long long summand = dc_fixpt_half.value;
+
+        ASSERT(LLONG_MAX - (long long)arg_value >= summand);
+
+        arg_value += summand;
+
+        if (arg.value >= 0)
+                return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
+        else
+                return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
+}
 
 /*
  * @brief
  * result = ceil(arg) := lowest integer greater than or equal to arg
  */
-int dal_fixed31_32_ceil(
-        struct fixed31_32 arg);
+static inline int dc_fixpt_ceil(struct fixed31_32 arg)
+{
+        unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value;
+
+        const long long summand = dc_fixpt_one.value -
+                dc_fixpt_epsilon.value;
+
+        ASSERT(LLONG_MAX - (long long)arg_value >= summand);
+
+        arg_value += summand;
+
+        if (arg.value >= 0)
+                return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
+        else
+                return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART);
+}
 
 /* the following two function are used in scaler hw programming to convert fixed
  * point value to format 2 bits from integer part and 19 bits from fractional
@@ -455,20 +496,31 @@ int dal_fixed31_32_ceil(
  * fractional
  */
 
-unsigned int dal_fixed31_32_u2d19(
-        struct fixed31_32 arg);
+unsigned int dc_fixpt_u2d19(struct fixed31_32 arg);
+
+unsigned int dc_fixpt_u0d19(struct fixed31_32 arg);
 
-unsigned int dal_fixed31_32_u0d19(
-        struct fixed31_32 arg);
+unsigned int dc_fixpt_clamp_u0d14(struct fixed31_32 arg);
 
+unsigned int dc_fixpt_clamp_u0d10(struct fixed31_32 arg);
 
-unsigned int dal_fixed31_32_clamp_u0d14(
-        struct fixed31_32 arg);
+int dc_fixpt_s4d19(struct fixed31_32 arg);
 
-unsigned int dal_fixed31_32_clamp_u0d10(
-        struct fixed31_32 arg);
+static inline struct fixed31_32 dc_fixpt_truncate(struct fixed31_32 arg, unsigned int frac_bits)
+{
+        bool negative = arg.value < 0;
 
-int dal_fixed31_32_s4d19(
-        struct fixed31_32 arg);
+        if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) {
+                ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART);
+                return arg;
+        }
+
+        if (negative)
+                arg.value = -arg.value;
+        arg.value &= (~0LL) << (FIXED31_32_BITS_PER_FRACTIONAL_PART - frac_bits);
+        if (negative)
+                arg.value = -arg.value;
+        return arg;
+}
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/include/fixed32_32.h b/drivers/gpu/drm/amd/display/include/fixed32_32.h
deleted file mode 100644
index 9c70341fe026..000000000000
--- a/drivers/gpu/drm/amd/display/include/fixed32_32.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-
-#ifndef __DAL_FIXED32_32_H__
-#define __DAL_FIXED32_32_H__
-
-#include "os_types.h"
-
-struct fixed32_32 {
-        uint64_t value;
-};
-
-static const struct fixed32_32 dal_fixed32_32_zero = { 0 };
-static const struct fixed32_32 dal_fixed32_32_one = { 0x100000000LL };
-static const struct fixed32_32 dal_fixed32_32_half = { 0x80000000LL };
-
-struct fixed32_32 dal_fixed32_32_from_fraction(uint32_t n, uint32_t d);
-static inline struct fixed32_32 dal_fixed32_32_from_int(uint32_t value)
-{
-        struct fixed32_32 fx;
-
-        fx.value = (uint64_t)value<<32;
-        return fx;
-}
-
-struct fixed32_32 dal_fixed32_32_add(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs);
-struct fixed32_32 dal_fixed32_32_add_int(
-        struct fixed32_32 lhs,
-        uint32_t rhs);
-struct fixed32_32 dal_fixed32_32_sub(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs);
-struct fixed32_32 dal_fixed32_32_sub_int(
-        struct fixed32_32 lhs,
-        uint32_t rhs);
-struct fixed32_32 dal_fixed32_32_mul(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs);
-struct fixed32_32 dal_fixed32_32_mul_int(
-        struct fixed32_32 lhs,
-        uint32_t rhs);
-struct fixed32_32 dal_fixed32_32_div(
-        struct fixed32_32 lhs,
-        struct fixed32_32 rhs);
-struct fixed32_32 dal_fixed32_32_div_int(
-        struct fixed32_32 lhs,
-        uint32_t rhs);
-
-static inline struct fixed32_32 dal_fixed32_32_min(struct fixed32_32 lhs,
-                                                   struct fixed32_32 rhs)
-{
-        return (lhs.value < rhs.value) ? lhs : rhs;
-}
-
-static inline struct fixed32_32 dal_fixed32_32_max(struct fixed32_32 lhs,
-                                                   struct fixed32_32 rhs)
-{
-        return (lhs.value > rhs.value) ? lhs : rhs;
-}
-
-static inline bool dal_fixed32_32_gt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-        return lhs.value > rhs.value;
-}
-
-static inline bool dal_fixed32_32_gt_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-        return lhs.value > ((uint64_t)rhs<<32);
-}
-
-static inline bool dal_fixed32_32_lt(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-        return lhs.value < rhs.value;
-}
-
-static inline bool dal_fixed32_32_lt_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-        return lhs.value < ((uint64_t)rhs<<32);
-}
-
-static inline bool dal_fixed32_32_le(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-        return lhs.value <= rhs.value;
-}
-
-static inline bool dal_fixed32_32_le_int(struct fixed32_32 lhs, uint32_t rhs)
-{
-        return lhs.value <= ((uint64_t)rhs<<32);
-}
-
-static inline bool dal_fixed32_32_eq(struct fixed32_32 lhs, struct fixed32_32 rhs)
-{
-        return lhs.value == rhs.value;
-}
-
-uint32_t dal_fixed32_32_ceil(struct fixed32_32 value);
-static inline uint32_t dal_fixed32_32_floor(struct fixed32_32 value)
-{
-        return value.value>>32;
-}
-
-uint32_t dal_fixed32_32_round(struct fixed32_32 value);
-
-#endif
diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h
index 28dee960d509..dc98d6d4b2bd 100644
--- a/drivers/gpu/drm/amd/display/include/logger_interface.h
+++ b/drivers/gpu/drm/amd/display/include/logger_interface.h
@@ -190,4 +190,13 @@ void context_clock_trace(
         } \
 } while (0)
 
+#define DISPLAY_STATS_BEGIN(entry) \
+        dm_logger_open(dc->ctx->logger, &entry, LOG_DISPLAYSTATS)
+
+#define DISPLAY_STATS(msg, ...) \
+        dm_logger_append(&log_entry, msg, ##__VA_ARGS__)
+
+#define DISPLAY_STATS_END(entry) \
+        dm_logger_close(&entry)
+
 #endif /* __DAL_LOGGER_INTERFACE_H__ */
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index b608a0830801..0a540b9897a6 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -98,7 +98,7 @@ enum dc_log_type {
         LOG_EVENT_UNDERFLOW,
         LOG_IF_TRACE,
         LOG_PERF_TRACE,
-        LOG_PROFILING,
+        LOG_DISPLAYSTATS,
 
         LOG_SECTION_TOTAL_COUNT
 };
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 8446e0876ac8..0cd111d59018 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -43,7 +43,7 @@ static bool de_pq_initialized; /* = false; */
 /* one-time setup of X points */
 void setup_x_points_distribution(void)
 {
-        struct fixed31_32 region_size = dal_fixed31_32_from_int(128);
+        struct fixed31_32 region_size = dc_fixpt_from_int(128);
         int32_t segment;
         uint32_t seg_offset;
         uint32_t index;
@@ -53,8 +53,8 @@ void setup_x_points_distribution(void)
         coordinates_x[MAX_HW_POINTS + 1].x = region_size;
 
         for (segment = 6; segment > (6 - NUM_REGIONS); segment--) {
-                region_size = dal_fixed31_32_div_int(region_size, 2);
-                increment = dal_fixed31_32_div_int(region_size,
+                region_size = dc_fixpt_div_int(region_size, 2);
+                increment = dc_fixpt_div_int(region_size,
                                                 NUM_PTS_IN_REGION);
                 seg_offset = (segment + (NUM_REGIONS - 7)) * NUM_PTS_IN_REGION;
                 coordinates_x[seg_offset].x = region_size;
@@ -62,7 +62,7 @@ void setup_x_points_distribution(void)
                 for (index = seg_offset + 1;
                                 index < seg_offset + NUM_PTS_IN_REGION;
                                 index++) {
-                        coordinates_x[index].x = dal_fixed31_32_add
+                        coordinates_x[index].x = dc_fixpt_add
                                         (coordinates_x[index-1].x, increment);
                 }
         }
@@ -72,63 +72,63 @@ static void compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
 {
         /* consts for PQ gamma formula. */
         const struct fixed31_32 m1 =
-                dal_fixed31_32_from_fraction(159301758, 1000000000);
+                dc_fixpt_from_fraction(159301758, 1000000000);
         const struct fixed31_32 m2 =
-                dal_fixed31_32_from_fraction(7884375, 100000);
+                dc_fixpt_from_fraction(7884375, 100000);
         const struct fixed31_32 c1 =
-                dal_fixed31_32_from_fraction(8359375, 10000000);
+                dc_fixpt_from_fraction(8359375, 10000000);
         const struct fixed31_32 c2 =
-                dal_fixed31_32_from_fraction(188515625, 10000000);
+                dc_fixpt_from_fraction(188515625, 10000000);
         const struct fixed31_32 c3 =
-                dal_fixed31_32_from_fraction(186875, 10000);
+                dc_fixpt_from_fraction(186875, 10000);
 
         struct fixed31_32 l_pow_m1;
         struct fixed31_32 base;
 
-        if (dal_fixed31_32_lt(in_x, dal_fixed31_32_zero))
-                in_x = dal_fixed31_32_zero;
+        if (dc_fixpt_lt(in_x, dc_fixpt_zero))
+                in_x = dc_fixpt_zero;
 
-        l_pow_m1 = dal_fixed31_32_pow(in_x, m1);
-        base = dal_fixed31_32_div(
-                        dal_fixed31_32_add(c1,
-                                        (dal_fixed31_32_mul(c2, l_pow_m1))),
-                        dal_fixed31_32_add(dal_fixed31_32_one,
-                                        (dal_fixed31_32_mul(c3, l_pow_m1))));
-        *out_y = dal_fixed31_32_pow(base, m2);
+        l_pow_m1 = dc_fixpt_pow(in_x, m1);
+        base = dc_fixpt_div(
+                        dc_fixpt_add(c1,
+                                        (dc_fixpt_mul(c2, l_pow_m1))),
+                        dc_fixpt_add(dc_fixpt_one,
+                                        (dc_fixpt_mul(c3, l_pow_m1))));
+        *out_y = dc_fixpt_pow(base, m2);
 }
 
 static void compute_de_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
 {
         /* consts for dePQ gamma formula. */
         const struct fixed31_32 m1 =
-                dal_fixed31_32_from_fraction(159301758, 1000000000);
+                dc_fixpt_from_fraction(159301758, 1000000000);
         const struct fixed31_32 m2 =
-                dal_fixed31_32_from_fraction(7884375, 100000);
+                dc_fixpt_from_fraction(7884375, 100000);
         const struct fixed31_32 c1 =
-                dal_fixed31_32_from_fraction(8359375, 10000000);
+                dc_fixpt_from_fraction(8359375, 10000000);
         const struct fixed31_32 c2 =
-                dal_fixed31_32_from_fraction(188515625, 10000000);
+                dc_fixpt_from_fraction(188515625, 10000000);
         const struct fixed31_32 c3 =
-                dal_fixed31_32_from_fraction(186875, 10000);
+                dc_fixpt_from_fraction(186875, 10000);
 
         struct fixed31_32 l_pow_m1;
         struct fixed31_32 base, div;
 
 
-        if (dal_fixed31_32_lt(in_x, dal_fixed31_32_zero))
-                in_x = dal_fixed31_32_zero;
+        if (dc_fixpt_lt(in_x, dc_fixpt_zero))
+                in_x = dc_fixpt_zero;
 
-        l_pow_m1 = dal_fixed31_32_pow(in_x,
-                        dal_fixed31_32_div(dal_fixed31_32_one, m2));
-        base = dal_fixed31_32_sub(l_pow_m1, c1);
+        l_pow_m1 = dc_fixpt_pow(in_x,
+                        dc_fixpt_div(dc_fixpt_one, m2));
+        base = dc_fixpt_sub(l_pow_m1, c1);
 
-        if (dal_fixed31_32_lt(base, dal_fixed31_32_zero))
-                base = dal_fixed31_32_zero;
+        if (dc_fixpt_lt(base, dc_fixpt_zero))
+                base = dc_fixpt_zero;
 
-        div = dal_fixed31_32_sub(c2, dal_fixed31_32_mul(c3, l_pow_m1));
+        div = dc_fixpt_sub(c2, dc_fixpt_mul(c3, l_pow_m1));
 
-        *out_y = dal_fixed31_32_pow(dal_fixed31_32_div(base, div),
-                        dal_fixed31_32_div(dal_fixed31_32_one, m1));
+        *out_y = dc_fixpt_pow(dc_fixpt_div(base, div),
+                        dc_fixpt_div(dc_fixpt_one, m1));
 
 }
 /* one-time pre-compute PQ values - only for sdr_white_level 80 */
@@ -138,14 +138,14 @@ void precompute_pq(void)
         struct fixed31_32 x;
         const struct hw_x_point *coord_x = coordinates_x + 32;
         struct fixed31_32 scaling_factor =
-                        dal_fixed31_32_from_fraction(80, 10000);
+                        dc_fixpt_from_fraction(80, 10000);
 
         /* pow function has problems with arguments too small */
         for (i = 0; i < 32; i++)
-                pq_table[i] = dal_fixed31_32_zero;
+                pq_table[i] = dc_fixpt_zero;
 
         for (i = 32; i <= MAX_HW_POINTS; i++) {
-                x = dal_fixed31_32_mul(coord_x->x, scaling_factor);
+                x = dc_fixpt_mul(coord_x->x, scaling_factor);
                 compute_pq(x, &pq_table[i]);
                 ++coord_x;
         }
@@ -158,7 +158,7 @@ void precompute_de_pq(void)
         struct fixed31_32  y;
         uint32_t begin_index, end_index;
 
-        struct fixed31_32 scaling_factor = dal_fixed31_32_from_int(125);
+        struct fixed31_32 scaling_factor = dc_fixpt_from_int(125);
 
         /* X points is 2^-25 to 2^7
          * De-gamma X is 2^-12 to 2^0 – we are skipping first -12-(-25) = 13 regions
@@ -167,11 +167,11 @@ void precompute_de_pq(void)
         end_index = begin_index + 12 * NUM_PTS_IN_REGION;
 
         for (i = 0; i <= begin_index; i++)
-                de_pq_table[i] = dal_fixed31_32_zero;
+                de_pq_table[i] = dc_fixpt_zero;
 
         for (; i <= end_index; i++) {
                 compute_de_pq(coordinates_x[i].x, &y);
-                de_pq_table[i] = dal_fixed31_32_mul(y, scaling_factor);
+                de_pq_table[i] = dc_fixpt_mul(y, scaling_factor);
         }
 
         for (; i <= MAX_HW_POINTS; i++)
@@ -195,15 +195,15 @@ static void build_coefficients(struct gamma_coefficients *coefficients, bool is_
         uint32_t index = is_2_4 == true ? 0:1;
 
         do {
-                coefficients->a0[i] = dal_fixed31_32_from_fraction(
+                coefficients->a0[i] = dc_fixpt_from_fraction(
                         numerator01[index], 10000000);
-                coefficients->a1[i] = dal_fixed31_32_from_fraction(
+                coefficients->a1[i] = dc_fixpt_from_fraction(
                         numerator02[index], 1000);
-                coefficients->a2[i] = dal_fixed31_32_from_fraction(
+                coefficients->a2[i] = dc_fixpt_from_fraction(
                         numerator03[index], 1000);
-                coefficients->a3[i] = dal_fixed31_32_from_fraction(
+                coefficients->a3[i] = dc_fixpt_from_fraction(
                         numerator04[index], 1000);
-                coefficients->user_gamma[i] = dal_fixed31_32_from_fraction(
+                coefficients->user_gamma[i] = dc_fixpt_from_fraction(
                         numerator05[index], 1000);
 
                 ++i;
@@ -218,33 +218,33 @@ static struct fixed31_32 translate_from_linear_space(
         struct fixed31_32 a3,
         struct fixed31_32 gamma)
 {
-        const struct fixed31_32 one = dal_fixed31_32_from_int(1);
+        const struct fixed31_32 one = dc_fixpt_from_int(1);
 
-        if (dal_fixed31_32_lt(one, arg))
+        if (dc_fixpt_lt(one, arg))
                 return one;
 
-        if (dal_fixed31_32_le(arg, dal_fixed31_32_neg(a0)))
-                return dal_fixed31_32_sub(
+        if (dc_fixpt_le(arg, dc_fixpt_neg(a0)))
+                return dc_fixpt_sub(
                         a2,
-                        dal_fixed31_32_mul(
-                                dal_fixed31_32_add(
+                        dc_fixpt_mul(
+                                dc_fixpt_add(
                                         one,
                                         a3),
-                                dal_fixed31_32_pow(
-                                        dal_fixed31_32_neg(arg),
-                                        dal_fixed31_32_recip(gamma))));
-        else if (dal_fixed31_32_le(a0, arg))
-                return dal_fixed31_32_sub(
-                        dal_fixed31_32_mul(
-                                dal_fixed31_32_add(
+                                dc_fixpt_pow(
+                                        dc_fixpt_neg(arg),
+                                        dc_fixpt_recip(gamma))));
+        else if (dc_fixpt_le(a0, arg))
+                return dc_fixpt_sub(
+                        dc_fixpt_mul(
+                                dc_fixpt_add(
                                         one,
                                         a3),
-                                dal_fixed31_32_pow(
+                                dc_fixpt_pow(
                                         arg,
-                                        dal_fixed31_32_recip(gamma))),
+                                        dc_fixpt_recip(gamma))),
                         a2);
         else
-                return dal_fixed31_32_mul(
+                return dc_fixpt_mul(
                         arg,
                         a1);
 }
@@ -259,25 +259,25 @@ static struct fixed31_32 translate_to_linear_space(
 {
         struct fixed31_32 linear;
 
-        a0 = dal_fixed31_32_mul(a0, a1);
-        if (dal_fixed31_32_le(arg, dal_fixed31_32_neg(a0)))
+        a0 = dc_fixpt_mul(a0, a1);
+        if (dc_fixpt_le(arg, dc_fixpt_neg(a0)))
 
-                linear = dal_fixed31_32_neg(
-                                 dal_fixed31_32_pow(
-                                 dal_fixed31_32_div(
-                                 dal_fixed31_32_sub(a2, arg),
-                                 dal_fixed31_32_add(
-                                 dal_fixed31_32_one, a3)), gamma));
+                linear = dc_fixpt_neg(
+                                 dc_fixpt_pow(
+                                 dc_fixpt_div(
+                                 dc_fixpt_sub(a2, arg),
+                                 dc_fixpt_add(
+                                 dc_fixpt_one, a3)), gamma));
 
-        else if (dal_fixed31_32_le(dal_fixed31_32_neg(a0), arg) &&
-                         dal_fixed31_32_le(arg, a0))
-                linear = dal_fixed31_32_div(arg, a1);
+        else if (dc_fixpt_le(dc_fixpt_neg(a0), arg) &&
+                         dc_fixpt_le(arg, a0))
+                linear = dc_fixpt_div(arg, a1);
         else
-                linear =  dal_fixed31_32_pow(
-                                        dal_fixed31_32_div(
-                                        dal_fixed31_32_add(a2, arg),
-                                        dal_fixed31_32_add(
-                                        dal_fixed31_32_one, a3)), gamma);
+                linear =  dc_fixpt_pow(
+                                        dc_fixpt_div(
+                                        dc_fixpt_add(a2, arg),
+                                        dc_fixpt_add(
+                                        dc_fixpt_one, a3)), gamma);
 
         return linear;
 }
@@ -352,8 +352,8 @@ static bool find_software_points(
                                 right = axis_x[max_number - 1].b;
                 }
 
-                if (dal_fixed31_32_le(left, hw_point) &&
-                        dal_fixed31_32_le(hw_point, right)) {
+                if (dc_fixpt_le(left, hw_point) &&
+                        dc_fixpt_le(hw_point, right)) {
                         *index_to_start = i;
                         *index_left = i;
 
@@ -366,7 +366,7 @@ static bool find_software_points(
 
                         return true;
                 } else if ((i == *index_to_start) &&
-                        dal_fixed31_32_le(hw_point, left)) {
+                        dc_fixpt_le(hw_point, left)) {
                         *index_to_start = i;
                         *index_left = i;
                         *index_right = i;
@@ -375,7 +375,7 @@ static bool find_software_points(
 
                         return true;
                 } else if ((i == max_number - 1) &&
-                        dal_fixed31_32_le(right, hw_point)) {
+                        dc_fixpt_le(right, hw_point)) {
                         *index_to_start = i;
                         *index_left = i;
                         *index_right = i;
@@ -457,17 +457,17 @@ static bool build_custom_gamma_mapping_coefficients_worker(
                 }
 
                 if (hw_pos == HW_POINT_POSITION_MIDDLE)
-                        point->coeff = dal_fixed31_32_div(
-                                dal_fixed31_32_sub(
+                        point->coeff = dc_fixpt_div(
+                                dc_fixpt_sub(
                                         coord_x,
                                         left_pos),
-                                dal_fixed31_32_sub(
+                                dc_fixpt_sub(
                                         right_pos,
                                         left_pos));
                 else if (hw_pos == HW_POINT_POSITION_LEFT)
-                        point->coeff = dal_fixed31_32_zero;
+                        point->coeff = dc_fixpt_zero;
                 else if (hw_pos == HW_POINT_POSITION_RIGHT)
-                        point->coeff = dal_fixed31_32_from_int(2);
+                        point->coeff = dc_fixpt_from_int(2);
                 else {
                         BREAK_TO_DEBUGGER();
                         return false;
@@ -502,45 +502,45 @@ static struct fixed31_32 calculate_mapped_value(
 
         if ((point->left_index < 0) || (point->left_index > max_index)) {
                 BREAK_TO_DEBUGGER();
-                return dal_fixed31_32_zero;
+                return dc_fixpt_zero;
         }
 
         if ((point->right_index < 0) || (point->right_index > max_index)) {
                 BREAK_TO_DEBUGGER();
-                return dal_fixed31_32_zero;
+                return dc_fixpt_zero;
         }
 
         if (point->pos == HW_POINT_POSITION_MIDDLE)
                 if (channel == CHANNEL_NAME_RED)
-                        result = dal_fixed31_32_add(
-                                dal_fixed31_32_mul(
+                        result = dc_fixpt_add(
+                                dc_fixpt_mul(
                                         point->coeff,
-                                        dal_fixed31_32_sub(
+                                        dc_fixpt_sub(
                                                 rgb[point->right_index].r,
                                                 rgb[point->left_index].r)),
                                 rgb[point->left_index].r);
                 else if (channel == CHANNEL_NAME_GREEN)
-                        result = dal_fixed31_32_add(
-                                dal_fixed31_32_mul(
+                        result = dc_fixpt_add(
+                                dc_fixpt_mul(
                                         point->coeff,
-                                        dal_fixed31_32_sub(
+                                        dc_fixpt_sub(
                                                 rgb[point->right_index].g,
                                                 rgb[point->left_index].g)),
                                 rgb[point->left_index].g);
                 else
-                        result = dal_fixed31_32_add(
-                                dal_fixed31_32_mul(
+                        result = dc_fixpt_add(
+                                dc_fixpt_mul(
                                         point->coeff,
-                                        dal_fixed31_32_sub(
+                                        dc_fixpt_sub(
                                                 rgb[point->right_index].b,
                                                 rgb[point->left_index].b)),
                                 rgb[point->left_index].b);
         else if (point->pos == HW_POINT_POSITION_LEFT) {
                 BREAK_TO_DEBUGGER();
-                result = dal_fixed31_32_zero;
+                result = dc_fixpt_zero;
         } else {
                 BREAK_TO_DEBUGGER();
-                result = dal_fixed31_32_one;
+                result = dc_fixpt_one;
         }
 
         return result;
@@ -558,7 +558,7 @@ static void build_pq(struct pwl_float_data_ex *rgb_regamma,
         struct fixed31_32 x;
         struct fixed31_32 output;
         struct fixed31_32 scaling_factor =
-                        dal_fixed31_32_from_fraction(sdr_white_level, 10000);
+                        dc_fixpt_from_fraction(sdr_white_level, 10000);
 
         if (!pq_initialized && sdr_white_level == 80) {
                 precompute_pq();
@@ -579,15 +579,15 @@ static void build_pq(struct pwl_float_data_ex *rgb_regamma,
                 if (sdr_white_level == 80) {
                         output = pq_table[i];
                 } else {
-                        x = dal_fixed31_32_mul(coord_x->x, scaling_factor);
+                        x = dc_fixpt_mul(coord_x->x, scaling_factor);
                         compute_pq(x, &output);
                 }
 
                 /* should really not happen? */
-                if (dal_fixed31_32_lt(output, dal_fixed31_32_zero))
-                        output = dal_fixed31_32_zero;
-                else if (dal_fixed31_32_lt(dal_fixed31_32_one, output))
-                        output = dal_fixed31_32_one;
+                if (dc_fixpt_lt(output, dc_fixpt_zero))
+                        output = dc_fixpt_zero;
+                else if (dc_fixpt_lt(dc_fixpt_one, output))
+                        output = dc_fixpt_one;
 
                 rgb->r = output;
                 rgb->g = output;
@@ -605,7 +605,7 @@ static void build_de_pq(struct pwl_float_data_ex *de_pq,
         uint32_t i;
         struct fixed31_32 output;
 
-        struct fixed31_32 scaling_factor = dal_fixed31_32_from_int(125);
+        struct fixed31_32 scaling_factor = dc_fixpt_from_int(125);
 
         if (!de_pq_initialized) {
                 precompute_de_pq();
@@ -616,9 +616,9 @@ static void build_de_pq(struct pwl_float_data_ex *de_pq,
         for (i = 0; i <= hw_points_num; i++) {
                 output = de_pq_table[i];
                 /* should really not happen? */
-                if (dal_fixed31_32_lt(output, dal_fixed31_32_zero))
-                        output = dal_fixed31_32_zero;
-                else if (dal_fixed31_32_lt(scaling_factor, output))
+                if (dc_fixpt_lt(output, dc_fixpt_zero))
+                        output = dc_fixpt_zero;
+                else if (dc_fixpt_lt(scaling_factor, output))
                         output = scaling_factor;
                 de_pq[i].r = output;
                 de_pq[i].g = output;
@@ -670,9 +670,9 @@ static void build_degamma(struct pwl_float_data_ex *curve,
         end_index = begin_index + 12 * NUM_PTS_IN_REGION;
 
         while (i != begin_index) {
-                curve[i].r = dal_fixed31_32_zero;
-                curve[i].g = dal_fixed31_32_zero;
-                curve[i].b = dal_fixed31_32_zero;
+                curve[i].r = dc_fixpt_zero;
+                curve[i].g = dc_fixpt_zero;
+                curve[i].b = dc_fixpt_zero;
                 i++;
         }
 
@@ -684,9 +684,9 @@ static void build_degamma(struct pwl_float_data_ex *curve,
                 i++;
         }
         while (i != hw_points_num + 1) {
-                curve[i].r = dal_fixed31_32_one;
-                curve[i].g = dal_fixed31_32_one;
-                curve[i].b = dal_fixed31_32_one;
+                curve[i].r = dc_fixpt_one;
+                curve[i].g = dc_fixpt_one;
+                curve[i].b = dc_fixpt_one;
                 i++;
         }
 }
@@ -695,8 +695,8 @@ static void scale_gamma(struct pwl_float_data *pwl_rgb,
                 const struct dc_gamma *ramp,
                 struct dividers dividers)
 {
-        const struct fixed31_32 max_driver = dal_fixed31_32_from_int(0xFFFF);
-        const struct fixed31_32 max_os = dal_fixed31_32_from_int(0xFF00);
+        const struct fixed31_32 max_driver = dc_fixpt_from_int(0xFFFF);
+        const struct fixed31_32 max_os = dc_fixpt_from_int(0xFF00);
         struct fixed31_32 scaler = max_os;
         uint32_t i;
         struct pwl_float_data *rgb = pwl_rgb;
@@ -705,9 +705,9 @@ static void scale_gamma(struct pwl_float_data *pwl_rgb,
         i = 0;
 
         do {
-                if (dal_fixed31_32_lt(max_os, ramp->entries.red[i]) ||
-                        dal_fixed31_32_lt(max_os, ramp->entries.green[i]) ||
-                        dal_fixed31_32_lt(max_os, ramp->entries.blue[i])) {
+                if (dc_fixpt_lt(max_os, ramp->entries.red[i]) ||
+                        dc_fixpt_lt(max_os, ramp->entries.green[i]) ||
+                        dc_fixpt_lt(max_os, ramp->entries.blue[i])) {
                         scaler = max_driver;
                         break;
                 }
@@ -717,40 +717,40 @@ static void scale_gamma(struct pwl_float_data *pwl_rgb,
         i = 0;
 
         do {
-                rgb->r = dal_fixed31_32_div(
+                rgb->r = dc_fixpt_div(
                         ramp->entries.red[i], scaler);
-                rgb->g = dal_fixed31_32_div(
+                rgb->g = dc_fixpt_div(
                         ramp->entries.green[i], scaler);
-                rgb->b = dal_fixed31_32_div(
+                rgb->b = dc_fixpt_div(
                         ramp->entries.blue[i], scaler);
 
                 ++rgb;
                 ++i;
         } while (i != ramp->num_entries);
 
-        rgb->r = dal_fixed31_32_mul(rgb_last->r,
+        rgb->r = dc_fixpt_mul(rgb_last->r,
                         dividers.divider1);
-        rgb->g = dal_fixed31_32_mul(rgb_last->g,
+        rgb->g = dc_fixpt_mul(rgb_last->g,
                         dividers.divider1);
-        rgb->b = dal_fixed31_32_mul(rgb_last->b,
+        rgb->b = dc_fixpt_mul(rgb_last->b,
                         dividers.divider1);
 
         ++rgb;
 
-        rgb->r = dal_fixed31_32_mul(rgb_last->r,
+        rgb->r = dc_fixpt_mul(rgb_last->r,
                         dividers.divider2);
-        rgb->g = dal_fixed31_32_mul(rgb_last->g,
+        rgb->g = dc_fixpt_mul(rgb_last->g,
                         dividers.divider2);
-        rgb->b = dal_fixed31_32_mul(rgb_last->b,
+        rgb->b = dc_fixpt_mul(rgb_last->b,
                         dividers.divider2);
 
         ++rgb;
 
-        rgb->r = dal_fixed31_32_mul(rgb_last->r,
+        rgb->r = dc_fixpt_mul(rgb_last->r,
                         dividers.divider3);
-        rgb->g = dal_fixed31_32_mul(rgb_last->g,
+        rgb->g = dc_fixpt_mul(rgb_last->g,
                         dividers.divider3);
-        rgb->b = dal_fixed31_32_mul(rgb_last->b,
+        rgb->b = dc_fixpt_mul(rgb_last->b,
                         dividers.divider3);
 }
 
@@ -759,62 +759,62 @@ static void scale_gamma_dx(struct pwl_float_data *pwl_rgb,
                 struct dividers dividers)
 {
         uint32_t i;
-        struct fixed31_32 min = dal_fixed31_32_zero;
-        struct fixed31_32 max = dal_fixed31_32_one;
+        struct fixed31_32 min = dc_fixpt_zero;
+        struct fixed31_32 max = dc_fixpt_one;
 
-        struct fixed31_32 delta = dal_fixed31_32_zero;
-        struct fixed31_32 offset = dal_fixed31_32_zero;
+        struct fixed31_32 delta = dc_fixpt_zero;
+        struct fixed31_32 offset = dc_fixpt_zero;
 
         for (i = 0 ; i < ramp->num_entries; i++) {
-                if (dal_fixed31_32_lt(ramp->entries.red[i], min))
+                if (dc_fixpt_lt(ramp->entries.red[i], min))
                         min = ramp->entries.red[i];
 
-                if (dal_fixed31_32_lt(ramp->entries.green[i], min))
+                if (dc_fixpt_lt(ramp->entries.green[i], min))
                         min = ramp->entries.green[i];
 
-                if (dal_fixed31_32_lt(ramp->entries.blue[i], min))
+                if (dc_fixpt_lt(ramp->entries.blue[i], min))
                         min = ramp->entries.blue[i];
 
-                if (dal_fixed31_32_lt(max, ramp->entries.red[i]))
+                if (dc_fixpt_lt(max, ramp->entries.red[i]))
                         max = ramp->entries.red[i];
 
-                if (dal_fixed31_32_lt(max, ramp->entries.green[i]))
+                if (dc_fixpt_lt(max, ramp->entries.green[i]))
                         max = ramp->entries.green[i];
 
-                if (dal_fixed31_32_lt(max, ramp->entries.blue[i]))
+                if (dc_fixpt_lt(max, ramp->entries.blue[i]))
                         max = ramp->entries.blue[i];
         }
 
-        if (dal_fixed31_32_lt(min, dal_fixed31_32_zero))
-                delta = dal_fixed31_32_neg(min);
+        if (dc_fixpt_lt(min, dc_fixpt_zero))
+                delta = dc_fixpt_neg(min);
 
-        offset = dal_fixed31_32_add(min, max);
+        offset = dc_fixpt_add(min, max);
 
         for (i = 0 ; i < ramp->num_entries; i++) {
-                pwl_rgb[i].r = dal_fixed31_32_div(
-                        dal_fixed31_32_add(
+                pwl_rgb[i].r = dc_fixpt_div(
+                        dc_fixpt_add(
                                 ramp->entries.red[i], delta), offset);
-                pwl_rgb[i].g = dal_fixed31_32_div(
-                        dal_fixed31_32_add(
+                pwl_rgb[i].g = dc_fixpt_div(
+                        dc_fixpt_add(
                                 ramp->entries.green[i], delta), offset);
-                pwl_rgb[i].b = dal_fixed31_32_div(
-                        dal_fixed31_32_add(
+                pwl_rgb[i].b = dc_fixpt_div(
+                        dc_fixpt_add(
                                 ramp->entries.blue[i], delta), offset);
 
         }
 
-        pwl_rgb[i].r =  dal_fixed31_32_sub(dal_fixed31_32_mul_int(
+        pwl_rgb[i].r =  dc_fixpt_sub(dc_fixpt_mul_int(
                                 pwl_rgb[i-1].r, 2), pwl_rgb[i-2].r);
-        pwl_rgb[i].g =  dal_fixed31_32_sub(dal_fixed31_32_mul_int(
+        pwl_rgb[i].g =  dc_fixpt_sub(dc_fixpt_mul_int(
                                 pwl_rgb[i-1].g, 2), pwl_rgb[i-2].g);
-        pwl_rgb[i].b =  dal_fixed31_32_sub(dal_fixed31_32_mul_int(
+        pwl_rgb[i].b =  dc_fixpt_sub(dc_fixpt_mul_int(
                                 pwl_rgb[i-1].b, 2), pwl_rgb[i-2].b);
         ++i;
-        pwl_rgb[i].r =  dal_fixed31_32_sub(dal_fixed31_32_mul_int(
+        pwl_rgb[i].r =  dc_fixpt_sub(dc_fixpt_mul_int(
                                 pwl_rgb[i-1].r, 2), pwl_rgb[i-2].r);
-        pwl_rgb[i].g =  dal_fixed31_32_sub(dal_fixed31_32_mul_int(
+        pwl_rgb[i].g =  dc_fixpt_sub(dc_fixpt_mul_int(
                                 pwl_rgb[i-1].g, 2), pwl_rgb[i-2].g);
-        pwl_rgb[i].b =  dal_fixed31_32_sub(dal_fixed31_32_mul_int(
+        pwl_rgb[i].b =  dc_fixpt_sub(dc_fixpt_mul_int(
                                 pwl_rgb[i-1].b, 2), pwl_rgb[i-2].b);
 }
 
@@ -846,40 +846,40 @@ static void scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb,
 
         i = 0;
         do {
-                rgb->r = dal_fixed31_32_from_fraction(
+                rgb->r = dc_fixpt_from_fraction(
                                 ramp->gamma[i], scaler);
-                rgb->g = dal_fixed31_32_from_fraction(
+                rgb->g = dc_fixpt_from_fraction(
                                 ramp->gamma[i + 256], scaler);
-                rgb->b = dal_fixed31_32_from_fraction(
+                rgb->b = dc_fixpt_from_fraction(
                                 ramp->gamma[i + 512], scaler);
 
                 ++rgb;
                 ++i;
         } while (i != GAMMA_RGB_256_ENTRIES);
 
-        rgb->r = dal_fixed31_32_mul(rgb_last->r,
+        rgb->r = dc_fixpt_mul(rgb_last->r,
                         dividers.divider1);
-        rgb->g = dal_fixed31_32_mul(rgb_last->g,
+        rgb->g = dc_fixpt_mul(rgb_last->g,
                         dividers.divider1);
-        rgb->b = dal_fixed31_32_mul(rgb_last->b,
+        rgb->b = dc_fixpt_mul(rgb_last->b,
                         dividers.divider1);
 
         ++rgb;
 
-        rgb->r = dal_fixed31_32_mul(rgb_last->r,
+        rgb->r = dc_fixpt_mul(rgb_last->r,
                         dividers.divider2);
-        rgb->g = dal_fixed31_32_mul(rgb_last->g,
+        rgb->g = dc_fixpt_mul(rgb_last->g,
                         dividers.divider2);
-        rgb->b = dal_fixed31_32_mul(rgb_last->b,
+        rgb->b = dc_fixpt_mul(rgb_last->b,
                         dividers.divider2);
 
         ++rgb;
 
-        rgb->r = dal_fixed31_32_mul(rgb_last->r,
+        rgb->r = dc_fixpt_mul(rgb_last->r,
                         dividers.divider3);
-        rgb->g = dal_fixed31_32_mul(rgb_last->g,
+        rgb->g = dc_fixpt_mul(rgb_last->g,
                         dividers.divider3);
-        rgb->b = dal_fixed31_32_mul(rgb_last->b,
+        rgb->b = dc_fixpt_mul(rgb_last->b,
                         dividers.divider3);
 }
 
@@ -913,7 +913,7 @@ static void apply_lut_1d(
         struct fixed31_32 lut2;
         const int max_lut_index = 4095;
         const struct fixed31_32 max_lut_index_f =
-                        dal_fixed31_32_from_int_nonconst(max_lut_index);
+                        dc_fixpt_from_int(max_lut_index);
         int32_t index = 0, index_next = 0;
         struct fixed31_32 index_f;
         struct fixed31_32 delta_lut;
@@ -931,10 +931,10 @@ static void apply_lut_1d(
                         else
                                 regamma_y = &tf_pts->blue[i];
 
-                        norm_y = dal_fixed31_32_mul(max_lut_index_f,
+                        norm_y = dc_fixpt_mul(max_lut_index_f,
                                                    *regamma_y);
-                        index = dal_fixed31_32_floor(norm_y);
-                        index_f = dal_fixed31_32_from_int_nonconst(index);
+                        index = dc_fixpt_floor(norm_y);
+                        index_f = dc_fixpt_from_int(index);
 
                         if (index < 0 || index > max_lut_index)
                                 continue;
@@ -953,11 +953,11 @@ static void apply_lut_1d(
                         }
 
                         // we have everything now, so interpolate
-                        delta_lut = dal_fixed31_32_sub(lut2, lut1);
-                        delta_index = dal_fixed31_32_sub(norm_y, index_f);
+                        delta_lut = dc_fixpt_sub(lut2, lut1);
+                        delta_index = dc_fixpt_sub(norm_y, index_f);
 
-                        *regamma_y = dal_fixed31_32_add(lut1,
-                                dal_fixed31_32_mul(delta_index, delta_lut));
+                        *regamma_y = dc_fixpt_add(lut1,
+                                dc_fixpt_mul(delta_index, delta_lut));
                 }
         }
 }
@@ -973,7 +973,7 @@ static void build_evenly_distributed_points(
         uint32_t i = 0;
 
         do {
-                struct fixed31_32 value = dal_fixed31_32_from_fraction(i,
+                struct fixed31_32 value = dc_fixpt_from_fraction(i,
                         numberof_points - 1);
 
                 p->r = value;
@@ -984,21 +984,21 @@ static void build_evenly_distributed_points(
                 ++i;
         } while (i != numberof_points);
 
-        p->r = dal_fixed31_32_div(p_last->r, dividers.divider1);
-        p->g = dal_fixed31_32_div(p_last->g, dividers.divider1);
-        p->b = dal_fixed31_32_div(p_last->b, dividers.divider1);
+        p->r = dc_fixpt_div(p_last->r, dividers.divider1);
+        p->g = dc_fixpt_div(p_last->g, dividers.divider1);
+        p->b = dc_fixpt_div(p_last->b, dividers.divider1);
 
         ++p;
 
-        p->r = dal_fixed31_32_div(p_last->r, dividers.divider2);
-        p->g = dal_fixed31_32_div(p_last->g, dividers.divider2);
-        p->b = dal_fixed31_32_div(p_last->b, dividers.divider2);
+        p->r = dc_fixpt_div(p_last->r, dividers.divider2);
+        p->g = dc_fixpt_div(p_last->g, dividers.divider2);
+        p->b = dc_fixpt_div(p_last->b, dividers.divider2);
 
         ++p;
 
-        p->r = dal_fixed31_32_div(p_last->r, dividers.divider3);
-        p->g = dal_fixed31_32_div(p_last->g, dividers.divider3);
-        p->b = dal_fixed31_32_div(p_last->b, dividers.divider3);
+        p->r = dc_fixpt_div(p_last->r, dividers.divider3);
+        p->g = dc_fixpt_div(p_last->g, dividers.divider3);
+        p->b = dc_fixpt_div(p_last->b, dividers.divider3);
 }
 
 static inline void copy_rgb_regamma_to_coordinates_x(
@@ -1094,7 +1094,7 @@ static void interpolate_user_regamma(uint32_t hw_points_num,
         struct fixed31_32 *tf_point;
         struct fixed31_32 hw_x;
         struct fixed31_32 norm_factor =
-                        dal_fixed31_32_from_int_nonconst(255);
+                        dc_fixpt_from_int(255);
         struct fixed31_32 norm_x;
         struct fixed31_32 index_f;
         struct fixed31_32 lut1;
@@ -1105,9 +1105,9 @@ static void interpolate_user_regamma(uint32_t hw_points_num,
         i = 0;
         /* fixed_pt library has problems handling too small values */
         while (i != 32) {
-                tf_pts->red[i] = dal_fixed31_32_zero;
-                tf_pts->green[i] = dal_fixed31_32_zero;
-                tf_pts->blue[i] = dal_fixed31_32_zero;
+                tf_pts->red[i] = dc_fixpt_zero;
+                tf_pts->green[i] = dc_fixpt_zero;
+                tf_pts->blue[i] = dc_fixpt_zero;
                 ++i;
         }
         while (i <= hw_points_num + 1) {
@@ -1129,12 +1129,12 @@ static void interpolate_user_regamma(uint32_t hw_points_num,
                         } else
                                 hw_x = coordinates_x[i].x;
 
-                        norm_x = dal_fixed31_32_mul(norm_factor, hw_x);
-                        index = dal_fixed31_32_floor(norm_x);
+                        norm_x = dc_fixpt_mul(norm_factor, hw_x);
+                        index = dc_fixpt_floor(norm_x);
                         if (index < 0 || index > 255)
                                 continue;
 
-                        index_f = dal_fixed31_32_from_int_nonconst(index);
+                        index_f = dc_fixpt_from_int(index);
                         index_next = (index == 255) ? index : index + 1;
 
                         if (color == 0) {
@@ -1149,11 +1149,11 @@ static void interpolate_user_regamma(uint32_t hw_points_num,
                         }
 
                         // we have everything now, so interpolate
-                        delta_lut = dal_fixed31_32_sub(lut2, lut1);
-                        delta_index = dal_fixed31_32_sub(norm_x, index_f);
+                        delta_lut = dc_fixpt_sub(lut2, lut1);
+                        delta_index = dc_fixpt_sub(norm_x, index_f);
 
-                        *tf_point = dal_fixed31_32_add(lut1,
-                                dal_fixed31_32_mul(delta_index, delta_lut));
+                        *tf_point = dc_fixpt_add(lut1,
+                                dc_fixpt_mul(delta_index, delta_lut));
                 }
                 ++i;
         }
@@ -1168,15 +1168,15 @@ static void build_new_custom_resulted_curve(
         i = 0;
 
         while (i != hw_points_num + 1) {
-                tf_pts->red[i] = dal_fixed31_32_clamp(
-                        tf_pts->red[i], dal_fixed31_32_zero,
-                        dal_fixed31_32_one);
-                tf_pts->green[i] = dal_fixed31_32_clamp(
-                        tf_pts->green[i], dal_fixed31_32_zero,
-                        dal_fixed31_32_one);
-                tf_pts->blue[i] = dal_fixed31_32_clamp(
-                        tf_pts->blue[i], dal_fixed31_32_zero,
-                        dal_fixed31_32_one);
+                tf_pts->red[i] = dc_fixpt_clamp(
+                        tf_pts->red[i], dc_fixpt_zero,
+                        dc_fixpt_one);
+                tf_pts->green[i] = dc_fixpt_clamp(
+                        tf_pts->green[i], dc_fixpt_zero,
+                        dc_fixpt_one);
+                tf_pts->blue[i] = dc_fixpt_clamp(
+                        tf_pts->blue[i], dc_fixpt_zero,
+                        dc_fixpt_one);
 
                 ++i;
         }
@@ -1290,9 +1290,9 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
         if (!coeff)
                 goto coeff_alloc_fail;
 
-        dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
-        dividers.divider2 = dal_fixed31_32_from_int(2);
-        dividers.divider3 = dal_fixed31_32_from_fraction(5, 2);
+        dividers.divider1 = dc_fixpt_from_fraction(3, 2);
+        dividers.divider2 = dc_fixpt_from_int(2);
+        dividers.divider3 = dc_fixpt_from_fraction(5, 2);
 
         tf = output_tf->tf;
 
@@ -1357,15 +1357,15 @@ bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
         uint32_t i = 0;
 
         do {
-                coeff.a0[i] = dal_fixed31_32_from_fraction(
+                coeff.a0[i] = dc_fixpt_from_fraction(
                                 regamma->coeff.A0[i], 10000000);
-                coeff.a1[i] = dal_fixed31_32_from_fraction(
+                coeff.a1[i] = dc_fixpt_from_fraction(
                                 regamma->coeff.A1[i], 1000);
-                coeff.a2[i] = dal_fixed31_32_from_fraction(
+                coeff.a2[i] = dc_fixpt_from_fraction(
                                 regamma->coeff.A2[i], 1000);
-                coeff.a3[i] = dal_fixed31_32_from_fraction(
+                coeff.a3[i] = dc_fixpt_from_fraction(
                                 regamma->coeff.A3[i], 1000);
-                coeff.user_gamma[i] = dal_fixed31_32_from_fraction(
+                coeff.user_gamma[i] = dc_fixpt_from_fraction(
                                 regamma->coeff.gamma[i], 1000);
 
                 ++i;
@@ -1374,9 +1374,9 @@ bool calculate_user_regamma_coeff(struct dc_transfer_func *output_tf,
         i = 0;
         /* fixed_pt library has problems handling too small values */
         while (i != 32) {
-                output_tf->tf_pts.red[i] = dal_fixed31_32_zero;
-                output_tf->tf_pts.green[i] = dal_fixed31_32_zero;
-                output_tf->tf_pts.blue[i] = dal_fixed31_32_zero;
+                output_tf->tf_pts.red[i] = dc_fixpt_zero;
+                output_tf->tf_pts.green[i] = dc_fixpt_zero;
+                output_tf->tf_pts.blue[i] = dc_fixpt_zero;
                 ++coord_x;
                 ++i;
         }
@@ -1423,9 +1423,9 @@ bool calculate_user_regamma_ramp(struct dc_transfer_func *output_tf,
         if (!rgb_regamma)
                 goto rgb_regamma_alloc_fail;
 
-        dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
-        dividers.divider2 = dal_fixed31_32_from_int(2);
-        dividers.divider3 = dal_fixed31_32_from_fraction(5, 2);
+        dividers.divider1 = dc_fixpt_from_fraction(3, 2);
+        dividers.divider2 = dc_fixpt_from_int(2);
+        dividers.divider3 = dc_fixpt_from_fraction(5, 2);
 
         scale_user_regamma_ramp(rgb_user, &regamma->ramp, dividers);
 
@@ -1496,9 +1496,9 @@ bool mod_color_calculate_degamma_params(struct dc_transfer_func *input_tf,
         if (!coeff)
                 goto coeff_alloc_fail;
 
-        dividers.divider1 = dal_fixed31_32_from_fraction(3, 2);
-        dividers.divider2 = dal_fixed31_32_from_int(2);
-        dividers.divider3 = dal_fixed31_32_from_fraction(5, 2);
+        dividers.divider1 = dc_fixpt_from_fraction(3, 2);
+        dividers.divider2 = dc_fixpt_from_int(2);
+        dividers.divider3 = dc_fixpt_from_fraction(5, 2);
 
         tf = input_tf->tf;
 
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
index 3230e2adb870..3812094b52e8 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_stats.h
@@ -46,6 +46,10 @@ void mod_stats_dump(struct mod_stats *mod_stats);
 
 void mod_stats_reset_data(struct mod_stats *mod_stats);
 
+void mod_stats_update_event(struct mod_stats *mod_stats,
+                char *event_string,
+                unsigned int length);
+
 void mod_stats_update_flip(struct mod_stats *mod_stats,
                 unsigned long timestamp_in_ns);
 
diff --git a/drivers/gpu/drm/amd/display/modules/stats/stats.c b/drivers/gpu/drm/amd/display/modules/stats/stats.c
index 48e02197919f..3f7d47fdc367 100644
--- a/drivers/gpu/drm/amd/display/modules/stats/stats.c
+++ b/drivers/gpu/drm/amd/display/modules/stats/stats.c
@@ -36,9 +36,14 @@
 #define DAL_STATS_ENTRIES_REGKEY_DEFAULT        0x00350000
 #define DAL_STATS_ENTRIES_REGKEY_MAX            0x01000000
 
+#define DAL_STATS_EVENT_ENTRIES_DEFAULT         0x00000100
+
 #define MOD_STATS_NUM_VSYNCS                    5
+#define MOD_STATS_EVENT_STRING_MAX              512
 
 struct stats_time_cache {
+        unsigned int entry_id;
+
         unsigned long flip_timestamp_in_ns;
         unsigned long vupdate_timestamp_in_ns;
 
@@ -63,15 +68,26 @@ struct stats_time_cache {
         unsigned int flags;
 };
 
+struct stats_event_cache {
+        unsigned int entry_id;
+        char event_string[MOD_STATS_EVENT_STRING_MAX];
+};
+
 struct core_stats {
         struct mod_stats public;
         struct dc *dc;
 
+        bool enabled;
+        unsigned int entries;
+        unsigned int event_entries;
+        unsigned int entry_id;
+
         struct stats_time_cache *time;
         unsigned int index;
 
-        bool enabled;
-        unsigned int entries;
+        struct stats_event_cache *events;
+        unsigned int event_index;
+
 };
 
 #define MOD_STATS_TO_CORE(mod_stats)\
@@ -99,12 +115,12 @@ struct mod_stats *mod_stats_create(struct dc *dc)
         unsigned int reg_data;
         int i = 0;
 
+        if (dc == NULL)
+                goto fail_construct;
+
         core_stats = kzalloc(sizeof(struct core_stats), GFP_KERNEL);
 
         if (core_stats == NULL)
-                goto fail_alloc_context;
-
-        if (dc == NULL)
                 goto fail_construct;
 
         core_stats->dc = dc;
@@ -125,27 +141,45 @@ struct mod_stats *mod_stats_create(struct dc *dc)
                         else
                                 core_stats->entries = reg_data;
                 }
+                core_stats->time = kzalloc(
+                        sizeof(struct stats_time_cache) *
+                                core_stats->entries,
+                                                GFP_KERNEL);
+
+                if (core_stats->time == NULL)
+                        goto fail_construct_time;
 
-                core_stats->time = kzalloc(sizeof(struct stats_time_cache) * core_stats->entries,
+                core_stats->event_entries = DAL_STATS_EVENT_ENTRIES_DEFAULT;
+                core_stats->events = kzalloc(
+                        sizeof(struct stats_event_cache) *
+                                core_stats->event_entries,
                                                 GFP_KERNEL);
+
+                if (core_stats->events == NULL)
+                        goto fail_construct_events;
+
         } else {
                 core_stats->entries = 0;
         }
 
-        if (core_stats->time == NULL)
-                goto fail_construct;
-
         /* Purposely leave index 0 unused so we don't need special logic to
          * handle calculation cases that depend on previous flip data.
          */
         core_stats->index = 1;
+        core_stats->event_index = 0;
+
+        // Keeps track of ordering within the different stats structures
+        core_stats->entry_id = 0;
 
         return &core_stats->public;
 
-fail_construct:
+fail_construct_events:
+        kfree(core_stats->time);
+
+fail_construct_time:
         kfree(core_stats);
 
-fail_alloc_context:
+fail_construct:
         return NULL;
 }
 
@@ -157,6 +191,9 @@ void mod_stats_destroy(struct mod_stats *mod_stats)
                 if (core_stats->time != NULL)
                         kfree(core_stats->time);
 
+                if (core_stats->events != NULL)
+                        kfree(core_stats->events);
+
                 kfree(core_stats);
         }
 }
@@ -167,7 +204,11 @@ void mod_stats_dump(struct mod_stats *mod_stats)
         struct dal_logger *logger = NULL;
         struct core_stats *core_stats = NULL;
         struct stats_time_cache *time = NULL;
+        struct stats_event_cache *events = NULL;
+        unsigned int time_index = 1;
+        unsigned int event_index = 0;
         unsigned int index = 0;
+        struct log_entry log_entry;
 
         if (mod_stats == NULL)
                 return;
@@ -176,45 +217,62 @@ void mod_stats_dump(struct mod_stats *mod_stats)
         dc = core_stats->dc;
         logger = dc->ctx->logger;
         time = core_stats->time;
-
-        //LogEntry* pLog = GetLog()->Open(LogMajor_ISR, LogMinor_ISR_FreeSyncSW);
-
-        //if (!pLog->IsDummyEntry())
-        {
-                dm_logger_write(logger, LOG_PROFILING, "==Display Caps==\n");
-                dm_logger_write(logger, LOG_PROFILING, "\n");
-                dm_logger_write(logger, LOG_PROFILING, "\n");
-
-                dm_logger_write(logger, LOG_PROFILING, "==Stats==\n");
-                dm_logger_write(logger, LOG_PROFILING,
-                        "render avgRender minWindow midPoint maxWindow vsyncToFlip flipToVsync #vsyncBetweenFlip #frame insertDuration vTotalMin vTotalMax eventTrigs vSyncTime1 vSyncTime2 vSyncTime3 vSyncTime4 vSyncTime5 flags\n");
-
-                for (int i = 0; i < core_stats->index && i < core_stats->entries; i++) {
-                        dm_logger_write(logger, LOG_PROFILING,
-                                        "%u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u  %u",
-                                        time[i].render_time_in_us,
-                                        time[i].avg_render_time_in_us_last_ten,
-                                        time[i].min_window,
-                                        time[i].lfc_mid_point_in_us,
-                                        time[i].max_window,
-                                        time[i].vsync_to_flip_time_in_us,
-                                        time[i].flip_to_vsync_time_in_us,
-                                        time[i].num_vsync_between_flips,
-                                        time[i].num_frames_inserted,
-                                        time[i].inserted_duration_in_us,
-                                        time[i].v_total_min,
-                                        time[i].v_total_max,
-                                        time[i].event_triggers,
-                                        time[i].v_sync_time_in_us[0],
-                                        time[i].v_sync_time_in_us[1],
-                                        time[i].v_sync_time_in_us[2],
-                                        time[i].v_sync_time_in_us[3],
-                                        time[i].v_sync_time_in_us[4],
-                                        time[i].flags);
+        events = core_stats->events;
+
+        DISPLAY_STATS_BEGIN(log_entry);
+
+        DISPLAY_STATS("==Display Caps==\n");
+
+        DISPLAY_STATS("==Display Stats==\n");
+
+        DISPLAY_STATS("%10s %10s %10s %10s %10s"
+                        " %11s %11s %17s %10s %14s"
+                        " %10s %10s %10s %10s %10s"
+                        " %10s %10s %10s %10s\n",
+                "render", "avgRender",
+                "minWindow", "midPoint", "maxWindow",
+                "vsyncToFlip", "flipToVsync", "vsyncsBetweenFlip",
+                "numFrame", "insertDuration",
+                "vTotalMin", "vTotalMax", "eventTrigs",
+                "vSyncTime1", "vSyncTime2", "vSyncTime3",
+                "vSyncTime4", "vSyncTime5", "flags");
+
+        for (int i = 0; i < core_stats->entry_id; i++) {
+                if (event_index < core_stats->event_index &&
+                                i == events[event_index].entry_id) {
+                        DISPLAY_STATS("%s\n", events[event_index].event_string);
+                        event_index++;
+                } else if (time_index < core_stats->index &&
+                                i == time[time_index].entry_id) {
+                        DISPLAY_STATS("%10u %10u %10u %10u %10u"
+                                        " %11u %11u %17u %10u %14u"
+                                        " %10u %10u %10u %10u %10u"
+                                        " %10u %10u %10u %10u\n",
+                                time[time_index].render_time_in_us,
+                                time[time_index].avg_render_time_in_us_last_ten,
+                                time[time_index].min_window,
+                                time[time_index].lfc_mid_point_in_us,
+                                time[time_index].max_window,
+                                time[time_index].vsync_to_flip_time_in_us,
+                                time[time_index].flip_to_vsync_time_in_us,
+                                time[time_index].num_vsync_between_flips,
+                                time[time_index].num_frames_inserted,
+                                time[time_index].inserted_duration_in_us,
+                                time[time_index].v_total_min,
+                                time[time_index].v_total_max,
+                                time[time_index].event_triggers,
+                                time[time_index].v_sync_time_in_us[0],
+                                time[time_index].v_sync_time_in_us[1],
+                                time[time_index].v_sync_time_in_us[2],
+                                time[time_index].v_sync_time_in_us[3],
+                                time[time_index].v_sync_time_in_us[4],
+                                time[time_index].flags);
+
+                        time_index++;
                 }
         }
-        //GetLog()->Close(pLog);
-        //GetLog()->UnSetLogMask(LogMajor_ISR, LogMinor_ISR_FreeSyncSW);
+
+        DISPLAY_STATS_END(log_entry);
 }
 
 void mod_stats_reset_data(struct mod_stats *mod_stats)
@@ -231,7 +289,46 @@ void mod_stats_reset_data(struct mod_stats *mod_stats)
         memset(core_stats->time, 0,
                 sizeof(struct stats_time_cache) * core_stats->entries);
 
+        memset(core_stats->events, 0,
+                sizeof(struct stats_event_cache) * core_stats->event_entries);
+
         core_stats->index = 1;
+        core_stats->event_index = 0;
+
+        // Keeps track of ordering within the different stats structures
+        core_stats->entry_id = 0;
+}
+
+void mod_stats_update_event(struct mod_stats *mod_stats,
+                char *event_string,
+                unsigned int length)
+{
+        struct core_stats *core_stats = NULL;
+        struct stats_event_cache *events = NULL;
+        unsigned int index = 0;
+        unsigned int copy_length = 0;
+
+        if (mod_stats == NULL)
+                return;
+
+        core_stats = MOD_STATS_TO_CORE(mod_stats);
+
+        if (core_stats->event_index >= core_stats->event_entries)
+                return;
+
+        events = core_stats->events;
+        index = core_stats->event_index;
+
+        copy_length = length;
+        if (length > MOD_STATS_EVENT_STRING_MAX)
+                copy_length = MOD_STATS_EVENT_STRING_MAX;
+
+        memcpy(&events[index].event_string, event_string, copy_length);
+        events[index].event_string[copy_length - 1] = '\0';
+
+        events[index].entry_id = core_stats->entry_id;
+        core_stats->event_index++;
+        core_stats->entry_id++;
 }
 
 void mod_stats_update_flip(struct mod_stats *mod_stats,
@@ -272,7 +369,9 @@ void mod_stats_update_flip(struct mod_stats *mod_stats,
                         (timestamp_in_ns -
                                 time[index - 1].vupdate_timestamp_in_ns) / 1000;
 
+        time[index].entry_id = core_stats->entry_id;
         core_stats->index++;
+        core_stats->entry_id++;
 }
 
 void mod_stats_update_vupdate(struct mod_stats *mod_stats,
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 33de33016bda..b178176b72ac 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -92,7 +92,7 @@ enum amd_powergating_state {
 #define AMD_CG_SUPPORT_GFX_3D_CGLS              (1 << 21)
 #define AMD_CG_SUPPORT_DRM_MGCG                 (1 << 22)
 #define AMD_CG_SUPPORT_DF_MGCG                  (1 << 23)
-
+#define AMD_CG_SUPPORT_VCN_MGCG                 (1 << 24)
 /* PG flags */
 #define AMD_PG_SUPPORT_GFX_PG                   (1 << 0)
 #define AMD_PG_SUPPORT_GFX_SMG                  (1 << 1)
@@ -108,6 +108,7 @@ enum amd_powergating_state {
 #define AMD_PG_SUPPORT_GFX_QUICK_MG             (1 << 11)
 #define AMD_PG_SUPPORT_GFX_PIPELINE             (1 << 12)
 #define AMD_PG_SUPPORT_MMHUB                    (1 << 13)
+#define AMD_PG_SUPPORT_VCN                      (1 << 14)
 
 enum PP_FEATURE_MASK {
         PP_SCLK_DPM_MASK = 0x1,
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
index f730d0629020..b6f74bf4af02 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
@@ -2095,6 +2095,18 @@
 #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
 #define mmDC_GPIO_RXEN                                                                                 0x212f
 #define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define mmDC_GPIO_AUX_CTRL_3                                                                           0x2130
+#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_4                                                                           0x2131
+#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define mmDC_GPIO_AUX_CTRL_5                                                                           0x2132
+#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x2133
+#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+#define mmDC_GPIO_PULLUPEN                                                                             0x2134
+#define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define mmDC_GPIO_AUX_CTRL_6                                                                           0x2135
+#define mmDC_GPIO_AUX_CTRL_6_BASE_IDX                                                                  2
 #define mmBPHYC_DAC_MACRO_CNTL                                                                         0x2136
 #define mmBPHYC_DAC_MACRO_CNTL_BASE_IDX                                                                2
 #define mmDAC_MACRO_CNTL_RESERVED0                                                                     0x2136
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
index 6d3162c42957..bcd190a3fcdd 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
@@ -10971,6 +10971,158 @@
 #define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK                                                                  0x00100000L
 #define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK                                                                 0x00200000L
 #define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK                                                                0x00400000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT                                                           0x14
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT                                                          0x15
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT                                                         0x16
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK                                                             0x00100000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK                                                            0x00200000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK                                                           0x00400000L
+//DC_GPIO_AUX_CTRL_6
+#define DC_GPIO_AUX_CTRL_6__AUX1_PAD_RXSEL__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_6__AUX2_PAD_RXSEL__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_6__AUX3_PAD_RXSEL__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_6__AUX4_PAD_RXSEL__SHIFT                                                             0x6
+#define DC_GPIO_AUX_CTRL_6__AUX5_PAD_RXSEL__SHIFT                                                             0x8
+#define DC_GPIO_AUX_CTRL_6__AUX6_PAD_RXSEL__SHIFT                                                             0xa
+#define DC_GPIO_AUX_CTRL_6__AUX1_PAD_RXSEL_MASK                                                               0x00000003L
+#define DC_GPIO_AUX_CTRL_6__AUX2_PAD_RXSEL_MASK                                                               0x0000000CL
+#define DC_GPIO_AUX_CTRL_6__AUX3_PAD_RXSEL_MASK                                                               0x00000030L
+#define DC_GPIO_AUX_CTRL_6__AUX4_PAD_RXSEL_MASK                                                               0x000000C0L
+#define DC_GPIO_AUX_CTRL_6__AUX5_PAD_RXSEL_MASK                                                               0x00000300L
+#define DC_GPIO_AUX_CTRL_6__AUX6_PAD_RXSEL_MASK                                                               0x00000C00L
 //BPHYC_DAC_MACRO_CNTL
 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT                                                    0x0
 #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT                                             0x8
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
index 2b305dd021e8..e6044e27a913 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
@@ -30,4 +30,8 @@
 #define mmDF_CS_AON0_DramBaseAddress0                                                                   0x0044
 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                          0
 
+#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0                                                            0x0214
+#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX                                                   0
+
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
index 2ba849798924..a78c99480e2d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
@@ -45,4 +45,8 @@
 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                  0x00000700L
 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                  0xFFFFF000L
 
+//DF_CS_AON0_CoherentSlaveModeCtrlA0
+#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT                                        0x3
+#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK                                          0x00000008L
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h
new file mode 100644
index 000000000000..e58c207ac980
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _df_3_6_DEFAULT_HEADER
+#define _df_3_6_DEFAULT_HEADER
+
+#define mmFabricConfigAccessControl_DEFAULT                                             0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
new file mode 100644
index 000000000000..a9575db8d7aa
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _df_3_6_OFFSET_HEADER
+#define _df_3_6_OFFSET_HEADER
+
+#define mmFabricConfigAccessControl                                                                     0x0410
+#define mmFabricConfigAccessControl_BASE_IDX                                                            0
+
+#define mmDF_PIE_AON0_DfGlobalClkGater                                                                  0x00fc
+#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                         0
+
+#define mmDF_CS_UMC_AON0_DramBaseAddress0                                                               0x0044
+#define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX                                                      0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
new file mode 100644
index 000000000000..88f7c69df6b9
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _df_3_6_SH_MASK_HEADER
+#define _df_3_6_SH_MASK_HEADER
+
+/* FabricConfigAccessControl */
+#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                               0x0
+#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                          0x1
+#define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                  0x10
+#define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                 0x00000001L
+#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                            0x00000002L
+#define FabricConfigAccessControl__CfgRegInstID_MASK                                                    0x00FF0000L
+
+/* DF_PIE_AON0_DfGlobalClkGater */
+#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                   0x0
+#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                     0x0000000FL
+
+/* DF_CS_AON0_DramBaseAddress0 */
+#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                              0x0
+#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                          0x1
+#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                            0x4
+#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                            0x8
+#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                            0xc
+#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK                                                0x00000001L
+#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                            0x00000002L
+#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK                                              0x000000F0L
+#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                              0x00000700L
+#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK                                              0xFFFFF000L
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index de177ce8ca80..c6c1666ac120 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1219,6 +1219,41 @@ struct  atom_gfx_info_v2_3 {
   uint32_t rm21_sram_vmin_value;
 };
 
+struct  atom_gfx_info_v2_4 {
+  struct  atom_common_table_header  table_header;
+  uint8_t gfxip_min_ver;
+  uint8_t gfxip_max_ver;
+  uint8_t gc_num_se;
+  uint8_t max_tile_pipes;
+  uint8_t gc_num_cu_per_sh;
+  uint8_t gc_num_sh_per_se;
+  uint8_t gc_num_rb_per_se;
+  uint8_t gc_num_tccs;
+  uint32_t regaddr_cp_dma_src_addr;
+  uint32_t regaddr_cp_dma_src_addr_hi;
+  uint32_t regaddr_cp_dma_dst_addr;
+  uint32_t regaddr_cp_dma_dst_addr_hi;
+  uint32_t regaddr_cp_dma_command;
+  uint32_t regaddr_cp_status;
+  uint32_t regaddr_rlc_gpu_clock_32;
+  uint32_t rlc_gpu_timer_refclk;
+  uint8_t active_cu_per_sh;
+  uint8_t active_rb_per_se;
+  uint16_t gcgoldenoffset;
+  uint16_t gc_num_gprs;
+  uint16_t gc_gsprim_buff_depth;
+  uint16_t gc_parameter_cache_depth;
+  uint16_t gc_wave_size;
+  uint16_t gc_max_waves_per_simd;
+  uint16_t gc_lds_size;
+  uint8_t gc_num_max_gs_thds;
+  uint8_t gc_gs_table_depth;
+  uint8_t gc_double_offchip_lds_buffer;
+  uint8_t gc_max_scratch_slots_per_cu;
+  uint32_t sram_rm_fuses_val;
+  uint32_t sram_custom_rm_fuses_val;
+};
+
 /* 
   ***************************************************************************
     Data Table smu_info  structure
diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
index a12d4f27cfa4..12e196c15bbe 100644
--- a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
+++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
@@ -43,6 +43,7 @@ enum soc15_ih_clientid {
         SOC15_IH_CLIENTID_SE2SH         = 0x0c,
         SOC15_IH_CLIENTID_SE3SH         = 0x0d,
         SOC15_IH_CLIENTID_SYSHUB        = 0x0e,
+        SOC15_IH_CLIENTID_UVD1          = 0x0e,
         SOC15_IH_CLIENTID_THM           = 0x0f,
         SOC15_IH_CLIENTID_UVD           = 0x10,
         SOC15_IH_CLIENTID_VCE0          = 0x11,
diff --git a/drivers/gpu/drm/amd/include/vega20_ip_offset.h b/drivers/gpu/drm/amd/include/vega20_ip_offset.h
new file mode 100644
index 000000000000..2a2a9cc8bedb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/vega20_ip_offset.h
@@ -0,0 +1,1051 @@
+/*
+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _vega20_ip_offset_HEADER
+#define _vega20_ip_offset_HEADER
+
+#define MAX_INSTANCE                                       6
+#define MAX_SEGMENT                                        6
+
+
+struct IP_BASE_INSTANCE
+{
+    unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C20, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE            ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCE_BASE            ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE            ={ { { { 0x00017400, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE            ={ { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE            ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE            ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE            ={ { { { 0x00001260, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA1_BASE            ={ { { { 0x00001860, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE            ={ { { { 0x00014000, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UVD_BASE            ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } },
+                                        { { 0, 0x00009000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+/* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/
+static const struct IP_BASE VCE_BASE            ={ { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE XDMA_BASE            ={ { { { 0x00003400, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE RSMU_BASE            ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ATHUB_BASE__INST0_SEG0                     0x00000C20
+#define ATHUB_BASE__INST0_SEG1                     0
+#define ATHUB_BASE__INST0_SEG2                     0
+#define ATHUB_BASE__INST0_SEG3                     0
+#define ATHUB_BASE__INST0_SEG4                     0
+#define ATHUB_BASE__INST0_SEG5                     0
+
+#define ATHUB_BASE__INST1_SEG0                     0
+#define ATHUB_BASE__INST1_SEG1                     0
+#define ATHUB_BASE__INST1_SEG2                     0
+#define ATHUB_BASE__INST1_SEG3                     0
+#define ATHUB_BASE__INST1_SEG4                     0
+#define ATHUB_BASE__INST1_SEG5                     0
+
+#define ATHUB_BASE__INST2_SEG0                     0
+#define ATHUB_BASE__INST2_SEG1                     0
+#define ATHUB_BASE__INST2_SEG2                     0
+#define ATHUB_BASE__INST2_SEG3                     0
+#define ATHUB_BASE__INST2_SEG4                     0
+#define ATHUB_BASE__INST2_SEG5                     0
+
+#define ATHUB_BASE__INST3_SEG0                     0
+#define ATHUB_BASE__INST3_SEG1                     0
+#define ATHUB_BASE__INST3_SEG2                     0
+#define ATHUB_BASE__INST3_SEG3                     0
+#define ATHUB_BASE__INST3_SEG4                     0
+#define ATHUB_BASE__INST3_SEG5                     0
+
+#define ATHUB_BASE__INST4_SEG0                     0
+#define ATHUB_BASE__INST4_SEG1                     0
+#define ATHUB_BASE__INST4_SEG2                     0
+#define ATHUB_BASE__INST4_SEG3                     0
+#define ATHUB_BASE__INST4_SEG4                     0
+#define ATHUB_BASE__INST4_SEG5                     0
+
+#define ATHUB_BASE__INST5_SEG0                     0
+#define ATHUB_BASE__INST5_SEG1                     0
+#define ATHUB_BASE__INST5_SEG2                     0
+#define ATHUB_BASE__INST5_SEG3                     0
+#define ATHUB_BASE__INST5_SEG4                     0
+#define ATHUB_BASE__INST5_SEG5                     0
+
+#define CLK_BASE__INST0_SEG0                       0x00016C00
+#define CLK_BASE__INST0_SEG1                       0x00016E00
+#define CLK_BASE__INST0_SEG2                       0x00017000
+#define CLK_BASE__INST0_SEG3                       0x00017200
+#define CLK_BASE__INST0_SEG4                       0x0001B000
+#define CLK_BASE__INST0_SEG5                       0x0001B200
+
+#define CLK_BASE__INST1_SEG0                       0
+#define CLK_BASE__INST1_SEG1                       0
+#define CLK_BASE__INST1_SEG2                       0
+#define CLK_BASE__INST1_SEG3                       0
+#define CLK_BASE__INST1_SEG4                       0
+#define CLK_BASE__INST1_SEG5                       0
+
+#define CLK_BASE__INST2_SEG0                       0
+#define CLK_BASE__INST2_SEG1                       0
+#define CLK_BASE__INST2_SEG2                       0
+#define CLK_BASE__INST2_SEG3                       0
+#define CLK_BASE__INST2_SEG4                       0
+#define CLK_BASE__INST2_SEG5                       0
+
+#define CLK_BASE__INST3_SEG0                       0
+#define CLK_BASE__INST3_SEG1                       0
+#define CLK_BASE__INST3_SEG2                       0
+#define CLK_BASE__INST3_SEG3                       0
+#define CLK_BASE__INST3_SEG4                       0
+#define CLK_BASE__INST3_SEG5                       0
+
+#define CLK_BASE__INST4_SEG0                       0
+#define CLK_BASE__INST4_SEG1                       0
+#define CLK_BASE__INST4_SEG2                       0
+#define CLK_BASE__INST4_SEG3                       0
+#define CLK_BASE__INST4_SEG4                       0
+#define CLK_BASE__INST4_SEG5                       0
+
+#define CLK_BASE__INST5_SEG0                       0
+#define CLK_BASE__INST5_SEG1                       0
+#define CLK_BASE__INST5_SEG2                       0
+#define CLK_BASE__INST5_SEG3                       0
+#define CLK_BASE__INST5_SEG4                       0
+#define CLK_BASE__INST5_SEG5                       0
+
+#define DCE_BASE__INST0_SEG0                       0x00000012
+#define DCE_BASE__INST0_SEG1                       0x000000C0
+#define DCE_BASE__INST0_SEG2                       0x000034C0
+#define DCE_BASE__INST0_SEG3                       0
+#define DCE_BASE__INST0_SEG4                       0
+#define DCE_BASE__INST0_SEG5                       0
+
+#define DCE_BASE__INST1_SEG0                       0
+#define DCE_BASE__INST1_SEG1                       0
+#define DCE_BASE__INST1_SEG2                       0
+#define DCE_BASE__INST1_SEG3                       0
+#define DCE_BASE__INST1_SEG4                       0
+#define DCE_BASE__INST1_SEG5                       0
+
+#define DCE_BASE__INST2_SEG0                       0
+#define DCE_BASE__INST2_SEG1                       0
+#define DCE_BASE__INST2_SEG2                       0
+#define DCE_BASE__INST2_SEG3                       0
+#define DCE_BASE__INST2_SEG4                       0
+#define DCE_BASE__INST2_SEG5                       0
+
+#define DCE_BASE__INST3_SEG0                       0
+#define DCE_BASE__INST3_SEG1                       0
+#define DCE_BASE__INST3_SEG2                       0
+#define DCE_BASE__INST3_SEG3                       0
+#define DCE_BASE__INST3_SEG4                       0
+#define DCE_BASE__INST3_SEG5                       0
+
+#define DCE_BASE__INST4_SEG0                       0
+#define DCE_BASE__INST4_SEG1                       0
+#define DCE_BASE__INST4_SEG2                       0
+#define DCE_BASE__INST4_SEG3                       0
+#define DCE_BASE__INST4_SEG4                       0
+#define DCE_BASE__INST4_SEG5                       0
+
+#define DCE_BASE__INST5_SEG0                       0
+#define DCE_BASE__INST5_SEG1                       0
+#define DCE_BASE__INST5_SEG2                       0
+#define DCE_BASE__INST5_SEG3                       0
+#define DCE_BASE__INST5_SEG4                       0
+#define DCE_BASE__INST5_SEG5                       0
+
+#define DF_BASE__INST0_SEG0                        0x00007000
+#define DF_BASE__INST0_SEG1                        0
+#define DF_BASE__INST0_SEG2                        0
+#define DF_BASE__INST0_SEG3                        0
+#define DF_BASE__INST0_SEG4                        0
+#define DF_BASE__INST0_SEG5                        0
+
+#define DF_BASE__INST1_SEG0                        0
+#define DF_BASE__INST1_SEG1                        0
+#define DF_BASE__INST1_SEG2                        0
+#define DF_BASE__INST1_SEG3                        0
+#define DF_BASE__INST1_SEG4                        0
+#define DF_BASE__INST1_SEG5                        0
+
+#define DF_BASE__INST2_SEG0                        0
+#define DF_BASE__INST2_SEG1                        0
+#define DF_BASE__INST2_SEG2                        0
+#define DF_BASE__INST2_SEG3                        0
+#define DF_BASE__INST2_SEG4                        0
+#define DF_BASE__INST2_SEG5                        0
+
+#define DF_BASE__INST3_SEG0                        0
+#define DF_BASE__INST3_SEG1                        0
+#define DF_BASE__INST3_SEG2                        0
+#define DF_BASE__INST3_SEG3                        0
+#define DF_BASE__INST3_SEG4                        0
+#define DF_BASE__INST3_SEG5                        0
+
+#define DF_BASE__INST4_SEG0                        0
+#define DF_BASE__INST4_SEG1                        0
+#define DF_BASE__INST4_SEG2                        0
+#define DF_BASE__INST4_SEG3                        0
+#define DF_BASE__INST4_SEG4                        0
+#define DF_BASE__INST4_SEG5                        0
+
+#define DF_BASE__INST5_SEG0                        0
+#define DF_BASE__INST5_SEG1                        0
+#define DF_BASE__INST5_SEG2                        0
+#define DF_BASE__INST5_SEG3                        0
+#define DF_BASE__INST5_SEG4                        0
+#define DF_BASE__INST5_SEG5                        0
+
+#define FUSE_BASE__INST0_SEG0                      0x00017400
+#define FUSE_BASE__INST0_SEG1                      0
+#define FUSE_BASE__INST0_SEG2                      0
+#define FUSE_BASE__INST0_SEG3                      0
+#define FUSE_BASE__INST0_SEG4                      0
+#define FUSE_BASE__INST0_SEG5                      0
+
+#define FUSE_BASE__INST1_SEG0                      0
+#define FUSE_BASE__INST1_SEG1                      0
+#define FUSE_BASE__INST1_SEG2                      0
+#define FUSE_BASE__INST1_SEG3                      0
+#define FUSE_BASE__INST1_SEG4                      0
+#define FUSE_BASE__INST1_SEG5                      0
+
+#define FUSE_BASE__INST2_SEG0                      0
+#define FUSE_BASE__INST2_SEG1                      0
+#define FUSE_BASE__INST2_SEG2                      0
+#define FUSE_BASE__INST2_SEG3                      0
+#define FUSE_BASE__INST2_SEG4                      0
+#define FUSE_BASE__INST2_SEG5                      0
+
+#define FUSE_BASE__INST3_SEG0                      0
+#define FUSE_BASE__INST3_SEG1                      0
+#define FUSE_BASE__INST3_SEG2                      0
+#define FUSE_BASE__INST3_SEG3                      0
+#define FUSE_BASE__INST3_SEG4                      0
+#define FUSE_BASE__INST3_SEG5                      0
+
+#define FUSE_BASE__INST4_SEG0                      0
+#define FUSE_BASE__INST4_SEG1                      0
+#define FUSE_BASE__INST4_SEG2                      0
+#define FUSE_BASE__INST4_SEG3                      0
+#define FUSE_BASE__INST4_SEG4                      0
+#define FUSE_BASE__INST4_SEG5                      0
+
+#define FUSE_BASE__INST5_SEG0                      0
+#define FUSE_BASE__INST5_SEG1                      0
+#define FUSE_BASE__INST5_SEG2                      0
+#define FUSE_BASE__INST5_SEG3                      0
+#define FUSE_BASE__INST5_SEG4                      0
+#define FUSE_BASE__INST5_SEG5                      0
+
+#define GC_BASE__INST0_SEG0                        0x00002000
+#define GC_BASE__INST0_SEG1                        0x0000A000
+#define GC_BASE__INST0_SEG2                        0
+#define GC_BASE__INST0_SEG3                        0
+#define GC_BASE__INST0_SEG4                        0
+#define GC_BASE__INST0_SEG5                        0
+
+#define GC_BASE__INST1_SEG0                        0
+#define GC_BASE__INST1_SEG1                        0
+#define GC_BASE__INST1_SEG2                        0
+#define GC_BASE__INST1_SEG3                        0
+#define GC_BASE__INST1_SEG4                        0
+#define GC_BASE__INST1_SEG5                        0
+
+#define GC_BASE__INST2_SEG0                        0
+#define GC_BASE__INST2_SEG1                        0
+#define GC_BASE__INST2_SEG2                        0
+#define GC_BASE__INST2_SEG3                        0
+#define GC_BASE__INST2_SEG4                        0
+#define GC_BASE__INST2_SEG5                        0
+
+#define GC_BASE__INST3_SEG0                        0
+#define GC_BASE__INST3_SEG1                        0
+#define GC_BASE__INST3_SEG2                        0
+#define GC_BASE__INST3_SEG3                        0
+#define GC_BASE__INST3_SEG4                        0
+#define GC_BASE__INST3_SEG5                        0
+
+#define GC_BASE__INST4_SEG0                        0
+#define GC_BASE__INST4_SEG1                        0
+#define GC_BASE__INST4_SEG2                        0
+#define GC_BASE__INST4_SEG3                        0
+#define GC_BASE__INST4_SEG4                        0
+#define GC_BASE__INST4_SEG5                        0
+
+#define GC_BASE__INST5_SEG0                        0
+#define GC_BASE__INST5_SEG1                        0
+#define GC_BASE__INST5_SEG2                        0
+#define GC_BASE__INST5_SEG3                        0
+#define GC_BASE__INST5_SEG4                        0
+#define GC_BASE__INST5_SEG5                        0
+
+#define HDP_BASE__INST0_SEG0                       0x00000F20
+#define HDP_BASE__INST0_SEG1                       0
+#define HDP_BASE__INST0_SEG2                       0
+#define HDP_BASE__INST0_SEG3                       0
+#define HDP_BASE__INST0_SEG4                       0
+#define HDP_BASE__INST0_SEG5                       0
+
+#define HDP_BASE__INST1_SEG0                       0
+#define HDP_BASE__INST1_SEG1                       0
+#define HDP_BASE__INST1_SEG2                       0
+#define HDP_BASE__INST1_SEG3                       0
+#define HDP_BASE__INST1_SEG4                       0
+#define HDP_BASE__INST1_SEG5                       0
+
+#define HDP_BASE__INST2_SEG0                       0
+#define HDP_BASE__INST2_SEG1                       0
+#define HDP_BASE__INST2_SEG2                       0
+#define HDP_BASE__INST2_SEG3                       0
+#define HDP_BASE__INST2_SEG4                       0
+#define HDP_BASE__INST2_SEG5                       0
+
+#define HDP_BASE__INST3_SEG0                       0
+#define HDP_BASE__INST3_SEG1                       0
+#define HDP_BASE__INST3_SEG2                       0
+#define HDP_BASE__INST3_SEG3                       0
+#define HDP_BASE__INST3_SEG4                       0
+#define HDP_BASE__INST3_SEG5                       0
+
+#define HDP_BASE__INST4_SEG0                       0
+#define HDP_BASE__INST4_SEG1                       0
+#define HDP_BASE__INST4_SEG2                       0
+#define HDP_BASE__INST4_SEG3                       0
+#define HDP_BASE__INST4_SEG4                       0
+#define HDP_BASE__INST4_SEG5                       0
+
+#define HDP_BASE__INST5_SEG0                       0
+#define HDP_BASE__INST5_SEG1                       0
+#define HDP_BASE__INST5_SEG2                       0
+#define HDP_BASE__INST5_SEG3                       0
+#define HDP_BASE__INST5_SEG4                       0
+#define HDP_BASE__INST5_SEG5                       0
+
+#define MMHUB_BASE__INST0_SEG0                     0x0001A000
+#define MMHUB_BASE__INST0_SEG1                     0
+#define MMHUB_BASE__INST0_SEG2                     0
+#define MMHUB_BASE__INST0_SEG3                     0
+#define MMHUB_BASE__INST0_SEG4                     0
+#define MMHUB_BASE__INST0_SEG5                     0
+
+#define MMHUB_BASE__INST1_SEG0                     0
+#define MMHUB_BASE__INST1_SEG1                     0
+#define MMHUB_BASE__INST1_SEG2                     0
+#define MMHUB_BASE__INST1_SEG3                     0
+#define MMHUB_BASE__INST1_SEG4                     0
+#define MMHUB_BASE__INST1_SEG5                     0
+
+#define MMHUB_BASE__INST2_SEG0                     0
+#define MMHUB_BASE__INST2_SEG1                     0
+#define MMHUB_BASE__INST2_SEG2                     0
+#define MMHUB_BASE__INST2_SEG3                     0
+#define MMHUB_BASE__INST2_SEG4                     0
+#define MMHUB_BASE__INST2_SEG5                     0
+
+#define MMHUB_BASE__INST3_SEG0                     0
+#define MMHUB_BASE__INST3_SEG1                     0
+#define MMHUB_BASE__INST3_SEG2                     0
+#define MMHUB_BASE__INST3_SEG3                     0
+#define MMHUB_BASE__INST3_SEG4                     0
+#define MMHUB_BASE__INST3_SEG5                     0
+
+#define MMHUB_BASE__INST4_SEG0                     0
+#define MMHUB_BASE__INST4_SEG1                     0
+#define MMHUB_BASE__INST4_SEG2                     0
+#define MMHUB_BASE__INST4_SEG3                     0
+#define MMHUB_BASE__INST4_SEG4                     0
+#define MMHUB_BASE__INST4_SEG5                     0
+
+#define MMHUB_BASE__INST5_SEG0                     0
+#define MMHUB_BASE__INST5_SEG1                     0
+#define MMHUB_BASE__INST5_SEG2                     0
+#define MMHUB_BASE__INST5_SEG3                     0
+#define MMHUB_BASE__INST5_SEG4                     0
+#define MMHUB_BASE__INST5_SEG5                     0
+
+#define MP0_BASE__INST0_SEG0                       0x00016000
+#define MP0_BASE__INST0_SEG1                       0
+#define MP0_BASE__INST0_SEG2                       0
+#define MP0_BASE__INST0_SEG3                       0
+#define MP0_BASE__INST0_SEG4                       0
+#define MP0_BASE__INST0_SEG5                       0
+
+#define MP0_BASE__INST1_SEG0                       0
+#define MP0_BASE__INST1_SEG1                       0
+#define MP0_BASE__INST1_SEG2                       0
+#define MP0_BASE__INST1_SEG3                       0
+#define MP0_BASE__INST1_SEG4                       0
+#define MP0_BASE__INST1_SEG5                       0
+
+#define MP0_BASE__INST2_SEG0                       0
+#define MP0_BASE__INST2_SEG1                       0
+#define MP0_BASE__INST2_SEG2                       0
+#define MP0_BASE__INST2_SEG3                       0
+#define MP0_BASE__INST2_SEG4                       0
+#define MP0_BASE__INST2_SEG5                       0
+
+#define MP0_BASE__INST3_SEG0                       0
+#define MP0_BASE__INST3_SEG1                       0
+#define MP0_BASE__INST3_SEG2                       0
+#define MP0_BASE__INST3_SEG3                       0
+#define MP0_BASE__INST3_SEG4                       0
+#define MP0_BASE__INST3_SEG5                       0
+
+#define MP0_BASE__INST4_SEG0                       0
+#define MP0_BASE__INST4_SEG1                       0
+#define MP0_BASE__INST4_SEG2                       0
+#define MP0_BASE__INST4_SEG3                       0
+#define MP0_BASE__INST4_SEG4                       0
+#define MP0_BASE__INST4_SEG5                       0
+
+#define MP0_BASE__INST5_SEG0                       0
+#define MP0_BASE__INST5_SEG1                       0
+#define MP0_BASE__INST5_SEG2                       0
+#define MP0_BASE__INST5_SEG3                       0
+#define MP0_BASE__INST5_SEG4                       0
+#define MP0_BASE__INST5_SEG5                       0
+
+#define MP1_BASE__INST0_SEG0                       0x00016000
+#define MP1_BASE__INST0_SEG1                       0
+#define MP1_BASE__INST0_SEG2                       0
+#define MP1_BASE__INST0_SEG3                       0
+#define MP1_BASE__INST0_SEG4                       0
+#define MP1_BASE__INST0_SEG5                       0
+
+#define MP1_BASE__INST1_SEG0                       0
+#define MP1_BASE__INST1_SEG1                       0
+#define MP1_BASE__INST1_SEG2                       0
+#define MP1_BASE__INST1_SEG3                       0
+#define MP1_BASE__INST1_SEG4                       0
+#define MP1_BASE__INST1_SEG5                       0
+
+#define MP1_BASE__INST2_SEG0                       0
+#define MP1_BASE__INST2_SEG1                       0
+#define MP1_BASE__INST2_SEG2                       0
+#define MP1_BASE__INST2_SEG3                       0
+#define MP1_BASE__INST2_SEG4                       0
+#define MP1_BASE__INST2_SEG5                       0
+
+#define MP1_BASE__INST3_SEG0                       0
+#define MP1_BASE__INST3_SEG1                       0
+#define MP1_BASE__INST3_SEG2                       0
+#define MP1_BASE__INST3_SEG3                       0
+#define MP1_BASE__INST3_SEG4                       0
+#define MP1_BASE__INST3_SEG5                       0
+
+#define MP1_BASE__INST4_SEG0                       0
+#define MP1_BASE__INST4_SEG1                       0
+#define MP1_BASE__INST4_SEG2                       0
+#define MP1_BASE__INST4_SEG3                       0
+#define MP1_BASE__INST4_SEG4                       0
+#define MP1_BASE__INST4_SEG5                       0
+
+#define MP1_BASE__INST5_SEG0                       0
+#define MP1_BASE__INST5_SEG1                       0
+#define MP1_BASE__INST5_SEG2                       0
+#define MP1_BASE__INST5_SEG3                       0
+#define MP1_BASE__INST5_SEG4                       0
+#define MP1_BASE__INST5_SEG5                       0
+
+#define NBIO_BASE__INST0_SEG0                      0x00000000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+#define NBIO_BASE__INST0_SEG2                      0x00000D20
+#define NBIO_BASE__INST0_SEG3                      0x00010400
+#define NBIO_BASE__INST0_SEG4                      0
+#define NBIO_BASE__INST0_SEG5                      0
+
+#define NBIO_BASE__INST1_SEG0                      0
+#define NBIO_BASE__INST1_SEG1                      0
+#define NBIO_BASE__INST1_SEG2                      0
+#define NBIO_BASE__INST1_SEG3                      0
+#define NBIO_BASE__INST1_SEG4                      0
+#define NBIO_BASE__INST1_SEG5                      0
+
+#define NBIO_BASE__INST2_SEG0                      0
+#define NBIO_BASE__INST2_SEG1                      0
+#define NBIO_BASE__INST2_SEG2                      0
+#define NBIO_BASE__INST2_SEG3                      0
+#define NBIO_BASE__INST2_SEG4                      0
+#define NBIO_BASE__INST2_SEG5                      0
+
+#define NBIO_BASE__INST3_SEG0                      0
+#define NBIO_BASE__INST3_SEG1                      0
+#define NBIO_BASE__INST3_SEG2                      0
+#define NBIO_BASE__INST3_SEG3                      0
+#define NBIO_BASE__INST3_SEG4                      0
+#define NBIO_BASE__INST3_SEG5                      0
+
+#define NBIO_BASE__INST4_SEG0                      0
+#define NBIO_BASE__INST4_SEG1                      0
+#define NBIO_BASE__INST4_SEG2                      0
+#define NBIO_BASE__INST4_SEG3                      0
+#define NBIO_BASE__INST4_SEG4                      0
+#define NBIO_BASE__INST4_SEG5                      0
+
+#define NBIO_BASE__INST5_SEG0                      0
+#define NBIO_BASE__INST5_SEG1                      0
+#define NBIO_BASE__INST5_SEG2                      0
+#define NBIO_BASE__INST5_SEG3                      0
+#define NBIO_BASE__INST5_SEG4                      0
+#define NBIO_BASE__INST5_SEG5                      0
+
+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
+#define OSSSYS_BASE__INST0_SEG1                    0
+#define OSSSYS_BASE__INST0_SEG2                    0
+#define OSSSYS_BASE__INST0_SEG3                    0
+#define OSSSYS_BASE__INST0_SEG4                    0
+#define OSSSYS_BASE__INST0_SEG5                    0
+
+#define OSSSYS_BASE__INST1_SEG0                    0
+#define OSSSYS_BASE__INST1_SEG1                    0
+#define OSSSYS_BASE__INST1_SEG2                    0
+#define OSSSYS_BASE__INST1_SEG3                    0
+#define OSSSYS_BASE__INST1_SEG4                    0
+#define OSSSYS_BASE__INST1_SEG5                    0
+
+#define OSSSYS_BASE__INST2_SEG0                    0
+#define OSSSYS_BASE__INST2_SEG1                    0
+#define OSSSYS_BASE__INST2_SEG2                    0
+#define OSSSYS_BASE__INST2_SEG3                    0
+#define OSSSYS_BASE__INST2_SEG4                    0
+#define OSSSYS_BASE__INST2_SEG5                    0
+
+#define OSSSYS_BASE__INST3_SEG0                    0
+#define OSSSYS_BASE__INST3_SEG1                    0
+#define OSSSYS_BASE__INST3_SEG2                    0
+#define OSSSYS_BASE__INST3_SEG3                    0
+#define OSSSYS_BASE__INST3_SEG4                    0
+#define OSSSYS_BASE__INST3_SEG5                    0
+
+#define OSSSYS_BASE__INST4_SEG0                    0
+#define OSSSYS_BASE__INST4_SEG1                    0
+#define OSSSYS_BASE__INST4_SEG2                    0
+#define OSSSYS_BASE__INST4_SEG3                    0
+#define OSSSYS_BASE__INST4_SEG4                    0
+#define OSSSYS_BASE__INST4_SEG5                    0
+
+#define OSSSYS_BASE__INST5_SEG0                    0
+#define OSSSYS_BASE__INST5_SEG1                    0
+#define OSSSYS_BASE__INST5_SEG2                    0
+#define OSSSYS_BASE__INST5_SEG3                    0
+#define OSSSYS_BASE__INST5_SEG4                    0
+#define OSSSYS_BASE__INST5_SEG5                    0
+
+#define SDMA0_BASE__INST0_SEG0                     0x00001260
+#define SDMA0_BASE__INST0_SEG1                     0
+#define SDMA0_BASE__INST0_SEG2                     0
+#define SDMA0_BASE__INST0_SEG3                     0
+#define SDMA0_BASE__INST0_SEG4                     0
+#define SDMA0_BASE__INST0_SEG5                     0
+
+#define SDMA0_BASE__INST1_SEG0                     0
+#define SDMA0_BASE__INST1_SEG1                     0
+#define SDMA0_BASE__INST1_SEG2                     0
+#define SDMA0_BASE__INST1_SEG3                     0
+#define SDMA0_BASE__INST1_SEG4                     0
+#define SDMA0_BASE__INST1_SEG5                     0
+
+#define SDMA0_BASE__INST2_SEG0                     0
+#define SDMA0_BASE__INST2_SEG1                     0
+#define SDMA0_BASE__INST2_SEG2                     0
+#define SDMA0_BASE__INST2_SEG3                     0
+#define SDMA0_BASE__INST2_SEG4                     0
+#define SDMA0_BASE__INST2_SEG5                     0
+
+#define SDMA0_BASE__INST3_SEG0                     0
+#define SDMA0_BASE__INST3_SEG1                     0
+#define SDMA0_BASE__INST3_SEG2                     0
+#define SDMA0_BASE__INST3_SEG3                     0
+#define SDMA0_BASE__INST3_SEG4                     0
+#define SDMA0_BASE__INST3_SEG5                     0
+
+#define SDMA0_BASE__INST4_SEG0                     0
+#define SDMA0_BASE__INST4_SEG1                     0
+#define SDMA0_BASE__INST4_SEG2                     0
+#define SDMA0_BASE__INST4_SEG3                     0
+#define SDMA0_BASE__INST4_SEG4                     0
+#define SDMA0_BASE__INST4_SEG5                     0
+
+#define SDMA0_BASE__INST5_SEG0                     0
+#define SDMA0_BASE__INST5_SEG1                     0
+#define SDMA0_BASE__INST5_SEG2                     0
+#define SDMA0_BASE__INST5_SEG3                     0
+#define SDMA0_BASE__INST5_SEG4                     0
+#define SDMA0_BASE__INST5_SEG5                     0
+
+#define SDMA1_BASE__INST0_SEG0                     0x00001860
+#define SDMA1_BASE__INST0_SEG1                     0
+#define SDMA1_BASE__INST0_SEG2                     0
+#define SDMA1_BASE__INST0_SEG3                     0
+#define SDMA1_BASE__INST0_SEG4                     0
+#define SDMA1_BASE__INST0_SEG5                     0
+
+#define SDMA1_BASE__INST1_SEG0                     0
+#define SDMA1_BASE__INST1_SEG1                     0
+#define SDMA1_BASE__INST1_SEG2                     0
+#define SDMA1_BASE__INST1_SEG3                     0
+#define SDMA1_BASE__INST1_SEG4                     0
+#define SDMA1_BASE__INST1_SEG5                     0
+
+#define SDMA1_BASE__INST2_SEG0                     0
+#define SDMA1_BASE__INST2_SEG1                     0
+#define SDMA1_BASE__INST2_SEG2                     0
+#define SDMA1_BASE__INST2_SEG3                     0
+#define SDMA1_BASE__INST2_SEG4                     0
+#define SDMA1_BASE__INST2_SEG5                     0
+
+#define SDMA1_BASE__INST3_SEG0                     0
+#define SDMA1_BASE__INST3_SEG1                     0
+#define SDMA1_BASE__INST3_SEG2                     0
+#define SDMA1_BASE__INST3_SEG3                     0
+#define SDMA1_BASE__INST3_SEG4                     0
+#define SDMA1_BASE__INST3_SEG5                     0
+
+#define SDMA1_BASE__INST4_SEG0                     0
+#define SDMA1_BASE__INST4_SEG1                     0
+#define SDMA1_BASE__INST4_SEG2                     0
+#define SDMA1_BASE__INST4_SEG3                     0
+#define SDMA1_BASE__INST4_SEG4                     0
+#define SDMA1_BASE__INST4_SEG5                     0
+
+#define SDMA1_BASE__INST5_SEG0                     0
+#define SDMA1_BASE__INST5_SEG1                     0
+#define SDMA1_BASE__INST5_SEG2                     0
+#define SDMA1_BASE__INST5_SEG3                     0
+#define SDMA1_BASE__INST5_SEG4                     0
+#define SDMA1_BASE__INST5_SEG5                     0
+
+#define SMUIO_BASE__INST0_SEG0                     0x00016800
+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
+#define SMUIO_BASE__INST0_SEG2                     0
+#define SMUIO_BASE__INST0_SEG3                     0
+#define SMUIO_BASE__INST0_SEG4                     0
+#define SMUIO_BASE__INST0_SEG5                     0
+
+#define SMUIO_BASE__INST1_SEG0                     0
+#define SMUIO_BASE__INST1_SEG1                     0
+#define SMUIO_BASE__INST1_SEG2                     0
+#define SMUIO_BASE__INST1_SEG3                     0
+#define SMUIO_BASE__INST1_SEG4                     0
+#define SMUIO_BASE__INST1_SEG5                     0
+
+#define SMUIO_BASE__INST2_SEG0                     0
+#define SMUIO_BASE__INST2_SEG1                     0
+#define SMUIO_BASE__INST2_SEG2                     0
+#define SMUIO_BASE__INST2_SEG3                     0
+#define SMUIO_BASE__INST2_SEG4                     0
+#define SMUIO_BASE__INST2_SEG5                     0
+
+#define SMUIO_BASE__INST3_SEG0                     0
+#define SMUIO_BASE__INST3_SEG1                     0
+#define SMUIO_BASE__INST3_SEG2                     0
+#define SMUIO_BASE__INST3_SEG3                     0
+#define SMUIO_BASE__INST3_SEG4                     0
+#define SMUIO_BASE__INST3_SEG5                     0
+
+#define SMUIO_BASE__INST4_SEG0                     0
+#define SMUIO_BASE__INST4_SEG1                     0
+#define SMUIO_BASE__INST4_SEG2                     0
+#define SMUIO_BASE__INST4_SEG3                     0
+#define SMUIO_BASE__INST4_SEG4                     0
+#define SMUIO_BASE__INST4_SEG5                     0
+
+#define SMUIO_BASE__INST5_SEG0                     0
+#define SMUIO_BASE__INST5_SEG1                     0
+#define SMUIO_BASE__INST5_SEG2                     0
+#define SMUIO_BASE__INST5_SEG3                     0
+#define SMUIO_BASE__INST5_SEG4                     0
+#define SMUIO_BASE__INST5_SEG5                     0
+
+#define THM_BASE__INST0_SEG0                       0x00016600
+#define THM_BASE__INST0_SEG1                       0
+#define THM_BASE__INST0_SEG2                       0
+#define THM_BASE__INST0_SEG3                       0
+#define THM_BASE__INST0_SEG4                       0
+#define THM_BASE__INST0_SEG5                       0
+
+#define THM_BASE__INST1_SEG0                       0
+#define THM_BASE__INST1_SEG1                       0
+#define THM_BASE__INST1_SEG2                       0
+#define THM_BASE__INST1_SEG3                       0
+#define THM_BASE__INST1_SEG4                       0
+#define THM_BASE__INST1_SEG5                       0
+
+#define THM_BASE__INST2_SEG0                       0
+#define THM_BASE__INST2_SEG1                       0
+#define THM_BASE__INST2_SEG2                       0
+#define THM_BASE__INST2_SEG3                       0
+#define THM_BASE__INST2_SEG4                       0
+#define THM_BASE__INST2_SEG5                       0
+
+#define THM_BASE__INST3_SEG0                       0
+#define THM_BASE__INST3_SEG1                       0
+#define THM_BASE__INST3_SEG2                       0
+#define THM_BASE__INST3_SEG3                       0
+#define THM_BASE__INST3_SEG4                       0
+#define THM_BASE__INST3_SEG5                       0
+
+#define THM_BASE__INST4_SEG0                       0
+#define THM_BASE__INST4_SEG1                       0
+#define THM_BASE__INST4_SEG2                       0
+#define THM_BASE__INST4_SEG3                       0
+#define THM_BASE__INST4_SEG4                       0
+#define THM_BASE__INST4_SEG5                       0
+
+#define THM_BASE__INST5_SEG0                       0
+#define THM_BASE__INST5_SEG1                       0
+#define THM_BASE__INST5_SEG2                       0
+#define THM_BASE__INST5_SEG3                       0
+#define THM_BASE__INST5_SEG4                       0
+#define THM_BASE__INST5_SEG5                       0
+
+#define UMC_BASE__INST0_SEG0                       0x00014000
+#define UMC_BASE__INST0_SEG1                       0
+#define UMC_BASE__INST0_SEG2                       0
+#define UMC_BASE__INST0_SEG3                       0
+#define UMC_BASE__INST0_SEG4                       0
+#define UMC_BASE__INST0_SEG5                       0
+
+#define UMC_BASE__INST1_SEG0                       0
+#define UMC_BASE__INST1_SEG1                       0
+#define UMC_BASE__INST1_SEG2                       0
+#define UMC_BASE__INST1_SEG3                       0
+#define UMC_BASE__INST1_SEG4                       0
+#define UMC_BASE__INST1_SEG5                       0
+
+#define UMC_BASE__INST2_SEG0                       0
+#define UMC_BASE__INST2_SEG1                       0
+#define UMC_BASE__INST2_SEG2                       0
+#define UMC_BASE__INST2_SEG3                       0
+#define UMC_BASE__INST2_SEG4                       0
+#define UMC_BASE__INST2_SEG5                       0
+
+#define UMC_BASE__INST3_SEG0                       0
+#define UMC_BASE__INST3_SEG1                       0
+#define UMC_BASE__INST3_SEG2                       0
+#define UMC_BASE__INST3_SEG3                       0
+#define UMC_BASE__INST3_SEG4                       0
+#define UMC_BASE__INST3_SEG5                       0
+
+#define UMC_BASE__INST4_SEG0                       0
+#define UMC_BASE__INST4_SEG1                       0
+#define UMC_BASE__INST4_SEG2                       0
+#define UMC_BASE__INST4_SEG3                       0
+#define UMC_BASE__INST4_SEG4                       0
+#define UMC_BASE__INST4_SEG5                       0
+
+#define UMC_BASE__INST5_SEG0                       0
+#define UMC_BASE__INST5_SEG1                       0
+#define UMC_BASE__INST5_SEG2                       0
+#define UMC_BASE__INST5_SEG3                       0
+#define UMC_BASE__INST5_SEG4                       0
+#define UMC_BASE__INST5_SEG5                       0
+
+#define UVD_BASE__INST0_SEG0                       0x00007800
+#define UVD_BASE__INST0_SEG1                       0x00007E00
+#define UVD_BASE__INST0_SEG2                       0
+#define UVD_BASE__INST0_SEG3                       0
+#define UVD_BASE__INST0_SEG4                       0
+#define UVD_BASE__INST0_SEG5                       0
+
+#define UVD_BASE__INST1_SEG0                       0
+#define UVD_BASE__INST1_SEG1                       0x00009000
+#define UVD_BASE__INST1_SEG2                       0
+#define UVD_BASE__INST1_SEG3                       0
+#define UVD_BASE__INST1_SEG4                       0
+#define UVD_BASE__INST1_SEG5                       0
+
+#define UVD_BASE__INST2_SEG0                       0
+#define UVD_BASE__INST2_SEG1                       0
+#define UVD_BASE__INST2_SEG2                       0
+#define UVD_BASE__INST2_SEG3                       0
+#define UVD_BASE__INST2_SEG4                       0
+#define UVD_BASE__INST2_SEG5                       0
+
+#define UVD_BASE__INST3_SEG0                       0
+#define UVD_BASE__INST3_SEG1                       0
+#define UVD_BASE__INST3_SEG2                       0
+#define UVD_BASE__INST3_SEG3                       0
+#define UVD_BASE__INST3_SEG4                       0
+#define UVD_BASE__INST3_SEG5                       0
+
+#define UVD_BASE__INST4_SEG0                       0
+#define UVD_BASE__INST4_SEG1                       0
+#define UVD_BASE__INST4_SEG2                       0
+#define UVD_BASE__INST4_SEG3                       0
+#define UVD_BASE__INST4_SEG4                       0
+#define UVD_BASE__INST4_SEG5                       0
+
+#define UVD_BASE__INST5_SEG0                       0
+#define UVD_BASE__INST5_SEG1                       0
+#define UVD_BASE__INST5_SEG2                       0
+#define UVD_BASE__INST5_SEG3                       0
+#define UVD_BASE__INST5_SEG4                       0
+#define UVD_BASE__INST5_SEG5                       0
+
+#define VCE_BASE__INST0_SEG0                       0x00008800
+#define VCE_BASE__INST0_SEG1                       0
+#define VCE_BASE__INST0_SEG2                       0
+#define VCE_BASE__INST0_SEG3                       0
+#define VCE_BASE__INST0_SEG4                       0
+#define VCE_BASE__INST0_SEG5                       0
+
+#define VCE_BASE__INST1_SEG0                       0
+#define VCE_BASE__INST1_SEG1                       0
+#define VCE_BASE__INST1_SEG2                       0
+#define VCE_BASE__INST1_SEG3                       0
+#define VCE_BASE__INST1_SEG4                       0
+#define VCE_BASE__INST1_SEG5                       0
+
+#define VCE_BASE__INST2_SEG0                       0
+#define VCE_BASE__INST2_SEG1                       0
+#define VCE_BASE__INST2_SEG2                       0
+#define VCE_BASE__INST2_SEG3                       0
+#define VCE_BASE__INST2_SEG4                       0
+#define VCE_BASE__INST2_SEG5                       0
+
+#define VCE_BASE__INST3_SEG0                       0
+#define VCE_BASE__INST3_SEG1                       0
+#define VCE_BASE__INST3_SEG2                       0
+#define VCE_BASE__INST3_SEG3                       0
+#define VCE_BASE__INST3_SEG4                       0
+#define VCE_BASE__INST3_SEG5                       0
+
+#define VCE_BASE__INST4_SEG0                       0
+#define VCE_BASE__INST4_SEG1                       0
+#define VCE_BASE__INST4_SEG2                       0
+#define VCE_BASE__INST4_SEG3                       0
+#define VCE_BASE__INST4_SEG4                       0
+#define VCE_BASE__INST4_SEG5                       0
+
+#define VCE_BASE__INST5_SEG0                       0
+#define VCE_BASE__INST5_SEG1                       0
+#define VCE_BASE__INST5_SEG2                       0
+#define VCE_BASE__INST5_SEG3                       0
+#define VCE_BASE__INST5_SEG4                       0
+#define VCE_BASE__INST5_SEG5                       0
+
+#define XDMA_BASE__INST0_SEG0                      0x00003400
+#define XDMA_BASE__INST0_SEG1                      0
+#define XDMA_BASE__INST0_SEG2                      0
+#define XDMA_BASE__INST0_SEG3                      0
+#define XDMA_BASE__INST0_SEG4                      0
+#define XDMA_BASE__INST0_SEG5                      0
+
+#define XDMA_BASE__INST1_SEG0                      0
+#define XDMA_BASE__INST1_SEG1                      0
+#define XDMA_BASE__INST1_SEG2                      0
+#define XDMA_BASE__INST1_SEG3                      0
+#define XDMA_BASE__INST1_SEG4                      0
+#define XDMA_BASE__INST1_SEG5                      0
+
+#define XDMA_BASE__INST2_SEG0                      0
+#define XDMA_BASE__INST2_SEG1                      0
+#define XDMA_BASE__INST2_SEG2                      0
+#define XDMA_BASE__INST2_SEG3                      0
+#define XDMA_BASE__INST2_SEG4                      0
+#define XDMA_BASE__INST2_SEG5                      0
+
+#define XDMA_BASE__INST3_SEG0                      0
+#define XDMA_BASE__INST3_SEG1                      0
+#define XDMA_BASE__INST3_SEG2                      0
+#define XDMA_BASE__INST3_SEG3                      0
+#define XDMA_BASE__INST3_SEG4                      0
+#define XDMA_BASE__INST3_SEG5                      0
+
+#define XDMA_BASE__INST4_SEG0                      0
+#define XDMA_BASE__INST4_SEG1                      0
+#define XDMA_BASE__INST4_SEG2                      0
+#define XDMA_BASE__INST4_SEG3                      0
+#define XDMA_BASE__INST4_SEG4                      0
+#define XDMA_BASE__INST4_SEG5                      0
+
+#define XDMA_BASE__INST5_SEG0                      0
+#define XDMA_BASE__INST5_SEG1                      0
+#define XDMA_BASE__INST5_SEG2                      0
+#define XDMA_BASE__INST5_SEG3                      0
+#define XDMA_BASE__INST5_SEG4                      0
+#define XDMA_BASE__INST5_SEG5                      0
+
+#define RSMU_BASE__INST0_SEG0                      0x00012000
+#define RSMU_BASE__INST0_SEG1                      0
+#define RSMU_BASE__INST0_SEG2                      0
+#define RSMU_BASE__INST0_SEG3                      0
+#define RSMU_BASE__INST0_SEG4                      0
+#define RSMU_BASE__INST0_SEG5                      0
+
+#define RSMU_BASE__INST1_SEG0                      0
+#define RSMU_BASE__INST1_SEG1                      0
+#define RSMU_BASE__INST1_SEG2                      0
+#define RSMU_BASE__INST1_SEG3                      0
+#define RSMU_BASE__INST1_SEG4                      0
+#define RSMU_BASE__INST1_SEG5                      0
+
+#define RSMU_BASE__INST2_SEG0                      0
+#define RSMU_BASE__INST2_SEG1                      0
+#define RSMU_BASE__INST2_SEG2                      0
+#define RSMU_BASE__INST2_SEG3                      0
+#define RSMU_BASE__INST2_SEG4                      0
+#define RSMU_BASE__INST2_SEG5                      0
+
+#define RSMU_BASE__INST3_SEG0                      0
+#define RSMU_BASE__INST3_SEG1                      0
+#define RSMU_BASE__INST3_SEG2                      0
+#define RSMU_BASE__INST3_SEG3                      0
+#define RSMU_BASE__INST3_SEG4                      0
+#define RSMU_BASE__INST3_SEG5                      0
+
+#define RSMU_BASE__INST4_SEG0                      0
+#define RSMU_BASE__INST4_SEG1                      0
+#define RSMU_BASE__INST4_SEG2                      0
+#define RSMU_BASE__INST4_SEG3                      0
+#define RSMU_BASE__INST4_SEG4                      0
+#define RSMU_BASE__INST4_SEG5                      0
+
+#define RSMU_BASE__INST5_SEG0                      0
+#define RSMU_BASE__INST5_SEG1                      0
+#define RSMU_BASE__INST5_SEG2                      0
+#define RSMU_BASE__INST5_SEG3                      0
+#define RSMU_BASE__INST5_SEG4                      0
+#define RSMU_BASE__INST5_SEG5                      0
+
+#endif
+
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index e411012b3dcb..a0bb921fac22 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -132,6 +132,15 @@ int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
         return 0;
 }
 
+int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr)
+{
+        PHM_FUNC_CHECK(hwmgr);
+
+        if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL)
+                return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr);
+        return 0;
+}
+
 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 {
         PHM_FUNC_CHECK(hwmgr);
@@ -161,6 +170,16 @@ int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
+int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr)
+{
+        PHM_FUNC_CHECK(hwmgr);
+
+        if (NULL != hwmgr->hwmgr_func->pre_display_config_changed)
+                hwmgr->hwmgr_func->pre_display_config_changed(hwmgr);
+
+        return 0;
+
+}
 
 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 71b42331f185..e63bc47dc715 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -151,6 +151,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
                 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
                 switch (hwmgr->chip_id) {
                 case CHIP_VEGA10:
+                case CHIP_VEGA20:
                         hwmgr->smumgr_funcs = &vega10_smu_funcs;
                         vega10_hwmgr_init(hwmgr);
                         break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
index 308bff2b5d1d..0af13c154328 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c
@@ -265,6 +265,15 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip,
         if (skip)
                 return 0;
 
+        if (!hwmgr->ps)
+                /*
+                 * for vega12/vega20 which does not support power state manager
+                 * DAL clock limits should also be honoured
+                 */
+                phm_apply_clock_adjust_rules(hwmgr);
+
+        phm_pre_display_configuration_changed(hwmgr);
+
         phm_display_configuration_changed(hwmgr);
 
         if (hwmgr->ps)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index cf99c5eaf080..7047e29755c3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -320,7 +320,7 @@ int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
                                         pp_atomctrl_memory_clock_param_ai *mpll_param)
 {
         struct amdgpu_device *adev = hwmgr->adev;
-        COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {0};
+        COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {{0}, 0, 0};
         int result;
 
         mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
@@ -1104,10 +1104,8 @@ int atomctrl_get_voltage_evv_on_sclk(
                         GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
                         (uint32_t *)&get_voltage_info_param_space);
 
-        if (0 != result)
-                return result;
-
-        *voltage = le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
+        *voltage = result ? 0 :
+                        le16_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 *)
                                 (&get_voltage_info_param_space))->usVoltageLevel);
 
         return result;
@@ -1312,8 +1310,7 @@ int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
         result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
                         GetIndexIntoMasterTable(COMMAND, ReadEfuseValue),
                         (uint32_t *)&efuse_param);
-        if (!result)
-                *efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask;
+        *efuse = result ? 0 : le32_to_cpu(efuse_param.ulEfuseValue) & mask;
 
         return result;
 }
@@ -1354,11 +1351,8 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_
                         GetIndexIntoMasterTable(COMMAND, GetVoltageInfo),
                         (uint32_t *)&get_voltage_info_param_space);
 
-        if (0 != result)
-                return result;
-
-        *voltage = le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)
-                                (&get_voltage_info_param_space))->ulVoltageLevel);
+        *voltage = result ? 0 :
+                le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel);
 
         return result;
 }
@@ -1552,15 +1546,17 @@ void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
                 case CHIP_FIJI:
                         *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMaxVddc/4);
                         *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_3 *)profile)->ulMinVddc/4);
-                        break;
+                        return;
                 case CHIP_POLARIS11:
                 case CHIP_POLARIS10:
                 case CHIP_POLARIS12:
                         *max_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMaxVddc/100);
                         *min_vddc = le32_to_cpu(((ATOM_ASIC_PROFILING_INFO_V3_6 *)profile)->ulMinVddc/100);
-                        break;
-                default:
                         return;
+                default:
+                        break;
                 }
         }
+        *max_vddc = 0;
+        *min_vddc = 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 2f69bfa478a7..85f84f4d8be5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -600,7 +600,10 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
                                                 data->gfx_min_freq_limit/100);
                 smum_send_msg_to_smc_with_parameter(hwmgr,
                                                 PPSMC_MSG_SetHardMinFclkByFreq,
+                                                hwmgr->display_config->num_display > 3 ?
+                                                SMU10_UMD_PSTATE_PEAK_FCLK :
                                                 SMU10_UMD_PSTATE_MIN_FCLK);
+
                 smum_send_msg_to_smc_with_parameter(hwmgr,
                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
                                                 SMU10_UMD_PSTATE_MIN_SOCCLK);
@@ -1125,6 +1128,23 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
 }
 
+static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
+{
+        if (bgate) {
+                amdgpu_device_ip_set_powergating_state(hwmgr->adev,
+                                                AMD_IP_BLOCK_TYPE_VCN,
+                                                AMD_PG_STATE_GATE);
+                smum_send_msg_to_smc_with_parameter(hwmgr,
+                                        PPSMC_MSG_PowerDownVcn, 0);
+        } else {
+                smum_send_msg_to_smc_with_parameter(hwmgr,
+                                                PPSMC_MSG_PowerUpVcn, 0);
+                amdgpu_device_ip_set_powergating_state(hwmgr->adev,
+                                                AMD_IP_BLOCK_TYPE_VCN,
+                                                AMD_PG_STATE_UNGATE);
+        }
+}
+
 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
         .backend_init = smu10_hwmgr_backend_init,
         .backend_fini = smu10_hwmgr_backend_fini,
@@ -1133,7 +1153,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
         .force_dpm_level = smu10_dpm_force_dpm_level,
         .get_power_state_size = smu10_get_power_state_size,
         .powerdown_uvd = NULL,
-        .powergate_uvd = NULL,
+        .powergate_uvd = smu10_powergate_vcn,
         .powergate_vce = NULL,
         .get_mclk = smu10_dpm_get_mclk,
         .get_sclk = smu10_dpm_get_sclk,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 8eb3f5176646..45e9b8cb169d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -860,7 +860,8 @@ static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
         struct phm_ppt_v1_information *table_info =
                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
-        uint32_t min_vddc, max_vddc;
+        uint32_t min_vddc = 0;
+        uint32_t max_vddc = 0;
 
         if (!table_info)
                 return;
@@ -1018,7 +1019,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 
         /* enable SCLK dpm */
-        if (!data->sclk_dpm_key_disabled)
+        if (!data->sclk_dpm_key_disabled) {
                 if (hwmgr->chip_id == CHIP_VEGAM)
                         smu7_disable_sclk_vce_handshake(hwmgr);
 
@@ -1026,6 +1027,7 @@ static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
                 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
                 "Failed to enable SCLK DPM during DPM Start Function!",
                 return -EINVAL);
+        }
 
         /* enable MCLK dpm */
         if (0 == data->mclk_dpm_key_disabled) {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
index 99b29ff45d91..c952845833d7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c
@@ -936,45 +936,49 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
 
                         if (hwmgr->chip_id == CHIP_POLARIS10) {
                                 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                                 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                         } else if (hwmgr->chip_id == CHIP_POLARIS11) {
                                 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                                 if (hwmgr->is_kicker)
                                         result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
                                 else
                                         result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                         } else if (hwmgr->chip_id == CHIP_POLARIS12) {
                                 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                                 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris12);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                         } else if (hwmgr->chip_id == CHIP_VEGAM) {
                                 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_VegaM);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                                 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_VegaM);
-                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
+                                PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error);
                         }
                 }
                 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2);
 
                 result = smu7_enable_didt(hwmgr, true);
-                PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
+                PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error);
 
                 if (hwmgr->chip_id == CHIP_POLARIS11) {
                         result = smum_send_msg_to_smc(hwmgr,
                                                 (uint16_t)(PPSMC_MSG_EnableDpmDidt));
                         PP_ASSERT_WITH_CODE((0 == result),
-                                        "Failed to enable DPM DIDT.", return result);
+                                        "Failed to enable DPM DIDT.", goto error);
                 }
                 mutex_unlock(&adev->grbm_idx_mutex);
                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
         }
 
         return 0;
+error:
+        mutex_unlock(&adev->grbm_idx_mutex);
+        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        return result;
 }
 
 int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
@@ -992,17 +996,20 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
                 result = smu7_enable_didt(hwmgr, false);
                 PP_ASSERT_WITH_CODE((result == 0),
                                 "Post DIDT enable clock gating failed.",
-                                return result);
+                                goto error);
                 if (hwmgr->chip_id == CHIP_POLARIS11) {
                         result = smum_send_msg_to_smc(hwmgr,
                                                 (uint16_t)(PPSMC_MSG_DisableDpmDidt));
                         PP_ASSERT_WITH_CODE((0 == result),
-                                        "Failed to disable DPM DIDT.", return result);
+                                        "Failed to disable DPM DIDT.", goto error);
                 }
                 adev->gfx.rlc.funcs->exit_safe_mode(adev);
         }
 
         return 0;
+error:
+        adev->gfx.rlc.funcs->exit_safe_mode(adev);
+        return result;
 }
 
 int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 9bb87857a20f..a202247c9894 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -410,7 +410,10 @@ extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                                    struct pp_power_state *adjusted_ps,
                              const struct pp_power_state *current_ps);
 
+extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);
+
 extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
+extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
 extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
 extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
 extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 3c321c7d9626..b99fb8ac822c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -229,6 +229,8 @@ struct pp_hwmgr_func {
                                 struct pp_power_state  *prequest_ps,
                         const struct pp_power_state *pcurrent_ps);
 
+        int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
+
         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
                                         enum amd_dpm_forced_level level);
 
@@ -252,6 +254,7 @@ struct pp_hwmgr_func {
                                                 const void *state);
         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
+        int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 64d33b775906..d644a9bb9078 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -283,11 +283,9 @@ int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t
 
         result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
 
-        if (result)
-                return result;
+        *value = result ? 0 : cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
 
-        *value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
-        return 0;
+        return result;
 }
 
 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index ee236dfbf1d6..c9837935f0f5 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -45,6 +45,7 @@ MODULE_FIRMWARE("amdgpu/vegam_smc.bin");
 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
 MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
 MODULE_FIRMWARE("amdgpu/vega12_smc.bin");
+MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
 
 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
index c9a563399330..2de48959ac93 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c
@@ -1366,10 +1366,12 @@ static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
 {
         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
         struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
-        struct SMU75_Discrete_MCArbDramTimingTable arb_regs = {0};
+        struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
         uint32_t i, j;
         int result = 0;
 
+        memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
+
         for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
                 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
                         result = vegam_populate_memory_timing_parameters(hwmgr,
@@ -2377,6 +2379,5 @@ const struct pp_smumgr_func vegam_smu_funcs = {
         .update_sclk_threshold = vegam_update_sclk_threshold,
         .is_hw_avfs_present = vegam_is_hw_avfs_present,
         .thermal_avfs_enable = vegam_thermal_avfs_enable,
-        .is_dpm_running = vegam_is_dpm_running,
         .thermal_setup_fan_table = vegam_thermal_setup_fan_table,
 };
diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c b/drivers/gpu/drm/scheduler/gpu_scheduler.c
index a364fc0b38c3..df1578d6f42e 100644
--- a/drivers/gpu/drm/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
@@ -139,7 +139,6 @@ int drm_sched_entity_init(struct drm_gpu_scheduler *sched,
         entity->last_scheduled = NULL;
 
         spin_lock_init(&entity->rq_lock);
-        spin_lock_init(&entity->queue_lock);
         spsc_queue_init(&entity->job_queue);
 
         atomic_set(&entity->fence_seq, 0);
@@ -413,6 +412,10 @@ drm_sched_entity_pop_job(struct drm_sched_entity *entity)
  *
  * @sched_job           The pointer to job required to submit
  *
+ * Note: To guarantee that the order of insertion to queue matches
+ * the job's fence sequence number this function should be
+ * called with drm_sched_job_init under common lock.
+ *
  * Returns 0 for success, negative error code otherwise.
  */
 void drm_sched_entity_push_job(struct drm_sched_job *sched_job,
@@ -423,11 +426,8 @@ void drm_sched_entity_push_job(struct drm_sched_job *sched_job,
 
         trace_drm_sched_job(sched_job, entity);
 
-        spin_lock(&entity->queue_lock);
         first = spsc_queue_push(&entity->job_queue, &sched_job->queue_node);
 
-        spin_unlock(&entity->queue_lock);
-
         /* first job wakes up scheduler */
         if (first) {
                 /* Add the entity to the run queue */
@@ -593,7 +593,12 @@ void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
 }
 EXPORT_SYMBOL(drm_sched_job_recovery);
 
-/* init a sched_job with basic field */
+/**
+ * Init a sched_job with basic field
+ *
+ * Note: Refer to drm_sched_entity_push_job documentation
+ * for locking considerations.
+ */
 int drm_sched_job_init(struct drm_sched_job *job,
                        struct drm_gpu_scheduler *sched,
                        struct drm_sched_entity *entity,
diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c
index 69aab086b913..df4461648e3f 100644
--- a/drivers/gpu/drm/scheduler/sched_fence.c
+++ b/drivers/gpu/drm/scheduler/sched_fence.c
@@ -87,7 +87,7 @@ static bool drm_sched_fence_enable_signaling(struct dma_fence *f)
 }
 
 /**
- * amd_sched_fence_free - free up the fence memory
+ * drm_sched_fence_free - free up the fence memory
  *
  * @rcu: RCU callback head
  *
@@ -98,12 +98,11 @@ static void drm_sched_fence_free(struct rcu_head *rcu)
         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
         struct drm_sched_fence *fence = to_drm_sched_fence(f);
 
-        dma_fence_put(fence->parent);
         kmem_cache_free(sched_fence_slab, fence);
 }
 
 /**
- * amd_sched_fence_release_scheduled - callback that fence can be freed
+ * drm_sched_fence_release_scheduled - callback that fence can be freed
  *
  * @fence: fence
  *
@@ -114,11 +113,12 @@ static void drm_sched_fence_release_scheduled(struct dma_fence *f)
 {
         struct drm_sched_fence *fence = to_drm_sched_fence(f);
 
+        dma_fence_put(fence->parent);
         call_rcu(&fence->finished.rcu, drm_sched_fence_free);
 }
 
 /**
- * amd_sched_fence_release_finished - drop extra reference
+ * drm_sched_fence_release_finished - drop extra reference
  *
  * @f: fence
  *
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index 695bde7eb055..dd63d08cc54e 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -47,6 +47,7 @@ enum amd_asic_type {
         CHIP_VEGAM,
         CHIP_VEGA10,
         CHIP_VEGA12,
+        CHIP_VEGA20,
         CHIP_RAVEN,
         CHIP_LAST,
 };
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index 52380067a43f..dec655894d08 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -56,7 +56,6 @@ struct drm_sched_entity {
         spinlock_t                      rq_lock;
         struct drm_gpu_scheduler        *sched;
 
-        spinlock_t                      queue_lock;
         struct spsc_queue               job_queue;
 
         atomic_t                        fence_seq;